1 /*
2 * Copyright (C) 2012 Invensense, Inc.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/i2c.h>
17 #include <linux/err.h>
18 #include <linux/delay.h>
19 #include <linux/sysfs.h>
20 #include <linux/jiffies.h>
21 #include <linux/irq.h>
22 #include <linux/interrupt.h>
23 #include <linux/kfifo.h>
24 #include <linux/spinlock.h>
25 #include <linux/iio/iio.h>
26 #include <linux/acpi.h>
27 #include "inv_mpu_iio.h"
28
29 /*
30 * this is the gyro scale translated from dynamic range plus/minus
31 * {250, 500, 1000, 2000} to rad/s
32 */
33 static const int gyro_scale_6050[] = {133090, 266181, 532362, 1064724};
34
35 /*
36 * this is the accel scale translated from dynamic range plus/minus
37 * {2, 4, 8, 16} to m/s^2
38 */
39 static const int accel_scale[] = {598, 1196, 2392, 4785};
40
41 static const struct inv_mpu6050_reg_map reg_set_6500 = {
42 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
43 .lpf = INV_MPU6050_REG_CONFIG,
44 .accel_lpf = INV_MPU6500_REG_ACCEL_CONFIG_2,
45 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
46 .fifo_en = INV_MPU6050_REG_FIFO_EN,
47 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
48 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
49 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
50 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
51 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
52 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
53 .temperature = INV_MPU6050_REG_TEMPERATURE,
54 .int_enable = INV_MPU6050_REG_INT_ENABLE,
55 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
56 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
57 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
58 .accl_offset = INV_MPU6500_REG_ACCEL_OFFSET,
59 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
60 };
61
62 static const struct inv_mpu6050_reg_map reg_set_6050 = {
63 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
64 .lpf = INV_MPU6050_REG_CONFIG,
65 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
66 .fifo_en = INV_MPU6050_REG_FIFO_EN,
67 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
68 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
69 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
70 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
71 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
72 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
73 .temperature = INV_MPU6050_REG_TEMPERATURE,
74 .int_enable = INV_MPU6050_REG_INT_ENABLE,
75 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
76 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
77 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
78 .accl_offset = INV_MPU6050_REG_ACCEL_OFFSET,
79 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
80 };
81
82 static const struct inv_mpu6050_chip_config chip_config_6050 = {
83 .fsr = INV_MPU6050_FSR_2000DPS,
84 .lpf = INV_MPU6050_FILTER_20HZ,
85 .fifo_rate = INV_MPU6050_INIT_FIFO_RATE,
86 .gyro_fifo_enable = false,
87 .accl_fifo_enable = false,
88 .accl_fs = INV_MPU6050_FS_02G,
89 };
90
91 /* Indexed by enum inv_devices */
92 static const struct inv_mpu6050_hw hw_info[] = {
93 {
94 .whoami = INV_MPU6050_WHOAMI_VALUE,
95 .name = "MPU6050",
96 .reg = ®_set_6050,
97 .config = &chip_config_6050,
98 },
99 {
100 .whoami = INV_MPU6500_WHOAMI_VALUE,
101 .name = "MPU6500",
102 .reg = ®_set_6500,
103 .config = &chip_config_6050,
104 },
105 {
106 .whoami = INV_MPU6000_WHOAMI_VALUE,
107 .name = "MPU6000",
108 .reg = ®_set_6050,
109 .config = &chip_config_6050,
110 },
111 {
112 .whoami = INV_MPU9150_WHOAMI_VALUE,
113 .name = "MPU9150",
114 .reg = ®_set_6050,
115 .config = &chip_config_6050,
116 },
117 {
118 .whoami = INV_MPU9250_WHOAMI_VALUE,
119 .name = "MPU9250",
120 .reg = ®_set_6500,
121 .config = &chip_config_6050,
122 },
123 {
124 .whoami = INV_ICM20608_WHOAMI_VALUE,
125 .name = "ICM20608",
126 .reg = ®_set_6500,
127 .config = &chip_config_6050,
128 },
129 };
130
inv_mpu6050_switch_engine(struct inv_mpu6050_state * st,bool en,u32 mask)131 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask)
132 {
133 unsigned int d, mgmt_1;
134 int result;
135 /*
136 * switch clock needs to be careful. Only when gyro is on, can
137 * clock source be switched to gyro. Otherwise, it must be set to
138 * internal clock
139 */
140 if (mask == INV_MPU6050_BIT_PWR_GYRO_STBY) {
141 result = regmap_read(st->map, st->reg->pwr_mgmt_1, &mgmt_1);
142 if (result)
143 return result;
144
145 mgmt_1 &= ~INV_MPU6050_BIT_CLK_MASK;
146 }
147
148 if ((mask == INV_MPU6050_BIT_PWR_GYRO_STBY) && (!en)) {
149 /*
150 * turning off gyro requires switch to internal clock first.
151 * Then turn off gyro engine
152 */
153 mgmt_1 |= INV_CLK_INTERNAL;
154 result = regmap_write(st->map, st->reg->pwr_mgmt_1, mgmt_1);
155 if (result)
156 return result;
157 }
158
159 result = regmap_read(st->map, st->reg->pwr_mgmt_2, &d);
160 if (result)
161 return result;
162 if (en)
163 d &= ~mask;
164 else
165 d |= mask;
166 result = regmap_write(st->map, st->reg->pwr_mgmt_2, d);
167 if (result)
168 return result;
169
170 if (en) {
171 /* Wait for output stabilize */
172 msleep(INV_MPU6050_TEMP_UP_TIME);
173 if (mask == INV_MPU6050_BIT_PWR_GYRO_STBY) {
174 /* switch internal clock to PLL */
175 mgmt_1 |= INV_CLK_PLL;
176 result = regmap_write(st->map,
177 st->reg->pwr_mgmt_1, mgmt_1);
178 if (result)
179 return result;
180 }
181 }
182
183 return 0;
184 }
185
inv_mpu6050_set_power_itg(struct inv_mpu6050_state * st,bool power_on)186 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on)
187 {
188 int result = 0;
189
190 if (power_on) {
191 if (!st->powerup_count)
192 result = regmap_write(st->map, st->reg->pwr_mgmt_1, 0);
193 if (!result)
194 st->powerup_count++;
195 } else {
196 st->powerup_count--;
197 if (!st->powerup_count)
198 result = regmap_write(st->map, st->reg->pwr_mgmt_1,
199 INV_MPU6050_BIT_SLEEP);
200 }
201
202 if (result)
203 return result;
204
205 if (power_on)
206 usleep_range(INV_MPU6050_REG_UP_TIME_MIN,
207 INV_MPU6050_REG_UP_TIME_MAX);
208
209 return 0;
210 }
211 EXPORT_SYMBOL_GPL(inv_mpu6050_set_power_itg);
212
213 /**
214 * inv_mpu6050_set_lpf_regs() - set low pass filter registers, chip dependent
215 *
216 * MPU60xx/MPU9150 use only 1 register for accelerometer + gyroscope
217 * MPU6500 and above have a dedicated register for accelerometer
218 */
inv_mpu6050_set_lpf_regs(struct inv_mpu6050_state * st,enum inv_mpu6050_filter_e val)219 static int inv_mpu6050_set_lpf_regs(struct inv_mpu6050_state *st,
220 enum inv_mpu6050_filter_e val)
221 {
222 int result;
223
224 result = regmap_write(st->map, st->reg->lpf, val);
225 if (result)
226 return result;
227
228 switch (st->chip_type) {
229 case INV_MPU6050:
230 case INV_MPU6000:
231 case INV_MPU9150:
232 /* old chips, nothing to do */
233 result = 0;
234 break;
235 default:
236 /* set accel lpf */
237 result = regmap_write(st->map, st->reg->accel_lpf, val);
238 break;
239 }
240
241 return result;
242 }
243
244 /**
245 * inv_mpu6050_init_config() - Initialize hardware, disable FIFO.
246 *
247 * Initial configuration:
248 * FSR: ± 2000DPS
249 * DLPF: 20Hz
250 * FIFO rate: 50Hz
251 * Clock source: Gyro PLL
252 */
inv_mpu6050_init_config(struct iio_dev * indio_dev)253 static int inv_mpu6050_init_config(struct iio_dev *indio_dev)
254 {
255 int result;
256 u8 d;
257 struct inv_mpu6050_state *st = iio_priv(indio_dev);
258
259 result = inv_mpu6050_set_power_itg(st, true);
260 if (result)
261 return result;
262 d = (INV_MPU6050_FSR_2000DPS << INV_MPU6050_GYRO_CONFIG_FSR_SHIFT);
263 result = regmap_write(st->map, st->reg->gyro_config, d);
264 if (result)
265 return result;
266
267 result = inv_mpu6050_set_lpf_regs(st, INV_MPU6050_FILTER_20HZ);
268 if (result)
269 return result;
270
271 d = INV_MPU6050_ONE_K_HZ / INV_MPU6050_INIT_FIFO_RATE - 1;
272 result = regmap_write(st->map, st->reg->sample_rate_div, d);
273 if (result)
274 return result;
275
276 d = (INV_MPU6050_FS_02G << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
277 result = regmap_write(st->map, st->reg->accl_config, d);
278 if (result)
279 return result;
280
281 memcpy(&st->chip_config, hw_info[st->chip_type].config,
282 sizeof(struct inv_mpu6050_chip_config));
283 result = inv_mpu6050_set_power_itg(st, false);
284
285 return result;
286 }
287
inv_mpu6050_sensor_set(struct inv_mpu6050_state * st,int reg,int axis,int val)288 static int inv_mpu6050_sensor_set(struct inv_mpu6050_state *st, int reg,
289 int axis, int val)
290 {
291 int ind, result;
292 __be16 d = cpu_to_be16(val);
293
294 ind = (axis - IIO_MOD_X) * 2;
295 result = regmap_bulk_write(st->map, reg + ind, (u8 *)&d, 2);
296 if (result)
297 return -EINVAL;
298
299 return 0;
300 }
301
inv_mpu6050_sensor_show(struct inv_mpu6050_state * st,int reg,int axis,int * val)302 static int inv_mpu6050_sensor_show(struct inv_mpu6050_state *st, int reg,
303 int axis, int *val)
304 {
305 int ind, result;
306 __be16 d;
307
308 ind = (axis - IIO_MOD_X) * 2;
309 result = regmap_bulk_read(st->map, reg + ind, (u8 *)&d, 2);
310 if (result)
311 return -EINVAL;
312 *val = (short)be16_to_cpup(&d);
313
314 return IIO_VAL_INT;
315 }
316
317 static int
inv_mpu6050_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)318 inv_mpu6050_read_raw(struct iio_dev *indio_dev,
319 struct iio_chan_spec const *chan,
320 int *val, int *val2, long mask)
321 {
322 struct inv_mpu6050_state *st = iio_priv(indio_dev);
323 int ret = 0;
324
325 switch (mask) {
326 case IIO_CHAN_INFO_RAW:
327 {
328 int result;
329
330 ret = IIO_VAL_INT;
331 mutex_lock(&st->lock);
332 result = iio_device_claim_direct_mode(indio_dev);
333 if (result)
334 goto error_read_raw_unlock;
335 result = inv_mpu6050_set_power_itg(st, true);
336 if (result)
337 goto error_read_raw_release;
338 switch (chan->type) {
339 case IIO_ANGL_VEL:
340 result = inv_mpu6050_switch_engine(st, true,
341 INV_MPU6050_BIT_PWR_GYRO_STBY);
342 if (result)
343 goto error_read_raw_power_off;
344 ret = inv_mpu6050_sensor_show(st, st->reg->raw_gyro,
345 chan->channel2, val);
346 result = inv_mpu6050_switch_engine(st, false,
347 INV_MPU6050_BIT_PWR_GYRO_STBY);
348 if (result)
349 goto error_read_raw_power_off;
350 break;
351 case IIO_ACCEL:
352 result = inv_mpu6050_switch_engine(st, true,
353 INV_MPU6050_BIT_PWR_ACCL_STBY);
354 if (result)
355 goto error_read_raw_power_off;
356 ret = inv_mpu6050_sensor_show(st, st->reg->raw_accl,
357 chan->channel2, val);
358 result = inv_mpu6050_switch_engine(st, false,
359 INV_MPU6050_BIT_PWR_ACCL_STBY);
360 if (result)
361 goto error_read_raw_power_off;
362 break;
363 case IIO_TEMP:
364 /* wait for stablization */
365 msleep(INV_MPU6050_SENSOR_UP_TIME);
366 ret = inv_mpu6050_sensor_show(st, st->reg->temperature,
367 IIO_MOD_X, val);
368 break;
369 default:
370 ret = -EINVAL;
371 break;
372 }
373 error_read_raw_power_off:
374 result |= inv_mpu6050_set_power_itg(st, false);
375 error_read_raw_release:
376 iio_device_release_direct_mode(indio_dev);
377 error_read_raw_unlock:
378 mutex_unlock(&st->lock);
379 if (result)
380 return result;
381
382 return ret;
383 }
384 case IIO_CHAN_INFO_SCALE:
385 switch (chan->type) {
386 case IIO_ANGL_VEL:
387 mutex_lock(&st->lock);
388 *val = 0;
389 *val2 = gyro_scale_6050[st->chip_config.fsr];
390 mutex_unlock(&st->lock);
391
392 return IIO_VAL_INT_PLUS_NANO;
393 case IIO_ACCEL:
394 mutex_lock(&st->lock);
395 *val = 0;
396 *val2 = accel_scale[st->chip_config.accl_fs];
397 mutex_unlock(&st->lock);
398
399 return IIO_VAL_INT_PLUS_MICRO;
400 case IIO_TEMP:
401 *val = 0;
402 *val2 = INV_MPU6050_TEMP_SCALE;
403
404 return IIO_VAL_INT_PLUS_MICRO;
405 default:
406 return -EINVAL;
407 }
408 case IIO_CHAN_INFO_OFFSET:
409 switch (chan->type) {
410 case IIO_TEMP:
411 *val = INV_MPU6050_TEMP_OFFSET;
412
413 return IIO_VAL_INT;
414 default:
415 return -EINVAL;
416 }
417 case IIO_CHAN_INFO_CALIBBIAS:
418 switch (chan->type) {
419 case IIO_ANGL_VEL:
420 mutex_lock(&st->lock);
421 ret = inv_mpu6050_sensor_show(st, st->reg->gyro_offset,
422 chan->channel2, val);
423 mutex_unlock(&st->lock);
424 return IIO_VAL_INT;
425 case IIO_ACCEL:
426 mutex_lock(&st->lock);
427 ret = inv_mpu6050_sensor_show(st, st->reg->accl_offset,
428 chan->channel2, val);
429 mutex_unlock(&st->lock);
430 return IIO_VAL_INT;
431
432 default:
433 return -EINVAL;
434 }
435 default:
436 return -EINVAL;
437 }
438 }
439
inv_mpu6050_write_gyro_scale(struct inv_mpu6050_state * st,int val)440 static int inv_mpu6050_write_gyro_scale(struct inv_mpu6050_state *st, int val)
441 {
442 int result, i;
443 u8 d;
444
445 for (i = 0; i < ARRAY_SIZE(gyro_scale_6050); ++i) {
446 if (gyro_scale_6050[i] == val) {
447 d = (i << INV_MPU6050_GYRO_CONFIG_FSR_SHIFT);
448 result = regmap_write(st->map, st->reg->gyro_config, d);
449 if (result)
450 return result;
451
452 st->chip_config.fsr = i;
453 return 0;
454 }
455 }
456
457 return -EINVAL;
458 }
459
inv_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)460 static int inv_write_raw_get_fmt(struct iio_dev *indio_dev,
461 struct iio_chan_spec const *chan, long mask)
462 {
463 switch (mask) {
464 case IIO_CHAN_INFO_SCALE:
465 switch (chan->type) {
466 case IIO_ANGL_VEL:
467 return IIO_VAL_INT_PLUS_NANO;
468 default:
469 return IIO_VAL_INT_PLUS_MICRO;
470 }
471 default:
472 return IIO_VAL_INT_PLUS_MICRO;
473 }
474
475 return -EINVAL;
476 }
477
inv_mpu6050_write_accel_scale(struct inv_mpu6050_state * st,int val)478 static int inv_mpu6050_write_accel_scale(struct inv_mpu6050_state *st, int val)
479 {
480 int result, i;
481 u8 d;
482
483 for (i = 0; i < ARRAY_SIZE(accel_scale); ++i) {
484 if (accel_scale[i] == val) {
485 d = (i << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
486 result = regmap_write(st->map, st->reg->accl_config, d);
487 if (result)
488 return result;
489
490 st->chip_config.accl_fs = i;
491 return 0;
492 }
493 }
494
495 return -EINVAL;
496 }
497
inv_mpu6050_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)498 static int inv_mpu6050_write_raw(struct iio_dev *indio_dev,
499 struct iio_chan_spec const *chan,
500 int val, int val2, long mask)
501 {
502 struct inv_mpu6050_state *st = iio_priv(indio_dev);
503 int result;
504
505 mutex_lock(&st->lock);
506 /*
507 * we should only update scale when the chip is disabled, i.e.
508 * not running
509 */
510 result = iio_device_claim_direct_mode(indio_dev);
511 if (result)
512 goto error_write_raw_unlock;
513 result = inv_mpu6050_set_power_itg(st, true);
514 if (result)
515 goto error_write_raw_release;
516
517 switch (mask) {
518 case IIO_CHAN_INFO_SCALE:
519 switch (chan->type) {
520 case IIO_ANGL_VEL:
521 result = inv_mpu6050_write_gyro_scale(st, val2);
522 break;
523 case IIO_ACCEL:
524 result = inv_mpu6050_write_accel_scale(st, val2);
525 break;
526 default:
527 result = -EINVAL;
528 break;
529 }
530 break;
531 case IIO_CHAN_INFO_CALIBBIAS:
532 switch (chan->type) {
533 case IIO_ANGL_VEL:
534 result = inv_mpu6050_sensor_set(st,
535 st->reg->gyro_offset,
536 chan->channel2, val);
537 break;
538 case IIO_ACCEL:
539 result = inv_mpu6050_sensor_set(st,
540 st->reg->accl_offset,
541 chan->channel2, val);
542 break;
543 default:
544 result = -EINVAL;
545 }
546 default:
547 result = -EINVAL;
548 break;
549 }
550
551 result |= inv_mpu6050_set_power_itg(st, false);
552 error_write_raw_release:
553 iio_device_release_direct_mode(indio_dev);
554 error_write_raw_unlock:
555 mutex_unlock(&st->lock);
556
557 return result;
558 }
559
560 /**
561 * inv_mpu6050_set_lpf() - set low pass filer based on fifo rate.
562 *
563 * Based on the Nyquist principle, the sampling rate must
564 * exceed twice of the bandwidth of the signal, or there
565 * would be alising. This function basically search for the
566 * correct low pass parameters based on the fifo rate, e.g,
567 * sampling frequency.
568 *
569 * lpf is set automatically when setting sampling rate to avoid any aliases.
570 */
inv_mpu6050_set_lpf(struct inv_mpu6050_state * st,int rate)571 static int inv_mpu6050_set_lpf(struct inv_mpu6050_state *st, int rate)
572 {
573 const int hz[] = {188, 98, 42, 20, 10, 5};
574 const int d[] = {INV_MPU6050_FILTER_188HZ, INV_MPU6050_FILTER_98HZ,
575 INV_MPU6050_FILTER_42HZ, INV_MPU6050_FILTER_20HZ,
576 INV_MPU6050_FILTER_10HZ, INV_MPU6050_FILTER_5HZ};
577 int i, h, result;
578 u8 data;
579
580 h = (rate >> 1);
581 i = 0;
582 while ((h < hz[i]) && (i < ARRAY_SIZE(d) - 1))
583 i++;
584 data = d[i];
585 result = inv_mpu6050_set_lpf_regs(st, data);
586 if (result)
587 return result;
588 st->chip_config.lpf = data;
589
590 return 0;
591 }
592
593 /**
594 * inv_mpu6050_fifo_rate_store() - Set fifo rate.
595 */
596 static ssize_t
inv_mpu6050_fifo_rate_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)597 inv_mpu6050_fifo_rate_store(struct device *dev, struct device_attribute *attr,
598 const char *buf, size_t count)
599 {
600 s32 fifo_rate;
601 u8 d;
602 int result;
603 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
604 struct inv_mpu6050_state *st = iio_priv(indio_dev);
605
606 if (kstrtoint(buf, 10, &fifo_rate))
607 return -EINVAL;
608 if (fifo_rate < INV_MPU6050_MIN_FIFO_RATE ||
609 fifo_rate > INV_MPU6050_MAX_FIFO_RATE)
610 return -EINVAL;
611
612 mutex_lock(&st->lock);
613 if (fifo_rate == st->chip_config.fifo_rate) {
614 result = 0;
615 goto fifo_rate_fail_unlock;
616 }
617 result = iio_device_claim_direct_mode(indio_dev);
618 if (result)
619 goto fifo_rate_fail_unlock;
620 result = inv_mpu6050_set_power_itg(st, true);
621 if (result)
622 goto fifo_rate_fail_release;
623
624 d = INV_MPU6050_ONE_K_HZ / fifo_rate - 1;
625 result = regmap_write(st->map, st->reg->sample_rate_div, d);
626 if (result)
627 goto fifo_rate_fail_power_off;
628 st->chip_config.fifo_rate = fifo_rate;
629
630 result = inv_mpu6050_set_lpf(st, fifo_rate);
631 if (result)
632 goto fifo_rate_fail_power_off;
633
634 fifo_rate_fail_power_off:
635 result |= inv_mpu6050_set_power_itg(st, false);
636 fifo_rate_fail_release:
637 iio_device_release_direct_mode(indio_dev);
638 fifo_rate_fail_unlock:
639 mutex_unlock(&st->lock);
640 if (result)
641 return result;
642
643 return count;
644 }
645
646 /**
647 * inv_fifo_rate_show() - Get the current sampling rate.
648 */
649 static ssize_t
inv_fifo_rate_show(struct device * dev,struct device_attribute * attr,char * buf)650 inv_fifo_rate_show(struct device *dev, struct device_attribute *attr,
651 char *buf)
652 {
653 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
654 unsigned fifo_rate;
655
656 mutex_lock(&st->lock);
657 fifo_rate = st->chip_config.fifo_rate;
658 mutex_unlock(&st->lock);
659
660 return scnprintf(buf, PAGE_SIZE, "%u\n", fifo_rate);
661 }
662
663 /**
664 * inv_attr_show() - calling this function will show current
665 * parameters.
666 *
667 * Deprecated in favor of IIO mounting matrix API.
668 *
669 * See inv_get_mount_matrix()
670 */
inv_attr_show(struct device * dev,struct device_attribute * attr,char * buf)671 static ssize_t inv_attr_show(struct device *dev, struct device_attribute *attr,
672 char *buf)
673 {
674 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
675 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
676 s8 *m;
677
678 switch (this_attr->address) {
679 /*
680 * In MPU6050, the two matrix are the same because gyro and accel
681 * are integrated in one chip
682 */
683 case ATTR_GYRO_MATRIX:
684 case ATTR_ACCL_MATRIX:
685 m = st->plat_data.orientation;
686
687 return scnprintf(buf, PAGE_SIZE,
688 "%d, %d, %d; %d, %d, %d; %d, %d, %d\n",
689 m[0], m[1], m[2], m[3], m[4], m[5], m[6], m[7], m[8]);
690 default:
691 return -EINVAL;
692 }
693 }
694
695 /**
696 * inv_mpu6050_validate_trigger() - validate_trigger callback for invensense
697 * MPU6050 device.
698 * @indio_dev: The IIO device
699 * @trig: The new trigger
700 *
701 * Returns: 0 if the 'trig' matches the trigger registered by the MPU6050
702 * device, -EINVAL otherwise.
703 */
inv_mpu6050_validate_trigger(struct iio_dev * indio_dev,struct iio_trigger * trig)704 static int inv_mpu6050_validate_trigger(struct iio_dev *indio_dev,
705 struct iio_trigger *trig)
706 {
707 struct inv_mpu6050_state *st = iio_priv(indio_dev);
708
709 if (st->trig != trig)
710 return -EINVAL;
711
712 return 0;
713 }
714
715 static const struct iio_mount_matrix *
inv_get_mount_matrix(const struct iio_dev * indio_dev,const struct iio_chan_spec * chan)716 inv_get_mount_matrix(const struct iio_dev *indio_dev,
717 const struct iio_chan_spec *chan)
718 {
719 return &((struct inv_mpu6050_state *)iio_priv(indio_dev))->orientation;
720 }
721
722 static const struct iio_chan_spec_ext_info inv_ext_info[] = {
723 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, inv_get_mount_matrix),
724 { },
725 };
726
727 #define INV_MPU6050_CHAN(_type, _channel2, _index) \
728 { \
729 .type = _type, \
730 .modified = 1, \
731 .channel2 = _channel2, \
732 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
733 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
734 BIT(IIO_CHAN_INFO_CALIBBIAS), \
735 .scan_index = _index, \
736 .scan_type = { \
737 .sign = 's', \
738 .realbits = 16, \
739 .storagebits = 16, \
740 .shift = 0, \
741 .endianness = IIO_BE, \
742 }, \
743 .ext_info = inv_ext_info, \
744 }
745
746 static const struct iio_chan_spec inv_mpu_channels[] = {
747 IIO_CHAN_SOFT_TIMESTAMP(INV_MPU6050_SCAN_TIMESTAMP),
748 /*
749 * Note that temperature should only be via polled reading only,
750 * not the final scan elements output.
751 */
752 {
753 .type = IIO_TEMP,
754 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW)
755 | BIT(IIO_CHAN_INFO_OFFSET)
756 | BIT(IIO_CHAN_INFO_SCALE),
757 .scan_index = -1,
758 },
759 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
760 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
761 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
762
763 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
764 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
765 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
766 };
767
768 /* constant IIO attribute */
769 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 20 50 100 200 500");
770 static IIO_CONST_ATTR(in_anglvel_scale_available,
771 "0.000133090 0.000266181 0.000532362 0.001064724");
772 static IIO_CONST_ATTR(in_accel_scale_available,
773 "0.000598 0.001196 0.002392 0.004785");
774 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR, inv_fifo_rate_show,
775 inv_mpu6050_fifo_rate_store);
776
777 /* Deprecated: kept for userspace backward compatibility. */
778 static IIO_DEVICE_ATTR(in_gyro_matrix, S_IRUGO, inv_attr_show, NULL,
779 ATTR_GYRO_MATRIX);
780 static IIO_DEVICE_ATTR(in_accel_matrix, S_IRUGO, inv_attr_show, NULL,
781 ATTR_ACCL_MATRIX);
782
783 static struct attribute *inv_attributes[] = {
784 &iio_dev_attr_in_gyro_matrix.dev_attr.attr, /* deprecated */
785 &iio_dev_attr_in_accel_matrix.dev_attr.attr, /* deprecated */
786 &iio_dev_attr_sampling_frequency.dev_attr.attr,
787 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
788 &iio_const_attr_in_accel_scale_available.dev_attr.attr,
789 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
790 NULL,
791 };
792
793 static const struct attribute_group inv_attribute_group = {
794 .attrs = inv_attributes
795 };
796
797 static const struct iio_info mpu_info = {
798 .driver_module = THIS_MODULE,
799 .read_raw = &inv_mpu6050_read_raw,
800 .write_raw = &inv_mpu6050_write_raw,
801 .write_raw_get_fmt = &inv_write_raw_get_fmt,
802 .attrs = &inv_attribute_group,
803 .validate_trigger = inv_mpu6050_validate_trigger,
804 };
805
806 /**
807 * inv_check_and_setup_chip() - check and setup chip.
808 */
inv_check_and_setup_chip(struct inv_mpu6050_state * st)809 static int inv_check_and_setup_chip(struct inv_mpu6050_state *st)
810 {
811 int result;
812 unsigned int regval;
813 int i;
814
815 st->hw = &hw_info[st->chip_type];
816 st->reg = hw_info[st->chip_type].reg;
817
818 /* check chip self-identification */
819 result = regmap_read(st->map, INV_MPU6050_REG_WHOAMI, ®val);
820 if (result)
821 return result;
822 if (regval != st->hw->whoami) {
823 /* check whoami against all possible values */
824 for (i = 0; i < INV_NUM_PARTS; ++i) {
825 if (regval == hw_info[i].whoami) {
826 dev_warn(regmap_get_device(st->map),
827 "whoami mismatch got %#02x (%s)"
828 "expected %#02hhx (%s)\n",
829 regval, hw_info[i].name,
830 st->hw->whoami, st->hw->name);
831 break;
832 }
833 }
834 if (i >= INV_NUM_PARTS) {
835 dev_err(regmap_get_device(st->map),
836 "invalid whoami %#02x expected %#02hhx (%s)\n",
837 regval, st->hw->whoami, st->hw->name);
838 return -ENODEV;
839 }
840 }
841
842 /* reset to make sure previous state are not there */
843 result = regmap_write(st->map, st->reg->pwr_mgmt_1,
844 INV_MPU6050_BIT_H_RESET);
845 if (result)
846 return result;
847 msleep(INV_MPU6050_POWER_UP_TIME);
848
849 /*
850 * toggle power state. After reset, the sleep bit could be on
851 * or off depending on the OTP settings. Toggling power would
852 * make it in a definite state as well as making the hardware
853 * state align with the software state
854 */
855 result = inv_mpu6050_set_power_itg(st, false);
856 if (result)
857 return result;
858 result = inv_mpu6050_set_power_itg(st, true);
859 if (result)
860 return result;
861
862 result = inv_mpu6050_switch_engine(st, false,
863 INV_MPU6050_BIT_PWR_ACCL_STBY);
864 if (result)
865 return result;
866 result = inv_mpu6050_switch_engine(st, false,
867 INV_MPU6050_BIT_PWR_GYRO_STBY);
868 if (result)
869 return result;
870
871 return 0;
872 }
873
inv_mpu_core_probe(struct regmap * regmap,int irq,const char * name,int (* inv_mpu_bus_setup)(struct iio_dev *),int chip_type)874 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
875 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type)
876 {
877 struct inv_mpu6050_state *st;
878 struct iio_dev *indio_dev;
879 struct inv_mpu6050_platform_data *pdata;
880 struct device *dev = regmap_get_device(regmap);
881 int result;
882
883 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
884 if (!indio_dev)
885 return -ENOMEM;
886
887 BUILD_BUG_ON(ARRAY_SIZE(hw_info) != INV_NUM_PARTS);
888 if (chip_type < 0 || chip_type >= INV_NUM_PARTS) {
889 dev_err(dev, "Bad invensense chip_type=%d name=%s\n",
890 chip_type, name);
891 return -ENODEV;
892 }
893 st = iio_priv(indio_dev);
894 mutex_init(&st->lock);
895 st->chip_type = chip_type;
896 st->powerup_count = 0;
897 st->irq = irq;
898 st->map = regmap;
899
900 pdata = dev_get_platdata(dev);
901 if (!pdata) {
902 result = of_iio_read_mount_matrix(dev, "mount-matrix",
903 &st->orientation);
904 if (result) {
905 dev_err(dev, "Failed to retrieve mounting matrix %d\n",
906 result);
907 return result;
908 }
909 } else {
910 st->plat_data = *pdata;
911 }
912
913 /* power is turned on inside check chip type*/
914 result = inv_check_and_setup_chip(st);
915 if (result)
916 return result;
917
918 if (inv_mpu_bus_setup)
919 inv_mpu_bus_setup(indio_dev);
920
921 result = inv_mpu6050_init_config(indio_dev);
922 if (result) {
923 dev_err(dev, "Could not initialize device.\n");
924 return result;
925 }
926
927 dev_set_drvdata(dev, indio_dev);
928 indio_dev->dev.parent = dev;
929 /* name will be NULL when enumerated via ACPI */
930 if (name)
931 indio_dev->name = name;
932 else
933 indio_dev->name = dev_name(dev);
934 indio_dev->channels = inv_mpu_channels;
935 indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);
936
937 indio_dev->info = &mpu_info;
938 indio_dev->modes = INDIO_BUFFER_TRIGGERED;
939
940 result = iio_triggered_buffer_setup(indio_dev,
941 inv_mpu6050_irq_handler,
942 inv_mpu6050_read_fifo,
943 NULL);
944 if (result) {
945 dev_err(dev, "configure buffer fail %d\n", result);
946 return result;
947 }
948 result = inv_mpu6050_probe_trigger(indio_dev);
949 if (result) {
950 dev_err(dev, "trigger probe fail %d\n", result);
951 goto out_unreg_ring;
952 }
953
954 INIT_KFIFO(st->timestamps);
955 spin_lock_init(&st->time_stamp_lock);
956 result = iio_device_register(indio_dev);
957 if (result) {
958 dev_err(dev, "IIO register fail %d\n", result);
959 goto out_remove_trigger;
960 }
961
962 return 0;
963
964 out_remove_trigger:
965 inv_mpu6050_remove_trigger(st);
966 out_unreg_ring:
967 iio_triggered_buffer_cleanup(indio_dev);
968 return result;
969 }
970 EXPORT_SYMBOL_GPL(inv_mpu_core_probe);
971
inv_mpu_core_remove(struct device * dev)972 int inv_mpu_core_remove(struct device *dev)
973 {
974 struct iio_dev *indio_dev = dev_get_drvdata(dev);
975
976 iio_device_unregister(indio_dev);
977 inv_mpu6050_remove_trigger(iio_priv(indio_dev));
978 iio_triggered_buffer_cleanup(indio_dev);
979
980 return 0;
981 }
982 EXPORT_SYMBOL_GPL(inv_mpu_core_remove);
983
984 #ifdef CONFIG_PM_SLEEP
985
inv_mpu_resume(struct device * dev)986 static int inv_mpu_resume(struct device *dev)
987 {
988 struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev));
989 int result;
990
991 mutex_lock(&st->lock);
992 result = inv_mpu6050_set_power_itg(st, true);
993 mutex_unlock(&st->lock);
994
995 return result;
996 }
997
inv_mpu_suspend(struct device * dev)998 static int inv_mpu_suspend(struct device *dev)
999 {
1000 struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev));
1001 int result;
1002
1003 mutex_lock(&st->lock);
1004 result = inv_mpu6050_set_power_itg(st, false);
1005 mutex_unlock(&st->lock);
1006
1007 return result;
1008 }
1009 #endif /* CONFIG_PM_SLEEP */
1010
1011 SIMPLE_DEV_PM_OPS(inv_mpu_pmops, inv_mpu_suspend, inv_mpu_resume);
1012 EXPORT_SYMBOL_GPL(inv_mpu_pmops);
1013
1014 MODULE_AUTHOR("Invensense Corporation");
1015 MODULE_DESCRIPTION("Invensense device MPU6050 driver");
1016 MODULE_LICENSE("GPL");
1017