1 /*
2 * Copyright(c) 2015, 2016 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
47
48 #include <linux/spinlock.h>
49 #include <linux/seqlock.h>
50 #include <linux/netdevice.h>
51 #include <linux/moduleparam.h>
52 #include <linux/bitops.h>
53 #include <linux/timer.h>
54 #include <linux/vmalloc.h>
55 #include <linux/highmem.h>
56
57 #include "hfi.h"
58 #include "common.h"
59 #include "qp.h"
60 #include "sdma.h"
61 #include "iowait.h"
62 #include "trace.h"
63
64 /* must be a power of 2 >= 64 <= 32768 */
65 #define SDMA_DESCQ_CNT 2048
66 #define SDMA_DESC_INTR 64
67 #define INVALID_TAIL 0xffff
68
69 static uint sdma_descq_cnt = SDMA_DESCQ_CNT;
70 module_param(sdma_descq_cnt, uint, S_IRUGO);
71 MODULE_PARM_DESC(sdma_descq_cnt, "Number of SDMA descq entries");
72
73 static uint sdma_idle_cnt = 250;
74 module_param(sdma_idle_cnt, uint, S_IRUGO);
75 MODULE_PARM_DESC(sdma_idle_cnt, "sdma interrupt idle delay (ns,default 250)");
76
77 uint mod_num_sdma;
78 module_param_named(num_sdma, mod_num_sdma, uint, S_IRUGO);
79 MODULE_PARM_DESC(num_sdma, "Set max number SDMA engines to use");
80
81 static uint sdma_desct_intr = SDMA_DESC_INTR;
82 module_param_named(desct_intr, sdma_desct_intr, uint, S_IRUGO | S_IWUSR);
83 MODULE_PARM_DESC(desct_intr, "Number of SDMA descriptor before interrupt");
84
85 #define SDMA_WAIT_BATCH_SIZE 20
86 /* max wait time for a SDMA engine to indicate it has halted */
87 #define SDMA_ERR_HALT_TIMEOUT 10 /* ms */
88 /* all SDMA engine errors that cause a halt */
89
90 #define SD(name) SEND_DMA_##name
91 #define ALL_SDMA_ENG_HALT_ERRS \
92 (SD(ENG_ERR_STATUS_SDMA_WRONG_DW_ERR_SMASK) \
93 | SD(ENG_ERR_STATUS_SDMA_GEN_MISMATCH_ERR_SMASK) \
94 | SD(ENG_ERR_STATUS_SDMA_TOO_LONG_ERR_SMASK) \
95 | SD(ENG_ERR_STATUS_SDMA_TAIL_OUT_OF_BOUNDS_ERR_SMASK) \
96 | SD(ENG_ERR_STATUS_SDMA_FIRST_DESC_ERR_SMASK) \
97 | SD(ENG_ERR_STATUS_SDMA_MEM_READ_ERR_SMASK) \
98 | SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK) \
99 | SD(ENG_ERR_STATUS_SDMA_LENGTH_MISMATCH_ERR_SMASK) \
100 | SD(ENG_ERR_STATUS_SDMA_PACKET_DESC_OVERFLOW_ERR_SMASK) \
101 | SD(ENG_ERR_STATUS_SDMA_HEADER_SELECT_ERR_SMASK) \
102 | SD(ENG_ERR_STATUS_SDMA_HEADER_ADDRESS_ERR_SMASK) \
103 | SD(ENG_ERR_STATUS_SDMA_HEADER_LENGTH_ERR_SMASK) \
104 | SD(ENG_ERR_STATUS_SDMA_TIMEOUT_ERR_SMASK) \
105 | SD(ENG_ERR_STATUS_SDMA_DESC_TABLE_UNC_ERR_SMASK) \
106 | SD(ENG_ERR_STATUS_SDMA_ASSEMBLY_UNC_ERR_SMASK) \
107 | SD(ENG_ERR_STATUS_SDMA_PACKET_TRACKING_UNC_ERR_SMASK) \
108 | SD(ENG_ERR_STATUS_SDMA_HEADER_STORAGE_UNC_ERR_SMASK) \
109 | SD(ENG_ERR_STATUS_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SMASK))
110
111 /* sdma_sendctrl operations */
112 #define SDMA_SENDCTRL_OP_ENABLE BIT(0)
113 #define SDMA_SENDCTRL_OP_INTENABLE BIT(1)
114 #define SDMA_SENDCTRL_OP_HALT BIT(2)
115 #define SDMA_SENDCTRL_OP_CLEANUP BIT(3)
116
117 /* handle long defines */
118 #define SDMA_EGRESS_PACKET_OCCUPANCY_SMASK \
119 SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SMASK
120 #define SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT \
121 SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT
122
123 static const char * const sdma_state_names[] = {
124 [sdma_state_s00_hw_down] = "s00_HwDown",
125 [sdma_state_s10_hw_start_up_halt_wait] = "s10_HwStartUpHaltWait",
126 [sdma_state_s15_hw_start_up_clean_wait] = "s15_HwStartUpCleanWait",
127 [sdma_state_s20_idle] = "s20_Idle",
128 [sdma_state_s30_sw_clean_up_wait] = "s30_SwCleanUpWait",
129 [sdma_state_s40_hw_clean_up_wait] = "s40_HwCleanUpWait",
130 [sdma_state_s50_hw_halt_wait] = "s50_HwHaltWait",
131 [sdma_state_s60_idle_halt_wait] = "s60_IdleHaltWait",
132 [sdma_state_s80_hw_freeze] = "s80_HwFreeze",
133 [sdma_state_s82_freeze_sw_clean] = "s82_FreezeSwClean",
134 [sdma_state_s99_running] = "s99_Running",
135 };
136
137 #ifdef CONFIG_SDMA_VERBOSITY
138 static const char * const sdma_event_names[] = {
139 [sdma_event_e00_go_hw_down] = "e00_GoHwDown",
140 [sdma_event_e10_go_hw_start] = "e10_GoHwStart",
141 [sdma_event_e15_hw_halt_done] = "e15_HwHaltDone",
142 [sdma_event_e25_hw_clean_up_done] = "e25_HwCleanUpDone",
143 [sdma_event_e30_go_running] = "e30_GoRunning",
144 [sdma_event_e40_sw_cleaned] = "e40_SwCleaned",
145 [sdma_event_e50_hw_cleaned] = "e50_HwCleaned",
146 [sdma_event_e60_hw_halted] = "e60_HwHalted",
147 [sdma_event_e70_go_idle] = "e70_GoIdle",
148 [sdma_event_e80_hw_freeze] = "e80_HwFreeze",
149 [sdma_event_e81_hw_frozen] = "e81_HwFrozen",
150 [sdma_event_e82_hw_unfreeze] = "e82_HwUnfreeze",
151 [sdma_event_e85_link_down] = "e85_LinkDown",
152 [sdma_event_e90_sw_halted] = "e90_SwHalted",
153 };
154 #endif
155
156 static const struct sdma_set_state_action sdma_action_table[] = {
157 [sdma_state_s00_hw_down] = {
158 .go_s99_running_tofalse = 1,
159 .op_enable = 0,
160 .op_intenable = 0,
161 .op_halt = 0,
162 .op_cleanup = 0,
163 },
164 [sdma_state_s10_hw_start_up_halt_wait] = {
165 .op_enable = 0,
166 .op_intenable = 0,
167 .op_halt = 1,
168 .op_cleanup = 0,
169 },
170 [sdma_state_s15_hw_start_up_clean_wait] = {
171 .op_enable = 0,
172 .op_intenable = 1,
173 .op_halt = 0,
174 .op_cleanup = 1,
175 },
176 [sdma_state_s20_idle] = {
177 .op_enable = 0,
178 .op_intenable = 1,
179 .op_halt = 0,
180 .op_cleanup = 0,
181 },
182 [sdma_state_s30_sw_clean_up_wait] = {
183 .op_enable = 0,
184 .op_intenable = 0,
185 .op_halt = 0,
186 .op_cleanup = 0,
187 },
188 [sdma_state_s40_hw_clean_up_wait] = {
189 .op_enable = 0,
190 .op_intenable = 0,
191 .op_halt = 0,
192 .op_cleanup = 1,
193 },
194 [sdma_state_s50_hw_halt_wait] = {
195 .op_enable = 0,
196 .op_intenable = 0,
197 .op_halt = 0,
198 .op_cleanup = 0,
199 },
200 [sdma_state_s60_idle_halt_wait] = {
201 .go_s99_running_tofalse = 1,
202 .op_enable = 0,
203 .op_intenable = 0,
204 .op_halt = 1,
205 .op_cleanup = 0,
206 },
207 [sdma_state_s80_hw_freeze] = {
208 .op_enable = 0,
209 .op_intenable = 0,
210 .op_halt = 0,
211 .op_cleanup = 0,
212 },
213 [sdma_state_s82_freeze_sw_clean] = {
214 .op_enable = 0,
215 .op_intenable = 0,
216 .op_halt = 0,
217 .op_cleanup = 0,
218 },
219 [sdma_state_s99_running] = {
220 .op_enable = 1,
221 .op_intenable = 1,
222 .op_halt = 0,
223 .op_cleanup = 0,
224 .go_s99_running_totrue = 1,
225 },
226 };
227
228 #define SDMA_TAIL_UPDATE_THRESH 0x1F
229
230 /* declare all statics here rather than keep sorting */
231 static void sdma_complete(struct kref *);
232 static void sdma_finalput(struct sdma_state *);
233 static void sdma_get(struct sdma_state *);
234 static void sdma_hw_clean_up_task(unsigned long);
235 static void sdma_put(struct sdma_state *);
236 static void sdma_set_state(struct sdma_engine *, enum sdma_states);
237 static void sdma_start_hw_clean_up(struct sdma_engine *);
238 static void sdma_sw_clean_up_task(unsigned long);
239 static void sdma_sendctrl(struct sdma_engine *, unsigned);
240 static void init_sdma_regs(struct sdma_engine *, u32, uint);
241 static void sdma_process_event(
242 struct sdma_engine *sde,
243 enum sdma_events event);
244 static void __sdma_process_event(
245 struct sdma_engine *sde,
246 enum sdma_events event);
247 static void dump_sdma_state(struct sdma_engine *sde);
248 static void sdma_make_progress(struct sdma_engine *sde, u64 status);
249 static void sdma_desc_avail(struct sdma_engine *sde, uint avail);
250 static void sdma_flush_descq(struct sdma_engine *sde);
251
252 /**
253 * sdma_state_name() - return state string from enum
254 * @state: state
255 */
sdma_state_name(enum sdma_states state)256 static const char *sdma_state_name(enum sdma_states state)
257 {
258 return sdma_state_names[state];
259 }
260
sdma_get(struct sdma_state * ss)261 static void sdma_get(struct sdma_state *ss)
262 {
263 kref_get(&ss->kref);
264 }
265
sdma_complete(struct kref * kref)266 static void sdma_complete(struct kref *kref)
267 {
268 struct sdma_state *ss =
269 container_of(kref, struct sdma_state, kref);
270
271 complete(&ss->comp);
272 }
273
sdma_put(struct sdma_state * ss)274 static void sdma_put(struct sdma_state *ss)
275 {
276 kref_put(&ss->kref, sdma_complete);
277 }
278
sdma_finalput(struct sdma_state * ss)279 static void sdma_finalput(struct sdma_state *ss)
280 {
281 sdma_put(ss);
282 wait_for_completion(&ss->comp);
283 }
284
write_sde_csr(struct sdma_engine * sde,u32 offset0,u64 value)285 static inline void write_sde_csr(
286 struct sdma_engine *sde,
287 u32 offset0,
288 u64 value)
289 {
290 write_kctxt_csr(sde->dd, sde->this_idx, offset0, value);
291 }
292
read_sde_csr(struct sdma_engine * sde,u32 offset0)293 static inline u64 read_sde_csr(
294 struct sdma_engine *sde,
295 u32 offset0)
296 {
297 return read_kctxt_csr(sde->dd, sde->this_idx, offset0);
298 }
299
300 /*
301 * sdma_wait_for_packet_egress() - wait for the VL FIFO occupancy for
302 * sdma engine 'sde' to drop to 0.
303 */
sdma_wait_for_packet_egress(struct sdma_engine * sde,int pause)304 static void sdma_wait_for_packet_egress(struct sdma_engine *sde,
305 int pause)
306 {
307 u64 off = 8 * sde->this_idx;
308 struct hfi1_devdata *dd = sde->dd;
309 int lcnt = 0;
310 u64 reg_prev;
311 u64 reg = 0;
312
313 while (1) {
314 reg_prev = reg;
315 reg = read_csr(dd, off + SEND_EGRESS_SEND_DMA_STATUS);
316
317 reg &= SDMA_EGRESS_PACKET_OCCUPANCY_SMASK;
318 reg >>= SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT;
319 if (reg == 0)
320 break;
321 /* counter is reest if accupancy count changes */
322 if (reg != reg_prev)
323 lcnt = 0;
324 if (lcnt++ > 500) {
325 /* timed out - bounce the link */
326 dd_dev_err(dd, "%s: engine %u timeout waiting for packets to egress, remaining count %u, bouncing link\n",
327 __func__, sde->this_idx, (u32)reg);
328 queue_work(dd->pport->link_wq,
329 &dd->pport->link_bounce_work);
330 break;
331 }
332 udelay(1);
333 }
334 }
335
336 /*
337 * sdma_wait() - wait for packet egress to complete for all SDMA engines,
338 * and pause for credit return.
339 */
sdma_wait(struct hfi1_devdata * dd)340 void sdma_wait(struct hfi1_devdata *dd)
341 {
342 int i;
343
344 for (i = 0; i < dd->num_sdma; i++) {
345 struct sdma_engine *sde = &dd->per_sdma[i];
346
347 sdma_wait_for_packet_egress(sde, 0);
348 }
349 }
350
sdma_set_desc_cnt(struct sdma_engine * sde,unsigned cnt)351 static inline void sdma_set_desc_cnt(struct sdma_engine *sde, unsigned cnt)
352 {
353 u64 reg;
354
355 if (!(sde->dd->flags & HFI1_HAS_SDMA_TIMEOUT))
356 return;
357 reg = cnt;
358 reg &= SD(DESC_CNT_CNT_MASK);
359 reg <<= SD(DESC_CNT_CNT_SHIFT);
360 write_sde_csr(sde, SD(DESC_CNT), reg);
361 }
362
complete_tx(struct sdma_engine * sde,struct sdma_txreq * tx,int res)363 static inline void complete_tx(struct sdma_engine *sde,
364 struct sdma_txreq *tx,
365 int res)
366 {
367 /* protect against complete modifying */
368 struct iowait *wait = tx->wait;
369 callback_t complete = tx->complete;
370
371 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
372 trace_hfi1_sdma_out_sn(sde, tx->sn);
373 if (WARN_ON_ONCE(sde->head_sn != tx->sn))
374 dd_dev_err(sde->dd, "expected %llu got %llu\n",
375 sde->head_sn, tx->sn);
376 sde->head_sn++;
377 #endif
378 __sdma_txclean(sde->dd, tx);
379 if (complete)
380 (*complete)(tx, res);
381 if (wait && iowait_sdma_dec(wait))
382 iowait_drain_wakeup(wait);
383 }
384
385 /*
386 * Complete all the sdma requests with a SDMA_TXREQ_S_ABORTED status
387 *
388 * Depending on timing there can be txreqs in two places:
389 * - in the descq ring
390 * - in the flush list
391 *
392 * To avoid ordering issues the descq ring needs to be flushed
393 * first followed by the flush list.
394 *
395 * This routine is called from two places
396 * - From a work queue item
397 * - Directly from the state machine just before setting the
398 * state to running
399 *
400 * Must be called with head_lock held
401 *
402 */
sdma_flush(struct sdma_engine * sde)403 static void sdma_flush(struct sdma_engine *sde)
404 {
405 struct sdma_txreq *txp, *txp_next;
406 LIST_HEAD(flushlist);
407 unsigned long flags;
408
409 /* flush from head to tail */
410 sdma_flush_descq(sde);
411 spin_lock_irqsave(&sde->flushlist_lock, flags);
412 /* copy flush list */
413 list_for_each_entry_safe(txp, txp_next, &sde->flushlist, list) {
414 list_del_init(&txp->list);
415 list_add_tail(&txp->list, &flushlist);
416 }
417 spin_unlock_irqrestore(&sde->flushlist_lock, flags);
418 /* flush from flush list */
419 list_for_each_entry_safe(txp, txp_next, &flushlist, list)
420 complete_tx(sde, txp, SDMA_TXREQ_S_ABORTED);
421 }
422
423 /*
424 * Fields a work request for flushing the descq ring
425 * and the flush list
426 *
427 * If the engine has been brought to running during
428 * the scheduling delay, the flush is ignored, assuming
429 * that the process of bringing the engine to running
430 * would have done this flush prior to going to running.
431 *
432 */
sdma_field_flush(struct work_struct * work)433 static void sdma_field_flush(struct work_struct *work)
434 {
435 unsigned long flags;
436 struct sdma_engine *sde =
437 container_of(work, struct sdma_engine, flush_worker);
438
439 write_seqlock_irqsave(&sde->head_lock, flags);
440 if (!__sdma_running(sde))
441 sdma_flush(sde);
442 write_sequnlock_irqrestore(&sde->head_lock, flags);
443 }
444
sdma_err_halt_wait(struct work_struct * work)445 static void sdma_err_halt_wait(struct work_struct *work)
446 {
447 struct sdma_engine *sde = container_of(work, struct sdma_engine,
448 err_halt_worker);
449 u64 statuscsr;
450 unsigned long timeout;
451
452 timeout = jiffies + msecs_to_jiffies(SDMA_ERR_HALT_TIMEOUT);
453 while (1) {
454 statuscsr = read_sde_csr(sde, SD(STATUS));
455 statuscsr &= SD(STATUS_ENG_HALTED_SMASK);
456 if (statuscsr)
457 break;
458 if (time_after(jiffies, timeout)) {
459 dd_dev_err(sde->dd,
460 "SDMA engine %d - timeout waiting for engine to halt\n",
461 sde->this_idx);
462 /*
463 * Continue anyway. This could happen if there was
464 * an uncorrectable error in the wrong spot.
465 */
466 break;
467 }
468 usleep_range(80, 120);
469 }
470
471 sdma_process_event(sde, sdma_event_e15_hw_halt_done);
472 }
473
sdma_err_progress_check_schedule(struct sdma_engine * sde)474 static void sdma_err_progress_check_schedule(struct sdma_engine *sde)
475 {
476 if (!is_bx(sde->dd) && HFI1_CAP_IS_KSET(SDMA_AHG)) {
477 unsigned index;
478 struct hfi1_devdata *dd = sde->dd;
479
480 for (index = 0; index < dd->num_sdma; index++) {
481 struct sdma_engine *curr_sdma = &dd->per_sdma[index];
482
483 if (curr_sdma != sde)
484 curr_sdma->progress_check_head =
485 curr_sdma->descq_head;
486 }
487 dd_dev_err(sde->dd,
488 "SDMA engine %d - check scheduled\n",
489 sde->this_idx);
490 mod_timer(&sde->err_progress_check_timer, jiffies + 10);
491 }
492 }
493
sdma_err_progress_check(unsigned long data)494 static void sdma_err_progress_check(unsigned long data)
495 {
496 unsigned index;
497 struct sdma_engine *sde = (struct sdma_engine *)data;
498
499 dd_dev_err(sde->dd, "SDE progress check event\n");
500 for (index = 0; index < sde->dd->num_sdma; index++) {
501 struct sdma_engine *curr_sde = &sde->dd->per_sdma[index];
502 unsigned long flags;
503
504 /* check progress on each engine except the current one */
505 if (curr_sde == sde)
506 continue;
507 /*
508 * We must lock interrupts when acquiring sde->lock,
509 * to avoid a deadlock if interrupt triggers and spins on
510 * the same lock on same CPU
511 */
512 spin_lock_irqsave(&curr_sde->tail_lock, flags);
513 write_seqlock(&curr_sde->head_lock);
514
515 /* skip non-running queues */
516 if (curr_sde->state.current_state != sdma_state_s99_running) {
517 write_sequnlock(&curr_sde->head_lock);
518 spin_unlock_irqrestore(&curr_sde->tail_lock, flags);
519 continue;
520 }
521
522 if ((curr_sde->descq_head != curr_sde->descq_tail) &&
523 (curr_sde->descq_head ==
524 curr_sde->progress_check_head))
525 __sdma_process_event(curr_sde,
526 sdma_event_e90_sw_halted);
527 write_sequnlock(&curr_sde->head_lock);
528 spin_unlock_irqrestore(&curr_sde->tail_lock, flags);
529 }
530 schedule_work(&sde->err_halt_worker);
531 }
532
sdma_hw_clean_up_task(unsigned long opaque)533 static void sdma_hw_clean_up_task(unsigned long opaque)
534 {
535 struct sdma_engine *sde = (struct sdma_engine *)opaque;
536 u64 statuscsr;
537
538 while (1) {
539 #ifdef CONFIG_SDMA_VERBOSITY
540 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
541 sde->this_idx, slashstrip(__FILE__), __LINE__,
542 __func__);
543 #endif
544 statuscsr = read_sde_csr(sde, SD(STATUS));
545 statuscsr &= SD(STATUS_ENG_CLEANED_UP_SMASK);
546 if (statuscsr)
547 break;
548 udelay(10);
549 }
550
551 sdma_process_event(sde, sdma_event_e25_hw_clean_up_done);
552 }
553
get_txhead(struct sdma_engine * sde)554 static inline struct sdma_txreq *get_txhead(struct sdma_engine *sde)
555 {
556 smp_read_barrier_depends(); /* see sdma_update_tail() */
557 return sde->tx_ring[sde->tx_head & sde->sdma_mask];
558 }
559
560 /*
561 * flush ring for recovery
562 */
sdma_flush_descq(struct sdma_engine * sde)563 static void sdma_flush_descq(struct sdma_engine *sde)
564 {
565 u16 head, tail;
566 int progress = 0;
567 struct sdma_txreq *txp = get_txhead(sde);
568
569 /* The reason for some of the complexity of this code is that
570 * not all descriptors have corresponding txps. So, we have to
571 * be able to skip over descs until we wander into the range of
572 * the next txp on the list.
573 */
574 head = sde->descq_head & sde->sdma_mask;
575 tail = sde->descq_tail & sde->sdma_mask;
576 while (head != tail) {
577 /* advance head, wrap if needed */
578 head = ++sde->descq_head & sde->sdma_mask;
579 /* if now past this txp's descs, do the callback */
580 if (txp && txp->next_descq_idx == head) {
581 /* remove from list */
582 sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL;
583 complete_tx(sde, txp, SDMA_TXREQ_S_ABORTED);
584 trace_hfi1_sdma_progress(sde, head, tail, txp);
585 txp = get_txhead(sde);
586 }
587 progress++;
588 }
589 if (progress)
590 sdma_desc_avail(sde, sdma_descq_freecnt(sde));
591 }
592
sdma_sw_clean_up_task(unsigned long opaque)593 static void sdma_sw_clean_up_task(unsigned long opaque)
594 {
595 struct sdma_engine *sde = (struct sdma_engine *)opaque;
596 unsigned long flags;
597
598 spin_lock_irqsave(&sde->tail_lock, flags);
599 write_seqlock(&sde->head_lock);
600
601 /*
602 * At this point, the following should always be true:
603 * - We are halted, so no more descriptors are getting retired.
604 * - We are not running, so no one is submitting new work.
605 * - Only we can send the e40_sw_cleaned, so we can't start
606 * running again until we say so. So, the active list and
607 * descq are ours to play with.
608 */
609
610 /*
611 * In the error clean up sequence, software clean must be called
612 * before the hardware clean so we can use the hardware head in
613 * the progress routine. A hardware clean or SPC unfreeze will
614 * reset the hardware head.
615 *
616 * Process all retired requests. The progress routine will use the
617 * latest physical hardware head - we are not running so speed does
618 * not matter.
619 */
620 sdma_make_progress(sde, 0);
621
622 sdma_flush(sde);
623
624 /*
625 * Reset our notion of head and tail.
626 * Note that the HW registers have been reset via an earlier
627 * clean up.
628 */
629 sde->descq_tail = 0;
630 sde->descq_head = 0;
631 sde->desc_avail = sdma_descq_freecnt(sde);
632 *sde->head_dma = 0;
633
634 __sdma_process_event(sde, sdma_event_e40_sw_cleaned);
635
636 write_sequnlock(&sde->head_lock);
637 spin_unlock_irqrestore(&sde->tail_lock, flags);
638 }
639
sdma_sw_tear_down(struct sdma_engine * sde)640 static void sdma_sw_tear_down(struct sdma_engine *sde)
641 {
642 struct sdma_state *ss = &sde->state;
643
644 /* Releasing this reference means the state machine has stopped. */
645 sdma_put(ss);
646
647 /* stop waiting for all unfreeze events to complete */
648 atomic_set(&sde->dd->sdma_unfreeze_count, -1);
649 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
650 }
651
sdma_start_hw_clean_up(struct sdma_engine * sde)652 static void sdma_start_hw_clean_up(struct sdma_engine *sde)
653 {
654 tasklet_hi_schedule(&sde->sdma_hw_clean_up_task);
655 }
656
sdma_set_state(struct sdma_engine * sde,enum sdma_states next_state)657 static void sdma_set_state(struct sdma_engine *sde,
658 enum sdma_states next_state)
659 {
660 struct sdma_state *ss = &sde->state;
661 const struct sdma_set_state_action *action = sdma_action_table;
662 unsigned op = 0;
663
664 trace_hfi1_sdma_state(
665 sde,
666 sdma_state_names[ss->current_state],
667 sdma_state_names[next_state]);
668
669 /* debugging bookkeeping */
670 ss->previous_state = ss->current_state;
671 ss->previous_op = ss->current_op;
672 ss->current_state = next_state;
673
674 if (ss->previous_state != sdma_state_s99_running &&
675 next_state == sdma_state_s99_running)
676 sdma_flush(sde);
677
678 if (action[next_state].op_enable)
679 op |= SDMA_SENDCTRL_OP_ENABLE;
680
681 if (action[next_state].op_intenable)
682 op |= SDMA_SENDCTRL_OP_INTENABLE;
683
684 if (action[next_state].op_halt)
685 op |= SDMA_SENDCTRL_OP_HALT;
686
687 if (action[next_state].op_cleanup)
688 op |= SDMA_SENDCTRL_OP_CLEANUP;
689
690 if (action[next_state].go_s99_running_tofalse)
691 ss->go_s99_running = 0;
692
693 if (action[next_state].go_s99_running_totrue)
694 ss->go_s99_running = 1;
695
696 ss->current_op = op;
697 sdma_sendctrl(sde, ss->current_op);
698 }
699
700 /**
701 * sdma_get_descq_cnt() - called when device probed
702 *
703 * Return a validated descq count.
704 *
705 * This is currently only used in the verbs initialization to build the tx
706 * list.
707 *
708 * This will probably be deleted in favor of a more scalable approach to
709 * alloc tx's.
710 *
711 */
sdma_get_descq_cnt(void)712 u16 sdma_get_descq_cnt(void)
713 {
714 u16 count = sdma_descq_cnt;
715
716 if (!count)
717 return SDMA_DESCQ_CNT;
718 /* count must be a power of 2 greater than 64 and less than
719 * 32768. Otherwise return default.
720 */
721 if (!is_power_of_2(count))
722 return SDMA_DESCQ_CNT;
723 if (count < 64 || count > 32768)
724 return SDMA_DESCQ_CNT;
725 return count;
726 }
727
728 /**
729 * sdma_engine_get_vl() - return vl for a given sdma engine
730 * @sde: sdma engine
731 *
732 * This function returns the vl mapped to a given engine, or an error if
733 * the mapping can't be found. The mapping fields are protected by RCU.
734 */
sdma_engine_get_vl(struct sdma_engine * sde)735 int sdma_engine_get_vl(struct sdma_engine *sde)
736 {
737 struct hfi1_devdata *dd = sde->dd;
738 struct sdma_vl_map *m;
739 u8 vl;
740
741 if (sde->this_idx >= TXE_NUM_SDMA_ENGINES)
742 return -EINVAL;
743
744 rcu_read_lock();
745 m = rcu_dereference(dd->sdma_map);
746 if (unlikely(!m)) {
747 rcu_read_unlock();
748 return -EINVAL;
749 }
750 vl = m->engine_to_vl[sde->this_idx];
751 rcu_read_unlock();
752
753 return vl;
754 }
755
756 /**
757 * sdma_select_engine_vl() - select sdma engine
758 * @dd: devdata
759 * @selector: a spreading factor
760 * @vl: this vl
761 *
762 *
763 * This function returns an engine based on the selector and a vl. The
764 * mapping fields are protected by RCU.
765 */
sdma_select_engine_vl(struct hfi1_devdata * dd,u32 selector,u8 vl)766 struct sdma_engine *sdma_select_engine_vl(
767 struct hfi1_devdata *dd,
768 u32 selector,
769 u8 vl)
770 {
771 struct sdma_vl_map *m;
772 struct sdma_map_elem *e;
773 struct sdma_engine *rval;
774
775 /* NOTE This should only happen if SC->VL changed after the initial
776 * checks on the QP/AH
777 * Default will return engine 0 below
778 */
779 if (vl >= num_vls) {
780 rval = NULL;
781 goto done;
782 }
783
784 rcu_read_lock();
785 m = rcu_dereference(dd->sdma_map);
786 if (unlikely(!m)) {
787 rcu_read_unlock();
788 return &dd->per_sdma[0];
789 }
790 e = m->map[vl & m->mask];
791 rval = e->sde[selector & e->mask];
792 rcu_read_unlock();
793
794 done:
795 rval = !rval ? &dd->per_sdma[0] : rval;
796 trace_hfi1_sdma_engine_select(dd, selector, vl, rval->this_idx);
797 return rval;
798 }
799
800 /**
801 * sdma_select_engine_sc() - select sdma engine
802 * @dd: devdata
803 * @selector: a spreading factor
804 * @sc5: the 5 bit sc
805 *
806 *
807 * This function returns an engine based on the selector and an sc.
808 */
sdma_select_engine_sc(struct hfi1_devdata * dd,u32 selector,u8 sc5)809 struct sdma_engine *sdma_select_engine_sc(
810 struct hfi1_devdata *dd,
811 u32 selector,
812 u8 sc5)
813 {
814 u8 vl = sc_to_vlt(dd, sc5);
815
816 return sdma_select_engine_vl(dd, selector, vl);
817 }
818
819 struct sdma_rht_map_elem {
820 u32 mask;
821 u8 ctr;
822 struct sdma_engine *sde[0];
823 };
824
825 struct sdma_rht_node {
826 unsigned long cpu_id;
827 struct sdma_rht_map_elem *map[HFI1_MAX_VLS_SUPPORTED];
828 struct rhash_head node;
829 };
830
831 #define NR_CPUS_HINT 192
832
833 static const struct rhashtable_params sdma_rht_params = {
834 .nelem_hint = NR_CPUS_HINT,
835 .head_offset = offsetof(struct sdma_rht_node, node),
836 .key_offset = offsetof(struct sdma_rht_node, cpu_id),
837 .key_len = FIELD_SIZEOF(struct sdma_rht_node, cpu_id),
838 .max_size = NR_CPUS,
839 .min_size = 8,
840 .automatic_shrinking = true,
841 };
842
843 /*
844 * sdma_select_user_engine() - select sdma engine based on user setup
845 * @dd: devdata
846 * @selector: a spreading factor
847 * @vl: this vl
848 *
849 * This function returns an sdma engine for a user sdma request.
850 * User defined sdma engine affinity setting is honored when applicable,
851 * otherwise system default sdma engine mapping is used. To ensure correct
852 * ordering, the mapping from <selector, vl> to sde must remain unchanged.
853 */
sdma_select_user_engine(struct hfi1_devdata * dd,u32 selector,u8 vl)854 struct sdma_engine *sdma_select_user_engine(struct hfi1_devdata *dd,
855 u32 selector, u8 vl)
856 {
857 struct sdma_rht_node *rht_node;
858 struct sdma_engine *sde = NULL;
859 const struct cpumask *current_mask = ¤t->cpus_allowed;
860 unsigned long cpu_id;
861
862 /*
863 * To ensure that always the same sdma engine(s) will be
864 * selected make sure the process is pinned to this CPU only.
865 */
866 if (cpumask_weight(current_mask) != 1)
867 goto out;
868
869 cpu_id = smp_processor_id();
870 rcu_read_lock();
871 rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpu_id,
872 sdma_rht_params);
873
874 if (rht_node && rht_node->map[vl]) {
875 struct sdma_rht_map_elem *map = rht_node->map[vl];
876
877 sde = map->sde[selector & map->mask];
878 }
879 rcu_read_unlock();
880
881 if (sde)
882 return sde;
883
884 out:
885 return sdma_select_engine_vl(dd, selector, vl);
886 }
887
sdma_populate_sde_map(struct sdma_rht_map_elem * map)888 static void sdma_populate_sde_map(struct sdma_rht_map_elem *map)
889 {
890 int i;
891
892 for (i = 0; i < roundup_pow_of_two(map->ctr ? : 1) - map->ctr; i++)
893 map->sde[map->ctr + i] = map->sde[i];
894 }
895
sdma_cleanup_sde_map(struct sdma_rht_map_elem * map,struct sdma_engine * sde)896 static void sdma_cleanup_sde_map(struct sdma_rht_map_elem *map,
897 struct sdma_engine *sde)
898 {
899 unsigned int i, pow;
900
901 /* only need to check the first ctr entries for a match */
902 for (i = 0; i < map->ctr; i++) {
903 if (map->sde[i] == sde) {
904 memmove(&map->sde[i], &map->sde[i + 1],
905 (map->ctr - i - 1) * sizeof(map->sde[0]));
906 map->ctr--;
907 pow = roundup_pow_of_two(map->ctr ? : 1);
908 map->mask = pow - 1;
909 sdma_populate_sde_map(map);
910 break;
911 }
912 }
913 }
914
915 /*
916 * Prevents concurrent reads and writes of the sdma engine cpu_mask
917 */
918 static DEFINE_MUTEX(process_to_sde_mutex);
919
sdma_set_cpu_to_sde_map(struct sdma_engine * sde,const char * buf,size_t count)920 ssize_t sdma_set_cpu_to_sde_map(struct sdma_engine *sde, const char *buf,
921 size_t count)
922 {
923 struct hfi1_devdata *dd = sde->dd;
924 cpumask_var_t mask, new_mask;
925 unsigned long cpu;
926 int ret, vl, sz;
927
928 vl = sdma_engine_get_vl(sde);
929 if (unlikely(vl < 0))
930 return -EINVAL;
931
932 ret = zalloc_cpumask_var(&mask, GFP_KERNEL);
933 if (!ret)
934 return -ENOMEM;
935
936 ret = zalloc_cpumask_var(&new_mask, GFP_KERNEL);
937 if (!ret) {
938 free_cpumask_var(mask);
939 return -ENOMEM;
940 }
941 ret = cpulist_parse(buf, mask);
942 if (ret)
943 goto out_free;
944
945 if (!cpumask_subset(mask, cpu_online_mask)) {
946 dd_dev_warn(sde->dd, "Invalid CPU mask\n");
947 ret = -EINVAL;
948 goto out_free;
949 }
950
951 sz = sizeof(struct sdma_rht_map_elem) +
952 (TXE_NUM_SDMA_ENGINES * sizeof(struct sdma_engine *));
953
954 mutex_lock(&process_to_sde_mutex);
955
956 for_each_cpu(cpu, mask) {
957 struct sdma_rht_node *rht_node;
958
959 /* Check if we have this already mapped */
960 if (cpumask_test_cpu(cpu, &sde->cpu_mask)) {
961 cpumask_set_cpu(cpu, new_mask);
962 continue;
963 }
964
965 if (vl >= ARRAY_SIZE(rht_node->map)) {
966 ret = -EINVAL;
967 goto out;
968 }
969
970 rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpu,
971 sdma_rht_params);
972 if (!rht_node) {
973 rht_node = kzalloc(sizeof(*rht_node), GFP_KERNEL);
974 if (!rht_node) {
975 ret = -ENOMEM;
976 goto out;
977 }
978
979 rht_node->map[vl] = kzalloc(sz, GFP_KERNEL);
980 if (!rht_node->map[vl]) {
981 kfree(rht_node);
982 ret = -ENOMEM;
983 goto out;
984 }
985 rht_node->cpu_id = cpu;
986 rht_node->map[vl]->mask = 0;
987 rht_node->map[vl]->ctr = 1;
988 rht_node->map[vl]->sde[0] = sde;
989
990 ret = rhashtable_insert_fast(dd->sdma_rht,
991 &rht_node->node,
992 sdma_rht_params);
993 if (ret) {
994 kfree(rht_node->map[vl]);
995 kfree(rht_node);
996 dd_dev_err(sde->dd, "Failed to set process to sde affinity for cpu %lu\n",
997 cpu);
998 goto out;
999 }
1000
1001 } else {
1002 int ctr, pow;
1003
1004 /* Add new user mappings */
1005 if (!rht_node->map[vl])
1006 rht_node->map[vl] = kzalloc(sz, GFP_KERNEL);
1007
1008 if (!rht_node->map[vl]) {
1009 ret = -ENOMEM;
1010 goto out;
1011 }
1012
1013 rht_node->map[vl]->ctr++;
1014 ctr = rht_node->map[vl]->ctr;
1015 rht_node->map[vl]->sde[ctr - 1] = sde;
1016 pow = roundup_pow_of_two(ctr);
1017 rht_node->map[vl]->mask = pow - 1;
1018
1019 /* Populate the sde map table */
1020 sdma_populate_sde_map(rht_node->map[vl]);
1021 }
1022 cpumask_set_cpu(cpu, new_mask);
1023 }
1024
1025 /* Clean up old mappings */
1026 for_each_cpu(cpu, cpu_online_mask) {
1027 struct sdma_rht_node *rht_node;
1028
1029 /* Don't cleanup sdes that are set in the new mask */
1030 if (cpumask_test_cpu(cpu, mask))
1031 continue;
1032
1033 rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpu,
1034 sdma_rht_params);
1035 if (rht_node) {
1036 bool empty = true;
1037 int i;
1038
1039 /* Remove mappings for old sde */
1040 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++)
1041 if (rht_node->map[i])
1042 sdma_cleanup_sde_map(rht_node->map[i],
1043 sde);
1044
1045 /* Free empty hash table entries */
1046 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) {
1047 if (!rht_node->map[i])
1048 continue;
1049
1050 if (rht_node->map[i]->ctr) {
1051 empty = false;
1052 break;
1053 }
1054 }
1055
1056 if (empty) {
1057 ret = rhashtable_remove_fast(dd->sdma_rht,
1058 &rht_node->node,
1059 sdma_rht_params);
1060 WARN_ON(ret);
1061
1062 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++)
1063 kfree(rht_node->map[i]);
1064
1065 kfree(rht_node);
1066 }
1067 }
1068 }
1069
1070 cpumask_copy(&sde->cpu_mask, new_mask);
1071 out:
1072 mutex_unlock(&process_to_sde_mutex);
1073 out_free:
1074 free_cpumask_var(mask);
1075 free_cpumask_var(new_mask);
1076 return ret ? : strnlen(buf, PAGE_SIZE);
1077 }
1078
sdma_get_cpu_to_sde_map(struct sdma_engine * sde,char * buf)1079 ssize_t sdma_get_cpu_to_sde_map(struct sdma_engine *sde, char *buf)
1080 {
1081 mutex_lock(&process_to_sde_mutex);
1082 if (cpumask_empty(&sde->cpu_mask))
1083 snprintf(buf, PAGE_SIZE, "%s\n", "empty");
1084 else
1085 cpumap_print_to_pagebuf(true, buf, &sde->cpu_mask);
1086 mutex_unlock(&process_to_sde_mutex);
1087 return strnlen(buf, PAGE_SIZE);
1088 }
1089
sdma_rht_free(void * ptr,void * arg)1090 static void sdma_rht_free(void *ptr, void *arg)
1091 {
1092 struct sdma_rht_node *rht_node = ptr;
1093 int i;
1094
1095 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++)
1096 kfree(rht_node->map[i]);
1097
1098 kfree(rht_node);
1099 }
1100
1101 /**
1102 * sdma_seqfile_dump_cpu_list() - debugfs dump the cpu to sdma mappings
1103 * @s: seq file
1104 * @dd: hfi1_devdata
1105 * @cpuid: cpu id
1106 *
1107 * This routine dumps the process to sde mappings per cpu
1108 */
sdma_seqfile_dump_cpu_list(struct seq_file * s,struct hfi1_devdata * dd,unsigned long cpuid)1109 void sdma_seqfile_dump_cpu_list(struct seq_file *s,
1110 struct hfi1_devdata *dd,
1111 unsigned long cpuid)
1112 {
1113 struct sdma_rht_node *rht_node;
1114 int i, j;
1115
1116 rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpuid,
1117 sdma_rht_params);
1118 if (!rht_node)
1119 return;
1120
1121 seq_printf(s, "cpu%3lu: ", cpuid);
1122 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) {
1123 if (!rht_node->map[i] || !rht_node->map[i]->ctr)
1124 continue;
1125
1126 seq_printf(s, " vl%d: [", i);
1127
1128 for (j = 0; j < rht_node->map[i]->ctr; j++) {
1129 if (!rht_node->map[i]->sde[j])
1130 continue;
1131
1132 if (j > 0)
1133 seq_puts(s, ",");
1134
1135 seq_printf(s, " sdma%2d",
1136 rht_node->map[i]->sde[j]->this_idx);
1137 }
1138 seq_puts(s, " ]");
1139 }
1140
1141 seq_puts(s, "\n");
1142 }
1143
1144 /*
1145 * Free the indicated map struct
1146 */
sdma_map_free(struct sdma_vl_map * m)1147 static void sdma_map_free(struct sdma_vl_map *m)
1148 {
1149 int i;
1150
1151 for (i = 0; m && i < m->actual_vls; i++)
1152 kfree(m->map[i]);
1153 kfree(m);
1154 }
1155
1156 /*
1157 * Handle RCU callback
1158 */
sdma_map_rcu_callback(struct rcu_head * list)1159 static void sdma_map_rcu_callback(struct rcu_head *list)
1160 {
1161 struct sdma_vl_map *m = container_of(list, struct sdma_vl_map, list);
1162
1163 sdma_map_free(m);
1164 }
1165
1166 /**
1167 * sdma_map_init - called when # vls change
1168 * @dd: hfi1_devdata
1169 * @port: port number
1170 * @num_vls: number of vls
1171 * @vl_engines: per vl engine mapping (optional)
1172 *
1173 * This routine changes the mapping based on the number of vls.
1174 *
1175 * vl_engines is used to specify a non-uniform vl/engine loading. NULL
1176 * implies auto computing the loading and giving each VLs a uniform
1177 * distribution of engines per VL.
1178 *
1179 * The auto algorithm computes the sde_per_vl and the number of extra
1180 * engines. Any extra engines are added from the last VL on down.
1181 *
1182 * rcu locking is used here to control access to the mapping fields.
1183 *
1184 * If either the num_vls or num_sdma are non-power of 2, the array sizes
1185 * in the struct sdma_vl_map and the struct sdma_map_elem are rounded
1186 * up to the next highest power of 2 and the first entry is reused
1187 * in a round robin fashion.
1188 *
1189 * If an error occurs the map change is not done and the mapping is
1190 * not changed.
1191 *
1192 */
sdma_map_init(struct hfi1_devdata * dd,u8 port,u8 num_vls,u8 * vl_engines)1193 int sdma_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls, u8 *vl_engines)
1194 {
1195 int i, j;
1196 int extra, sde_per_vl;
1197 int engine = 0;
1198 u8 lvl_engines[OPA_MAX_VLS];
1199 struct sdma_vl_map *oldmap, *newmap;
1200
1201 if (!(dd->flags & HFI1_HAS_SEND_DMA))
1202 return 0;
1203
1204 if (!vl_engines) {
1205 /* truncate divide */
1206 sde_per_vl = dd->num_sdma / num_vls;
1207 /* extras */
1208 extra = dd->num_sdma % num_vls;
1209 vl_engines = lvl_engines;
1210 /* add extras from last vl down */
1211 for (i = num_vls - 1; i >= 0; i--, extra--)
1212 vl_engines[i] = sde_per_vl + (extra > 0 ? 1 : 0);
1213 }
1214 /* build new map */
1215 newmap = kzalloc(
1216 sizeof(struct sdma_vl_map) +
1217 roundup_pow_of_two(num_vls) *
1218 sizeof(struct sdma_map_elem *),
1219 GFP_KERNEL);
1220 if (!newmap)
1221 goto bail;
1222 newmap->actual_vls = num_vls;
1223 newmap->vls = roundup_pow_of_two(num_vls);
1224 newmap->mask = (1 << ilog2(newmap->vls)) - 1;
1225 /* initialize back-map */
1226 for (i = 0; i < TXE_NUM_SDMA_ENGINES; i++)
1227 newmap->engine_to_vl[i] = -1;
1228 for (i = 0; i < newmap->vls; i++) {
1229 /* save for wrap around */
1230 int first_engine = engine;
1231
1232 if (i < newmap->actual_vls) {
1233 int sz = roundup_pow_of_two(vl_engines[i]);
1234
1235 /* only allocate once */
1236 newmap->map[i] = kzalloc(
1237 sizeof(struct sdma_map_elem) +
1238 sz * sizeof(struct sdma_engine *),
1239 GFP_KERNEL);
1240 if (!newmap->map[i])
1241 goto bail;
1242 newmap->map[i]->mask = (1 << ilog2(sz)) - 1;
1243 /* assign engines */
1244 for (j = 0; j < sz; j++) {
1245 newmap->map[i]->sde[j] =
1246 &dd->per_sdma[engine];
1247 if (++engine >= first_engine + vl_engines[i])
1248 /* wrap back to first engine */
1249 engine = first_engine;
1250 }
1251 /* assign back-map */
1252 for (j = 0; j < vl_engines[i]; j++)
1253 newmap->engine_to_vl[first_engine + j] = i;
1254 } else {
1255 /* just re-use entry without allocating */
1256 newmap->map[i] = newmap->map[i % num_vls];
1257 }
1258 engine = first_engine + vl_engines[i];
1259 }
1260 /* newmap in hand, save old map */
1261 spin_lock_irq(&dd->sde_map_lock);
1262 oldmap = rcu_dereference_protected(dd->sdma_map,
1263 lockdep_is_held(&dd->sde_map_lock));
1264
1265 /* publish newmap */
1266 rcu_assign_pointer(dd->sdma_map, newmap);
1267
1268 spin_unlock_irq(&dd->sde_map_lock);
1269 /* success, free any old map after grace period */
1270 if (oldmap)
1271 call_rcu(&oldmap->list, sdma_map_rcu_callback);
1272 return 0;
1273 bail:
1274 /* free any partial allocation */
1275 sdma_map_free(newmap);
1276 return -ENOMEM;
1277 }
1278
1279 /*
1280 * Clean up allocated memory.
1281 *
1282 * This routine is can be called regardless of the success of sdma_init()
1283 *
1284 */
sdma_clean(struct hfi1_devdata * dd,size_t num_engines)1285 static void sdma_clean(struct hfi1_devdata *dd, size_t num_engines)
1286 {
1287 size_t i;
1288 struct sdma_engine *sde;
1289
1290 if (dd->sdma_pad_dma) {
1291 dma_free_coherent(&dd->pcidev->dev, 4,
1292 (void *)dd->sdma_pad_dma,
1293 dd->sdma_pad_phys);
1294 dd->sdma_pad_dma = NULL;
1295 dd->sdma_pad_phys = 0;
1296 }
1297 if (dd->sdma_heads_dma) {
1298 dma_free_coherent(&dd->pcidev->dev, dd->sdma_heads_size,
1299 (void *)dd->sdma_heads_dma,
1300 dd->sdma_heads_phys);
1301 dd->sdma_heads_dma = NULL;
1302 dd->sdma_heads_phys = 0;
1303 }
1304 for (i = 0; dd->per_sdma && i < num_engines; ++i) {
1305 sde = &dd->per_sdma[i];
1306
1307 sde->head_dma = NULL;
1308 sde->head_phys = 0;
1309
1310 if (sde->descq) {
1311 dma_free_coherent(
1312 &dd->pcidev->dev,
1313 sde->descq_cnt * sizeof(u64[2]),
1314 sde->descq,
1315 sde->descq_phys
1316 );
1317 sde->descq = NULL;
1318 sde->descq_phys = 0;
1319 }
1320 kvfree(sde->tx_ring);
1321 sde->tx_ring = NULL;
1322 }
1323 spin_lock_irq(&dd->sde_map_lock);
1324 sdma_map_free(rcu_access_pointer(dd->sdma_map));
1325 RCU_INIT_POINTER(dd->sdma_map, NULL);
1326 spin_unlock_irq(&dd->sde_map_lock);
1327 synchronize_rcu();
1328 kfree(dd->per_sdma);
1329 dd->per_sdma = NULL;
1330
1331 if (dd->sdma_rht) {
1332 rhashtable_free_and_destroy(dd->sdma_rht, sdma_rht_free, NULL);
1333 kfree(dd->sdma_rht);
1334 dd->sdma_rht = NULL;
1335 }
1336 }
1337
1338 /**
1339 * sdma_init() - called when device probed
1340 * @dd: hfi1_devdata
1341 * @port: port number (currently only zero)
1342 *
1343 * Initializes each sde and its csrs.
1344 * Interrupts are not required to be enabled.
1345 *
1346 * Returns:
1347 * 0 - success, -errno on failure
1348 */
sdma_init(struct hfi1_devdata * dd,u8 port)1349 int sdma_init(struct hfi1_devdata *dd, u8 port)
1350 {
1351 unsigned this_idx;
1352 struct sdma_engine *sde;
1353 struct rhashtable *tmp_sdma_rht;
1354 u16 descq_cnt;
1355 void *curr_head;
1356 struct hfi1_pportdata *ppd = dd->pport + port;
1357 u32 per_sdma_credits;
1358 uint idle_cnt = sdma_idle_cnt;
1359 size_t num_engines = dd->chip_sdma_engines;
1360 int ret = -ENOMEM;
1361
1362 if (!HFI1_CAP_IS_KSET(SDMA)) {
1363 HFI1_CAP_CLEAR(SDMA_AHG);
1364 return 0;
1365 }
1366 if (mod_num_sdma &&
1367 /* can't exceed chip support */
1368 mod_num_sdma <= dd->chip_sdma_engines &&
1369 /* count must be >= vls */
1370 mod_num_sdma >= num_vls)
1371 num_engines = mod_num_sdma;
1372
1373 dd_dev_info(dd, "SDMA mod_num_sdma: %u\n", mod_num_sdma);
1374 dd_dev_info(dd, "SDMA chip_sdma_engines: %u\n", dd->chip_sdma_engines);
1375 dd_dev_info(dd, "SDMA chip_sdma_mem_size: %u\n",
1376 dd->chip_sdma_mem_size);
1377
1378 per_sdma_credits =
1379 dd->chip_sdma_mem_size / (num_engines * SDMA_BLOCK_SIZE);
1380
1381 /* set up freeze waitqueue */
1382 init_waitqueue_head(&dd->sdma_unfreeze_wq);
1383 atomic_set(&dd->sdma_unfreeze_count, 0);
1384
1385 descq_cnt = sdma_get_descq_cnt();
1386 dd_dev_info(dd, "SDMA engines %zu descq_cnt %u\n",
1387 num_engines, descq_cnt);
1388
1389 /* alloc memory for array of send engines */
1390 dd->per_sdma = kcalloc(num_engines, sizeof(*dd->per_sdma), GFP_KERNEL);
1391 if (!dd->per_sdma)
1392 return ret;
1393
1394 idle_cnt = ns_to_cclock(dd, idle_cnt);
1395 if (!sdma_desct_intr)
1396 sdma_desct_intr = SDMA_DESC_INTR;
1397
1398 /* Allocate memory for SendDMA descriptor FIFOs */
1399 for (this_idx = 0; this_idx < num_engines; ++this_idx) {
1400 sde = &dd->per_sdma[this_idx];
1401 sde->dd = dd;
1402 sde->ppd = ppd;
1403 sde->this_idx = this_idx;
1404 sde->descq_cnt = descq_cnt;
1405 sde->desc_avail = sdma_descq_freecnt(sde);
1406 sde->sdma_shift = ilog2(descq_cnt);
1407 sde->sdma_mask = (1 << sde->sdma_shift) - 1;
1408
1409 /* Create a mask specifically for each interrupt source */
1410 sde->int_mask = (u64)1 << (0 * TXE_NUM_SDMA_ENGINES +
1411 this_idx);
1412 sde->progress_mask = (u64)1 << (1 * TXE_NUM_SDMA_ENGINES +
1413 this_idx);
1414 sde->idle_mask = (u64)1 << (2 * TXE_NUM_SDMA_ENGINES +
1415 this_idx);
1416 /* Create a combined mask to cover all 3 interrupt sources */
1417 sde->imask = sde->int_mask | sde->progress_mask |
1418 sde->idle_mask;
1419
1420 spin_lock_init(&sde->tail_lock);
1421 seqlock_init(&sde->head_lock);
1422 spin_lock_init(&sde->senddmactrl_lock);
1423 spin_lock_init(&sde->flushlist_lock);
1424 /* insure there is always a zero bit */
1425 sde->ahg_bits = 0xfffffffe00000000ULL;
1426
1427 sdma_set_state(sde, sdma_state_s00_hw_down);
1428
1429 /* set up reference counting */
1430 kref_init(&sde->state.kref);
1431 init_completion(&sde->state.comp);
1432
1433 INIT_LIST_HEAD(&sde->flushlist);
1434 INIT_LIST_HEAD(&sde->dmawait);
1435
1436 sde->tail_csr =
1437 get_kctxt_csr_addr(dd, this_idx, SD(TAIL));
1438
1439 if (idle_cnt)
1440 dd->default_desc1 =
1441 SDMA_DESC1_HEAD_TO_HOST_FLAG;
1442 else
1443 dd->default_desc1 =
1444 SDMA_DESC1_INT_REQ_FLAG;
1445
1446 tasklet_init(&sde->sdma_hw_clean_up_task, sdma_hw_clean_up_task,
1447 (unsigned long)sde);
1448
1449 tasklet_init(&sde->sdma_sw_clean_up_task, sdma_sw_clean_up_task,
1450 (unsigned long)sde);
1451 INIT_WORK(&sde->err_halt_worker, sdma_err_halt_wait);
1452 INIT_WORK(&sde->flush_worker, sdma_field_flush);
1453
1454 sde->progress_check_head = 0;
1455
1456 setup_timer(&sde->err_progress_check_timer,
1457 sdma_err_progress_check, (unsigned long)sde);
1458
1459 sde->descq = dma_zalloc_coherent(
1460 &dd->pcidev->dev,
1461 descq_cnt * sizeof(u64[2]),
1462 &sde->descq_phys,
1463 GFP_KERNEL
1464 );
1465 if (!sde->descq)
1466 goto bail;
1467 sde->tx_ring =
1468 kcalloc(descq_cnt, sizeof(struct sdma_txreq *),
1469 GFP_KERNEL);
1470 if (!sde->tx_ring)
1471 sde->tx_ring =
1472 vzalloc(
1473 sizeof(struct sdma_txreq *) *
1474 descq_cnt);
1475 if (!sde->tx_ring)
1476 goto bail;
1477 }
1478
1479 dd->sdma_heads_size = L1_CACHE_BYTES * num_engines;
1480 /* Allocate memory for DMA of head registers to memory */
1481 dd->sdma_heads_dma = dma_zalloc_coherent(
1482 &dd->pcidev->dev,
1483 dd->sdma_heads_size,
1484 &dd->sdma_heads_phys,
1485 GFP_KERNEL
1486 );
1487 if (!dd->sdma_heads_dma) {
1488 dd_dev_err(dd, "failed to allocate SendDMA head memory\n");
1489 goto bail;
1490 }
1491
1492 /* Allocate memory for pad */
1493 dd->sdma_pad_dma = dma_zalloc_coherent(
1494 &dd->pcidev->dev,
1495 sizeof(u32),
1496 &dd->sdma_pad_phys,
1497 GFP_KERNEL
1498 );
1499 if (!dd->sdma_pad_dma) {
1500 dd_dev_err(dd, "failed to allocate SendDMA pad memory\n");
1501 goto bail;
1502 }
1503
1504 /* assign each engine to different cacheline and init registers */
1505 curr_head = (void *)dd->sdma_heads_dma;
1506 for (this_idx = 0; this_idx < num_engines; ++this_idx) {
1507 unsigned long phys_offset;
1508
1509 sde = &dd->per_sdma[this_idx];
1510
1511 sde->head_dma = curr_head;
1512 curr_head += L1_CACHE_BYTES;
1513 phys_offset = (unsigned long)sde->head_dma -
1514 (unsigned long)dd->sdma_heads_dma;
1515 sde->head_phys = dd->sdma_heads_phys + phys_offset;
1516 init_sdma_regs(sde, per_sdma_credits, idle_cnt);
1517 }
1518 dd->flags |= HFI1_HAS_SEND_DMA;
1519 dd->flags |= idle_cnt ? HFI1_HAS_SDMA_TIMEOUT : 0;
1520 dd->num_sdma = num_engines;
1521 ret = sdma_map_init(dd, port, ppd->vls_operational, NULL);
1522 if (ret < 0)
1523 goto bail;
1524
1525 tmp_sdma_rht = kzalloc(sizeof(*tmp_sdma_rht), GFP_KERNEL);
1526 if (!tmp_sdma_rht) {
1527 ret = -ENOMEM;
1528 goto bail;
1529 }
1530
1531 ret = rhashtable_init(tmp_sdma_rht, &sdma_rht_params);
1532 if (ret < 0) {
1533 kfree(tmp_sdma_rht);
1534 goto bail;
1535 }
1536
1537 dd->sdma_rht = tmp_sdma_rht;
1538
1539 dd_dev_info(dd, "SDMA num_sdma: %u\n", dd->num_sdma);
1540 return 0;
1541
1542 bail:
1543 sdma_clean(dd, num_engines);
1544 return ret;
1545 }
1546
1547 /**
1548 * sdma_all_running() - called when the link goes up
1549 * @dd: hfi1_devdata
1550 *
1551 * This routine moves all engines to the running state.
1552 */
sdma_all_running(struct hfi1_devdata * dd)1553 void sdma_all_running(struct hfi1_devdata *dd)
1554 {
1555 struct sdma_engine *sde;
1556 unsigned int i;
1557
1558 /* move all engines to running */
1559 for (i = 0; i < dd->num_sdma; ++i) {
1560 sde = &dd->per_sdma[i];
1561 sdma_process_event(sde, sdma_event_e30_go_running);
1562 }
1563 }
1564
1565 /**
1566 * sdma_all_idle() - called when the link goes down
1567 * @dd: hfi1_devdata
1568 *
1569 * This routine moves all engines to the idle state.
1570 */
sdma_all_idle(struct hfi1_devdata * dd)1571 void sdma_all_idle(struct hfi1_devdata *dd)
1572 {
1573 struct sdma_engine *sde;
1574 unsigned int i;
1575
1576 /* idle all engines */
1577 for (i = 0; i < dd->num_sdma; ++i) {
1578 sde = &dd->per_sdma[i];
1579 sdma_process_event(sde, sdma_event_e70_go_idle);
1580 }
1581 }
1582
1583 /**
1584 * sdma_start() - called to kick off state processing for all engines
1585 * @dd: hfi1_devdata
1586 *
1587 * This routine is for kicking off the state processing for all required
1588 * sdma engines. Interrupts need to be working at this point.
1589 *
1590 */
sdma_start(struct hfi1_devdata * dd)1591 void sdma_start(struct hfi1_devdata *dd)
1592 {
1593 unsigned i;
1594 struct sdma_engine *sde;
1595
1596 /* kick off the engines state processing */
1597 for (i = 0; i < dd->num_sdma; ++i) {
1598 sde = &dd->per_sdma[i];
1599 sdma_process_event(sde, sdma_event_e10_go_hw_start);
1600 }
1601 }
1602
1603 /**
1604 * sdma_exit() - used when module is removed
1605 * @dd: hfi1_devdata
1606 */
sdma_exit(struct hfi1_devdata * dd)1607 void sdma_exit(struct hfi1_devdata *dd)
1608 {
1609 unsigned this_idx;
1610 struct sdma_engine *sde;
1611
1612 for (this_idx = 0; dd->per_sdma && this_idx < dd->num_sdma;
1613 ++this_idx) {
1614 sde = &dd->per_sdma[this_idx];
1615 if (!list_empty(&sde->dmawait))
1616 dd_dev_err(dd, "sde %u: dmawait list not empty!\n",
1617 sde->this_idx);
1618 sdma_process_event(sde, sdma_event_e00_go_hw_down);
1619
1620 del_timer_sync(&sde->err_progress_check_timer);
1621
1622 /*
1623 * This waits for the state machine to exit so it is not
1624 * necessary to kill the sdma_sw_clean_up_task to make sure
1625 * it is not running.
1626 */
1627 sdma_finalput(&sde->state);
1628 }
1629 sdma_clean(dd, dd->num_sdma);
1630 }
1631
1632 /*
1633 * unmap the indicated descriptor
1634 */
sdma_unmap_desc(struct hfi1_devdata * dd,struct sdma_desc * descp)1635 static inline void sdma_unmap_desc(
1636 struct hfi1_devdata *dd,
1637 struct sdma_desc *descp)
1638 {
1639 switch (sdma_mapping_type(descp)) {
1640 case SDMA_MAP_SINGLE:
1641 dma_unmap_single(
1642 &dd->pcidev->dev,
1643 sdma_mapping_addr(descp),
1644 sdma_mapping_len(descp),
1645 DMA_TO_DEVICE);
1646 break;
1647 case SDMA_MAP_PAGE:
1648 dma_unmap_page(
1649 &dd->pcidev->dev,
1650 sdma_mapping_addr(descp),
1651 sdma_mapping_len(descp),
1652 DMA_TO_DEVICE);
1653 break;
1654 }
1655 }
1656
1657 /*
1658 * return the mode as indicated by the first
1659 * descriptor in the tx.
1660 */
ahg_mode(struct sdma_txreq * tx)1661 static inline u8 ahg_mode(struct sdma_txreq *tx)
1662 {
1663 return (tx->descp[0].qw[1] & SDMA_DESC1_HEADER_MODE_SMASK)
1664 >> SDMA_DESC1_HEADER_MODE_SHIFT;
1665 }
1666
1667 /**
1668 * __sdma_txclean() - clean tx of mappings, descp *kmalloc's
1669 * @dd: hfi1_devdata for unmapping
1670 * @tx: tx request to clean
1671 *
1672 * This is used in the progress routine to clean the tx or
1673 * by the ULP to toss an in-process tx build.
1674 *
1675 * The code can be called multiple times without issue.
1676 *
1677 */
__sdma_txclean(struct hfi1_devdata * dd,struct sdma_txreq * tx)1678 void __sdma_txclean(
1679 struct hfi1_devdata *dd,
1680 struct sdma_txreq *tx)
1681 {
1682 u16 i;
1683
1684 if (tx->num_desc) {
1685 u8 skip = 0, mode = ahg_mode(tx);
1686
1687 /* unmap first */
1688 sdma_unmap_desc(dd, &tx->descp[0]);
1689 /* determine number of AHG descriptors to skip */
1690 if (mode > SDMA_AHG_APPLY_UPDATE1)
1691 skip = mode >> 1;
1692 for (i = 1 + skip; i < tx->num_desc; i++)
1693 sdma_unmap_desc(dd, &tx->descp[i]);
1694 tx->num_desc = 0;
1695 }
1696 kfree(tx->coalesce_buf);
1697 tx->coalesce_buf = NULL;
1698 /* kmalloc'ed descp */
1699 if (unlikely(tx->desc_limit > ARRAY_SIZE(tx->descs))) {
1700 tx->desc_limit = ARRAY_SIZE(tx->descs);
1701 kfree(tx->descp);
1702 }
1703 }
1704
sdma_gethead(struct sdma_engine * sde)1705 static inline u16 sdma_gethead(struct sdma_engine *sde)
1706 {
1707 struct hfi1_devdata *dd = sde->dd;
1708 int use_dmahead;
1709 u16 hwhead;
1710
1711 #ifdef CONFIG_SDMA_VERBOSITY
1712 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
1713 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
1714 #endif
1715
1716 retry:
1717 use_dmahead = HFI1_CAP_IS_KSET(USE_SDMA_HEAD) && __sdma_running(sde) &&
1718 (dd->flags & HFI1_HAS_SDMA_TIMEOUT);
1719 hwhead = use_dmahead ?
1720 (u16)le64_to_cpu(*sde->head_dma) :
1721 (u16)read_sde_csr(sde, SD(HEAD));
1722
1723 if (unlikely(HFI1_CAP_IS_KSET(SDMA_HEAD_CHECK))) {
1724 u16 cnt;
1725 u16 swtail;
1726 u16 swhead;
1727 int sane;
1728
1729 swhead = sde->descq_head & sde->sdma_mask;
1730 /* this code is really bad for cache line trading */
1731 swtail = ACCESS_ONCE(sde->descq_tail) & sde->sdma_mask;
1732 cnt = sde->descq_cnt;
1733
1734 if (swhead < swtail)
1735 /* not wrapped */
1736 sane = (hwhead >= swhead) & (hwhead <= swtail);
1737 else if (swhead > swtail)
1738 /* wrapped around */
1739 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
1740 (hwhead <= swtail);
1741 else
1742 /* empty */
1743 sane = (hwhead == swhead);
1744
1745 if (unlikely(!sane)) {
1746 dd_dev_err(dd, "SDMA(%u) bad head (%s) hwhd=%hu swhd=%hu swtl=%hu cnt=%hu\n",
1747 sde->this_idx,
1748 use_dmahead ? "dma" : "kreg",
1749 hwhead, swhead, swtail, cnt);
1750 if (use_dmahead) {
1751 /* try one more time, using csr */
1752 use_dmahead = 0;
1753 goto retry;
1754 }
1755 /* proceed as if no progress */
1756 hwhead = swhead;
1757 }
1758 }
1759 return hwhead;
1760 }
1761
1762 /*
1763 * This is called when there are send DMA descriptors that might be
1764 * available.
1765 *
1766 * This is called with head_lock held.
1767 */
sdma_desc_avail(struct sdma_engine * sde,uint avail)1768 static void sdma_desc_avail(struct sdma_engine *sde, uint avail)
1769 {
1770 struct iowait *wait, *nw;
1771 struct iowait *waits[SDMA_WAIT_BATCH_SIZE];
1772 uint i, n = 0, seq, max_idx = 0;
1773 struct sdma_txreq *stx;
1774 struct hfi1_ibdev *dev = &sde->dd->verbs_dev;
1775 u8 max_starved_cnt = 0;
1776
1777 #ifdef CONFIG_SDMA_VERBOSITY
1778 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
1779 slashstrip(__FILE__), __LINE__, __func__);
1780 dd_dev_err(sde->dd, "avail: %u\n", avail);
1781 #endif
1782
1783 do {
1784 seq = read_seqbegin(&dev->iowait_lock);
1785 if (!list_empty(&sde->dmawait)) {
1786 /* at least one item */
1787 write_seqlock(&dev->iowait_lock);
1788 /* Harvest waiters wanting DMA descriptors */
1789 list_for_each_entry_safe(
1790 wait,
1791 nw,
1792 &sde->dmawait,
1793 list) {
1794 u16 num_desc = 0;
1795
1796 if (!wait->wakeup)
1797 continue;
1798 if (n == ARRAY_SIZE(waits))
1799 break;
1800 if (!list_empty(&wait->tx_head)) {
1801 stx = list_first_entry(
1802 &wait->tx_head,
1803 struct sdma_txreq,
1804 list);
1805 num_desc = stx->num_desc;
1806 }
1807 if (num_desc > avail)
1808 break;
1809 avail -= num_desc;
1810 /* Find the most starved wait memeber */
1811 iowait_starve_find_max(wait, &max_starved_cnt,
1812 n, &max_idx);
1813 list_del_init(&wait->list);
1814 waits[n++] = wait;
1815 }
1816 write_sequnlock(&dev->iowait_lock);
1817 break;
1818 }
1819 } while (read_seqretry(&dev->iowait_lock, seq));
1820
1821 /* Schedule the most starved one first */
1822 if (n)
1823 waits[max_idx]->wakeup(waits[max_idx], SDMA_AVAIL_REASON);
1824
1825 for (i = 0; i < n; i++)
1826 if (i != max_idx)
1827 waits[i]->wakeup(waits[i], SDMA_AVAIL_REASON);
1828 }
1829
1830 /* head_lock must be held */
sdma_make_progress(struct sdma_engine * sde,u64 status)1831 static void sdma_make_progress(struct sdma_engine *sde, u64 status)
1832 {
1833 struct sdma_txreq *txp = NULL;
1834 int progress = 0;
1835 u16 hwhead, swhead;
1836 int idle_check_done = 0;
1837
1838 hwhead = sdma_gethead(sde);
1839
1840 /* The reason for some of the complexity of this code is that
1841 * not all descriptors have corresponding txps. So, we have to
1842 * be able to skip over descs until we wander into the range of
1843 * the next txp on the list.
1844 */
1845
1846 retry:
1847 txp = get_txhead(sde);
1848 swhead = sde->descq_head & sde->sdma_mask;
1849 trace_hfi1_sdma_progress(sde, hwhead, swhead, txp);
1850 while (swhead != hwhead) {
1851 /* advance head, wrap if needed */
1852 swhead = ++sde->descq_head & sde->sdma_mask;
1853
1854 /* if now past this txp's descs, do the callback */
1855 if (txp && txp->next_descq_idx == swhead) {
1856 /* remove from list */
1857 sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL;
1858 complete_tx(sde, txp, SDMA_TXREQ_S_OK);
1859 /* see if there is another txp */
1860 txp = get_txhead(sde);
1861 }
1862 trace_hfi1_sdma_progress(sde, hwhead, swhead, txp);
1863 progress++;
1864 }
1865
1866 /*
1867 * The SDMA idle interrupt is not guaranteed to be ordered with respect
1868 * to updates to the the dma_head location in host memory. The head
1869 * value read might not be fully up to date. If there are pending
1870 * descriptors and the SDMA idle interrupt fired then read from the
1871 * CSR SDMA head instead to get the latest value from the hardware.
1872 * The hardware SDMA head should be read at most once in this invocation
1873 * of sdma_make_progress(..) which is ensured by idle_check_done flag
1874 */
1875 if ((status & sde->idle_mask) && !idle_check_done) {
1876 u16 swtail;
1877
1878 swtail = ACCESS_ONCE(sde->descq_tail) & sde->sdma_mask;
1879 if (swtail != hwhead) {
1880 hwhead = (u16)read_sde_csr(sde, SD(HEAD));
1881 idle_check_done = 1;
1882 goto retry;
1883 }
1884 }
1885
1886 sde->last_status = status;
1887 if (progress)
1888 sdma_desc_avail(sde, sdma_descq_freecnt(sde));
1889 }
1890
1891 /*
1892 * sdma_engine_interrupt() - interrupt handler for engine
1893 * @sde: sdma engine
1894 * @status: sdma interrupt reason
1895 *
1896 * Status is a mask of the 3 possible interrupts for this engine. It will
1897 * contain bits _only_ for this SDMA engine. It will contain at least one
1898 * bit, it may contain more.
1899 */
sdma_engine_interrupt(struct sdma_engine * sde,u64 status)1900 void sdma_engine_interrupt(struct sdma_engine *sde, u64 status)
1901 {
1902 trace_hfi1_sdma_engine_interrupt(sde, status);
1903 write_seqlock(&sde->head_lock);
1904 sdma_set_desc_cnt(sde, sdma_desct_intr);
1905 if (status & sde->idle_mask)
1906 sde->idle_int_cnt++;
1907 else if (status & sde->progress_mask)
1908 sde->progress_int_cnt++;
1909 else if (status & sde->int_mask)
1910 sde->sdma_int_cnt++;
1911 sdma_make_progress(sde, status);
1912 write_sequnlock(&sde->head_lock);
1913 }
1914
1915 /**
1916 * sdma_engine_error() - error handler for engine
1917 * @sde: sdma engine
1918 * @status: sdma interrupt reason
1919 */
sdma_engine_error(struct sdma_engine * sde,u64 status)1920 void sdma_engine_error(struct sdma_engine *sde, u64 status)
1921 {
1922 unsigned long flags;
1923
1924 #ifdef CONFIG_SDMA_VERBOSITY
1925 dd_dev_err(sde->dd, "CONFIG SDMA(%u) error status 0x%llx state %s\n",
1926 sde->this_idx,
1927 (unsigned long long)status,
1928 sdma_state_names[sde->state.current_state]);
1929 #endif
1930 spin_lock_irqsave(&sde->tail_lock, flags);
1931 write_seqlock(&sde->head_lock);
1932 if (status & ALL_SDMA_ENG_HALT_ERRS)
1933 __sdma_process_event(sde, sdma_event_e60_hw_halted);
1934 if (status & ~SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK)) {
1935 dd_dev_err(sde->dd,
1936 "SDMA (%u) engine error: 0x%llx state %s\n",
1937 sde->this_idx,
1938 (unsigned long long)status,
1939 sdma_state_names[sde->state.current_state]);
1940 dump_sdma_state(sde);
1941 }
1942 write_sequnlock(&sde->head_lock);
1943 spin_unlock_irqrestore(&sde->tail_lock, flags);
1944 }
1945
sdma_sendctrl(struct sdma_engine * sde,unsigned op)1946 static void sdma_sendctrl(struct sdma_engine *sde, unsigned op)
1947 {
1948 u64 set_senddmactrl = 0;
1949 u64 clr_senddmactrl = 0;
1950 unsigned long flags;
1951
1952 #ifdef CONFIG_SDMA_VERBOSITY
1953 dd_dev_err(sde->dd, "CONFIG SDMA(%u) senddmactrl E=%d I=%d H=%d C=%d\n",
1954 sde->this_idx,
1955 (op & SDMA_SENDCTRL_OP_ENABLE) ? 1 : 0,
1956 (op & SDMA_SENDCTRL_OP_INTENABLE) ? 1 : 0,
1957 (op & SDMA_SENDCTRL_OP_HALT) ? 1 : 0,
1958 (op & SDMA_SENDCTRL_OP_CLEANUP) ? 1 : 0);
1959 #endif
1960
1961 if (op & SDMA_SENDCTRL_OP_ENABLE)
1962 set_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK);
1963 else
1964 clr_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK);
1965
1966 if (op & SDMA_SENDCTRL_OP_INTENABLE)
1967 set_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK);
1968 else
1969 clr_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK);
1970
1971 if (op & SDMA_SENDCTRL_OP_HALT)
1972 set_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK);
1973 else
1974 clr_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK);
1975
1976 spin_lock_irqsave(&sde->senddmactrl_lock, flags);
1977
1978 sde->p_senddmactrl |= set_senddmactrl;
1979 sde->p_senddmactrl &= ~clr_senddmactrl;
1980
1981 if (op & SDMA_SENDCTRL_OP_CLEANUP)
1982 write_sde_csr(sde, SD(CTRL),
1983 sde->p_senddmactrl |
1984 SD(CTRL_SDMA_CLEANUP_SMASK));
1985 else
1986 write_sde_csr(sde, SD(CTRL), sde->p_senddmactrl);
1987
1988 spin_unlock_irqrestore(&sde->senddmactrl_lock, flags);
1989
1990 #ifdef CONFIG_SDMA_VERBOSITY
1991 sdma_dumpstate(sde);
1992 #endif
1993 }
1994
sdma_setlengen(struct sdma_engine * sde)1995 static void sdma_setlengen(struct sdma_engine *sde)
1996 {
1997 #ifdef CONFIG_SDMA_VERBOSITY
1998 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
1999 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
2000 #endif
2001
2002 /*
2003 * Set SendDmaLenGen and clear-then-set the MSB of the generation
2004 * count to enable generation checking and load the internal
2005 * generation counter.
2006 */
2007 write_sde_csr(sde, SD(LEN_GEN),
2008 (sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT));
2009 write_sde_csr(sde, SD(LEN_GEN),
2010 ((sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT)) |
2011 (4ULL << SD(LEN_GEN_GENERATION_SHIFT)));
2012 }
2013
sdma_update_tail(struct sdma_engine * sde,u16 tail)2014 static inline void sdma_update_tail(struct sdma_engine *sde, u16 tail)
2015 {
2016 /* Commit writes to memory and advance the tail on the chip */
2017 smp_wmb(); /* see get_txhead() */
2018 writeq(tail, sde->tail_csr);
2019 }
2020
2021 /*
2022 * This is called when changing to state s10_hw_start_up_halt_wait as
2023 * a result of send buffer errors or send DMA descriptor errors.
2024 */
sdma_hw_start_up(struct sdma_engine * sde)2025 static void sdma_hw_start_up(struct sdma_engine *sde)
2026 {
2027 u64 reg;
2028
2029 #ifdef CONFIG_SDMA_VERBOSITY
2030 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
2031 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
2032 #endif
2033
2034 sdma_setlengen(sde);
2035 sdma_update_tail(sde, 0); /* Set SendDmaTail */
2036 *sde->head_dma = 0;
2037
2038 reg = SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_MASK) <<
2039 SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SHIFT);
2040 write_sde_csr(sde, SD(ENG_ERR_CLEAR), reg);
2041 }
2042
2043 /*
2044 * set_sdma_integrity
2045 *
2046 * Set the SEND_DMA_CHECK_ENABLE register for send DMA engine 'sde'.
2047 */
set_sdma_integrity(struct sdma_engine * sde)2048 static void set_sdma_integrity(struct sdma_engine *sde)
2049 {
2050 struct hfi1_devdata *dd = sde->dd;
2051
2052 write_sde_csr(sde, SD(CHECK_ENABLE),
2053 hfi1_pkt_base_sdma_integrity(dd));
2054 }
2055
init_sdma_regs(struct sdma_engine * sde,u32 credits,uint idle_cnt)2056 static void init_sdma_regs(
2057 struct sdma_engine *sde,
2058 u32 credits,
2059 uint idle_cnt)
2060 {
2061 u8 opval, opmask;
2062 #ifdef CONFIG_SDMA_VERBOSITY
2063 struct hfi1_devdata *dd = sde->dd;
2064
2065 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n",
2066 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
2067 #endif
2068
2069 write_sde_csr(sde, SD(BASE_ADDR), sde->descq_phys);
2070 sdma_setlengen(sde);
2071 sdma_update_tail(sde, 0); /* Set SendDmaTail */
2072 write_sde_csr(sde, SD(RELOAD_CNT), idle_cnt);
2073 write_sde_csr(sde, SD(DESC_CNT), 0);
2074 write_sde_csr(sde, SD(HEAD_ADDR), sde->head_phys);
2075 write_sde_csr(sde, SD(MEMORY),
2076 ((u64)credits << SD(MEMORY_SDMA_MEMORY_CNT_SHIFT)) |
2077 ((u64)(credits * sde->this_idx) <<
2078 SD(MEMORY_SDMA_MEMORY_INDEX_SHIFT)));
2079 write_sde_csr(sde, SD(ENG_ERR_MASK), ~0ull);
2080 set_sdma_integrity(sde);
2081 opmask = OPCODE_CHECK_MASK_DISABLED;
2082 opval = OPCODE_CHECK_VAL_DISABLED;
2083 write_sde_csr(sde, SD(CHECK_OPCODE),
2084 (opmask << SEND_CTXT_CHECK_OPCODE_MASK_SHIFT) |
2085 (opval << SEND_CTXT_CHECK_OPCODE_VALUE_SHIFT));
2086 }
2087
2088 #ifdef CONFIG_SDMA_VERBOSITY
2089
2090 #define sdma_dumpstate_helper0(reg) do { \
2091 csr = read_csr(sde->dd, reg); \
2092 dd_dev_err(sde->dd, "%36s 0x%016llx\n", #reg, csr); \
2093 } while (0)
2094
2095 #define sdma_dumpstate_helper(reg) do { \
2096 csr = read_sde_csr(sde, reg); \
2097 dd_dev_err(sde->dd, "%36s[%02u] 0x%016llx\n", \
2098 #reg, sde->this_idx, csr); \
2099 } while (0)
2100
2101 #define sdma_dumpstate_helper2(reg) do { \
2102 csr = read_csr(sde->dd, reg + (8 * i)); \
2103 dd_dev_err(sde->dd, "%33s_%02u 0x%016llx\n", \
2104 #reg, i, csr); \
2105 } while (0)
2106
sdma_dumpstate(struct sdma_engine * sde)2107 void sdma_dumpstate(struct sdma_engine *sde)
2108 {
2109 u64 csr;
2110 unsigned i;
2111
2112 sdma_dumpstate_helper(SD(CTRL));
2113 sdma_dumpstate_helper(SD(STATUS));
2114 sdma_dumpstate_helper0(SD(ERR_STATUS));
2115 sdma_dumpstate_helper0(SD(ERR_MASK));
2116 sdma_dumpstate_helper(SD(ENG_ERR_STATUS));
2117 sdma_dumpstate_helper(SD(ENG_ERR_MASK));
2118
2119 for (i = 0; i < CCE_NUM_INT_CSRS; ++i) {
2120 sdma_dumpstate_helper2(CCE_INT_STATUS);
2121 sdma_dumpstate_helper2(CCE_INT_MASK);
2122 sdma_dumpstate_helper2(CCE_INT_BLOCKED);
2123 }
2124
2125 sdma_dumpstate_helper(SD(TAIL));
2126 sdma_dumpstate_helper(SD(HEAD));
2127 sdma_dumpstate_helper(SD(PRIORITY_THLD));
2128 sdma_dumpstate_helper(SD(IDLE_CNT));
2129 sdma_dumpstate_helper(SD(RELOAD_CNT));
2130 sdma_dumpstate_helper(SD(DESC_CNT));
2131 sdma_dumpstate_helper(SD(DESC_FETCHED_CNT));
2132 sdma_dumpstate_helper(SD(MEMORY));
2133 sdma_dumpstate_helper0(SD(ENGINES));
2134 sdma_dumpstate_helper0(SD(MEM_SIZE));
2135 /* sdma_dumpstate_helper(SEND_EGRESS_SEND_DMA_STATUS); */
2136 sdma_dumpstate_helper(SD(BASE_ADDR));
2137 sdma_dumpstate_helper(SD(LEN_GEN));
2138 sdma_dumpstate_helper(SD(HEAD_ADDR));
2139 sdma_dumpstate_helper(SD(CHECK_ENABLE));
2140 sdma_dumpstate_helper(SD(CHECK_VL));
2141 sdma_dumpstate_helper(SD(CHECK_JOB_KEY));
2142 sdma_dumpstate_helper(SD(CHECK_PARTITION_KEY));
2143 sdma_dumpstate_helper(SD(CHECK_SLID));
2144 sdma_dumpstate_helper(SD(CHECK_OPCODE));
2145 }
2146 #endif
2147
dump_sdma_state(struct sdma_engine * sde)2148 static void dump_sdma_state(struct sdma_engine *sde)
2149 {
2150 struct hw_sdma_desc *descq;
2151 struct hw_sdma_desc *descqp;
2152 u64 desc[2];
2153 u64 addr;
2154 u8 gen;
2155 u16 len;
2156 u16 head, tail, cnt;
2157
2158 head = sde->descq_head & sde->sdma_mask;
2159 tail = sde->descq_tail & sde->sdma_mask;
2160 cnt = sdma_descq_freecnt(sde);
2161 descq = sde->descq;
2162
2163 dd_dev_err(sde->dd,
2164 "SDMA (%u) descq_head: %u descq_tail: %u freecnt: %u FLE %d\n",
2165 sde->this_idx, head, tail, cnt,
2166 !list_empty(&sde->flushlist));
2167
2168 /* print info for each entry in the descriptor queue */
2169 while (head != tail) {
2170 char flags[6] = { 'x', 'x', 'x', 'x', 0 };
2171
2172 descqp = &sde->descq[head];
2173 desc[0] = le64_to_cpu(descqp->qw[0]);
2174 desc[1] = le64_to_cpu(descqp->qw[1]);
2175 flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-';
2176 flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ?
2177 'H' : '-';
2178 flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-';
2179 flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-';
2180 addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT)
2181 & SDMA_DESC0_PHY_ADDR_MASK;
2182 gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT)
2183 & SDMA_DESC1_GENERATION_MASK;
2184 len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT)
2185 & SDMA_DESC0_BYTE_COUNT_MASK;
2186 dd_dev_err(sde->dd,
2187 "SDMA sdmadesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n",
2188 head, flags, addr, gen, len);
2189 dd_dev_err(sde->dd,
2190 "\tdesc0:0x%016llx desc1 0x%016llx\n",
2191 desc[0], desc[1]);
2192 if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG)
2193 dd_dev_err(sde->dd,
2194 "\taidx: %u amode: %u alen: %u\n",
2195 (u8)((desc[1] &
2196 SDMA_DESC1_HEADER_INDEX_SMASK) >>
2197 SDMA_DESC1_HEADER_INDEX_SHIFT),
2198 (u8)((desc[1] &
2199 SDMA_DESC1_HEADER_MODE_SMASK) >>
2200 SDMA_DESC1_HEADER_MODE_SHIFT),
2201 (u8)((desc[1] &
2202 SDMA_DESC1_HEADER_DWS_SMASK) >>
2203 SDMA_DESC1_HEADER_DWS_SHIFT));
2204 head++;
2205 head &= sde->sdma_mask;
2206 }
2207 }
2208
2209 #define SDE_FMT \
2210 "SDE %u CPU %d STE %s C 0x%llx S 0x%016llx E 0x%llx T(HW) 0x%llx T(SW) 0x%x H(HW) 0x%llx H(SW) 0x%x H(D) 0x%llx DM 0x%llx GL 0x%llx R 0x%llx LIS 0x%llx AHGI 0x%llx TXT %u TXH %u DT %u DH %u FLNE %d DQF %u SLC 0x%llx\n"
2211 /**
2212 * sdma_seqfile_dump_sde() - debugfs dump of sde
2213 * @s: seq file
2214 * @sde: send dma engine to dump
2215 *
2216 * This routine dumps the sde to the indicated seq file.
2217 */
sdma_seqfile_dump_sde(struct seq_file * s,struct sdma_engine * sde)2218 void sdma_seqfile_dump_sde(struct seq_file *s, struct sdma_engine *sde)
2219 {
2220 u16 head, tail;
2221 struct hw_sdma_desc *descqp;
2222 u64 desc[2];
2223 u64 addr;
2224 u8 gen;
2225 u16 len;
2226
2227 head = sde->descq_head & sde->sdma_mask;
2228 tail = ACCESS_ONCE(sde->descq_tail) & sde->sdma_mask;
2229 seq_printf(s, SDE_FMT, sde->this_idx,
2230 sde->cpu,
2231 sdma_state_name(sde->state.current_state),
2232 (unsigned long long)read_sde_csr(sde, SD(CTRL)),
2233 (unsigned long long)read_sde_csr(sde, SD(STATUS)),
2234 (unsigned long long)read_sde_csr(sde, SD(ENG_ERR_STATUS)),
2235 (unsigned long long)read_sde_csr(sde, SD(TAIL)), tail,
2236 (unsigned long long)read_sde_csr(sde, SD(HEAD)), head,
2237 (unsigned long long)le64_to_cpu(*sde->head_dma),
2238 (unsigned long long)read_sde_csr(sde, SD(MEMORY)),
2239 (unsigned long long)read_sde_csr(sde, SD(LEN_GEN)),
2240 (unsigned long long)read_sde_csr(sde, SD(RELOAD_CNT)),
2241 (unsigned long long)sde->last_status,
2242 (unsigned long long)sde->ahg_bits,
2243 sde->tx_tail,
2244 sde->tx_head,
2245 sde->descq_tail,
2246 sde->descq_head,
2247 !list_empty(&sde->flushlist),
2248 sde->descq_full_count,
2249 (unsigned long long)read_sde_csr(sde, SEND_DMA_CHECK_SLID));
2250
2251 /* print info for each entry in the descriptor queue */
2252 while (head != tail) {
2253 char flags[6] = { 'x', 'x', 'x', 'x', 0 };
2254
2255 descqp = &sde->descq[head];
2256 desc[0] = le64_to_cpu(descqp->qw[0]);
2257 desc[1] = le64_to_cpu(descqp->qw[1]);
2258 flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-';
2259 flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ?
2260 'H' : '-';
2261 flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-';
2262 flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-';
2263 addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT)
2264 & SDMA_DESC0_PHY_ADDR_MASK;
2265 gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT)
2266 & SDMA_DESC1_GENERATION_MASK;
2267 len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT)
2268 & SDMA_DESC0_BYTE_COUNT_MASK;
2269 seq_printf(s,
2270 "\tdesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n",
2271 head, flags, addr, gen, len);
2272 if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG)
2273 seq_printf(s, "\t\tahgidx: %u ahgmode: %u\n",
2274 (u8)((desc[1] &
2275 SDMA_DESC1_HEADER_INDEX_SMASK) >>
2276 SDMA_DESC1_HEADER_INDEX_SHIFT),
2277 (u8)((desc[1] &
2278 SDMA_DESC1_HEADER_MODE_SMASK) >>
2279 SDMA_DESC1_HEADER_MODE_SHIFT));
2280 head = (head + 1) & sde->sdma_mask;
2281 }
2282 }
2283
2284 /*
2285 * add the generation number into
2286 * the qw1 and return
2287 */
add_gen(struct sdma_engine * sde,u64 qw1)2288 static inline u64 add_gen(struct sdma_engine *sde, u64 qw1)
2289 {
2290 u8 generation = (sde->descq_tail >> sde->sdma_shift) & 3;
2291
2292 qw1 &= ~SDMA_DESC1_GENERATION_SMASK;
2293 qw1 |= ((u64)generation & SDMA_DESC1_GENERATION_MASK)
2294 << SDMA_DESC1_GENERATION_SHIFT;
2295 return qw1;
2296 }
2297
2298 /*
2299 * This routine submits the indicated tx
2300 *
2301 * Space has already been guaranteed and
2302 * tail side of ring is locked.
2303 *
2304 * The hardware tail update is done
2305 * in the caller and that is facilitated
2306 * by returning the new tail.
2307 *
2308 * There is special case logic for ahg
2309 * to not add the generation number for
2310 * up to 2 descriptors that follow the
2311 * first descriptor.
2312 *
2313 */
submit_tx(struct sdma_engine * sde,struct sdma_txreq * tx)2314 static inline u16 submit_tx(struct sdma_engine *sde, struct sdma_txreq *tx)
2315 {
2316 int i;
2317 u16 tail;
2318 struct sdma_desc *descp = tx->descp;
2319 u8 skip = 0, mode = ahg_mode(tx);
2320
2321 tail = sde->descq_tail & sde->sdma_mask;
2322 sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]);
2323 sde->descq[tail].qw[1] = cpu_to_le64(add_gen(sde, descp->qw[1]));
2324 trace_hfi1_sdma_descriptor(sde, descp->qw[0], descp->qw[1],
2325 tail, &sde->descq[tail]);
2326 tail = ++sde->descq_tail & sde->sdma_mask;
2327 descp++;
2328 if (mode > SDMA_AHG_APPLY_UPDATE1)
2329 skip = mode >> 1;
2330 for (i = 1; i < tx->num_desc; i++, descp++) {
2331 u64 qw1;
2332
2333 sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]);
2334 if (skip) {
2335 /* edits don't have generation */
2336 qw1 = descp->qw[1];
2337 skip--;
2338 } else {
2339 /* replace generation with real one for non-edits */
2340 qw1 = add_gen(sde, descp->qw[1]);
2341 }
2342 sde->descq[tail].qw[1] = cpu_to_le64(qw1);
2343 trace_hfi1_sdma_descriptor(sde, descp->qw[0], qw1,
2344 tail, &sde->descq[tail]);
2345 tail = ++sde->descq_tail & sde->sdma_mask;
2346 }
2347 tx->next_descq_idx = tail;
2348 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
2349 tx->sn = sde->tail_sn++;
2350 trace_hfi1_sdma_in_sn(sde, tx->sn);
2351 WARN_ON_ONCE(sde->tx_ring[sde->tx_tail & sde->sdma_mask]);
2352 #endif
2353 sde->tx_ring[sde->tx_tail++ & sde->sdma_mask] = tx;
2354 sde->desc_avail -= tx->num_desc;
2355 return tail;
2356 }
2357
2358 /*
2359 * Check for progress
2360 */
sdma_check_progress(struct sdma_engine * sde,struct iowait * wait,struct sdma_txreq * tx,bool pkts_sent)2361 static int sdma_check_progress(
2362 struct sdma_engine *sde,
2363 struct iowait *wait,
2364 struct sdma_txreq *tx,
2365 bool pkts_sent)
2366 {
2367 int ret;
2368
2369 sde->desc_avail = sdma_descq_freecnt(sde);
2370 if (tx->num_desc <= sde->desc_avail)
2371 return -EAGAIN;
2372 /* pulse the head_lock */
2373 if (wait && wait->sleep) {
2374 unsigned seq;
2375
2376 seq = raw_seqcount_begin(
2377 (const seqcount_t *)&sde->head_lock.seqcount);
2378 ret = wait->sleep(sde, wait, tx, seq, pkts_sent);
2379 if (ret == -EAGAIN)
2380 sde->desc_avail = sdma_descq_freecnt(sde);
2381 } else {
2382 ret = -EBUSY;
2383 }
2384 return ret;
2385 }
2386
2387 /**
2388 * sdma_send_txreq() - submit a tx req to ring
2389 * @sde: sdma engine to use
2390 * @wait: wait structure to use when full (may be NULL)
2391 * @tx: sdma_txreq to submit
2392 * @pkts_sent: has any packet been sent yet?
2393 *
2394 * The call submits the tx into the ring. If a iowait structure is non-NULL
2395 * the packet will be queued to the list in wait.
2396 *
2397 * Return:
2398 * 0 - Success, -EINVAL - sdma_txreq incomplete, -EBUSY - no space in
2399 * ring (wait == NULL)
2400 * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state
2401 */
sdma_send_txreq(struct sdma_engine * sde,struct iowait * wait,struct sdma_txreq * tx,bool pkts_sent)2402 int sdma_send_txreq(struct sdma_engine *sde,
2403 struct iowait *wait,
2404 struct sdma_txreq *tx,
2405 bool pkts_sent)
2406 {
2407 int ret = 0;
2408 u16 tail;
2409 unsigned long flags;
2410
2411 /* user should have supplied entire packet */
2412 if (unlikely(tx->tlen))
2413 return -EINVAL;
2414 tx->wait = wait;
2415 spin_lock_irqsave(&sde->tail_lock, flags);
2416 retry:
2417 if (unlikely(!__sdma_running(sde)))
2418 goto unlock_noconn;
2419 if (unlikely(tx->num_desc > sde->desc_avail))
2420 goto nodesc;
2421 tail = submit_tx(sde, tx);
2422 if (wait)
2423 iowait_sdma_inc(wait);
2424 sdma_update_tail(sde, tail);
2425 unlock:
2426 spin_unlock_irqrestore(&sde->tail_lock, flags);
2427 return ret;
2428 unlock_noconn:
2429 if (wait)
2430 iowait_sdma_inc(wait);
2431 tx->next_descq_idx = 0;
2432 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
2433 tx->sn = sde->tail_sn++;
2434 trace_hfi1_sdma_in_sn(sde, tx->sn);
2435 #endif
2436 spin_lock(&sde->flushlist_lock);
2437 list_add_tail(&tx->list, &sde->flushlist);
2438 spin_unlock(&sde->flushlist_lock);
2439 if (wait) {
2440 wait->tx_count++;
2441 wait->count += tx->num_desc;
2442 }
2443 schedule_work(&sde->flush_worker);
2444 ret = -ECOMM;
2445 goto unlock;
2446 nodesc:
2447 ret = sdma_check_progress(sde, wait, tx, pkts_sent);
2448 if (ret == -EAGAIN) {
2449 ret = 0;
2450 goto retry;
2451 }
2452 sde->descq_full_count++;
2453 goto unlock;
2454 }
2455
2456 /**
2457 * sdma_send_txlist() - submit a list of tx req to ring
2458 * @sde: sdma engine to use
2459 * @wait: wait structure to use when full (may be NULL)
2460 * @tx_list: list of sdma_txreqs to submit
2461 * @count: pointer to a u32 which, after return will contain the total number of
2462 * sdma_txreqs removed from the tx_list. This will include sdma_txreqs
2463 * whose SDMA descriptors are submitted to the ring and the sdma_txreqs
2464 * which are added to SDMA engine flush list if the SDMA engine state is
2465 * not running.
2466 *
2467 * The call submits the list into the ring.
2468 *
2469 * If the iowait structure is non-NULL and not equal to the iowait list
2470 * the unprocessed part of the list will be appended to the list in wait.
2471 *
2472 * In all cases, the tx_list will be updated so the head of the tx_list is
2473 * the list of descriptors that have yet to be transmitted.
2474 *
2475 * The intent of this call is to provide a more efficient
2476 * way of submitting multiple packets to SDMA while holding the tail
2477 * side locking.
2478 *
2479 * Return:
2480 * 0 - Success,
2481 * -EINVAL - sdma_txreq incomplete, -EBUSY - no space in ring (wait == NULL)
2482 * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state
2483 */
sdma_send_txlist(struct sdma_engine * sde,struct iowait * wait,struct list_head * tx_list,u32 * count_out)2484 int sdma_send_txlist(struct sdma_engine *sde, struct iowait *wait,
2485 struct list_head *tx_list, u32 *count_out)
2486 {
2487 struct sdma_txreq *tx, *tx_next;
2488 int ret = 0;
2489 unsigned long flags;
2490 u16 tail = INVALID_TAIL;
2491 u32 submit_count = 0, flush_count = 0, total_count;
2492
2493 spin_lock_irqsave(&sde->tail_lock, flags);
2494 retry:
2495 list_for_each_entry_safe(tx, tx_next, tx_list, list) {
2496 tx->wait = wait;
2497 if (unlikely(!__sdma_running(sde)))
2498 goto unlock_noconn;
2499 if (unlikely(tx->num_desc > sde->desc_avail))
2500 goto nodesc;
2501 if (unlikely(tx->tlen)) {
2502 ret = -EINVAL;
2503 goto update_tail;
2504 }
2505 list_del_init(&tx->list);
2506 tail = submit_tx(sde, tx);
2507 submit_count++;
2508 if (tail != INVALID_TAIL &&
2509 (submit_count & SDMA_TAIL_UPDATE_THRESH) == 0) {
2510 sdma_update_tail(sde, tail);
2511 tail = INVALID_TAIL;
2512 }
2513 }
2514 update_tail:
2515 total_count = submit_count + flush_count;
2516 if (wait) {
2517 iowait_sdma_add(wait, total_count);
2518 iowait_starve_clear(submit_count > 0, wait);
2519 }
2520 if (tail != INVALID_TAIL)
2521 sdma_update_tail(sde, tail);
2522 spin_unlock_irqrestore(&sde->tail_lock, flags);
2523 *count_out = total_count;
2524 return ret;
2525 unlock_noconn:
2526 spin_lock(&sde->flushlist_lock);
2527 list_for_each_entry_safe(tx, tx_next, tx_list, list) {
2528 tx->wait = wait;
2529 list_del_init(&tx->list);
2530 tx->next_descq_idx = 0;
2531 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
2532 tx->sn = sde->tail_sn++;
2533 trace_hfi1_sdma_in_sn(sde, tx->sn);
2534 #endif
2535 list_add_tail(&tx->list, &sde->flushlist);
2536 flush_count++;
2537 if (wait) {
2538 wait->tx_count++;
2539 wait->count += tx->num_desc;
2540 }
2541 }
2542 spin_unlock(&sde->flushlist_lock);
2543 schedule_work(&sde->flush_worker);
2544 ret = -ECOMM;
2545 goto update_tail;
2546 nodesc:
2547 ret = sdma_check_progress(sde, wait, tx, submit_count > 0);
2548 if (ret == -EAGAIN) {
2549 ret = 0;
2550 goto retry;
2551 }
2552 sde->descq_full_count++;
2553 goto update_tail;
2554 }
2555
sdma_process_event(struct sdma_engine * sde,enum sdma_events event)2556 static void sdma_process_event(struct sdma_engine *sde, enum sdma_events event)
2557 {
2558 unsigned long flags;
2559
2560 spin_lock_irqsave(&sde->tail_lock, flags);
2561 write_seqlock(&sde->head_lock);
2562
2563 __sdma_process_event(sde, event);
2564
2565 if (sde->state.current_state == sdma_state_s99_running)
2566 sdma_desc_avail(sde, sdma_descq_freecnt(sde));
2567
2568 write_sequnlock(&sde->head_lock);
2569 spin_unlock_irqrestore(&sde->tail_lock, flags);
2570 }
2571
__sdma_process_event(struct sdma_engine * sde,enum sdma_events event)2572 static void __sdma_process_event(struct sdma_engine *sde,
2573 enum sdma_events event)
2574 {
2575 struct sdma_state *ss = &sde->state;
2576 int need_progress = 0;
2577
2578 /* CONFIG SDMA temporary */
2579 #ifdef CONFIG_SDMA_VERBOSITY
2580 dd_dev_err(sde->dd, "CONFIG SDMA(%u) [%s] %s\n", sde->this_idx,
2581 sdma_state_names[ss->current_state],
2582 sdma_event_names[event]);
2583 #endif
2584
2585 switch (ss->current_state) {
2586 case sdma_state_s00_hw_down:
2587 switch (event) {
2588 case sdma_event_e00_go_hw_down:
2589 break;
2590 case sdma_event_e30_go_running:
2591 /*
2592 * If down, but running requested (usually result
2593 * of link up, then we need to start up.
2594 * This can happen when hw down is requested while
2595 * bringing the link up with traffic active on
2596 * 7220, e.g.
2597 */
2598 ss->go_s99_running = 1;
2599 /* fall through and start dma engine */
2600 case sdma_event_e10_go_hw_start:
2601 /* This reference means the state machine is started */
2602 sdma_get(&sde->state);
2603 sdma_set_state(sde,
2604 sdma_state_s10_hw_start_up_halt_wait);
2605 break;
2606 case sdma_event_e15_hw_halt_done:
2607 break;
2608 case sdma_event_e25_hw_clean_up_done:
2609 break;
2610 case sdma_event_e40_sw_cleaned:
2611 sdma_sw_tear_down(sde);
2612 break;
2613 case sdma_event_e50_hw_cleaned:
2614 break;
2615 case sdma_event_e60_hw_halted:
2616 break;
2617 case sdma_event_e70_go_idle:
2618 break;
2619 case sdma_event_e80_hw_freeze:
2620 break;
2621 case sdma_event_e81_hw_frozen:
2622 break;
2623 case sdma_event_e82_hw_unfreeze:
2624 break;
2625 case sdma_event_e85_link_down:
2626 break;
2627 case sdma_event_e90_sw_halted:
2628 break;
2629 }
2630 break;
2631
2632 case sdma_state_s10_hw_start_up_halt_wait:
2633 switch (event) {
2634 case sdma_event_e00_go_hw_down:
2635 sdma_set_state(sde, sdma_state_s00_hw_down);
2636 sdma_sw_tear_down(sde);
2637 break;
2638 case sdma_event_e10_go_hw_start:
2639 break;
2640 case sdma_event_e15_hw_halt_done:
2641 sdma_set_state(sde,
2642 sdma_state_s15_hw_start_up_clean_wait);
2643 sdma_start_hw_clean_up(sde);
2644 break;
2645 case sdma_event_e25_hw_clean_up_done:
2646 break;
2647 case sdma_event_e30_go_running:
2648 ss->go_s99_running = 1;
2649 break;
2650 case sdma_event_e40_sw_cleaned:
2651 break;
2652 case sdma_event_e50_hw_cleaned:
2653 break;
2654 case sdma_event_e60_hw_halted:
2655 schedule_work(&sde->err_halt_worker);
2656 break;
2657 case sdma_event_e70_go_idle:
2658 ss->go_s99_running = 0;
2659 break;
2660 case sdma_event_e80_hw_freeze:
2661 break;
2662 case sdma_event_e81_hw_frozen:
2663 break;
2664 case sdma_event_e82_hw_unfreeze:
2665 break;
2666 case sdma_event_e85_link_down:
2667 break;
2668 case sdma_event_e90_sw_halted:
2669 break;
2670 }
2671 break;
2672
2673 case sdma_state_s15_hw_start_up_clean_wait:
2674 switch (event) {
2675 case sdma_event_e00_go_hw_down:
2676 sdma_set_state(sde, sdma_state_s00_hw_down);
2677 sdma_sw_tear_down(sde);
2678 break;
2679 case sdma_event_e10_go_hw_start:
2680 break;
2681 case sdma_event_e15_hw_halt_done:
2682 break;
2683 case sdma_event_e25_hw_clean_up_done:
2684 sdma_hw_start_up(sde);
2685 sdma_set_state(sde, ss->go_s99_running ?
2686 sdma_state_s99_running :
2687 sdma_state_s20_idle);
2688 break;
2689 case sdma_event_e30_go_running:
2690 ss->go_s99_running = 1;
2691 break;
2692 case sdma_event_e40_sw_cleaned:
2693 break;
2694 case sdma_event_e50_hw_cleaned:
2695 break;
2696 case sdma_event_e60_hw_halted:
2697 break;
2698 case sdma_event_e70_go_idle:
2699 ss->go_s99_running = 0;
2700 break;
2701 case sdma_event_e80_hw_freeze:
2702 break;
2703 case sdma_event_e81_hw_frozen:
2704 break;
2705 case sdma_event_e82_hw_unfreeze:
2706 break;
2707 case sdma_event_e85_link_down:
2708 break;
2709 case sdma_event_e90_sw_halted:
2710 break;
2711 }
2712 break;
2713
2714 case sdma_state_s20_idle:
2715 switch (event) {
2716 case sdma_event_e00_go_hw_down:
2717 sdma_set_state(sde, sdma_state_s00_hw_down);
2718 sdma_sw_tear_down(sde);
2719 break;
2720 case sdma_event_e10_go_hw_start:
2721 break;
2722 case sdma_event_e15_hw_halt_done:
2723 break;
2724 case sdma_event_e25_hw_clean_up_done:
2725 break;
2726 case sdma_event_e30_go_running:
2727 sdma_set_state(sde, sdma_state_s99_running);
2728 ss->go_s99_running = 1;
2729 break;
2730 case sdma_event_e40_sw_cleaned:
2731 break;
2732 case sdma_event_e50_hw_cleaned:
2733 break;
2734 case sdma_event_e60_hw_halted:
2735 sdma_set_state(sde, sdma_state_s50_hw_halt_wait);
2736 schedule_work(&sde->err_halt_worker);
2737 break;
2738 case sdma_event_e70_go_idle:
2739 break;
2740 case sdma_event_e85_link_down:
2741 /* fall through */
2742 case sdma_event_e80_hw_freeze:
2743 sdma_set_state(sde, sdma_state_s80_hw_freeze);
2744 atomic_dec(&sde->dd->sdma_unfreeze_count);
2745 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
2746 break;
2747 case sdma_event_e81_hw_frozen:
2748 break;
2749 case sdma_event_e82_hw_unfreeze:
2750 break;
2751 case sdma_event_e90_sw_halted:
2752 break;
2753 }
2754 break;
2755
2756 case sdma_state_s30_sw_clean_up_wait:
2757 switch (event) {
2758 case sdma_event_e00_go_hw_down:
2759 sdma_set_state(sde, sdma_state_s00_hw_down);
2760 break;
2761 case sdma_event_e10_go_hw_start:
2762 break;
2763 case sdma_event_e15_hw_halt_done:
2764 break;
2765 case sdma_event_e25_hw_clean_up_done:
2766 break;
2767 case sdma_event_e30_go_running:
2768 ss->go_s99_running = 1;
2769 break;
2770 case sdma_event_e40_sw_cleaned:
2771 sdma_set_state(sde, sdma_state_s40_hw_clean_up_wait);
2772 sdma_start_hw_clean_up(sde);
2773 break;
2774 case sdma_event_e50_hw_cleaned:
2775 break;
2776 case sdma_event_e60_hw_halted:
2777 break;
2778 case sdma_event_e70_go_idle:
2779 ss->go_s99_running = 0;
2780 break;
2781 case sdma_event_e80_hw_freeze:
2782 break;
2783 case sdma_event_e81_hw_frozen:
2784 break;
2785 case sdma_event_e82_hw_unfreeze:
2786 break;
2787 case sdma_event_e85_link_down:
2788 ss->go_s99_running = 0;
2789 break;
2790 case sdma_event_e90_sw_halted:
2791 break;
2792 }
2793 break;
2794
2795 case sdma_state_s40_hw_clean_up_wait:
2796 switch (event) {
2797 case sdma_event_e00_go_hw_down:
2798 sdma_set_state(sde, sdma_state_s00_hw_down);
2799 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2800 break;
2801 case sdma_event_e10_go_hw_start:
2802 break;
2803 case sdma_event_e15_hw_halt_done:
2804 break;
2805 case sdma_event_e25_hw_clean_up_done:
2806 sdma_hw_start_up(sde);
2807 sdma_set_state(sde, ss->go_s99_running ?
2808 sdma_state_s99_running :
2809 sdma_state_s20_idle);
2810 break;
2811 case sdma_event_e30_go_running:
2812 ss->go_s99_running = 1;
2813 break;
2814 case sdma_event_e40_sw_cleaned:
2815 break;
2816 case sdma_event_e50_hw_cleaned:
2817 break;
2818 case sdma_event_e60_hw_halted:
2819 break;
2820 case sdma_event_e70_go_idle:
2821 ss->go_s99_running = 0;
2822 break;
2823 case sdma_event_e80_hw_freeze:
2824 break;
2825 case sdma_event_e81_hw_frozen:
2826 break;
2827 case sdma_event_e82_hw_unfreeze:
2828 break;
2829 case sdma_event_e85_link_down:
2830 ss->go_s99_running = 0;
2831 break;
2832 case sdma_event_e90_sw_halted:
2833 break;
2834 }
2835 break;
2836
2837 case sdma_state_s50_hw_halt_wait:
2838 switch (event) {
2839 case sdma_event_e00_go_hw_down:
2840 sdma_set_state(sde, sdma_state_s00_hw_down);
2841 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2842 break;
2843 case sdma_event_e10_go_hw_start:
2844 break;
2845 case sdma_event_e15_hw_halt_done:
2846 sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait);
2847 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2848 break;
2849 case sdma_event_e25_hw_clean_up_done:
2850 break;
2851 case sdma_event_e30_go_running:
2852 ss->go_s99_running = 1;
2853 break;
2854 case sdma_event_e40_sw_cleaned:
2855 break;
2856 case sdma_event_e50_hw_cleaned:
2857 break;
2858 case sdma_event_e60_hw_halted:
2859 schedule_work(&sde->err_halt_worker);
2860 break;
2861 case sdma_event_e70_go_idle:
2862 ss->go_s99_running = 0;
2863 break;
2864 case sdma_event_e80_hw_freeze:
2865 break;
2866 case sdma_event_e81_hw_frozen:
2867 break;
2868 case sdma_event_e82_hw_unfreeze:
2869 break;
2870 case sdma_event_e85_link_down:
2871 ss->go_s99_running = 0;
2872 break;
2873 case sdma_event_e90_sw_halted:
2874 break;
2875 }
2876 break;
2877
2878 case sdma_state_s60_idle_halt_wait:
2879 switch (event) {
2880 case sdma_event_e00_go_hw_down:
2881 sdma_set_state(sde, sdma_state_s00_hw_down);
2882 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2883 break;
2884 case sdma_event_e10_go_hw_start:
2885 break;
2886 case sdma_event_e15_hw_halt_done:
2887 sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait);
2888 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2889 break;
2890 case sdma_event_e25_hw_clean_up_done:
2891 break;
2892 case sdma_event_e30_go_running:
2893 ss->go_s99_running = 1;
2894 break;
2895 case sdma_event_e40_sw_cleaned:
2896 break;
2897 case sdma_event_e50_hw_cleaned:
2898 break;
2899 case sdma_event_e60_hw_halted:
2900 schedule_work(&sde->err_halt_worker);
2901 break;
2902 case sdma_event_e70_go_idle:
2903 ss->go_s99_running = 0;
2904 break;
2905 case sdma_event_e80_hw_freeze:
2906 break;
2907 case sdma_event_e81_hw_frozen:
2908 break;
2909 case sdma_event_e82_hw_unfreeze:
2910 break;
2911 case sdma_event_e85_link_down:
2912 break;
2913 case sdma_event_e90_sw_halted:
2914 break;
2915 }
2916 break;
2917
2918 case sdma_state_s80_hw_freeze:
2919 switch (event) {
2920 case sdma_event_e00_go_hw_down:
2921 sdma_set_state(sde, sdma_state_s00_hw_down);
2922 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2923 break;
2924 case sdma_event_e10_go_hw_start:
2925 break;
2926 case sdma_event_e15_hw_halt_done:
2927 break;
2928 case sdma_event_e25_hw_clean_up_done:
2929 break;
2930 case sdma_event_e30_go_running:
2931 ss->go_s99_running = 1;
2932 break;
2933 case sdma_event_e40_sw_cleaned:
2934 break;
2935 case sdma_event_e50_hw_cleaned:
2936 break;
2937 case sdma_event_e60_hw_halted:
2938 break;
2939 case sdma_event_e70_go_idle:
2940 ss->go_s99_running = 0;
2941 break;
2942 case sdma_event_e80_hw_freeze:
2943 break;
2944 case sdma_event_e81_hw_frozen:
2945 sdma_set_state(sde, sdma_state_s82_freeze_sw_clean);
2946 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2947 break;
2948 case sdma_event_e82_hw_unfreeze:
2949 break;
2950 case sdma_event_e85_link_down:
2951 break;
2952 case sdma_event_e90_sw_halted:
2953 break;
2954 }
2955 break;
2956
2957 case sdma_state_s82_freeze_sw_clean:
2958 switch (event) {
2959 case sdma_event_e00_go_hw_down:
2960 sdma_set_state(sde, sdma_state_s00_hw_down);
2961 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2962 break;
2963 case sdma_event_e10_go_hw_start:
2964 break;
2965 case sdma_event_e15_hw_halt_done:
2966 break;
2967 case sdma_event_e25_hw_clean_up_done:
2968 break;
2969 case sdma_event_e30_go_running:
2970 ss->go_s99_running = 1;
2971 break;
2972 case sdma_event_e40_sw_cleaned:
2973 /* notify caller this engine is done cleaning */
2974 atomic_dec(&sde->dd->sdma_unfreeze_count);
2975 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
2976 break;
2977 case sdma_event_e50_hw_cleaned:
2978 break;
2979 case sdma_event_e60_hw_halted:
2980 break;
2981 case sdma_event_e70_go_idle:
2982 ss->go_s99_running = 0;
2983 break;
2984 case sdma_event_e80_hw_freeze:
2985 break;
2986 case sdma_event_e81_hw_frozen:
2987 break;
2988 case sdma_event_e82_hw_unfreeze:
2989 sdma_hw_start_up(sde);
2990 sdma_set_state(sde, ss->go_s99_running ?
2991 sdma_state_s99_running :
2992 sdma_state_s20_idle);
2993 break;
2994 case sdma_event_e85_link_down:
2995 break;
2996 case sdma_event_e90_sw_halted:
2997 break;
2998 }
2999 break;
3000
3001 case sdma_state_s99_running:
3002 switch (event) {
3003 case sdma_event_e00_go_hw_down:
3004 sdma_set_state(sde, sdma_state_s00_hw_down);
3005 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
3006 break;
3007 case sdma_event_e10_go_hw_start:
3008 break;
3009 case sdma_event_e15_hw_halt_done:
3010 break;
3011 case sdma_event_e25_hw_clean_up_done:
3012 break;
3013 case sdma_event_e30_go_running:
3014 break;
3015 case sdma_event_e40_sw_cleaned:
3016 break;
3017 case sdma_event_e50_hw_cleaned:
3018 break;
3019 case sdma_event_e60_hw_halted:
3020 need_progress = 1;
3021 sdma_err_progress_check_schedule(sde);
3022 case sdma_event_e90_sw_halted:
3023 /*
3024 * SW initiated halt does not perform engines
3025 * progress check
3026 */
3027 sdma_set_state(sde, sdma_state_s50_hw_halt_wait);
3028 schedule_work(&sde->err_halt_worker);
3029 break;
3030 case sdma_event_e70_go_idle:
3031 sdma_set_state(sde, sdma_state_s60_idle_halt_wait);
3032 break;
3033 case sdma_event_e85_link_down:
3034 ss->go_s99_running = 0;
3035 /* fall through */
3036 case sdma_event_e80_hw_freeze:
3037 sdma_set_state(sde, sdma_state_s80_hw_freeze);
3038 atomic_dec(&sde->dd->sdma_unfreeze_count);
3039 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
3040 break;
3041 case sdma_event_e81_hw_frozen:
3042 break;
3043 case sdma_event_e82_hw_unfreeze:
3044 break;
3045 }
3046 break;
3047 }
3048
3049 ss->last_event = event;
3050 if (need_progress)
3051 sdma_make_progress(sde, 0);
3052 }
3053
3054 /*
3055 * _extend_sdma_tx_descs() - helper to extend txreq
3056 *
3057 * This is called once the initial nominal allocation
3058 * of descriptors in the sdma_txreq is exhausted.
3059 *
3060 * The code will bump the allocation up to the max
3061 * of MAX_DESC (64) descriptors. There doesn't seem
3062 * much point in an interim step. The last descriptor
3063 * is reserved for coalesce buffer in order to support
3064 * cases where input packet has >MAX_DESC iovecs.
3065 *
3066 */
_extend_sdma_tx_descs(struct hfi1_devdata * dd,struct sdma_txreq * tx)3067 static int _extend_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx)
3068 {
3069 int i;
3070
3071 /* Handle last descriptor */
3072 if (unlikely((tx->num_desc == (MAX_DESC - 1)))) {
3073 /* if tlen is 0, it is for padding, release last descriptor */
3074 if (!tx->tlen) {
3075 tx->desc_limit = MAX_DESC;
3076 } else if (!tx->coalesce_buf) {
3077 /* allocate coalesce buffer with space for padding */
3078 tx->coalesce_buf = kmalloc(tx->tlen + sizeof(u32),
3079 GFP_ATOMIC);
3080 if (!tx->coalesce_buf)
3081 goto enomem;
3082 tx->coalesce_idx = 0;
3083 }
3084 return 0;
3085 }
3086
3087 if (unlikely(tx->num_desc == MAX_DESC))
3088 goto enomem;
3089
3090 tx->descp = kmalloc_array(
3091 MAX_DESC,
3092 sizeof(struct sdma_desc),
3093 GFP_ATOMIC);
3094 if (!tx->descp)
3095 goto enomem;
3096
3097 /* reserve last descriptor for coalescing */
3098 tx->desc_limit = MAX_DESC - 1;
3099 /* copy ones already built */
3100 for (i = 0; i < tx->num_desc; i++)
3101 tx->descp[i] = tx->descs[i];
3102 return 0;
3103 enomem:
3104 __sdma_txclean(dd, tx);
3105 return -ENOMEM;
3106 }
3107
3108 /*
3109 * ext_coal_sdma_tx_descs() - extend or coalesce sdma tx descriptors
3110 *
3111 * This is called once the initial nominal allocation of descriptors
3112 * in the sdma_txreq is exhausted.
3113 *
3114 * This function calls _extend_sdma_tx_descs to extend or allocate
3115 * coalesce buffer. If there is a allocated coalesce buffer, it will
3116 * copy the input packet data into the coalesce buffer. It also adds
3117 * coalesce buffer descriptor once when whole packet is received.
3118 *
3119 * Return:
3120 * <0 - error
3121 * 0 - coalescing, don't populate descriptor
3122 * 1 - continue with populating descriptor
3123 */
ext_coal_sdma_tx_descs(struct hfi1_devdata * dd,struct sdma_txreq * tx,int type,void * kvaddr,struct page * page,unsigned long offset,u16 len)3124 int ext_coal_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx,
3125 int type, void *kvaddr, struct page *page,
3126 unsigned long offset, u16 len)
3127 {
3128 int pad_len, rval;
3129 dma_addr_t addr;
3130
3131 rval = _extend_sdma_tx_descs(dd, tx);
3132 if (rval) {
3133 __sdma_txclean(dd, tx);
3134 return rval;
3135 }
3136
3137 /* If coalesce buffer is allocated, copy data into it */
3138 if (tx->coalesce_buf) {
3139 if (type == SDMA_MAP_NONE) {
3140 __sdma_txclean(dd, tx);
3141 return -EINVAL;
3142 }
3143
3144 if (type == SDMA_MAP_PAGE) {
3145 kvaddr = kmap(page);
3146 kvaddr += offset;
3147 } else if (WARN_ON(!kvaddr)) {
3148 __sdma_txclean(dd, tx);
3149 return -EINVAL;
3150 }
3151
3152 memcpy(tx->coalesce_buf + tx->coalesce_idx, kvaddr, len);
3153 tx->coalesce_idx += len;
3154 if (type == SDMA_MAP_PAGE)
3155 kunmap(page);
3156
3157 /* If there is more data, return */
3158 if (tx->tlen - tx->coalesce_idx)
3159 return 0;
3160
3161 /* Whole packet is received; add any padding */
3162 pad_len = tx->packet_len & (sizeof(u32) - 1);
3163 if (pad_len) {
3164 pad_len = sizeof(u32) - pad_len;
3165 memset(tx->coalesce_buf + tx->coalesce_idx, 0, pad_len);
3166 /* padding is taken care of for coalescing case */
3167 tx->packet_len += pad_len;
3168 tx->tlen += pad_len;
3169 }
3170
3171 /* dma map the coalesce buffer */
3172 addr = dma_map_single(&dd->pcidev->dev,
3173 tx->coalesce_buf,
3174 tx->tlen,
3175 DMA_TO_DEVICE);
3176
3177 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) {
3178 __sdma_txclean(dd, tx);
3179 return -ENOSPC;
3180 }
3181
3182 /* Add descriptor for coalesce buffer */
3183 tx->desc_limit = MAX_DESC;
3184 return _sdma_txadd_daddr(dd, SDMA_MAP_SINGLE, tx,
3185 addr, tx->tlen);
3186 }
3187
3188 return 1;
3189 }
3190
3191 /* Update sdes when the lmc changes */
sdma_update_lmc(struct hfi1_devdata * dd,u64 mask,u32 lid)3192 void sdma_update_lmc(struct hfi1_devdata *dd, u64 mask, u32 lid)
3193 {
3194 struct sdma_engine *sde;
3195 int i;
3196 u64 sreg;
3197
3198 sreg = ((mask & SD(CHECK_SLID_MASK_MASK)) <<
3199 SD(CHECK_SLID_MASK_SHIFT)) |
3200 (((lid & mask) & SD(CHECK_SLID_VALUE_MASK)) <<
3201 SD(CHECK_SLID_VALUE_SHIFT));
3202
3203 for (i = 0; i < dd->num_sdma; i++) {
3204 hfi1_cdbg(LINKVERB, "SendDmaEngine[%d].SLID_CHECK = 0x%x",
3205 i, (u32)sreg);
3206 sde = &dd->per_sdma[i];
3207 write_sde_csr(sde, SD(CHECK_SLID), sreg);
3208 }
3209 }
3210
3211 /* tx not dword sized - pad */
_pad_sdma_tx_descs(struct hfi1_devdata * dd,struct sdma_txreq * tx)3212 int _pad_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx)
3213 {
3214 int rval = 0;
3215
3216 tx->num_desc++;
3217 if ((unlikely(tx->num_desc == tx->desc_limit))) {
3218 rval = _extend_sdma_tx_descs(dd, tx);
3219 if (rval) {
3220 __sdma_txclean(dd, tx);
3221 return rval;
3222 }
3223 }
3224 /* finish the one just added */
3225 make_tx_sdma_desc(
3226 tx,
3227 SDMA_MAP_NONE,
3228 dd->sdma_pad_phys,
3229 sizeof(u32) - (tx->packet_len & (sizeof(u32) - 1)));
3230 _sdma_close_tx(dd, tx);
3231 return rval;
3232 }
3233
3234 /*
3235 * Add ahg to the sdma_txreq
3236 *
3237 * The logic will consume up to 3
3238 * descriptors at the beginning of
3239 * sdma_txreq.
3240 */
_sdma_txreq_ahgadd(struct sdma_txreq * tx,u8 num_ahg,u8 ahg_entry,u32 * ahg,u8 ahg_hlen)3241 void _sdma_txreq_ahgadd(
3242 struct sdma_txreq *tx,
3243 u8 num_ahg,
3244 u8 ahg_entry,
3245 u32 *ahg,
3246 u8 ahg_hlen)
3247 {
3248 u32 i, shift = 0, desc = 0;
3249 u8 mode;
3250
3251 WARN_ON_ONCE(num_ahg > 9 || (ahg_hlen & 3) || ahg_hlen == 4);
3252 /* compute mode */
3253 if (num_ahg == 1)
3254 mode = SDMA_AHG_APPLY_UPDATE1;
3255 else if (num_ahg <= 5)
3256 mode = SDMA_AHG_APPLY_UPDATE2;
3257 else
3258 mode = SDMA_AHG_APPLY_UPDATE3;
3259 tx->num_desc++;
3260 /* initialize to consumed descriptors to zero */
3261 switch (mode) {
3262 case SDMA_AHG_APPLY_UPDATE3:
3263 tx->num_desc++;
3264 tx->descs[2].qw[0] = 0;
3265 tx->descs[2].qw[1] = 0;
3266 /* FALLTHROUGH */
3267 case SDMA_AHG_APPLY_UPDATE2:
3268 tx->num_desc++;
3269 tx->descs[1].qw[0] = 0;
3270 tx->descs[1].qw[1] = 0;
3271 break;
3272 }
3273 ahg_hlen >>= 2;
3274 tx->descs[0].qw[1] |=
3275 (((u64)ahg_entry & SDMA_DESC1_HEADER_INDEX_MASK)
3276 << SDMA_DESC1_HEADER_INDEX_SHIFT) |
3277 (((u64)ahg_hlen & SDMA_DESC1_HEADER_DWS_MASK)
3278 << SDMA_DESC1_HEADER_DWS_SHIFT) |
3279 (((u64)mode & SDMA_DESC1_HEADER_MODE_MASK)
3280 << SDMA_DESC1_HEADER_MODE_SHIFT) |
3281 (((u64)ahg[0] & SDMA_DESC1_HEADER_UPDATE1_MASK)
3282 << SDMA_DESC1_HEADER_UPDATE1_SHIFT);
3283 for (i = 0; i < (num_ahg - 1); i++) {
3284 if (!shift && !(i & 2))
3285 desc++;
3286 tx->descs[desc].qw[!!(i & 2)] |=
3287 (((u64)ahg[i + 1])
3288 << shift);
3289 shift = (shift + 32) & 63;
3290 }
3291 }
3292
3293 /**
3294 * sdma_ahg_alloc - allocate an AHG entry
3295 * @sde: engine to allocate from
3296 *
3297 * Return:
3298 * 0-31 when successful, -EOPNOTSUPP if AHG is not enabled,
3299 * -ENOSPC if an entry is not available
3300 */
sdma_ahg_alloc(struct sdma_engine * sde)3301 int sdma_ahg_alloc(struct sdma_engine *sde)
3302 {
3303 int nr;
3304 int oldbit;
3305
3306 if (!sde) {
3307 trace_hfi1_ahg_allocate(sde, -EINVAL);
3308 return -EINVAL;
3309 }
3310 while (1) {
3311 nr = ffz(ACCESS_ONCE(sde->ahg_bits));
3312 if (nr > 31) {
3313 trace_hfi1_ahg_allocate(sde, -ENOSPC);
3314 return -ENOSPC;
3315 }
3316 oldbit = test_and_set_bit(nr, &sde->ahg_bits);
3317 if (!oldbit)
3318 break;
3319 cpu_relax();
3320 }
3321 trace_hfi1_ahg_allocate(sde, nr);
3322 return nr;
3323 }
3324
3325 /**
3326 * sdma_ahg_free - free an AHG entry
3327 * @sde: engine to return AHG entry
3328 * @ahg_index: index to free
3329 *
3330 * This routine frees the indicate AHG entry.
3331 */
sdma_ahg_free(struct sdma_engine * sde,int ahg_index)3332 void sdma_ahg_free(struct sdma_engine *sde, int ahg_index)
3333 {
3334 if (!sde)
3335 return;
3336 trace_hfi1_ahg_deallocate(sde, ahg_index);
3337 if (ahg_index < 0 || ahg_index > 31)
3338 return;
3339 clear_bit(ahg_index, &sde->ahg_bits);
3340 }
3341
3342 /*
3343 * SPC freeze handling for SDMA engines. Called when the driver knows
3344 * the SPC is going into a freeze but before the freeze is fully
3345 * settled. Generally an error interrupt.
3346 *
3347 * This event will pull the engine out of running so no more entries can be
3348 * added to the engine's queue.
3349 */
sdma_freeze_notify(struct hfi1_devdata * dd,int link_down)3350 void sdma_freeze_notify(struct hfi1_devdata *dd, int link_down)
3351 {
3352 int i;
3353 enum sdma_events event = link_down ? sdma_event_e85_link_down :
3354 sdma_event_e80_hw_freeze;
3355
3356 /* set up the wait but do not wait here */
3357 atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma);
3358
3359 /* tell all engines to stop running and wait */
3360 for (i = 0; i < dd->num_sdma; i++)
3361 sdma_process_event(&dd->per_sdma[i], event);
3362
3363 /* sdma_freeze() will wait for all engines to have stopped */
3364 }
3365
3366 /*
3367 * SPC freeze handling for SDMA engines. Called when the driver knows
3368 * the SPC is fully frozen.
3369 */
sdma_freeze(struct hfi1_devdata * dd)3370 void sdma_freeze(struct hfi1_devdata *dd)
3371 {
3372 int i;
3373 int ret;
3374
3375 /*
3376 * Make sure all engines have moved out of the running state before
3377 * continuing.
3378 */
3379 ret = wait_event_interruptible(dd->sdma_unfreeze_wq,
3380 atomic_read(&dd->sdma_unfreeze_count) <=
3381 0);
3382 /* interrupted or count is negative, then unloading - just exit */
3383 if (ret || atomic_read(&dd->sdma_unfreeze_count) < 0)
3384 return;
3385
3386 /* set up the count for the next wait */
3387 atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma);
3388
3389 /* tell all engines that the SPC is frozen, they can start cleaning */
3390 for (i = 0; i < dd->num_sdma; i++)
3391 sdma_process_event(&dd->per_sdma[i], sdma_event_e81_hw_frozen);
3392
3393 /*
3394 * Wait for everyone to finish software clean before exiting. The
3395 * software clean will read engine CSRs, so must be completed before
3396 * the next step, which will clear the engine CSRs.
3397 */
3398 (void)wait_event_interruptible(dd->sdma_unfreeze_wq,
3399 atomic_read(&dd->sdma_unfreeze_count) <= 0);
3400 /* no need to check results - done no matter what */
3401 }
3402
3403 /*
3404 * SPC freeze handling for the SDMA engines. Called after the SPC is unfrozen.
3405 *
3406 * The SPC freeze acts like a SDMA halt and a hardware clean combined. All
3407 * that is left is a software clean. We could do it after the SPC is fully
3408 * frozen, but then we'd have to add another state to wait for the unfreeze.
3409 * Instead, just defer the software clean until the unfreeze step.
3410 */
sdma_unfreeze(struct hfi1_devdata * dd)3411 void sdma_unfreeze(struct hfi1_devdata *dd)
3412 {
3413 int i;
3414
3415 /* tell all engines start freeze clean up */
3416 for (i = 0; i < dd->num_sdma; i++)
3417 sdma_process_event(&dd->per_sdma[i],
3418 sdma_event_e82_hw_unfreeze);
3419 }
3420
3421 /**
3422 * _sdma_engine_progress_schedule() - schedule progress on engine
3423 * @sde: sdma_engine to schedule progress
3424 *
3425 */
_sdma_engine_progress_schedule(struct sdma_engine * sde)3426 void _sdma_engine_progress_schedule(
3427 struct sdma_engine *sde)
3428 {
3429 trace_hfi1_sdma_engine_progress(sde, sde->progress_mask);
3430 /* assume we have selected a good cpu */
3431 write_csr(sde->dd,
3432 CCE_INT_FORCE + (8 * (IS_SDMA_START / 64)),
3433 sde->progress_mask);
3434 }
3435