1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/debugfs.h>
34 #include <linux/highmem.h>
35 #include <linux/module.h>
36 #include <linux/init.h>
37 #include <linux/errno.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #if defined(CONFIG_X86)
42 #include <asm/pat.h>
43 #endif
44 #include <linux/sched.h>
45 #include <linux/sched/mm.h>
46 #include <linux/sched/task.h>
47 #include <linux/delay.h>
48 #include <rdma/ib_user_verbs.h>
49 #include <rdma/ib_addr.h>
50 #include <rdma/ib_cache.h>
51 #include <linux/mlx5/port.h>
52 #include <linux/mlx5/vport.h>
53 #include <linux/list.h>
54 #include <rdma/ib_smi.h>
55 #include <rdma/ib_umem.h>
56 #include <linux/in.h>
57 #include <linux/etherdevice.h>
58 #include <linux/mlx5/fs.h>
59 #include <linux/mlx5/vport.h>
60 #include "mlx5_ib.h"
61 #include "cmd.h"
62 #include <linux/mlx5/vport.h>
63
64 #define DRIVER_NAME "mlx5_ib"
65 #define DRIVER_VERSION "5.0-0"
66
67 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
68 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
69 MODULE_LICENSE("Dual BSD/GPL");
70
71 static char mlx5_version[] =
72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
73 DRIVER_VERSION "\n";
74
75 enum {
76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
77 };
78
79 static enum rdma_link_layer
mlx5_port_type_cap_to_rdma_ll(int port_type_cap)80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
81 {
82 switch (port_type_cap) {
83 case MLX5_CAP_PORT_TYPE_IB:
84 return IB_LINK_LAYER_INFINIBAND;
85 case MLX5_CAP_PORT_TYPE_ETH:
86 return IB_LINK_LAYER_ETHERNET;
87 default:
88 return IB_LINK_LAYER_UNSPECIFIED;
89 }
90 }
91
92 static enum rdma_link_layer
mlx5_ib_port_link_layer(struct ib_device * device,u8 port_num)93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
94 {
95 struct mlx5_ib_dev *dev = to_mdev(device);
96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
97
98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
99 }
100
get_port_state(struct ib_device * ibdev,u8 port_num,enum ib_port_state * state)101 static int get_port_state(struct ib_device *ibdev,
102 u8 port_num,
103 enum ib_port_state *state)
104 {
105 struct ib_port_attr attr;
106 int ret;
107
108 memset(&attr, 0, sizeof(attr));
109 ret = mlx5_ib_query_port(ibdev, port_num, &attr);
110 if (!ret)
111 *state = attr.state;
112 return ret;
113 }
114
mlx5_netdev_event(struct notifier_block * this,unsigned long event,void * ptr)115 static int mlx5_netdev_event(struct notifier_block *this,
116 unsigned long event, void *ptr)
117 {
118 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
119 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
120 roce.nb);
121
122 switch (event) {
123 case NETDEV_REGISTER:
124 case NETDEV_UNREGISTER:
125 write_lock(&ibdev->roce.netdev_lock);
126 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
127 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
128 NULL : ndev;
129 write_unlock(&ibdev->roce.netdev_lock);
130 break;
131
132 case NETDEV_CHANGE:
133 case NETDEV_UP:
134 case NETDEV_DOWN: {
135 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
136 struct net_device *upper = NULL;
137
138 if (lag_ndev) {
139 upper = netdev_master_upper_dev_get(lag_ndev);
140 dev_put(lag_ndev);
141 }
142
143 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
144 && ibdev->ib_active) {
145 struct ib_event ibev = { };
146 enum ib_port_state port_state;
147
148 if (get_port_state(&ibdev->ib_dev, 1, &port_state))
149 return NOTIFY_DONE;
150
151 if (ibdev->roce.last_port_state == port_state)
152 return NOTIFY_DONE;
153
154 ibdev->roce.last_port_state = port_state;
155 ibev.device = &ibdev->ib_dev;
156 if (port_state == IB_PORT_DOWN)
157 ibev.event = IB_EVENT_PORT_ERR;
158 else if (port_state == IB_PORT_ACTIVE)
159 ibev.event = IB_EVENT_PORT_ACTIVE;
160 else
161 return NOTIFY_DONE;
162
163 ibev.element.port_num = 1;
164 ib_dispatch_event(&ibev);
165 }
166 break;
167 }
168
169 default:
170 break;
171 }
172
173 return NOTIFY_DONE;
174 }
175
mlx5_ib_get_netdev(struct ib_device * device,u8 port_num)176 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
177 u8 port_num)
178 {
179 struct mlx5_ib_dev *ibdev = to_mdev(device);
180 struct net_device *ndev;
181
182 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
183 if (ndev)
184 return ndev;
185
186 /* Ensure ndev does not disappear before we invoke dev_hold()
187 */
188 read_lock(&ibdev->roce.netdev_lock);
189 ndev = ibdev->roce.netdev;
190 if (ndev)
191 dev_hold(ndev);
192 read_unlock(&ibdev->roce.netdev_lock);
193
194 return ndev;
195 }
196
translate_eth_proto_oper(u32 eth_proto_oper,u8 * active_speed,u8 * active_width)197 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
198 u8 *active_width)
199 {
200 switch (eth_proto_oper) {
201 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
202 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
203 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
204 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
205 *active_width = IB_WIDTH_1X;
206 *active_speed = IB_SPEED_SDR;
207 break;
208 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
209 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
210 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
211 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
212 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
213 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
214 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
215 *active_width = IB_WIDTH_1X;
216 *active_speed = IB_SPEED_QDR;
217 break;
218 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
219 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
220 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
221 *active_width = IB_WIDTH_1X;
222 *active_speed = IB_SPEED_EDR;
223 break;
224 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
225 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
226 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
227 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
228 *active_width = IB_WIDTH_4X;
229 *active_speed = IB_SPEED_QDR;
230 break;
231 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
232 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
233 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
234 *active_width = IB_WIDTH_1X;
235 *active_speed = IB_SPEED_HDR;
236 break;
237 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
238 *active_width = IB_WIDTH_4X;
239 *active_speed = IB_SPEED_FDR;
240 break;
241 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
242 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
243 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
244 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
245 *active_width = IB_WIDTH_4X;
246 *active_speed = IB_SPEED_EDR;
247 break;
248 default:
249 return -EINVAL;
250 }
251
252 return 0;
253 }
254
mlx5_query_port_roce(struct ib_device * device,u8 port_num,struct ib_port_attr * props)255 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
256 struct ib_port_attr *props)
257 {
258 struct mlx5_ib_dev *dev = to_mdev(device);
259 struct mlx5_core_dev *mdev = dev->mdev;
260 struct net_device *ndev, *upper;
261 enum ib_mtu ndev_ib_mtu;
262 u16 qkey_viol_cntr;
263 u32 eth_prot_oper;
264 int err;
265
266 /* Possible bad flows are checked before filling out props so in case
267 * of an error it will still be zeroed out.
268 */
269 err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper, port_num);
270 if (err)
271 return err;
272
273 props->active_width = IB_WIDTH_4X;
274 props->active_speed = IB_SPEED_QDR;
275
276 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
277 &props->active_width);
278
279 props->port_cap_flags |= IB_PORT_CM_SUP;
280 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
281
282 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
283 roce_address_table_size);
284 props->max_mtu = IB_MTU_4096;
285 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
286 props->pkey_tbl_len = 1;
287 props->state = IB_PORT_DOWN;
288 props->phys_state = 3;
289
290 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
291 props->qkey_viol_cntr = qkey_viol_cntr;
292
293 ndev = mlx5_ib_get_netdev(device, port_num);
294 if (!ndev)
295 return 0;
296
297 if (mlx5_lag_is_active(dev->mdev)) {
298 rcu_read_lock();
299 upper = netdev_master_upper_dev_get_rcu(ndev);
300 if (upper) {
301 dev_put(ndev);
302 ndev = upper;
303 dev_hold(ndev);
304 }
305 rcu_read_unlock();
306 }
307
308 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
309 props->state = IB_PORT_ACTIVE;
310 props->phys_state = 5;
311 }
312
313 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
314
315 dev_put(ndev);
316
317 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
318 return 0;
319 }
320
set_roce_addr(struct mlx5_ib_dev * dev,u8 port_num,unsigned int index,const union ib_gid * gid,const struct ib_gid_attr * attr)321 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
322 unsigned int index, const union ib_gid *gid,
323 const struct ib_gid_attr *attr)
324 {
325 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
326 u8 roce_version = 0;
327 u8 roce_l3_type = 0;
328 bool vlan = false;
329 u8 mac[ETH_ALEN];
330 u16 vlan_id = 0;
331
332 if (gid) {
333 gid_type = attr->gid_type;
334 ether_addr_copy(mac, attr->ndev->dev_addr);
335
336 if (is_vlan_dev(attr->ndev)) {
337 vlan = true;
338 vlan_id = vlan_dev_vlan_id(attr->ndev);
339 }
340 }
341
342 switch (gid_type) {
343 case IB_GID_TYPE_IB:
344 roce_version = MLX5_ROCE_VERSION_1;
345 break;
346 case IB_GID_TYPE_ROCE_UDP_ENCAP:
347 roce_version = MLX5_ROCE_VERSION_2;
348 if (ipv6_addr_v4mapped((void *)gid))
349 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
350 else
351 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
352 break;
353
354 default:
355 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
356 }
357
358 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
359 roce_l3_type, gid->raw, mac, vlan,
360 vlan_id);
361 }
362
mlx5_ib_add_gid(struct ib_device * device,u8 port_num,unsigned int index,const union ib_gid * gid,const struct ib_gid_attr * attr,__always_unused void ** context)363 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
364 unsigned int index, const union ib_gid *gid,
365 const struct ib_gid_attr *attr,
366 __always_unused void **context)
367 {
368 return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
369 }
370
mlx5_ib_del_gid(struct ib_device * device,u8 port_num,unsigned int index,__always_unused void ** context)371 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
372 unsigned int index, __always_unused void **context)
373 {
374 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
375 }
376
mlx5_get_roce_udp_sport(struct mlx5_ib_dev * dev,u8 port_num,int index)377 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
378 int index)
379 {
380 struct ib_gid_attr attr;
381 union ib_gid gid;
382
383 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
384 return 0;
385
386 if (!attr.ndev)
387 return 0;
388
389 dev_put(attr.ndev);
390
391 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
392 return 0;
393
394 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
395 }
396
mlx5_get_roce_gid_type(struct mlx5_ib_dev * dev,u8 port_num,int index,enum ib_gid_type * gid_type)397 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
398 int index, enum ib_gid_type *gid_type)
399 {
400 struct ib_gid_attr attr;
401 union ib_gid gid;
402 int ret;
403
404 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
405 if (ret)
406 return ret;
407
408 if (!attr.ndev)
409 return -ENODEV;
410
411 dev_put(attr.ndev);
412
413 *gid_type = attr.gid_type;
414
415 return 0;
416 }
417
mlx5_use_mad_ifc(struct mlx5_ib_dev * dev)418 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
419 {
420 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
421 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
422 return 0;
423 }
424
425 enum {
426 MLX5_VPORT_ACCESS_METHOD_MAD,
427 MLX5_VPORT_ACCESS_METHOD_HCA,
428 MLX5_VPORT_ACCESS_METHOD_NIC,
429 };
430
mlx5_get_vport_access_method(struct ib_device * ibdev)431 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
432 {
433 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
434 return MLX5_VPORT_ACCESS_METHOD_MAD;
435
436 if (mlx5_ib_port_link_layer(ibdev, 1) ==
437 IB_LINK_LAYER_ETHERNET)
438 return MLX5_VPORT_ACCESS_METHOD_NIC;
439
440 return MLX5_VPORT_ACCESS_METHOD_HCA;
441 }
442
get_atomic_caps(struct mlx5_ib_dev * dev,struct ib_device_attr * props)443 static void get_atomic_caps(struct mlx5_ib_dev *dev,
444 struct ib_device_attr *props)
445 {
446 u8 tmp;
447 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
448 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
449 u8 atomic_req_8B_endianness_mode =
450 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
451
452 /* Check if HW supports 8 bytes standard atomic operations and capable
453 * of host endianness respond
454 */
455 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
456 if (((atomic_operations & tmp) == tmp) &&
457 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
458 (atomic_req_8B_endianness_mode)) {
459 props->atomic_cap = IB_ATOMIC_HCA;
460 } else {
461 props->atomic_cap = IB_ATOMIC_NONE;
462 }
463 }
464
mlx5_query_system_image_guid(struct ib_device * ibdev,__be64 * sys_image_guid)465 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
466 __be64 *sys_image_guid)
467 {
468 struct mlx5_ib_dev *dev = to_mdev(ibdev);
469 struct mlx5_core_dev *mdev = dev->mdev;
470 u64 tmp;
471 int err;
472
473 switch (mlx5_get_vport_access_method(ibdev)) {
474 case MLX5_VPORT_ACCESS_METHOD_MAD:
475 return mlx5_query_mad_ifc_system_image_guid(ibdev,
476 sys_image_guid);
477
478 case MLX5_VPORT_ACCESS_METHOD_HCA:
479 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
480 break;
481
482 case MLX5_VPORT_ACCESS_METHOD_NIC:
483 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
484 break;
485
486 default:
487 return -EINVAL;
488 }
489
490 if (!err)
491 *sys_image_guid = cpu_to_be64(tmp);
492
493 return err;
494
495 }
496
mlx5_query_max_pkeys(struct ib_device * ibdev,u16 * max_pkeys)497 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
498 u16 *max_pkeys)
499 {
500 struct mlx5_ib_dev *dev = to_mdev(ibdev);
501 struct mlx5_core_dev *mdev = dev->mdev;
502
503 switch (mlx5_get_vport_access_method(ibdev)) {
504 case MLX5_VPORT_ACCESS_METHOD_MAD:
505 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
506
507 case MLX5_VPORT_ACCESS_METHOD_HCA:
508 case MLX5_VPORT_ACCESS_METHOD_NIC:
509 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
510 pkey_table_size));
511 return 0;
512
513 default:
514 return -EINVAL;
515 }
516 }
517
mlx5_query_vendor_id(struct ib_device * ibdev,u32 * vendor_id)518 static int mlx5_query_vendor_id(struct ib_device *ibdev,
519 u32 *vendor_id)
520 {
521 struct mlx5_ib_dev *dev = to_mdev(ibdev);
522
523 switch (mlx5_get_vport_access_method(ibdev)) {
524 case MLX5_VPORT_ACCESS_METHOD_MAD:
525 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
526
527 case MLX5_VPORT_ACCESS_METHOD_HCA:
528 case MLX5_VPORT_ACCESS_METHOD_NIC:
529 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
530
531 default:
532 return -EINVAL;
533 }
534 }
535
mlx5_query_node_guid(struct mlx5_ib_dev * dev,__be64 * node_guid)536 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
537 __be64 *node_guid)
538 {
539 u64 tmp;
540 int err;
541
542 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
543 case MLX5_VPORT_ACCESS_METHOD_MAD:
544 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
545
546 case MLX5_VPORT_ACCESS_METHOD_HCA:
547 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
548 break;
549
550 case MLX5_VPORT_ACCESS_METHOD_NIC:
551 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
552 break;
553
554 default:
555 return -EINVAL;
556 }
557
558 if (!err)
559 *node_guid = cpu_to_be64(tmp);
560
561 return err;
562 }
563
564 struct mlx5_reg_node_desc {
565 u8 desc[IB_DEVICE_NODE_DESC_MAX];
566 };
567
mlx5_query_node_desc(struct mlx5_ib_dev * dev,char * node_desc)568 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
569 {
570 struct mlx5_reg_node_desc in;
571
572 if (mlx5_use_mad_ifc(dev))
573 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
574
575 memset(&in, 0, sizeof(in));
576
577 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
578 sizeof(struct mlx5_reg_node_desc),
579 MLX5_REG_NODE_DESC, 0, 0);
580 }
581
mlx5_ib_query_device(struct ib_device * ibdev,struct ib_device_attr * props,struct ib_udata * uhw)582 static int mlx5_ib_query_device(struct ib_device *ibdev,
583 struct ib_device_attr *props,
584 struct ib_udata *uhw)
585 {
586 struct mlx5_ib_dev *dev = to_mdev(ibdev);
587 struct mlx5_core_dev *mdev = dev->mdev;
588 int err = -ENOMEM;
589 int max_sq_desc;
590 int max_rq_sg;
591 int max_sq_sg;
592 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
593 struct mlx5_ib_query_device_resp resp = {};
594 size_t resp_len;
595 u64 max_tso;
596
597 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
598 if (uhw->outlen && uhw->outlen < resp_len)
599 return -EINVAL;
600 else
601 resp.response_length = resp_len;
602
603 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
604 return -EINVAL;
605
606 memset(props, 0, sizeof(*props));
607 err = mlx5_query_system_image_guid(ibdev,
608 &props->sys_image_guid);
609 if (err)
610 return err;
611
612 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
613 if (err)
614 return err;
615
616 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
617 if (err)
618 return err;
619
620 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
621 (fw_rev_min(dev->mdev) << 16) |
622 fw_rev_sub(dev->mdev);
623 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
624 IB_DEVICE_PORT_ACTIVE_EVENT |
625 IB_DEVICE_SYS_IMAGE_GUID |
626 IB_DEVICE_RC_RNR_NAK_GEN;
627
628 if (MLX5_CAP_GEN(mdev, pkv))
629 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
630 if (MLX5_CAP_GEN(mdev, qkv))
631 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
632 if (MLX5_CAP_GEN(mdev, apm))
633 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
634 if (MLX5_CAP_GEN(mdev, xrc))
635 props->device_cap_flags |= IB_DEVICE_XRC;
636 if (MLX5_CAP_GEN(mdev, imaicl)) {
637 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
638 IB_DEVICE_MEM_WINDOW_TYPE_2B;
639 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
640 /* We support 'Gappy' memory registration too */
641 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
642 }
643 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
644 if (MLX5_CAP_GEN(mdev, sho)) {
645 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
646 /* At this stage no support for signature handover */
647 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
648 IB_PROT_T10DIF_TYPE_2 |
649 IB_PROT_T10DIF_TYPE_3;
650 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
651 IB_GUARD_T10DIF_CSUM;
652 }
653 if (MLX5_CAP_GEN(mdev, block_lb_mc))
654 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
655
656 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
657 if (MLX5_CAP_ETH(mdev, csum_cap)) {
658 /* Legacy bit to support old userspace libraries */
659 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
660 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
661 }
662
663 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
664 props->raw_packet_caps |=
665 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
666
667 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
668 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
669 if (max_tso) {
670 resp.tso_caps.max_tso = 1 << max_tso;
671 resp.tso_caps.supported_qpts |=
672 1 << IB_QPT_RAW_PACKET;
673 resp.response_length += sizeof(resp.tso_caps);
674 }
675 }
676
677 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
678 resp.rss_caps.rx_hash_function =
679 MLX5_RX_HASH_FUNC_TOEPLITZ;
680 resp.rss_caps.rx_hash_fields_mask =
681 MLX5_RX_HASH_SRC_IPV4 |
682 MLX5_RX_HASH_DST_IPV4 |
683 MLX5_RX_HASH_SRC_IPV6 |
684 MLX5_RX_HASH_DST_IPV6 |
685 MLX5_RX_HASH_SRC_PORT_TCP |
686 MLX5_RX_HASH_DST_PORT_TCP |
687 MLX5_RX_HASH_SRC_PORT_UDP |
688 MLX5_RX_HASH_DST_PORT_UDP;
689 resp.response_length += sizeof(resp.rss_caps);
690 }
691 } else {
692 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
693 resp.response_length += sizeof(resp.tso_caps);
694 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
695 resp.response_length += sizeof(resp.rss_caps);
696 }
697
698 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
699 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
700 props->device_cap_flags |= IB_DEVICE_UD_TSO;
701 }
702
703 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
704 MLX5_CAP_GEN(dev->mdev, general_notification_event))
705 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
706
707 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
708 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
709 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
710
711 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
712 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
713 /* Legacy bit to support old userspace libraries */
714 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
715 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
716 }
717
718 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
719 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
720
721 props->vendor_part_id = mdev->pdev->device;
722 props->hw_ver = mdev->pdev->revision;
723
724 props->max_mr_size = ~0ull;
725 props->page_size_cap = ~(min_page_size - 1);
726 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
727 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
728 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
729 sizeof(struct mlx5_wqe_data_seg);
730 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
731 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
732 sizeof(struct mlx5_wqe_raddr_seg)) /
733 sizeof(struct mlx5_wqe_data_seg);
734 props->max_sge = min(max_rq_sg, max_sq_sg);
735 props->max_sge_rd = MLX5_MAX_SGE_RD;
736 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
737 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
738 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
739 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
740 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
741 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
742 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
743 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
744 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
745 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
746 props->max_srq_sge = max_rq_sg - 1;
747 props->max_fast_reg_page_list_len =
748 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
749 get_atomic_caps(dev, props);
750 props->masked_atomic_cap = IB_ATOMIC_NONE;
751 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
752 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
753 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
754 props->max_mcast_grp;
755 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
756 props->max_ah = INT_MAX;
757 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
758 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
759
760 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
761 if (MLX5_CAP_GEN(mdev, pg))
762 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
763 props->odp_caps = dev->odp_caps;
764 #endif
765
766 if (MLX5_CAP_GEN(mdev, cd))
767 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
768
769 if (!mlx5_core_is_pf(mdev))
770 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
771
772 if (mlx5_ib_port_link_layer(ibdev, 1) ==
773 IB_LINK_LAYER_ETHERNET) {
774 props->rss_caps.max_rwq_indirection_tables =
775 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
776 props->rss_caps.max_rwq_indirection_table_size =
777 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
778 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
779 props->max_wq_type_rq =
780 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
781 }
782
783 if (MLX5_CAP_GEN(mdev, tag_matching)) {
784 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
785 props->tm_caps.max_num_tags =
786 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
787 props->tm_caps.flags = IB_TM_CAP_RC;
788 props->tm_caps.max_ops =
789 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
790 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
791 }
792
793 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
794 resp.cqe_comp_caps.max_num =
795 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
796 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
797 resp.cqe_comp_caps.supported_format =
798 MLX5_IB_CQE_RES_FORMAT_HASH |
799 MLX5_IB_CQE_RES_FORMAT_CSUM;
800 resp.response_length += sizeof(resp.cqe_comp_caps);
801 }
802
803 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
804 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
805 MLX5_CAP_GEN(mdev, qos)) {
806 resp.packet_pacing_caps.qp_rate_limit_max =
807 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
808 resp.packet_pacing_caps.qp_rate_limit_min =
809 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
810 resp.packet_pacing_caps.supported_qpts |=
811 1 << IB_QPT_RAW_PACKET;
812 }
813 resp.response_length += sizeof(resp.packet_pacing_caps);
814 }
815
816 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
817 uhw->outlen)) {
818 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
819 resp.mlx5_ib_support_multi_pkt_send_wqes =
820 MLX5_IB_ALLOW_MPW;
821
822 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
823 resp.mlx5_ib_support_multi_pkt_send_wqes |=
824 MLX5_IB_SUPPORT_EMPW;
825
826 resp.response_length +=
827 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
828 }
829
830 if (field_avail(typeof(resp), reserved, uhw->outlen))
831 resp.response_length += sizeof(resp.reserved);
832
833 if (field_avail(typeof(resp), sw_parsing_caps,
834 uhw->outlen)) {
835 resp.response_length += sizeof(resp.sw_parsing_caps);
836 if (MLX5_CAP_ETH(mdev, swp)) {
837 resp.sw_parsing_caps.sw_parsing_offloads |=
838 MLX5_IB_SW_PARSING;
839
840 if (MLX5_CAP_ETH(mdev, swp_csum))
841 resp.sw_parsing_caps.sw_parsing_offloads |=
842 MLX5_IB_SW_PARSING_CSUM;
843
844 if (MLX5_CAP_ETH(mdev, swp_lso))
845 resp.sw_parsing_caps.sw_parsing_offloads |=
846 MLX5_IB_SW_PARSING_LSO;
847
848 if (resp.sw_parsing_caps.sw_parsing_offloads)
849 resp.sw_parsing_caps.supported_qpts =
850 BIT(IB_QPT_RAW_PACKET);
851 }
852 }
853
854 if (uhw->outlen) {
855 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
856
857 if (err)
858 return err;
859 }
860
861 return 0;
862 }
863
864 enum mlx5_ib_width {
865 MLX5_IB_WIDTH_1X = 1 << 0,
866 MLX5_IB_WIDTH_2X = 1 << 1,
867 MLX5_IB_WIDTH_4X = 1 << 2,
868 MLX5_IB_WIDTH_8X = 1 << 3,
869 MLX5_IB_WIDTH_12X = 1 << 4
870 };
871
translate_active_width(struct ib_device * ibdev,u8 active_width,u8 * ib_width)872 static void translate_active_width(struct ib_device *ibdev, u8 active_width,
873 u8 *ib_width)
874 {
875 struct mlx5_ib_dev *dev = to_mdev(ibdev);
876
877 if (active_width & MLX5_IB_WIDTH_1X)
878 *ib_width = IB_WIDTH_1X;
879 else if (active_width & MLX5_IB_WIDTH_4X)
880 *ib_width = IB_WIDTH_4X;
881 else if (active_width & MLX5_IB_WIDTH_8X)
882 *ib_width = IB_WIDTH_8X;
883 else if (active_width & MLX5_IB_WIDTH_12X)
884 *ib_width = IB_WIDTH_12X;
885 else {
886 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
887 (int)active_width);
888 *ib_width = IB_WIDTH_4X;
889 }
890
891 return;
892 }
893
mlx5_mtu_to_ib_mtu(int mtu)894 static int mlx5_mtu_to_ib_mtu(int mtu)
895 {
896 switch (mtu) {
897 case 256: return 1;
898 case 512: return 2;
899 case 1024: return 3;
900 case 2048: return 4;
901 case 4096: return 5;
902 default:
903 pr_warn("invalid mtu\n");
904 return -1;
905 }
906 }
907
908 enum ib_max_vl_num {
909 __IB_MAX_VL_0 = 1,
910 __IB_MAX_VL_0_1 = 2,
911 __IB_MAX_VL_0_3 = 3,
912 __IB_MAX_VL_0_7 = 4,
913 __IB_MAX_VL_0_14 = 5,
914 };
915
916 enum mlx5_vl_hw_cap {
917 MLX5_VL_HW_0 = 1,
918 MLX5_VL_HW_0_1 = 2,
919 MLX5_VL_HW_0_2 = 3,
920 MLX5_VL_HW_0_3 = 4,
921 MLX5_VL_HW_0_4 = 5,
922 MLX5_VL_HW_0_5 = 6,
923 MLX5_VL_HW_0_6 = 7,
924 MLX5_VL_HW_0_7 = 8,
925 MLX5_VL_HW_0_14 = 15
926 };
927
translate_max_vl_num(struct ib_device * ibdev,u8 vl_hw_cap,u8 * max_vl_num)928 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
929 u8 *max_vl_num)
930 {
931 switch (vl_hw_cap) {
932 case MLX5_VL_HW_0:
933 *max_vl_num = __IB_MAX_VL_0;
934 break;
935 case MLX5_VL_HW_0_1:
936 *max_vl_num = __IB_MAX_VL_0_1;
937 break;
938 case MLX5_VL_HW_0_3:
939 *max_vl_num = __IB_MAX_VL_0_3;
940 break;
941 case MLX5_VL_HW_0_7:
942 *max_vl_num = __IB_MAX_VL_0_7;
943 break;
944 case MLX5_VL_HW_0_14:
945 *max_vl_num = __IB_MAX_VL_0_14;
946 break;
947
948 default:
949 return -EINVAL;
950 }
951
952 return 0;
953 }
954
mlx5_query_hca_port(struct ib_device * ibdev,u8 port,struct ib_port_attr * props)955 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
956 struct ib_port_attr *props)
957 {
958 struct mlx5_ib_dev *dev = to_mdev(ibdev);
959 struct mlx5_core_dev *mdev = dev->mdev;
960 struct mlx5_hca_vport_context *rep;
961 u16 max_mtu;
962 u16 oper_mtu;
963 int err;
964 u8 ib_link_width_oper;
965 u8 vl_hw_cap;
966
967 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
968 if (!rep) {
969 err = -ENOMEM;
970 goto out;
971 }
972
973 /* props being zeroed by the caller, avoid zeroing it here */
974
975 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
976 if (err)
977 goto out;
978
979 props->lid = rep->lid;
980 props->lmc = rep->lmc;
981 props->sm_lid = rep->sm_lid;
982 props->sm_sl = rep->sm_sl;
983 props->state = rep->vport_state;
984 props->phys_state = rep->port_physical_state;
985 props->port_cap_flags = rep->cap_mask1;
986 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
987 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
988 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
989 props->bad_pkey_cntr = rep->pkey_violation_counter;
990 props->qkey_viol_cntr = rep->qkey_violation_counter;
991 props->subnet_timeout = rep->subnet_timeout;
992 props->init_type_reply = rep->init_type_reply;
993 props->grh_required = rep->grh_required;
994
995 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
996 if (err)
997 goto out;
998
999 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1000
1001 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1002 if (err)
1003 goto out;
1004
1005 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1006
1007 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1008
1009 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1010
1011 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1012
1013 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1014 if (err)
1015 goto out;
1016
1017 err = translate_max_vl_num(ibdev, vl_hw_cap,
1018 &props->max_vl_num);
1019 out:
1020 kfree(rep);
1021 return err;
1022 }
1023
mlx5_ib_query_port(struct ib_device * ibdev,u8 port,struct ib_port_attr * props)1024 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1025 struct ib_port_attr *props)
1026 {
1027 unsigned int count;
1028 int ret;
1029
1030 switch (mlx5_get_vport_access_method(ibdev)) {
1031 case MLX5_VPORT_ACCESS_METHOD_MAD:
1032 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1033 break;
1034
1035 case MLX5_VPORT_ACCESS_METHOD_HCA:
1036 ret = mlx5_query_hca_port(ibdev, port, props);
1037 break;
1038
1039 case MLX5_VPORT_ACCESS_METHOD_NIC:
1040 ret = mlx5_query_port_roce(ibdev, port, props);
1041 break;
1042
1043 default:
1044 ret = -EINVAL;
1045 }
1046
1047 if (!ret && props) {
1048 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev);
1049 props->gid_tbl_len -= count;
1050 }
1051 return ret;
1052 }
1053
mlx5_ib_query_gid(struct ib_device * ibdev,u8 port,int index,union ib_gid * gid)1054 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1055 union ib_gid *gid)
1056 {
1057 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1058 struct mlx5_core_dev *mdev = dev->mdev;
1059
1060 switch (mlx5_get_vport_access_method(ibdev)) {
1061 case MLX5_VPORT_ACCESS_METHOD_MAD:
1062 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1063
1064 case MLX5_VPORT_ACCESS_METHOD_HCA:
1065 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1066
1067 default:
1068 return -EINVAL;
1069 }
1070
1071 }
1072
mlx5_ib_query_pkey(struct ib_device * ibdev,u8 port,u16 index,u16 * pkey)1073 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1074 u16 *pkey)
1075 {
1076 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1077 struct mlx5_core_dev *mdev = dev->mdev;
1078
1079 switch (mlx5_get_vport_access_method(ibdev)) {
1080 case MLX5_VPORT_ACCESS_METHOD_MAD:
1081 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1082
1083 case MLX5_VPORT_ACCESS_METHOD_HCA:
1084 case MLX5_VPORT_ACCESS_METHOD_NIC:
1085 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
1086 pkey);
1087 default:
1088 return -EINVAL;
1089 }
1090 }
1091
mlx5_ib_modify_device(struct ib_device * ibdev,int mask,struct ib_device_modify * props)1092 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1093 struct ib_device_modify *props)
1094 {
1095 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1096 struct mlx5_reg_node_desc in;
1097 struct mlx5_reg_node_desc out;
1098 int err;
1099
1100 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1101 return -EOPNOTSUPP;
1102
1103 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1104 return 0;
1105
1106 /*
1107 * If possible, pass node desc to FW, so it can generate
1108 * a 144 trap. If cmd fails, just ignore.
1109 */
1110 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1111 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1112 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1113 if (err)
1114 return err;
1115
1116 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1117
1118 return err;
1119 }
1120
set_port_caps_atomic(struct mlx5_ib_dev * dev,u8 port_num,u32 mask,u32 value)1121 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1122 u32 value)
1123 {
1124 struct mlx5_hca_vport_context ctx = {};
1125 int err;
1126
1127 err = mlx5_query_hca_vport_context(dev->mdev, 0,
1128 port_num, 0, &ctx);
1129 if (err)
1130 return err;
1131
1132 if (~ctx.cap_mask1_perm & mask) {
1133 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1134 mask, ctx.cap_mask1_perm);
1135 return -EINVAL;
1136 }
1137
1138 ctx.cap_mask1 = value;
1139 ctx.cap_mask1_perm = mask;
1140 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0,
1141 port_num, 0, &ctx);
1142
1143 return err;
1144 }
1145
mlx5_ib_modify_port(struct ib_device * ibdev,u8 port,int mask,struct ib_port_modify * props)1146 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1147 struct ib_port_modify *props)
1148 {
1149 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1150 struct ib_port_attr attr;
1151 u32 tmp;
1152 int err;
1153 u32 change_mask;
1154 u32 value;
1155 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1156 IB_LINK_LAYER_INFINIBAND);
1157
1158 /* CM layer calls ib_modify_port() regardless of the link layer. For
1159 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1160 */
1161 if (!is_ib)
1162 return 0;
1163
1164 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1165 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1166 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1167 return set_port_caps_atomic(dev, port, change_mask, value);
1168 }
1169
1170 mutex_lock(&dev->cap_mask_mutex);
1171
1172 err = ib_query_port(ibdev, port, &attr);
1173 if (err)
1174 goto out;
1175
1176 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1177 ~props->clr_port_cap_mask;
1178
1179 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1180
1181 out:
1182 mutex_unlock(&dev->cap_mask_mutex);
1183 return err;
1184 }
1185
print_lib_caps(struct mlx5_ib_dev * dev,u64 caps)1186 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1187 {
1188 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1189 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1190 }
1191
calc_total_bfregs(struct mlx5_ib_dev * dev,bool lib_uar_4k,struct mlx5_ib_alloc_ucontext_req_v2 * req,u32 * num_sys_pages)1192 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1193 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1194 u32 *num_sys_pages)
1195 {
1196 int uars_per_sys_page;
1197 int bfregs_per_sys_page;
1198 int ref_bfregs = req->total_num_bfregs;
1199
1200 if (req->total_num_bfregs == 0)
1201 return -EINVAL;
1202
1203 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1204 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1205
1206 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1207 return -ENOMEM;
1208
1209 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1210 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1211 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1212 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1213
1214 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1215 return -EINVAL;
1216
1217 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, using %d sys pages\n",
1218 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1219 lib_uar_4k ? "yes" : "no", ref_bfregs,
1220 req->total_num_bfregs, *num_sys_pages);
1221
1222 return 0;
1223 }
1224
allocate_uars(struct mlx5_ib_dev * dev,struct mlx5_ib_ucontext * context)1225 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1226 {
1227 struct mlx5_bfreg_info *bfregi;
1228 int err;
1229 int i;
1230
1231 bfregi = &context->bfregi;
1232 for (i = 0; i < bfregi->num_sys_pages; i++) {
1233 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1234 if (err)
1235 goto error;
1236
1237 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1238 }
1239 return 0;
1240
1241 error:
1242 for (--i; i >= 0; i--)
1243 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1244 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1245
1246 return err;
1247 }
1248
deallocate_uars(struct mlx5_ib_dev * dev,struct mlx5_ib_ucontext * context)1249 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1250 {
1251 struct mlx5_bfreg_info *bfregi;
1252 int err;
1253 int i;
1254
1255 bfregi = &context->bfregi;
1256 for (i = 0; i < bfregi->num_sys_pages; i++) {
1257 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1258 if (err) {
1259 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1260 return err;
1261 }
1262 }
1263 return 0;
1264 }
1265
mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev * dev,u32 * tdn)1266 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1267 {
1268 int err;
1269
1270 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1271 if (err)
1272 return err;
1273
1274 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1275 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1276 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1277 return err;
1278
1279 mutex_lock(&dev->lb_mutex);
1280 dev->user_td++;
1281
1282 if (dev->user_td == 2)
1283 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1284
1285 mutex_unlock(&dev->lb_mutex);
1286 return err;
1287 }
1288
mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev * dev,u32 tdn)1289 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1290 {
1291 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1292
1293 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1294 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1295 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1296 return;
1297
1298 mutex_lock(&dev->lb_mutex);
1299 dev->user_td--;
1300
1301 if (dev->user_td < 2)
1302 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1303
1304 mutex_unlock(&dev->lb_mutex);
1305 }
1306
mlx5_ib_alloc_ucontext(struct ib_device * ibdev,struct ib_udata * udata)1307 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1308 struct ib_udata *udata)
1309 {
1310 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1311 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1312 struct mlx5_ib_alloc_ucontext_resp resp = {};
1313 struct mlx5_ib_ucontext *context;
1314 struct mlx5_bfreg_info *bfregi;
1315 int ver;
1316 int err;
1317 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1318 max_cqe_version);
1319 bool lib_uar_4k;
1320
1321 if (!dev->ib_active)
1322 return ERR_PTR(-EAGAIN);
1323
1324 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1325 ver = 0;
1326 else if (udata->inlen >= min_req_v2)
1327 ver = 2;
1328 else
1329 return ERR_PTR(-EINVAL);
1330
1331 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1332 if (err)
1333 return ERR_PTR(err);
1334
1335 if (req.flags)
1336 return ERR_PTR(-EINVAL);
1337
1338 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1339 return ERR_PTR(-EOPNOTSUPP);
1340
1341 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1342 MLX5_NON_FP_BFREGS_PER_UAR);
1343 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1344 return ERR_PTR(-EINVAL);
1345
1346 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1347 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1348 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1349 resp.cache_line_size = cache_line_size();
1350 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1351 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1352 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1353 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1354 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1355 resp.cqe_version = min_t(__u8,
1356 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1357 req.max_cqe_version);
1358 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1359 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1360 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1361 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1362 resp.response_length = min(offsetof(typeof(resp), response_length) +
1363 sizeof(resp.response_length), udata->outlen);
1364
1365 context = kzalloc(sizeof(*context), GFP_KERNEL);
1366 if (!context)
1367 return ERR_PTR(-ENOMEM);
1368
1369 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1370 bfregi = &context->bfregi;
1371
1372 /* updates req->total_num_bfregs */
1373 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages);
1374 if (err)
1375 goto out_ctx;
1376
1377 mutex_init(&bfregi->lock);
1378 bfregi->lib_uar_4k = lib_uar_4k;
1379 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count),
1380 GFP_KERNEL);
1381 if (!bfregi->count) {
1382 err = -ENOMEM;
1383 goto out_ctx;
1384 }
1385
1386 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1387 sizeof(*bfregi->sys_pages),
1388 GFP_KERNEL);
1389 if (!bfregi->sys_pages) {
1390 err = -ENOMEM;
1391 goto out_count;
1392 }
1393
1394 err = allocate_uars(dev, context);
1395 if (err)
1396 goto out_sys_pages;
1397
1398 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1399 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1400 #endif
1401
1402 context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1403 if (!context->upd_xlt_page) {
1404 err = -ENOMEM;
1405 goto out_uars;
1406 }
1407 mutex_init(&context->upd_xlt_page_mutex);
1408
1409 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1410 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1411 if (err)
1412 goto out_page;
1413 }
1414
1415 INIT_LIST_HEAD(&context->vma_private_list);
1416 mutex_init(&context->vma_private_list_mutex);
1417 INIT_LIST_HEAD(&context->db_page_list);
1418 mutex_init(&context->db_page_mutex);
1419
1420 resp.tot_bfregs = req.total_num_bfregs;
1421 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1422
1423 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1424 resp.response_length += sizeof(resp.cqe_version);
1425
1426 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1427 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1428 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1429 resp.response_length += sizeof(resp.cmds_supp_uhw);
1430 }
1431
1432 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1433 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1434 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1435 resp.eth_min_inline++;
1436 }
1437 resp.response_length += sizeof(resp.eth_min_inline);
1438 }
1439
1440 /*
1441 * We don't want to expose information from the PCI bar that is located
1442 * after 4096 bytes, so if the arch only supports larger pages, let's
1443 * pretend we don't support reading the HCA's core clock. This is also
1444 * forced by mmap function.
1445 */
1446 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1447 if (PAGE_SIZE <= 4096) {
1448 resp.comp_mask |=
1449 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1450 resp.hca_core_clock_offset =
1451 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1452 }
1453 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1454 sizeof(resp.reserved2);
1455 }
1456
1457 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1458 resp.response_length += sizeof(resp.log_uar_size);
1459
1460 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1461 resp.response_length += sizeof(resp.num_uars_per_page);
1462
1463 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1464 if (err)
1465 goto out_td;
1466
1467 bfregi->ver = ver;
1468 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1469 context->cqe_version = resp.cqe_version;
1470 context->lib_caps = req.lib_caps;
1471 print_lib_caps(dev, context->lib_caps);
1472
1473 return &context->ibucontext;
1474
1475 out_td:
1476 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1477 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1478
1479 out_page:
1480 free_page(context->upd_xlt_page);
1481
1482 out_uars:
1483 deallocate_uars(dev, context);
1484
1485 out_sys_pages:
1486 kfree(bfregi->sys_pages);
1487
1488 out_count:
1489 kfree(bfregi->count);
1490
1491 out_ctx:
1492 kfree(context);
1493
1494 return ERR_PTR(err);
1495 }
1496
mlx5_ib_dealloc_ucontext(struct ib_ucontext * ibcontext)1497 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1498 {
1499 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1500 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1501 struct mlx5_bfreg_info *bfregi;
1502
1503 bfregi = &context->bfregi;
1504 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1505 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1506
1507 free_page(context->upd_xlt_page);
1508 deallocate_uars(dev, context);
1509 kfree(bfregi->sys_pages);
1510 kfree(bfregi->count);
1511 kfree(context);
1512
1513 return 0;
1514 }
1515
uar_index2pfn(struct mlx5_ib_dev * dev,struct mlx5_bfreg_info * bfregi,int idx)1516 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1517 struct mlx5_bfreg_info *bfregi,
1518 int idx)
1519 {
1520 int fw_uars_per_page;
1521
1522 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1523
1524 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) +
1525 bfregi->sys_pages[idx] / fw_uars_per_page;
1526 }
1527
get_command(unsigned long offset)1528 static int get_command(unsigned long offset)
1529 {
1530 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1531 }
1532
get_arg(unsigned long offset)1533 static int get_arg(unsigned long offset)
1534 {
1535 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1536 }
1537
get_index(unsigned long offset)1538 static int get_index(unsigned long offset)
1539 {
1540 return get_arg(offset);
1541 }
1542
mlx5_ib_vma_open(struct vm_area_struct * area)1543 static void mlx5_ib_vma_open(struct vm_area_struct *area)
1544 {
1545 /* vma_open is called when a new VMA is created on top of our VMA. This
1546 * is done through either mremap flow or split_vma (usually due to
1547 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1548 * as this VMA is strongly hardware related. Therefore we set the
1549 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1550 * calling us again and trying to do incorrect actions. We assume that
1551 * the original VMA size is exactly a single page, and therefore all
1552 * "splitting" operation will not happen to it.
1553 */
1554 area->vm_ops = NULL;
1555 }
1556
mlx5_ib_vma_close(struct vm_area_struct * area)1557 static void mlx5_ib_vma_close(struct vm_area_struct *area)
1558 {
1559 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1560
1561 /* It's guaranteed that all VMAs opened on a FD are closed before the
1562 * file itself is closed, therefore no sync is needed with the regular
1563 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1564 * However need a sync with accessing the vma as part of
1565 * mlx5_ib_disassociate_ucontext.
1566 * The close operation is usually called under mm->mmap_sem except when
1567 * process is exiting.
1568 * The exiting case is handled explicitly as part of
1569 * mlx5_ib_disassociate_ucontext.
1570 */
1571 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1572
1573 /* setting the vma context pointer to null in the mlx5_ib driver's
1574 * private data, to protect a race condition in
1575 * mlx5_ib_disassociate_ucontext().
1576 */
1577 mlx5_ib_vma_priv_data->vma = NULL;
1578 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1579 list_del(&mlx5_ib_vma_priv_data->list);
1580 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1581 kfree(mlx5_ib_vma_priv_data);
1582 }
1583
1584 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1585 .open = mlx5_ib_vma_open,
1586 .close = mlx5_ib_vma_close
1587 };
1588
mlx5_ib_set_vma_data(struct vm_area_struct * vma,struct mlx5_ib_ucontext * ctx)1589 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1590 struct mlx5_ib_ucontext *ctx)
1591 {
1592 struct mlx5_ib_vma_private_data *vma_prv;
1593 struct list_head *vma_head = &ctx->vma_private_list;
1594
1595 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1596 if (!vma_prv)
1597 return -ENOMEM;
1598
1599 vma_prv->vma = vma;
1600 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
1601 vma->vm_private_data = vma_prv;
1602 vma->vm_ops = &mlx5_ib_vm_ops;
1603
1604 mutex_lock(&ctx->vma_private_list_mutex);
1605 list_add(&vma_prv->list, vma_head);
1606 mutex_unlock(&ctx->vma_private_list_mutex);
1607
1608 return 0;
1609 }
1610
mlx5_ib_disassociate_ucontext(struct ib_ucontext * ibcontext)1611 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1612 {
1613 int ret;
1614 struct vm_area_struct *vma;
1615 struct mlx5_ib_vma_private_data *vma_private, *n;
1616 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1617 struct task_struct *owning_process = NULL;
1618 struct mm_struct *owning_mm = NULL;
1619
1620 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1621 if (!owning_process)
1622 return;
1623
1624 owning_mm = get_task_mm(owning_process);
1625 if (!owning_mm) {
1626 pr_info("no mm, disassociate ucontext is pending task termination\n");
1627 while (1) {
1628 put_task_struct(owning_process);
1629 usleep_range(1000, 2000);
1630 owning_process = get_pid_task(ibcontext->tgid,
1631 PIDTYPE_PID);
1632 if (!owning_process ||
1633 owning_process->state == TASK_DEAD) {
1634 pr_info("disassociate ucontext done, task was terminated\n");
1635 /* in case task was dead need to release the
1636 * task struct.
1637 */
1638 if (owning_process)
1639 put_task_struct(owning_process);
1640 return;
1641 }
1642 }
1643 }
1644
1645 /* need to protect from a race on closing the vma as part of
1646 * mlx5_ib_vma_close.
1647 */
1648 down_write(&owning_mm->mmap_sem);
1649 if (!mmget_still_valid(owning_mm))
1650 goto skip_mm;
1651 mutex_lock(&context->vma_private_list_mutex);
1652 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1653 list) {
1654 vma = vma_private->vma;
1655 ret = zap_vma_ptes(vma, vma->vm_start,
1656 PAGE_SIZE);
1657 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1658 /* context going to be destroyed, should
1659 * not access ops any more.
1660 */
1661 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
1662 vma->vm_ops = NULL;
1663 list_del(&vma_private->list);
1664 kfree(vma_private);
1665 }
1666 mutex_unlock(&context->vma_private_list_mutex);
1667 skip_mm:
1668 up_write(&owning_mm->mmap_sem);
1669 mmput(owning_mm);
1670 put_task_struct(owning_process);
1671 }
1672
mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)1673 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1674 {
1675 switch (cmd) {
1676 case MLX5_IB_MMAP_WC_PAGE:
1677 return "WC";
1678 case MLX5_IB_MMAP_REGULAR_PAGE:
1679 return "best effort WC";
1680 case MLX5_IB_MMAP_NC_PAGE:
1681 return "NC";
1682 default:
1683 return NULL;
1684 }
1685 }
1686
uar_mmap(struct mlx5_ib_dev * dev,enum mlx5_ib_mmap_cmd cmd,struct vm_area_struct * vma,struct mlx5_ib_ucontext * context)1687 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1688 struct vm_area_struct *vma,
1689 struct mlx5_ib_ucontext *context)
1690 {
1691 struct mlx5_bfreg_info *bfregi = &context->bfregi;
1692 int err;
1693 unsigned long idx;
1694 phys_addr_t pfn, pa;
1695 pgprot_t prot;
1696 int uars_per_page;
1697
1698 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1699 return -EINVAL;
1700
1701 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1702 idx = get_index(vma->vm_pgoff);
1703 if (idx % uars_per_page ||
1704 idx * uars_per_page >= bfregi->num_sys_pages) {
1705 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx);
1706 return -EINVAL;
1707 }
1708
1709 switch (cmd) {
1710 case MLX5_IB_MMAP_WC_PAGE:
1711 /* Some architectures don't support WC memory */
1712 #if defined(CONFIG_X86)
1713 if (!pat_enabled())
1714 return -EPERM;
1715 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1716 return -EPERM;
1717 #endif
1718 /* fall through */
1719 case MLX5_IB_MMAP_REGULAR_PAGE:
1720 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1721 prot = pgprot_writecombine(vma->vm_page_prot);
1722 break;
1723 case MLX5_IB_MMAP_NC_PAGE:
1724 prot = pgprot_noncached(vma->vm_page_prot);
1725 break;
1726 default:
1727 return -EINVAL;
1728 }
1729
1730 pfn = uar_index2pfn(dev, bfregi, idx);
1731 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1732
1733 vma->vm_page_prot = prot;
1734 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1735 PAGE_SIZE, vma->vm_page_prot);
1736 if (err) {
1737 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1738 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1739 return -EAGAIN;
1740 }
1741
1742 pa = pfn << PAGE_SHIFT;
1743 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1744 vma->vm_start, &pa);
1745
1746 return mlx5_ib_set_vma_data(vma, context);
1747 }
1748
mlx5_ib_mmap(struct ib_ucontext * ibcontext,struct vm_area_struct * vma)1749 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1750 {
1751 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1752 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1753 unsigned long command;
1754 phys_addr_t pfn;
1755
1756 command = get_command(vma->vm_pgoff);
1757 switch (command) {
1758 case MLX5_IB_MMAP_WC_PAGE:
1759 case MLX5_IB_MMAP_NC_PAGE:
1760 case MLX5_IB_MMAP_REGULAR_PAGE:
1761 return uar_mmap(dev, command, vma, context);
1762
1763 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1764 return -ENOSYS;
1765
1766 case MLX5_IB_MMAP_CORE_CLOCK:
1767 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1768 return -EINVAL;
1769
1770 if (vma->vm_flags & VM_WRITE)
1771 return -EPERM;
1772
1773 /* Don't expose to user-space information it shouldn't have */
1774 if (PAGE_SIZE > 4096)
1775 return -EOPNOTSUPP;
1776
1777 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1778 pfn = (dev->mdev->iseg_base +
1779 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1780 PAGE_SHIFT;
1781 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1782 PAGE_SIZE, vma->vm_page_prot))
1783 return -EAGAIN;
1784
1785 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1786 vma->vm_start,
1787 (unsigned long long)pfn << PAGE_SHIFT);
1788 break;
1789
1790 default:
1791 return -EINVAL;
1792 }
1793
1794 return 0;
1795 }
1796
mlx5_ib_alloc_pd(struct ib_device * ibdev,struct ib_ucontext * context,struct ib_udata * udata)1797 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1798 struct ib_ucontext *context,
1799 struct ib_udata *udata)
1800 {
1801 struct mlx5_ib_alloc_pd_resp resp;
1802 struct mlx5_ib_pd *pd;
1803 int err;
1804
1805 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1806 if (!pd)
1807 return ERR_PTR(-ENOMEM);
1808
1809 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1810 if (err) {
1811 kfree(pd);
1812 return ERR_PTR(err);
1813 }
1814
1815 if (context) {
1816 resp.pdn = pd->pdn;
1817 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1818 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1819 kfree(pd);
1820 return ERR_PTR(-EFAULT);
1821 }
1822 }
1823
1824 return &pd->ibpd;
1825 }
1826
mlx5_ib_dealloc_pd(struct ib_pd * pd)1827 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1828 {
1829 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1830 struct mlx5_ib_pd *mpd = to_mpd(pd);
1831
1832 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1833 kfree(mpd);
1834
1835 return 0;
1836 }
1837
1838 enum {
1839 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1840 MATCH_CRITERIA_ENABLE_MISC_BIT,
1841 MATCH_CRITERIA_ENABLE_INNER_BIT
1842 };
1843
1844 #define HEADER_IS_ZERO(match_criteria, headers) \
1845 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1846 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
1847
get_match_criteria_enable(u32 * match_criteria)1848 static u8 get_match_criteria_enable(u32 *match_criteria)
1849 {
1850 u8 match_criteria_enable;
1851
1852 match_criteria_enable =
1853 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1854 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1855 match_criteria_enable |=
1856 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1857 MATCH_CRITERIA_ENABLE_MISC_BIT;
1858 match_criteria_enable |=
1859 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1860 MATCH_CRITERIA_ENABLE_INNER_BIT;
1861
1862 return match_criteria_enable;
1863 }
1864
set_proto(void * outer_c,void * outer_v,u8 mask,u8 val)1865 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1866 {
1867 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1868 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1869 }
1870
set_flow_label(void * misc_c,void * misc_v,u8 mask,u8 val,bool inner)1871 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1872 bool inner)
1873 {
1874 if (inner) {
1875 MLX5_SET(fte_match_set_misc,
1876 misc_c, inner_ipv6_flow_label, mask);
1877 MLX5_SET(fte_match_set_misc,
1878 misc_v, inner_ipv6_flow_label, val);
1879 } else {
1880 MLX5_SET(fte_match_set_misc,
1881 misc_c, outer_ipv6_flow_label, mask);
1882 MLX5_SET(fte_match_set_misc,
1883 misc_v, outer_ipv6_flow_label, val);
1884 }
1885 }
1886
set_tos(void * outer_c,void * outer_v,u8 mask,u8 val)1887 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1888 {
1889 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1890 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1891 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1892 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1893 }
1894
1895 #define LAST_ETH_FIELD vlan_tag
1896 #define LAST_IB_FIELD sl
1897 #define LAST_IPV4_FIELD tos
1898 #define LAST_IPV6_FIELD traffic_class
1899 #define LAST_TCP_UDP_FIELD src_port
1900 #define LAST_TUNNEL_FIELD tunnel_id
1901 #define LAST_FLOW_TAG_FIELD tag_id
1902 #define LAST_DROP_FIELD size
1903
1904 /* Field is the last supported field */
1905 #define FIELDS_NOT_SUPPORTED(filter, field)\
1906 memchr_inv((void *)&filter.field +\
1907 sizeof(filter.field), 0,\
1908 sizeof(filter) -\
1909 offsetof(typeof(filter), field) -\
1910 sizeof(filter.field))
1911
1912 #define IPV4_VERSION 4
1913 #define IPV6_VERSION 6
parse_flow_attr(struct mlx5_core_dev * mdev,u32 * match_c,u32 * match_v,const union ib_flow_spec * ib_spec,u32 * tag_id,bool * is_drop)1914 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
1915 u32 *match_v, const union ib_flow_spec *ib_spec,
1916 u32 *tag_id, bool *is_drop)
1917 {
1918 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1919 misc_parameters);
1920 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1921 misc_parameters);
1922 void *headers_c;
1923 void *headers_v;
1924 int match_ipv;
1925
1926 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1927 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1928 inner_headers);
1929 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1930 inner_headers);
1931 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1932 ft_field_support.inner_ip_version);
1933 } else {
1934 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1935 outer_headers);
1936 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1937 outer_headers);
1938 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1939 ft_field_support.outer_ip_version);
1940 }
1941
1942 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
1943 case IB_FLOW_SPEC_ETH:
1944 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1945 return -EOPNOTSUPP;
1946
1947 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1948 dmac_47_16),
1949 ib_spec->eth.mask.dst_mac);
1950 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1951 dmac_47_16),
1952 ib_spec->eth.val.dst_mac);
1953
1954 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1955 smac_47_16),
1956 ib_spec->eth.mask.src_mac);
1957 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1958 smac_47_16),
1959 ib_spec->eth.val.src_mac);
1960
1961 if (ib_spec->eth.mask.vlan_tag) {
1962 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1963 cvlan_tag, 1);
1964 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1965 cvlan_tag, 1);
1966
1967 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1968 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1969 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1970 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1971
1972 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1973 first_cfi,
1974 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1975 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1976 first_cfi,
1977 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1978
1979 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1980 first_prio,
1981 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1982 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1983 first_prio,
1984 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1985 }
1986 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1987 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1988 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1989 ethertype, ntohs(ib_spec->eth.val.ether_type));
1990 break;
1991 case IB_FLOW_SPEC_IPV4:
1992 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1993 return -EOPNOTSUPP;
1994
1995 if (match_ipv) {
1996 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1997 ip_version, 0xf);
1998 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1999 ip_version, IPV4_VERSION);
2000 } else {
2001 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2002 ethertype, 0xffff);
2003 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2004 ethertype, ETH_P_IP);
2005 }
2006
2007 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2008 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2009 &ib_spec->ipv4.mask.src_ip,
2010 sizeof(ib_spec->ipv4.mask.src_ip));
2011 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2012 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2013 &ib_spec->ipv4.val.src_ip,
2014 sizeof(ib_spec->ipv4.val.src_ip));
2015 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2016 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2017 &ib_spec->ipv4.mask.dst_ip,
2018 sizeof(ib_spec->ipv4.mask.dst_ip));
2019 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2020 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2021 &ib_spec->ipv4.val.dst_ip,
2022 sizeof(ib_spec->ipv4.val.dst_ip));
2023
2024 set_tos(headers_c, headers_v,
2025 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2026
2027 set_proto(headers_c, headers_v,
2028 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
2029 break;
2030 case IB_FLOW_SPEC_IPV6:
2031 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2032 return -EOPNOTSUPP;
2033
2034 if (match_ipv) {
2035 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2036 ip_version, 0xf);
2037 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2038 ip_version, IPV6_VERSION);
2039 } else {
2040 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2041 ethertype, 0xffff);
2042 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2043 ethertype, ETH_P_IPV6);
2044 }
2045
2046 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2047 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2048 &ib_spec->ipv6.mask.src_ip,
2049 sizeof(ib_spec->ipv6.mask.src_ip));
2050 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2051 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2052 &ib_spec->ipv6.val.src_ip,
2053 sizeof(ib_spec->ipv6.val.src_ip));
2054 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2055 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2056 &ib_spec->ipv6.mask.dst_ip,
2057 sizeof(ib_spec->ipv6.mask.dst_ip));
2058 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2059 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2060 &ib_spec->ipv6.val.dst_ip,
2061 sizeof(ib_spec->ipv6.val.dst_ip));
2062
2063 set_tos(headers_c, headers_v,
2064 ib_spec->ipv6.mask.traffic_class,
2065 ib_spec->ipv6.val.traffic_class);
2066
2067 set_proto(headers_c, headers_v,
2068 ib_spec->ipv6.mask.next_hdr,
2069 ib_spec->ipv6.val.next_hdr);
2070
2071 set_flow_label(misc_params_c, misc_params_v,
2072 ntohl(ib_spec->ipv6.mask.flow_label),
2073 ntohl(ib_spec->ipv6.val.flow_label),
2074 ib_spec->type & IB_FLOW_SPEC_INNER);
2075
2076 break;
2077 case IB_FLOW_SPEC_TCP:
2078 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2079 LAST_TCP_UDP_FIELD))
2080 return -EOPNOTSUPP;
2081
2082 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2083 0xff);
2084 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2085 IPPROTO_TCP);
2086
2087 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2088 ntohs(ib_spec->tcp_udp.mask.src_port));
2089 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2090 ntohs(ib_spec->tcp_udp.val.src_port));
2091
2092 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2093 ntohs(ib_spec->tcp_udp.mask.dst_port));
2094 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2095 ntohs(ib_spec->tcp_udp.val.dst_port));
2096 break;
2097 case IB_FLOW_SPEC_UDP:
2098 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2099 LAST_TCP_UDP_FIELD))
2100 return -EOPNOTSUPP;
2101
2102 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2103 0xff);
2104 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2105 IPPROTO_UDP);
2106
2107 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2108 ntohs(ib_spec->tcp_udp.mask.src_port));
2109 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2110 ntohs(ib_spec->tcp_udp.val.src_port));
2111
2112 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2113 ntohs(ib_spec->tcp_udp.mask.dst_port));
2114 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2115 ntohs(ib_spec->tcp_udp.val.dst_port));
2116 break;
2117 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2118 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2119 LAST_TUNNEL_FIELD))
2120 return -EOPNOTSUPP;
2121
2122 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2123 ntohl(ib_spec->tunnel.mask.tunnel_id));
2124 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2125 ntohl(ib_spec->tunnel.val.tunnel_id));
2126 break;
2127 case IB_FLOW_SPEC_ACTION_TAG:
2128 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2129 LAST_FLOW_TAG_FIELD))
2130 return -EOPNOTSUPP;
2131 if (ib_spec->flow_tag.tag_id >= BIT(24))
2132 return -EINVAL;
2133
2134 *tag_id = ib_spec->flow_tag.tag_id;
2135 break;
2136 case IB_FLOW_SPEC_ACTION_DROP:
2137 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2138 LAST_DROP_FIELD))
2139 return -EOPNOTSUPP;
2140 *is_drop = true;
2141 break;
2142 default:
2143 return -EINVAL;
2144 }
2145
2146 return 0;
2147 }
2148
2149 /* If a flow could catch both multicast and unicast packets,
2150 * it won't fall into the multicast flow steering table and this rule
2151 * could steal other multicast packets.
2152 */
flow_is_multicast_only(const struct ib_flow_attr * ib_attr)2153 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
2154 {
2155 union ib_flow_spec *flow_spec;
2156
2157 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2158 ib_attr->num_of_specs < 1)
2159 return false;
2160
2161 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2162 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2163 struct ib_flow_spec_ipv4 *ipv4_spec;
2164
2165 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2166 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2167 return true;
2168
2169 return false;
2170 }
2171
2172 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2173 struct ib_flow_spec_eth *eth_spec;
2174
2175 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2176 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2177 is_multicast_ether_addr(eth_spec->val.dst_mac);
2178 }
2179
2180 return false;
2181 }
2182
is_valid_ethertype(struct mlx5_core_dev * mdev,const struct ib_flow_attr * flow_attr,bool check_inner)2183 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2184 const struct ib_flow_attr *flow_attr,
2185 bool check_inner)
2186 {
2187 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2188 int match_ipv = check_inner ?
2189 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2190 ft_field_support.inner_ip_version) :
2191 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2192 ft_field_support.outer_ip_version);
2193 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2194 bool ipv4_spec_valid, ipv6_spec_valid;
2195 unsigned int ip_spec_type = 0;
2196 bool has_ethertype = false;
2197 unsigned int spec_index;
2198 bool mask_valid = true;
2199 u16 eth_type = 0;
2200 bool type_valid;
2201
2202 /* Validate that ethertype is correct */
2203 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2204 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2205 ib_spec->eth.mask.ether_type) {
2206 mask_valid = (ib_spec->eth.mask.ether_type ==
2207 htons(0xffff));
2208 has_ethertype = true;
2209 eth_type = ntohs(ib_spec->eth.val.ether_type);
2210 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2211 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2212 ip_spec_type = ib_spec->type;
2213 }
2214 ib_spec = (void *)ib_spec + ib_spec->size;
2215 }
2216
2217 type_valid = (!has_ethertype) || (!ip_spec_type);
2218 if (!type_valid && mask_valid) {
2219 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2220 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2221 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2222 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2223
2224 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2225 (((eth_type == ETH_P_MPLS_UC) ||
2226 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2227 }
2228
2229 return type_valid;
2230 }
2231
is_valid_attr(struct mlx5_core_dev * mdev,const struct ib_flow_attr * flow_attr)2232 static bool is_valid_attr(struct mlx5_core_dev *mdev,
2233 const struct ib_flow_attr *flow_attr)
2234 {
2235 return is_valid_ethertype(mdev, flow_attr, false) &&
2236 is_valid_ethertype(mdev, flow_attr, true);
2237 }
2238
put_flow_table(struct mlx5_ib_dev * dev,struct mlx5_ib_flow_prio * prio,bool ft_added)2239 static void put_flow_table(struct mlx5_ib_dev *dev,
2240 struct mlx5_ib_flow_prio *prio, bool ft_added)
2241 {
2242 prio->refcount -= !!ft_added;
2243 if (!prio->refcount) {
2244 mlx5_destroy_flow_table(prio->flow_table);
2245 prio->flow_table = NULL;
2246 }
2247 }
2248
mlx5_ib_destroy_flow(struct ib_flow * flow_id)2249 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2250 {
2251 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2252 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2253 struct mlx5_ib_flow_handler,
2254 ibflow);
2255 struct mlx5_ib_flow_handler *iter, *tmp;
2256
2257 mutex_lock(&dev->flow_db.lock);
2258
2259 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2260 mlx5_del_flow_rules(iter->rule);
2261 put_flow_table(dev, iter->prio, true);
2262 list_del(&iter->list);
2263 kfree(iter);
2264 }
2265
2266 mlx5_del_flow_rules(handler->rule);
2267 put_flow_table(dev, handler->prio, true);
2268 mutex_unlock(&dev->flow_db.lock);
2269
2270 kfree(handler);
2271
2272 return 0;
2273 }
2274
ib_prio_to_core_prio(unsigned int priority,bool dont_trap)2275 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2276 {
2277 priority *= 2;
2278 if (!dont_trap)
2279 priority++;
2280 return priority;
2281 }
2282
2283 enum flow_table_type {
2284 MLX5_IB_FT_RX,
2285 MLX5_IB_FT_TX
2286 };
2287
2288 #define MLX5_FS_MAX_TYPES 6
2289 #define MLX5_FS_MAX_ENTRIES BIT(16)
get_flow_table(struct mlx5_ib_dev * dev,struct ib_flow_attr * flow_attr,enum flow_table_type ft_type)2290 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
2291 struct ib_flow_attr *flow_attr,
2292 enum flow_table_type ft_type)
2293 {
2294 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
2295 struct mlx5_flow_namespace *ns = NULL;
2296 struct mlx5_ib_flow_prio *prio;
2297 struct mlx5_flow_table *ft;
2298 int max_table_size;
2299 int num_entries;
2300 int num_groups;
2301 int priority;
2302 int err = 0;
2303
2304 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2305 log_max_ft_size));
2306 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2307 if (flow_is_multicast_only(flow_attr) &&
2308 !dont_trap)
2309 priority = MLX5_IB_FLOW_MCAST_PRIO;
2310 else
2311 priority = ib_prio_to_core_prio(flow_attr->priority,
2312 dont_trap);
2313 ns = mlx5_get_flow_namespace(dev->mdev,
2314 MLX5_FLOW_NAMESPACE_BYPASS);
2315 num_entries = MLX5_FS_MAX_ENTRIES;
2316 num_groups = MLX5_FS_MAX_TYPES;
2317 prio = &dev->flow_db.prios[priority];
2318 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2319 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2320 ns = mlx5_get_flow_namespace(dev->mdev,
2321 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2322 build_leftovers_ft_param(&priority,
2323 &num_entries,
2324 &num_groups);
2325 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
2326 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2327 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2328 allow_sniffer_and_nic_rx_shared_tir))
2329 return ERR_PTR(-ENOTSUPP);
2330
2331 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2332 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2333 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2334
2335 prio = &dev->flow_db.sniffer[ft_type];
2336 priority = 0;
2337 num_entries = 1;
2338 num_groups = 1;
2339 }
2340
2341 if (!ns)
2342 return ERR_PTR(-ENOTSUPP);
2343
2344 if (num_entries > max_table_size)
2345 return ERR_PTR(-ENOMEM);
2346
2347 ft = prio->flow_table;
2348 if (!ft) {
2349 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2350 num_entries,
2351 num_groups,
2352 0, 0);
2353
2354 if (!IS_ERR(ft)) {
2355 prio->refcount = 0;
2356 prio->flow_table = ft;
2357 } else {
2358 err = PTR_ERR(ft);
2359 }
2360 }
2361
2362 return err ? ERR_PTR(err) : prio;
2363 }
2364
set_underlay_qp(struct mlx5_ib_dev * dev,struct mlx5_flow_spec * spec,u32 underlay_qpn)2365 static void set_underlay_qp(struct mlx5_ib_dev *dev,
2366 struct mlx5_flow_spec *spec,
2367 u32 underlay_qpn)
2368 {
2369 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
2370 spec->match_criteria,
2371 misc_parameters);
2372 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2373 misc_parameters);
2374
2375 if (underlay_qpn &&
2376 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2377 ft_field_support.bth_dst_qp)) {
2378 MLX5_SET(fte_match_set_misc,
2379 misc_params_v, bth_dst_qp, underlay_qpn);
2380 MLX5_SET(fte_match_set_misc,
2381 misc_params_c, bth_dst_qp, 0xffffff);
2382 }
2383 }
2384
_create_flow_rule(struct mlx5_ib_dev * dev,struct mlx5_ib_flow_prio * ft_prio,const struct ib_flow_attr * flow_attr,struct mlx5_flow_destination * dst,u32 underlay_qpn)2385 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
2386 struct mlx5_ib_flow_prio *ft_prio,
2387 const struct ib_flow_attr *flow_attr,
2388 struct mlx5_flow_destination *dst,
2389 u32 underlay_qpn)
2390 {
2391 struct mlx5_flow_table *ft = ft_prio->flow_table;
2392 struct mlx5_ib_flow_handler *handler;
2393 struct mlx5_flow_act flow_act = {0};
2394 struct mlx5_flow_spec *spec;
2395 struct mlx5_flow_destination *rule_dst = dst;
2396 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
2397 unsigned int spec_index;
2398 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2399 bool is_drop = false;
2400 int err = 0;
2401 int dest_num = 1;
2402
2403 if (!is_valid_attr(dev->mdev, flow_attr))
2404 return ERR_PTR(-EINVAL);
2405
2406 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2407 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
2408 if (!handler || !spec) {
2409 err = -ENOMEM;
2410 goto free;
2411 }
2412
2413 INIT_LIST_HEAD(&handler->list);
2414
2415 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2416 err = parse_flow_attr(dev->mdev, spec->match_criteria,
2417 spec->match_value,
2418 ib_flow, &flow_tag, &is_drop);
2419 if (err < 0)
2420 goto free;
2421
2422 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2423 }
2424
2425 if (!flow_is_multicast_only(flow_attr))
2426 set_underlay_qp(dev, spec, underlay_qpn);
2427
2428 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
2429 if (is_drop) {
2430 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2431 rule_dst = NULL;
2432 dest_num = 0;
2433 } else {
2434 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2435 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2436 }
2437
2438 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2439 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2440 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2441 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2442 flow_tag, flow_attr->type);
2443 err = -EINVAL;
2444 goto free;
2445 }
2446 flow_act.flow_tag = flow_tag;
2447 handler->rule = mlx5_add_flow_rules(ft, spec,
2448 &flow_act,
2449 rule_dst, dest_num);
2450
2451 if (IS_ERR(handler->rule)) {
2452 err = PTR_ERR(handler->rule);
2453 goto free;
2454 }
2455
2456 ft_prio->refcount++;
2457 handler->prio = ft_prio;
2458
2459 ft_prio->flow_table = ft;
2460 free:
2461 if (err)
2462 kfree(handler);
2463 kvfree(spec);
2464 return err ? ERR_PTR(err) : handler;
2465 }
2466
create_flow_rule(struct mlx5_ib_dev * dev,struct mlx5_ib_flow_prio * ft_prio,const struct ib_flow_attr * flow_attr,struct mlx5_flow_destination * dst)2467 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2468 struct mlx5_ib_flow_prio *ft_prio,
2469 const struct ib_flow_attr *flow_attr,
2470 struct mlx5_flow_destination *dst)
2471 {
2472 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0);
2473 }
2474
create_dont_trap_rule(struct mlx5_ib_dev * dev,struct mlx5_ib_flow_prio * ft_prio,struct ib_flow_attr * flow_attr,struct mlx5_flow_destination * dst)2475 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2476 struct mlx5_ib_flow_prio *ft_prio,
2477 struct ib_flow_attr *flow_attr,
2478 struct mlx5_flow_destination *dst)
2479 {
2480 struct mlx5_ib_flow_handler *handler_dst = NULL;
2481 struct mlx5_ib_flow_handler *handler = NULL;
2482
2483 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2484 if (!IS_ERR(handler)) {
2485 handler_dst = create_flow_rule(dev, ft_prio,
2486 flow_attr, dst);
2487 if (IS_ERR(handler_dst)) {
2488 mlx5_del_flow_rules(handler->rule);
2489 ft_prio->refcount--;
2490 kfree(handler);
2491 handler = handler_dst;
2492 } else {
2493 list_add(&handler_dst->list, &handler->list);
2494 }
2495 }
2496
2497 return handler;
2498 }
2499 enum {
2500 LEFTOVERS_MC,
2501 LEFTOVERS_UC,
2502 };
2503
create_leftovers_rule(struct mlx5_ib_dev * dev,struct mlx5_ib_flow_prio * ft_prio,struct ib_flow_attr * flow_attr,struct mlx5_flow_destination * dst)2504 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2505 struct mlx5_ib_flow_prio *ft_prio,
2506 struct ib_flow_attr *flow_attr,
2507 struct mlx5_flow_destination *dst)
2508 {
2509 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2510 struct mlx5_ib_flow_handler *handler = NULL;
2511
2512 static struct {
2513 struct ib_flow_attr flow_attr;
2514 struct ib_flow_spec_eth eth_flow;
2515 } leftovers_specs[] = {
2516 [LEFTOVERS_MC] = {
2517 .flow_attr = {
2518 .num_of_specs = 1,
2519 .size = sizeof(leftovers_specs[0])
2520 },
2521 .eth_flow = {
2522 .type = IB_FLOW_SPEC_ETH,
2523 .size = sizeof(struct ib_flow_spec_eth),
2524 .mask = {.dst_mac = {0x1} },
2525 .val = {.dst_mac = {0x1} }
2526 }
2527 },
2528 [LEFTOVERS_UC] = {
2529 .flow_attr = {
2530 .num_of_specs = 1,
2531 .size = sizeof(leftovers_specs[0])
2532 },
2533 .eth_flow = {
2534 .type = IB_FLOW_SPEC_ETH,
2535 .size = sizeof(struct ib_flow_spec_eth),
2536 .mask = {.dst_mac = {0x1} },
2537 .val = {.dst_mac = {} }
2538 }
2539 }
2540 };
2541
2542 handler = create_flow_rule(dev, ft_prio,
2543 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2544 dst);
2545 if (!IS_ERR(handler) &&
2546 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2547 handler_ucast = create_flow_rule(dev, ft_prio,
2548 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2549 dst);
2550 if (IS_ERR(handler_ucast)) {
2551 mlx5_del_flow_rules(handler->rule);
2552 ft_prio->refcount--;
2553 kfree(handler);
2554 handler = handler_ucast;
2555 } else {
2556 list_add(&handler_ucast->list, &handler->list);
2557 }
2558 }
2559
2560 return handler;
2561 }
2562
create_sniffer_rule(struct mlx5_ib_dev * dev,struct mlx5_ib_flow_prio * ft_rx,struct mlx5_ib_flow_prio * ft_tx,struct mlx5_flow_destination * dst)2563 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2564 struct mlx5_ib_flow_prio *ft_rx,
2565 struct mlx5_ib_flow_prio *ft_tx,
2566 struct mlx5_flow_destination *dst)
2567 {
2568 struct mlx5_ib_flow_handler *handler_rx;
2569 struct mlx5_ib_flow_handler *handler_tx;
2570 int err;
2571 static const struct ib_flow_attr flow_attr = {
2572 .num_of_specs = 0,
2573 .size = sizeof(flow_attr)
2574 };
2575
2576 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2577 if (IS_ERR(handler_rx)) {
2578 err = PTR_ERR(handler_rx);
2579 goto err;
2580 }
2581
2582 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2583 if (IS_ERR(handler_tx)) {
2584 err = PTR_ERR(handler_tx);
2585 goto err_tx;
2586 }
2587
2588 list_add(&handler_tx->list, &handler_rx->list);
2589
2590 return handler_rx;
2591
2592 err_tx:
2593 mlx5_del_flow_rules(handler_rx->rule);
2594 ft_rx->refcount--;
2595 kfree(handler_rx);
2596 err:
2597 return ERR_PTR(err);
2598 }
2599
mlx5_ib_create_flow(struct ib_qp * qp,struct ib_flow_attr * flow_attr,int domain)2600 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2601 struct ib_flow_attr *flow_attr,
2602 int domain)
2603 {
2604 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2605 struct mlx5_ib_qp *mqp = to_mqp(qp);
2606 struct mlx5_ib_flow_handler *handler = NULL;
2607 struct mlx5_flow_destination *dst = NULL;
2608 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2609 struct mlx5_ib_flow_prio *ft_prio;
2610 int err;
2611 int underlay_qpn;
2612
2613 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2614 return ERR_PTR(-ENOMEM);
2615
2616 if (domain != IB_FLOW_DOMAIN_USER ||
2617 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2618 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2619 return ERR_PTR(-EINVAL);
2620
2621 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2622 if (!dst)
2623 return ERR_PTR(-ENOMEM);
2624
2625 mutex_lock(&dev->flow_db.lock);
2626
2627 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2628 if (IS_ERR(ft_prio)) {
2629 err = PTR_ERR(ft_prio);
2630 goto unlock;
2631 }
2632 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2633 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2634 if (IS_ERR(ft_prio_tx)) {
2635 err = PTR_ERR(ft_prio_tx);
2636 ft_prio_tx = NULL;
2637 goto destroy_ft;
2638 }
2639 }
2640
2641 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2642 if (mqp->flags & MLX5_IB_QP_RSS)
2643 dst->tir_num = mqp->rss_qp.tirn;
2644 else
2645 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2646
2647 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2648 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2649 handler = create_dont_trap_rule(dev, ft_prio,
2650 flow_attr, dst);
2651 } else {
2652 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
2653 mqp->underlay_qpn : 0;
2654 handler = _create_flow_rule(dev, ft_prio, flow_attr,
2655 dst, underlay_qpn);
2656 }
2657 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2658 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2659 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2660 dst);
2661 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2662 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2663 } else {
2664 err = -EINVAL;
2665 goto destroy_ft;
2666 }
2667
2668 if (IS_ERR(handler)) {
2669 err = PTR_ERR(handler);
2670 handler = NULL;
2671 goto destroy_ft;
2672 }
2673
2674 mutex_unlock(&dev->flow_db.lock);
2675 kfree(dst);
2676
2677 return &handler->ibflow;
2678
2679 destroy_ft:
2680 put_flow_table(dev, ft_prio, false);
2681 if (ft_prio_tx)
2682 put_flow_table(dev, ft_prio_tx, false);
2683 unlock:
2684 mutex_unlock(&dev->flow_db.lock);
2685 kfree(dst);
2686 kfree(handler);
2687 return ERR_PTR(err);
2688 }
2689
mlx5_ib_mcg_attach(struct ib_qp * ibqp,union ib_gid * gid,u16 lid)2690 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2691 {
2692 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2693 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
2694 int err;
2695
2696 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
2697 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2698 return -EOPNOTSUPP;
2699 }
2700
2701 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2702 if (err)
2703 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2704 ibqp->qp_num, gid->raw);
2705
2706 return err;
2707 }
2708
mlx5_ib_mcg_detach(struct ib_qp * ibqp,union ib_gid * gid,u16 lid)2709 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2710 {
2711 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2712 int err;
2713
2714 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2715 if (err)
2716 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2717 ibqp->qp_num, gid->raw);
2718
2719 return err;
2720 }
2721
init_node_data(struct mlx5_ib_dev * dev)2722 static int init_node_data(struct mlx5_ib_dev *dev)
2723 {
2724 int err;
2725
2726 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2727 if (err)
2728 return err;
2729
2730 dev->mdev->rev_id = dev->mdev->pdev->revision;
2731
2732 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2733 }
2734
show_fw_pages(struct device * device,struct device_attribute * attr,char * buf)2735 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2736 char *buf)
2737 {
2738 struct mlx5_ib_dev *dev =
2739 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2740
2741 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2742 }
2743
show_reg_pages(struct device * device,struct device_attribute * attr,char * buf)2744 static ssize_t show_reg_pages(struct device *device,
2745 struct device_attribute *attr, char *buf)
2746 {
2747 struct mlx5_ib_dev *dev =
2748 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2749
2750 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2751 }
2752
show_hca(struct device * device,struct device_attribute * attr,char * buf)2753 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2754 char *buf)
2755 {
2756 struct mlx5_ib_dev *dev =
2757 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2758 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2759 }
2760
show_rev(struct device * device,struct device_attribute * attr,char * buf)2761 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2762 char *buf)
2763 {
2764 struct mlx5_ib_dev *dev =
2765 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2766 return sprintf(buf, "%x\n", dev->mdev->rev_id);
2767 }
2768
show_board(struct device * device,struct device_attribute * attr,char * buf)2769 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2770 char *buf)
2771 {
2772 struct mlx5_ib_dev *dev =
2773 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2774 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2775 dev->mdev->board_id);
2776 }
2777
2778 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
2779 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2780 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2781 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2782 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2783
2784 static struct device_attribute *mlx5_class_attributes[] = {
2785 &dev_attr_hw_rev,
2786 &dev_attr_hca_type,
2787 &dev_attr_board_id,
2788 &dev_attr_fw_pages,
2789 &dev_attr_reg_pages,
2790 };
2791
pkey_change_handler(struct work_struct * work)2792 static void pkey_change_handler(struct work_struct *work)
2793 {
2794 struct mlx5_ib_port_resources *ports =
2795 container_of(work, struct mlx5_ib_port_resources,
2796 pkey_change_work);
2797
2798 mutex_lock(&ports->devr->mutex);
2799 mlx5_ib_gsi_pkey_change(ports->gsi);
2800 mutex_unlock(&ports->devr->mutex);
2801 }
2802
mlx5_ib_handle_internal_error(struct mlx5_ib_dev * ibdev)2803 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2804 {
2805 struct mlx5_ib_qp *mqp;
2806 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2807 struct mlx5_core_cq *mcq;
2808 struct list_head cq_armed_list;
2809 unsigned long flags_qp;
2810 unsigned long flags_cq;
2811 unsigned long flags;
2812
2813 INIT_LIST_HEAD(&cq_armed_list);
2814
2815 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2816 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2817 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2818 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2819 if (mqp->sq.tail != mqp->sq.head) {
2820 send_mcq = to_mcq(mqp->ibqp.send_cq);
2821 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2822 if (send_mcq->mcq.comp &&
2823 mqp->ibqp.send_cq->comp_handler) {
2824 if (!send_mcq->mcq.reset_notify_added) {
2825 send_mcq->mcq.reset_notify_added = 1;
2826 list_add_tail(&send_mcq->mcq.reset_notify,
2827 &cq_armed_list);
2828 }
2829 }
2830 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2831 }
2832 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2833 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2834 /* no handling is needed for SRQ */
2835 if (!mqp->ibqp.srq) {
2836 if (mqp->rq.tail != mqp->rq.head) {
2837 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2838 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2839 if (recv_mcq->mcq.comp &&
2840 mqp->ibqp.recv_cq->comp_handler) {
2841 if (!recv_mcq->mcq.reset_notify_added) {
2842 recv_mcq->mcq.reset_notify_added = 1;
2843 list_add_tail(&recv_mcq->mcq.reset_notify,
2844 &cq_armed_list);
2845 }
2846 }
2847 spin_unlock_irqrestore(&recv_mcq->lock,
2848 flags_cq);
2849 }
2850 }
2851 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2852 }
2853 /*At that point all inflight post send were put to be executed as of we
2854 * lock/unlock above locks Now need to arm all involved CQs.
2855 */
2856 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2857 mcq->comp(mcq);
2858 }
2859 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2860 }
2861
delay_drop_handler(struct work_struct * work)2862 static void delay_drop_handler(struct work_struct *work)
2863 {
2864 int err;
2865 struct mlx5_ib_delay_drop *delay_drop =
2866 container_of(work, struct mlx5_ib_delay_drop,
2867 delay_drop_work);
2868
2869 atomic_inc(&delay_drop->events_cnt);
2870
2871 mutex_lock(&delay_drop->lock);
2872 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
2873 delay_drop->timeout);
2874 if (err) {
2875 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2876 delay_drop->timeout);
2877 delay_drop->activate = false;
2878 }
2879 mutex_unlock(&delay_drop->lock);
2880 }
2881
mlx5_ib_event(struct mlx5_core_dev * dev,void * context,enum mlx5_dev_event event,unsigned long param)2882 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2883 enum mlx5_dev_event event, unsigned long param)
2884 {
2885 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2886 struct ib_event ibev;
2887 bool fatal = false;
2888 u8 port = 0;
2889
2890 switch (event) {
2891 case MLX5_DEV_EVENT_SYS_ERROR:
2892 ibev.event = IB_EVENT_DEVICE_FATAL;
2893 mlx5_ib_handle_internal_error(ibdev);
2894 fatal = true;
2895 break;
2896
2897 case MLX5_DEV_EVENT_PORT_UP:
2898 case MLX5_DEV_EVENT_PORT_DOWN:
2899 case MLX5_DEV_EVENT_PORT_INITIALIZED:
2900 port = (u8)param;
2901
2902 /* In RoCE, port up/down events are handled in
2903 * mlx5_netdev_event().
2904 */
2905 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2906 IB_LINK_LAYER_ETHERNET)
2907 return;
2908
2909 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2910 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2911 break;
2912
2913 case MLX5_DEV_EVENT_LID_CHANGE:
2914 ibev.event = IB_EVENT_LID_CHANGE;
2915 port = (u8)param;
2916 break;
2917
2918 case MLX5_DEV_EVENT_PKEY_CHANGE:
2919 ibev.event = IB_EVENT_PKEY_CHANGE;
2920 port = (u8)param;
2921
2922 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2923 break;
2924
2925 case MLX5_DEV_EVENT_GUID_CHANGE:
2926 ibev.event = IB_EVENT_GID_CHANGE;
2927 port = (u8)param;
2928 break;
2929
2930 case MLX5_DEV_EVENT_CLIENT_REREG:
2931 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2932 port = (u8)param;
2933 break;
2934 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
2935 schedule_work(&ibdev->delay_drop.delay_drop_work);
2936 goto out;
2937 default:
2938 goto out;
2939 }
2940
2941 ibev.device = &ibdev->ib_dev;
2942 ibev.element.port_num = port;
2943
2944 if (port < 1 || port > ibdev->num_ports) {
2945 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2946 goto out;
2947 }
2948
2949 if (ibdev->ib_active)
2950 ib_dispatch_event(&ibev);
2951
2952 if (fatal)
2953 ibdev->ib_active = false;
2954
2955 out:
2956 return;
2957 }
2958
set_has_smi_cap(struct mlx5_ib_dev * dev)2959 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2960 {
2961 struct mlx5_hca_vport_context vport_ctx;
2962 int err;
2963 int port;
2964
2965 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2966 dev->mdev->port_caps[port - 1].has_smi = false;
2967 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2968 MLX5_CAP_PORT_TYPE_IB) {
2969 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2970 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2971 port, 0,
2972 &vport_ctx);
2973 if (err) {
2974 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2975 port, err);
2976 return err;
2977 }
2978 dev->mdev->port_caps[port - 1].has_smi =
2979 vport_ctx.has_smi;
2980 } else {
2981 dev->mdev->port_caps[port - 1].has_smi = true;
2982 }
2983 }
2984 }
2985 return 0;
2986 }
2987
get_ext_port_caps(struct mlx5_ib_dev * dev)2988 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2989 {
2990 int port;
2991
2992 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2993 mlx5_query_ext_port_caps(dev, port);
2994 }
2995
get_port_caps(struct mlx5_ib_dev * dev)2996 static int get_port_caps(struct mlx5_ib_dev *dev)
2997 {
2998 struct ib_device_attr *dprops = NULL;
2999 struct ib_port_attr *pprops = NULL;
3000 int err = -ENOMEM;
3001 int port;
3002 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
3003
3004 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
3005 if (!pprops)
3006 goto out;
3007
3008 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
3009 if (!dprops)
3010 goto out;
3011
3012 err = set_has_smi_cap(dev);
3013 if (err)
3014 goto out;
3015
3016 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
3017 if (err) {
3018 mlx5_ib_warn(dev, "query_device failed %d\n", err);
3019 goto out;
3020 }
3021
3022 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
3023 memset(pprops, 0, sizeof(*pprops));
3024 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
3025 if (err) {
3026 mlx5_ib_warn(dev, "query_port %d failed %d\n",
3027 port, err);
3028 break;
3029 }
3030 dev->mdev->port_caps[port - 1].pkey_table_len =
3031 dprops->max_pkeys;
3032 dev->mdev->port_caps[port - 1].gid_table_len =
3033 pprops->gid_tbl_len;
3034 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
3035 dprops->max_pkeys, pprops->gid_tbl_len);
3036 }
3037
3038 out:
3039 kfree(pprops);
3040 kfree(dprops);
3041
3042 return err;
3043 }
3044
destroy_umrc_res(struct mlx5_ib_dev * dev)3045 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
3046 {
3047 int err;
3048
3049 err = mlx5_mr_cache_cleanup(dev);
3050 if (err)
3051 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
3052
3053 mlx5_ib_destroy_qp(dev->umrc.qp);
3054 ib_free_cq(dev->umrc.cq);
3055 ib_dealloc_pd(dev->umrc.pd);
3056 }
3057
3058 enum {
3059 MAX_UMR_WR = 128,
3060 };
3061
create_umr_res(struct mlx5_ib_dev * dev)3062 static int create_umr_res(struct mlx5_ib_dev *dev)
3063 {
3064 struct ib_qp_init_attr *init_attr = NULL;
3065 struct ib_qp_attr *attr = NULL;
3066 struct ib_pd *pd;
3067 struct ib_cq *cq;
3068 struct ib_qp *qp;
3069 int ret;
3070
3071 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
3072 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
3073 if (!attr || !init_attr) {
3074 ret = -ENOMEM;
3075 goto error_0;
3076 }
3077
3078 pd = ib_alloc_pd(&dev->ib_dev, 0);
3079 if (IS_ERR(pd)) {
3080 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3081 ret = PTR_ERR(pd);
3082 goto error_0;
3083 }
3084
3085 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
3086 if (IS_ERR(cq)) {
3087 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3088 ret = PTR_ERR(cq);
3089 goto error_2;
3090 }
3091
3092 init_attr->send_cq = cq;
3093 init_attr->recv_cq = cq;
3094 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3095 init_attr->cap.max_send_wr = MAX_UMR_WR;
3096 init_attr->cap.max_send_sge = 1;
3097 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3098 init_attr->port_num = 1;
3099 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3100 if (IS_ERR(qp)) {
3101 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3102 ret = PTR_ERR(qp);
3103 goto error_3;
3104 }
3105 qp->device = &dev->ib_dev;
3106 qp->real_qp = qp;
3107 qp->uobject = NULL;
3108 qp->qp_type = MLX5_IB_QPT_REG_UMR;
3109 qp->send_cq = init_attr->send_cq;
3110 qp->recv_cq = init_attr->recv_cq;
3111
3112 attr->qp_state = IB_QPS_INIT;
3113 attr->port_num = 1;
3114 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3115 IB_QP_PORT, NULL);
3116 if (ret) {
3117 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3118 goto error_4;
3119 }
3120
3121 memset(attr, 0, sizeof(*attr));
3122 attr->qp_state = IB_QPS_RTR;
3123 attr->path_mtu = IB_MTU_256;
3124
3125 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3126 if (ret) {
3127 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3128 goto error_4;
3129 }
3130
3131 memset(attr, 0, sizeof(*attr));
3132 attr->qp_state = IB_QPS_RTS;
3133 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3134 if (ret) {
3135 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3136 goto error_4;
3137 }
3138
3139 dev->umrc.qp = qp;
3140 dev->umrc.cq = cq;
3141 dev->umrc.pd = pd;
3142
3143 sema_init(&dev->umrc.sem, MAX_UMR_WR);
3144 ret = mlx5_mr_cache_init(dev);
3145 if (ret) {
3146 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3147 goto error_4;
3148 }
3149
3150 kfree(attr);
3151 kfree(init_attr);
3152
3153 return 0;
3154
3155 error_4:
3156 mlx5_ib_destroy_qp(qp);
3157
3158 error_3:
3159 ib_free_cq(cq);
3160
3161 error_2:
3162 ib_dealloc_pd(pd);
3163
3164 error_0:
3165 kfree(attr);
3166 kfree(init_attr);
3167 return ret;
3168 }
3169
mlx5_get_umr_fence(u8 umr_fence_cap)3170 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3171 {
3172 switch (umr_fence_cap) {
3173 case MLX5_CAP_UMR_FENCE_NONE:
3174 return MLX5_FENCE_MODE_NONE;
3175 case MLX5_CAP_UMR_FENCE_SMALL:
3176 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3177 default:
3178 return MLX5_FENCE_MODE_STRONG_ORDERING;
3179 }
3180 }
3181
create_dev_resources(struct mlx5_ib_resources * devr)3182 static int create_dev_resources(struct mlx5_ib_resources *devr)
3183 {
3184 struct ib_srq_init_attr attr;
3185 struct mlx5_ib_dev *dev;
3186 struct ib_cq_init_attr cq_attr = {.cqe = 1};
3187 int port;
3188 int ret = 0;
3189
3190 dev = container_of(devr, struct mlx5_ib_dev, devr);
3191
3192 mutex_init(&devr->mutex);
3193
3194 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
3195 if (IS_ERR(devr->p0)) {
3196 ret = PTR_ERR(devr->p0);
3197 goto error0;
3198 }
3199 devr->p0->device = &dev->ib_dev;
3200 devr->p0->uobject = NULL;
3201 atomic_set(&devr->p0->usecnt, 0);
3202
3203 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
3204 if (IS_ERR(devr->c0)) {
3205 ret = PTR_ERR(devr->c0);
3206 goto error1;
3207 }
3208 devr->c0->device = &dev->ib_dev;
3209 devr->c0->uobject = NULL;
3210 devr->c0->comp_handler = NULL;
3211 devr->c0->event_handler = NULL;
3212 devr->c0->cq_context = NULL;
3213 atomic_set(&devr->c0->usecnt, 0);
3214
3215 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3216 if (IS_ERR(devr->x0)) {
3217 ret = PTR_ERR(devr->x0);
3218 goto error2;
3219 }
3220 devr->x0->device = &dev->ib_dev;
3221 devr->x0->inode = NULL;
3222 atomic_set(&devr->x0->usecnt, 0);
3223 mutex_init(&devr->x0->tgt_qp_mutex);
3224 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3225
3226 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3227 if (IS_ERR(devr->x1)) {
3228 ret = PTR_ERR(devr->x1);
3229 goto error3;
3230 }
3231 devr->x1->device = &dev->ib_dev;
3232 devr->x1->inode = NULL;
3233 atomic_set(&devr->x1->usecnt, 0);
3234 mutex_init(&devr->x1->tgt_qp_mutex);
3235 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3236
3237 memset(&attr, 0, sizeof(attr));
3238 attr.attr.max_sge = 1;
3239 attr.attr.max_wr = 1;
3240 attr.srq_type = IB_SRQT_XRC;
3241 attr.ext.cq = devr->c0;
3242 attr.ext.xrc.xrcd = devr->x0;
3243
3244 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3245 if (IS_ERR(devr->s0)) {
3246 ret = PTR_ERR(devr->s0);
3247 goto error4;
3248 }
3249 devr->s0->device = &dev->ib_dev;
3250 devr->s0->pd = devr->p0;
3251 devr->s0->uobject = NULL;
3252 devr->s0->event_handler = NULL;
3253 devr->s0->srq_context = NULL;
3254 devr->s0->srq_type = IB_SRQT_XRC;
3255 devr->s0->ext.xrc.xrcd = devr->x0;
3256 devr->s0->ext.cq = devr->c0;
3257 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
3258 atomic_inc(&devr->s0->ext.cq->usecnt);
3259 atomic_inc(&devr->p0->usecnt);
3260 atomic_set(&devr->s0->usecnt, 0);
3261
3262 memset(&attr, 0, sizeof(attr));
3263 attr.attr.max_sge = 1;
3264 attr.attr.max_wr = 1;
3265 attr.srq_type = IB_SRQT_BASIC;
3266 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3267 if (IS_ERR(devr->s1)) {
3268 ret = PTR_ERR(devr->s1);
3269 goto error5;
3270 }
3271 devr->s1->device = &dev->ib_dev;
3272 devr->s1->pd = devr->p0;
3273 devr->s1->uobject = NULL;
3274 devr->s1->event_handler = NULL;
3275 devr->s1->srq_context = NULL;
3276 devr->s1->srq_type = IB_SRQT_BASIC;
3277 devr->s1->ext.cq = devr->c0;
3278 atomic_inc(&devr->p0->usecnt);
3279 atomic_set(&devr->s1->usecnt, 0);
3280
3281 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3282 INIT_WORK(&devr->ports[port].pkey_change_work,
3283 pkey_change_handler);
3284 devr->ports[port].devr = devr;
3285 }
3286
3287 return 0;
3288
3289 error5:
3290 mlx5_ib_destroy_srq(devr->s0);
3291 error4:
3292 mlx5_ib_dealloc_xrcd(devr->x1);
3293 error3:
3294 mlx5_ib_dealloc_xrcd(devr->x0);
3295 error2:
3296 mlx5_ib_destroy_cq(devr->c0);
3297 error1:
3298 mlx5_ib_dealloc_pd(devr->p0);
3299 error0:
3300 return ret;
3301 }
3302
destroy_dev_resources(struct mlx5_ib_resources * devr)3303 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3304 {
3305 struct mlx5_ib_dev *dev =
3306 container_of(devr, struct mlx5_ib_dev, devr);
3307 int port;
3308
3309 mlx5_ib_destroy_srq(devr->s1);
3310 mlx5_ib_destroy_srq(devr->s0);
3311 mlx5_ib_dealloc_xrcd(devr->x0);
3312 mlx5_ib_dealloc_xrcd(devr->x1);
3313 mlx5_ib_destroy_cq(devr->c0);
3314 mlx5_ib_dealloc_pd(devr->p0);
3315
3316 /* Make sure no change P_Key work items are still executing */
3317 for (port = 0; port < dev->num_ports; ++port)
3318 cancel_work_sync(&devr->ports[port].pkey_change_work);
3319 }
3320
get_core_cap_flags(struct ib_device * ibdev)3321 static u32 get_core_cap_flags(struct ib_device *ibdev)
3322 {
3323 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3324 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3325 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3326 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3327 u32 ret = 0;
3328
3329 if (ll == IB_LINK_LAYER_INFINIBAND)
3330 return RDMA_CORE_PORT_IBA_IB;
3331
3332 ret = RDMA_CORE_PORT_RAW_PACKET;
3333
3334 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
3335 return ret;
3336
3337 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
3338 return ret;
3339
3340 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3341 ret |= RDMA_CORE_PORT_IBA_ROCE;
3342
3343 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3344 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3345
3346 return ret;
3347 }
3348
mlx5_port_immutable(struct ib_device * ibdev,u8 port_num,struct ib_port_immutable * immutable)3349 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3350 struct ib_port_immutable *immutable)
3351 {
3352 struct ib_port_attr attr;
3353 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3354 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
3355 int err;
3356
3357 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3358
3359 err = ib_query_port(ibdev, port_num, &attr);
3360 if (err)
3361 return err;
3362
3363 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3364 immutable->gid_tbl_len = attr.gid_tbl_len;
3365 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3366 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3367 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3368
3369 return 0;
3370 }
3371
get_dev_fw_str(struct ib_device * ibdev,char * str)3372 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
3373 {
3374 struct mlx5_ib_dev *dev =
3375 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3376 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3377 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3378 fw_rev_sub(dev->mdev));
3379 }
3380
mlx5_eth_lag_init(struct mlx5_ib_dev * dev)3381 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3382 {
3383 struct mlx5_core_dev *mdev = dev->mdev;
3384 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3385 MLX5_FLOW_NAMESPACE_LAG);
3386 struct mlx5_flow_table *ft;
3387 int err;
3388
3389 if (!ns || !mlx5_lag_is_active(mdev))
3390 return 0;
3391
3392 err = mlx5_cmd_create_vport_lag(mdev);
3393 if (err)
3394 return err;
3395
3396 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3397 if (IS_ERR(ft)) {
3398 err = PTR_ERR(ft);
3399 goto err_destroy_vport_lag;
3400 }
3401
3402 dev->flow_db.lag_demux_ft = ft;
3403 return 0;
3404
3405 err_destroy_vport_lag:
3406 mlx5_cmd_destroy_vport_lag(mdev);
3407 return err;
3408 }
3409
mlx5_eth_lag_cleanup(struct mlx5_ib_dev * dev)3410 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3411 {
3412 struct mlx5_core_dev *mdev = dev->mdev;
3413
3414 if (dev->flow_db.lag_demux_ft) {
3415 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3416 dev->flow_db.lag_demux_ft = NULL;
3417
3418 mlx5_cmd_destroy_vport_lag(mdev);
3419 }
3420 }
3421
mlx5_add_netdev_notifier(struct mlx5_ib_dev * dev)3422 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
3423 {
3424 int err;
3425
3426 dev->roce.nb.notifier_call = mlx5_netdev_event;
3427 err = register_netdevice_notifier(&dev->roce.nb);
3428 if (err) {
3429 dev->roce.nb.notifier_call = NULL;
3430 return err;
3431 }
3432
3433 return 0;
3434 }
3435
mlx5_remove_netdev_notifier(struct mlx5_ib_dev * dev)3436 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
3437 {
3438 if (dev->roce.nb.notifier_call) {
3439 unregister_netdevice_notifier(&dev->roce.nb);
3440 dev->roce.nb.notifier_call = NULL;
3441 }
3442 }
3443
mlx5_enable_eth(struct mlx5_ib_dev * dev)3444 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3445 {
3446 int err;
3447
3448 err = mlx5_add_netdev_notifier(dev);
3449 if (err)
3450 return err;
3451
3452 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3453 err = mlx5_nic_vport_enable_roce(dev->mdev);
3454 if (err)
3455 goto err_unregister_netdevice_notifier;
3456 }
3457
3458 err = mlx5_eth_lag_init(dev);
3459 if (err)
3460 goto err_disable_roce;
3461
3462 return 0;
3463
3464 err_disable_roce:
3465 if (MLX5_CAP_GEN(dev->mdev, roce))
3466 mlx5_nic_vport_disable_roce(dev->mdev);
3467
3468 err_unregister_netdevice_notifier:
3469 mlx5_remove_netdev_notifier(dev);
3470 return err;
3471 }
3472
mlx5_disable_eth(struct mlx5_ib_dev * dev)3473 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3474 {
3475 mlx5_eth_lag_cleanup(dev);
3476 if (MLX5_CAP_GEN(dev->mdev, roce))
3477 mlx5_nic_vport_disable_roce(dev->mdev);
3478 }
3479
3480 struct mlx5_ib_counter {
3481 const char *name;
3482 size_t offset;
3483 };
3484
3485 #define INIT_Q_COUNTER(_name) \
3486 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3487
3488 static const struct mlx5_ib_counter basic_q_cnts[] = {
3489 INIT_Q_COUNTER(rx_write_requests),
3490 INIT_Q_COUNTER(rx_read_requests),
3491 INIT_Q_COUNTER(rx_atomic_requests),
3492 INIT_Q_COUNTER(out_of_buffer),
3493 };
3494
3495 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
3496 INIT_Q_COUNTER(out_of_sequence),
3497 };
3498
3499 static const struct mlx5_ib_counter retrans_q_cnts[] = {
3500 INIT_Q_COUNTER(duplicate_request),
3501 INIT_Q_COUNTER(rnr_nak_retry_err),
3502 INIT_Q_COUNTER(packet_seq_err),
3503 INIT_Q_COUNTER(implied_nak_seq_err),
3504 INIT_Q_COUNTER(local_ack_timeout_err),
3505 };
3506
3507 #define INIT_CONG_COUNTER(_name) \
3508 { .name = #_name, .offset = \
3509 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3510
3511 static const struct mlx5_ib_counter cong_cnts[] = {
3512 INIT_CONG_COUNTER(rp_cnp_ignored),
3513 INIT_CONG_COUNTER(rp_cnp_handled),
3514 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3515 INIT_CONG_COUNTER(np_cnp_sent),
3516 };
3517
3518 static const struct mlx5_ib_counter extended_err_cnts[] = {
3519 INIT_Q_COUNTER(resp_local_length_error),
3520 INIT_Q_COUNTER(resp_cqe_error),
3521 INIT_Q_COUNTER(req_cqe_error),
3522 INIT_Q_COUNTER(req_remote_invalid_request),
3523 INIT_Q_COUNTER(req_remote_access_errors),
3524 INIT_Q_COUNTER(resp_remote_access_errors),
3525 INIT_Q_COUNTER(resp_cqe_flush_error),
3526 INIT_Q_COUNTER(req_cqe_flush_error),
3527 };
3528
mlx5_ib_dealloc_counters(struct mlx5_ib_dev * dev)3529 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
3530 {
3531 unsigned int i;
3532
3533 for (i = 0; i < dev->num_ports; i++) {
3534 mlx5_core_dealloc_q_counter(dev->mdev,
3535 dev->port[i].cnts.set_id);
3536 kfree(dev->port[i].cnts.names);
3537 kfree(dev->port[i].cnts.offsets);
3538 }
3539 }
3540
__mlx5_ib_alloc_counters(struct mlx5_ib_dev * dev,struct mlx5_ib_counters * cnts)3541 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3542 struct mlx5_ib_counters *cnts)
3543 {
3544 u32 num_counters;
3545
3546 num_counters = ARRAY_SIZE(basic_q_cnts);
3547
3548 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3549 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3550
3551 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3552 num_counters += ARRAY_SIZE(retrans_q_cnts);
3553
3554 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
3555 num_counters += ARRAY_SIZE(extended_err_cnts);
3556
3557 cnts->num_q_counters = num_counters;
3558
3559 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3560 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3561 num_counters += ARRAY_SIZE(cong_cnts);
3562 }
3563
3564 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3565 if (!cnts->names)
3566 return -ENOMEM;
3567
3568 cnts->offsets = kcalloc(num_counters,
3569 sizeof(cnts->offsets), GFP_KERNEL);
3570 if (!cnts->offsets)
3571 goto err_names;
3572
3573 return 0;
3574
3575 err_names:
3576 kfree(cnts->names);
3577 return -ENOMEM;
3578 }
3579
mlx5_ib_fill_counters(struct mlx5_ib_dev * dev,const char ** names,size_t * offsets)3580 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3581 const char **names,
3582 size_t *offsets)
3583 {
3584 int i;
3585 int j = 0;
3586
3587 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3588 names[j] = basic_q_cnts[i].name;
3589 offsets[j] = basic_q_cnts[i].offset;
3590 }
3591
3592 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3593 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3594 names[j] = out_of_seq_q_cnts[i].name;
3595 offsets[j] = out_of_seq_q_cnts[i].offset;
3596 }
3597 }
3598
3599 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3600 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
3601 names[j] = retrans_q_cnts[i].name;
3602 offsets[j] = retrans_q_cnts[i].offset;
3603 }
3604 }
3605
3606 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
3607 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
3608 names[j] = extended_err_cnts[i].name;
3609 offsets[j] = extended_err_cnts[i].offset;
3610 }
3611 }
3612
3613 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3614 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
3615 names[j] = cong_cnts[i].name;
3616 offsets[j] = cong_cnts[i].offset;
3617 }
3618 }
3619 }
3620
mlx5_ib_alloc_counters(struct mlx5_ib_dev * dev)3621 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
3622 {
3623 int i;
3624 int ret;
3625
3626 for (i = 0; i < dev->num_ports; i++) {
3627 struct mlx5_ib_port *port = &dev->port[i];
3628
3629 ret = mlx5_core_alloc_q_counter(dev->mdev,
3630 &port->cnts.set_id);
3631 if (ret) {
3632 mlx5_ib_warn(dev,
3633 "couldn't allocate queue counter for port %d, err %d\n",
3634 i + 1, ret);
3635 goto dealloc_counters;
3636 }
3637
3638 ret = __mlx5_ib_alloc_counters(dev, &port->cnts);
3639 if (ret)
3640 goto dealloc_counters;
3641
3642 mlx5_ib_fill_counters(dev, port->cnts.names,
3643 port->cnts.offsets);
3644 }
3645
3646 return 0;
3647
3648 dealloc_counters:
3649 while (--i >= 0)
3650 mlx5_core_dealloc_q_counter(dev->mdev,
3651 dev->port[i].cnts.set_id);
3652
3653 return ret;
3654 }
3655
mlx5_ib_alloc_hw_stats(struct ib_device * ibdev,u8 port_num)3656 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3657 u8 port_num)
3658 {
3659 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3660 struct mlx5_ib_port *port = &dev->port[port_num - 1];
3661
3662 /* We support only per port stats */
3663 if (port_num == 0)
3664 return NULL;
3665
3666 return rdma_alloc_hw_stats_struct(port->cnts.names,
3667 port->cnts.num_q_counters +
3668 port->cnts.num_cong_counters,
3669 RDMA_HW_STATS_DEFAULT_LIFESPAN);
3670 }
3671
mlx5_ib_query_q_counters(struct mlx5_ib_dev * dev,struct mlx5_ib_port * port,struct rdma_hw_stats * stats)3672 static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev,
3673 struct mlx5_ib_port *port,
3674 struct rdma_hw_stats *stats)
3675 {
3676 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3677 void *out;
3678 __be32 val;
3679 int ret, i;
3680
3681 out = kvzalloc(outlen, GFP_KERNEL);
3682 if (!out)
3683 return -ENOMEM;
3684
3685 ret = mlx5_core_query_q_counter(dev->mdev,
3686 port->cnts.set_id, 0,
3687 out, outlen);
3688 if (ret)
3689 goto free;
3690
3691 for (i = 0; i < port->cnts.num_q_counters; i++) {
3692 val = *(__be32 *)(out + port->cnts.offsets[i]);
3693 stats->value[i] = (u64)be32_to_cpu(val);
3694 }
3695
3696 free:
3697 kvfree(out);
3698 return ret;
3699 }
3700
mlx5_ib_query_cong_counters(struct mlx5_ib_dev * dev,struct mlx5_ib_port * port,struct rdma_hw_stats * stats)3701 static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev,
3702 struct mlx5_ib_port *port,
3703 struct rdma_hw_stats *stats)
3704 {
3705 int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out);
3706 void *out;
3707 int ret, i;
3708 int offset = port->cnts.num_q_counters;
3709
3710 out = kvzalloc(outlen, GFP_KERNEL);
3711 if (!out)
3712 return -ENOMEM;
3713
3714 ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen);
3715 if (ret)
3716 goto free;
3717
3718 for (i = 0; i < port->cnts.num_cong_counters; i++) {
3719 stats->value[i + offset] =
3720 be64_to_cpup((__be64 *)(out +
3721 port->cnts.offsets[i + offset]));
3722 }
3723
3724 free:
3725 kvfree(out);
3726 return ret;
3727 }
3728
mlx5_ib_get_hw_stats(struct ib_device * ibdev,struct rdma_hw_stats * stats,u8 port_num,int index)3729 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3730 struct rdma_hw_stats *stats,
3731 u8 port_num, int index)
3732 {
3733 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3734 struct mlx5_ib_port *port = &dev->port[port_num - 1];
3735 int ret, num_counters;
3736
3737 if (!stats)
3738 return -EINVAL;
3739
3740 ret = mlx5_ib_query_q_counters(dev, port, stats);
3741 if (ret)
3742 return ret;
3743 num_counters = port->cnts.num_q_counters;
3744
3745 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3746 ret = mlx5_ib_query_cong_counters(dev, port, stats);
3747 if (ret)
3748 return ret;
3749 num_counters += port->cnts.num_cong_counters;
3750 }
3751
3752 return num_counters;
3753 }
3754
mlx5_ib_free_rdma_netdev(struct net_device * netdev)3755 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
3756 {
3757 return mlx5_rdma_netdev_free(netdev);
3758 }
3759
3760 static struct net_device*
mlx5_ib_alloc_rdma_netdev(struct ib_device * hca,u8 port_num,enum rdma_netdev_t type,const char * name,unsigned char name_assign_type,void (* setup)(struct net_device *))3761 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
3762 u8 port_num,
3763 enum rdma_netdev_t type,
3764 const char *name,
3765 unsigned char name_assign_type,
3766 void (*setup)(struct net_device *))
3767 {
3768 struct net_device *netdev;
3769 struct rdma_netdev *rn;
3770
3771 if (type != RDMA_NETDEV_IPOIB)
3772 return ERR_PTR(-EOPNOTSUPP);
3773
3774 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
3775 name, setup);
3776 if (likely(!IS_ERR_OR_NULL(netdev))) {
3777 rn = netdev_priv(netdev);
3778 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
3779 }
3780 return netdev;
3781 }
3782
delay_drop_debugfs_cleanup(struct mlx5_ib_dev * dev)3783 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
3784 {
3785 if (!dev->delay_drop.dbg)
3786 return;
3787 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
3788 kfree(dev->delay_drop.dbg);
3789 dev->delay_drop.dbg = NULL;
3790 }
3791
cancel_delay_drop(struct mlx5_ib_dev * dev)3792 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
3793 {
3794 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
3795 return;
3796
3797 cancel_work_sync(&dev->delay_drop.delay_drop_work);
3798 delay_drop_debugfs_cleanup(dev);
3799 }
3800
delay_drop_timeout_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)3801 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3802 size_t count, loff_t *pos)
3803 {
3804 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3805 char lbuf[20];
3806 int len;
3807
3808 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3809 return simple_read_from_buffer(buf, count, pos, lbuf, len);
3810 }
3811
delay_drop_timeout_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)3812 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3813 size_t count, loff_t *pos)
3814 {
3815 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3816 u32 timeout;
3817 u32 var;
3818
3819 if (kstrtouint_from_user(buf, count, 0, &var))
3820 return -EFAULT;
3821
3822 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3823 1000);
3824 if (timeout != var)
3825 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3826 timeout);
3827
3828 delay_drop->timeout = timeout;
3829
3830 return count;
3831 }
3832
3833 static const struct file_operations fops_delay_drop_timeout = {
3834 .owner = THIS_MODULE,
3835 .open = simple_open,
3836 .write = delay_drop_timeout_write,
3837 .read = delay_drop_timeout_read,
3838 };
3839
delay_drop_debugfs_init(struct mlx5_ib_dev * dev)3840 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
3841 {
3842 struct mlx5_ib_dbg_delay_drop *dbg;
3843
3844 if (!mlx5_debugfs_root)
3845 return 0;
3846
3847 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
3848 if (!dbg)
3849 return -ENOMEM;
3850
3851 dev->delay_drop.dbg = dbg;
3852
3853 dbg->dir_debugfs =
3854 debugfs_create_dir("delay_drop",
3855 dev->mdev->priv.dbg_root);
3856 if (!dbg->dir_debugfs)
3857 goto out_debugfs;
3858
3859 dbg->events_cnt_debugfs =
3860 debugfs_create_atomic_t("num_timeout_events", 0400,
3861 dbg->dir_debugfs,
3862 &dev->delay_drop.events_cnt);
3863 if (!dbg->events_cnt_debugfs)
3864 goto out_debugfs;
3865
3866 dbg->rqs_cnt_debugfs =
3867 debugfs_create_atomic_t("num_rqs", 0400,
3868 dbg->dir_debugfs,
3869 &dev->delay_drop.rqs_cnt);
3870 if (!dbg->rqs_cnt_debugfs)
3871 goto out_debugfs;
3872
3873 dbg->timeout_debugfs =
3874 debugfs_create_file("timeout", 0600,
3875 dbg->dir_debugfs,
3876 &dev->delay_drop,
3877 &fops_delay_drop_timeout);
3878 if (!dbg->timeout_debugfs)
3879 goto out_debugfs;
3880
3881 return 0;
3882
3883 out_debugfs:
3884 delay_drop_debugfs_cleanup(dev);
3885 return -ENOMEM;
3886 }
3887
init_delay_drop(struct mlx5_ib_dev * dev)3888 static void init_delay_drop(struct mlx5_ib_dev *dev)
3889 {
3890 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
3891 return;
3892
3893 mutex_init(&dev->delay_drop.lock);
3894 dev->delay_drop.dev = dev;
3895 dev->delay_drop.activate = false;
3896 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
3897 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
3898 atomic_set(&dev->delay_drop.rqs_cnt, 0);
3899 atomic_set(&dev->delay_drop.events_cnt, 0);
3900
3901 if (delay_drop_debugfs_init(dev))
3902 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
3903 }
3904
3905 static const struct cpumask *
mlx5_ib_get_vector_affinity(struct ib_device * ibdev,int comp_vector)3906 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
3907 {
3908 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3909
3910 return mlx5_get_vector_affinity_hint(dev->mdev, comp_vector);
3911 }
3912
mlx5_ib_add(struct mlx5_core_dev * mdev)3913 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
3914 {
3915 struct mlx5_ib_dev *dev;
3916 enum rdma_link_layer ll;
3917 int port_type_cap;
3918 const char *name;
3919 int err;
3920 int i;
3921
3922 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3923 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3924
3925 printk_once(KERN_INFO "%s", mlx5_version);
3926
3927 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3928 if (!dev)
3929 return NULL;
3930
3931 dev->mdev = mdev;
3932
3933 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3934 GFP_KERNEL);
3935 if (!dev->port)
3936 goto err_dealloc;
3937
3938 rwlock_init(&dev->roce.netdev_lock);
3939 err = get_port_caps(dev);
3940 if (err)
3941 goto err_free_port;
3942
3943 if (mlx5_use_mad_ifc(dev))
3944 get_ext_port_caps(dev);
3945
3946 if (!mlx5_lag_is_active(mdev))
3947 name = "mlx5_%d";
3948 else
3949 name = "mlx5_bond_%d";
3950
3951 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
3952 dev->ib_dev.owner = THIS_MODULE;
3953 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
3954 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
3955 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
3956 dev->ib_dev.phys_port_cnt = dev->num_ports;
3957 dev->ib_dev.num_comp_vectors =
3958 dev->mdev->priv.eq_table.num_comp_vectors;
3959 dev->ib_dev.dev.parent = &mdev->pdev->dev;
3960
3961 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
3962 dev->ib_dev.uverbs_cmd_mask =
3963 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
3964 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
3965 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
3966 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
3967 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
3968 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
3969 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
3970 (1ull << IB_USER_VERBS_CMD_REG_MR) |
3971 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
3972 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
3973 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3974 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
3975 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
3976 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
3977 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
3978 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
3979 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
3980 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
3981 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
3982 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
3983 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
3984 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
3985 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
3986 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
3987 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
3988 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
3989 dev->ib_dev.uverbs_ex_cmd_mask =
3990 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
3991 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
3992 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
3993 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP);
3994
3995 dev->ib_dev.query_device = mlx5_ib_query_device;
3996 dev->ib_dev.query_port = mlx5_ib_query_port;
3997 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
3998 if (ll == IB_LINK_LAYER_ETHERNET)
3999 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
4000 dev->ib_dev.query_gid = mlx5_ib_query_gid;
4001 dev->ib_dev.add_gid = mlx5_ib_add_gid;
4002 dev->ib_dev.del_gid = mlx5_ib_del_gid;
4003 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
4004 dev->ib_dev.modify_device = mlx5_ib_modify_device;
4005 dev->ib_dev.modify_port = mlx5_ib_modify_port;
4006 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
4007 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
4008 dev->ib_dev.mmap = mlx5_ib_mmap;
4009 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
4010 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
4011 dev->ib_dev.create_ah = mlx5_ib_create_ah;
4012 dev->ib_dev.query_ah = mlx5_ib_query_ah;
4013 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
4014 dev->ib_dev.create_srq = mlx5_ib_create_srq;
4015 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
4016 dev->ib_dev.query_srq = mlx5_ib_query_srq;
4017 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
4018 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
4019 dev->ib_dev.create_qp = mlx5_ib_create_qp;
4020 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
4021 dev->ib_dev.query_qp = mlx5_ib_query_qp;
4022 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
4023 dev->ib_dev.post_send = mlx5_ib_post_send;
4024 dev->ib_dev.post_recv = mlx5_ib_post_recv;
4025 dev->ib_dev.create_cq = mlx5_ib_create_cq;
4026 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
4027 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
4028 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
4029 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
4030 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
4031 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
4032 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
4033 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
4034 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
4035 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
4036 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
4037 dev->ib_dev.process_mad = mlx5_ib_process_mad;
4038 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
4039 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
4040 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
4041 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
4042 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
4043 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
4044 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
4045 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
4046
4047 if (mlx5_core_is_pf(mdev)) {
4048 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
4049 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
4050 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
4051 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
4052 }
4053
4054 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
4055
4056 mlx5_ib_internal_fill_odp_caps(dev);
4057
4058 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
4059
4060 if (MLX5_CAP_GEN(mdev, imaicl)) {
4061 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
4062 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
4063 dev->ib_dev.uverbs_cmd_mask |=
4064 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
4065 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
4066 }
4067
4068 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
4069 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
4070 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
4071 }
4072
4073 if (MLX5_CAP_GEN(mdev, xrc)) {
4074 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
4075 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
4076 dev->ib_dev.uverbs_cmd_mask |=
4077 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
4078 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
4079 }
4080
4081 dev->ib_dev.create_flow = mlx5_ib_create_flow;
4082 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
4083 dev->ib_dev.uverbs_ex_cmd_mask |=
4084 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
4085 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
4086
4087 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
4088 IB_LINK_LAYER_ETHERNET) {
4089 dev->ib_dev.create_wq = mlx5_ib_create_wq;
4090 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
4091 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
4092 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
4093 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
4094 dev->ib_dev.uverbs_ex_cmd_mask |=
4095 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
4096 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
4097 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
4098 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
4099 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
4100 }
4101 err = init_node_data(dev);
4102 if (err)
4103 goto err_free_port;
4104
4105 mutex_init(&dev->flow_db.lock);
4106 mutex_init(&dev->cap_mask_mutex);
4107 INIT_LIST_HEAD(&dev->qp_list);
4108 spin_lock_init(&dev->reset_flow_resource_lock);
4109
4110 if (ll == IB_LINK_LAYER_ETHERNET) {
4111 err = mlx5_enable_eth(dev);
4112 if (err)
4113 goto err_free_port;
4114 dev->roce.last_port_state = IB_PORT_DOWN;
4115 }
4116
4117 err = create_dev_resources(&dev->devr);
4118 if (err)
4119 goto err_disable_eth;
4120
4121 err = mlx5_ib_odp_init_one(dev);
4122 if (err)
4123 goto err_rsrc;
4124
4125 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
4126 err = mlx5_ib_alloc_counters(dev);
4127 if (err)
4128 goto err_odp;
4129 }
4130
4131 err = mlx5_ib_init_cong_debugfs(dev);
4132 if (err)
4133 goto err_cnt;
4134
4135 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4136 if (!dev->mdev->priv.uar)
4137 goto err_cong;
4138
4139 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4140 if (err)
4141 goto err_uar_page;
4142
4143 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4144 if (err)
4145 goto err_bfreg;
4146
4147 err = ib_register_device(&dev->ib_dev, NULL);
4148 if (err)
4149 goto err_fp_bfreg;
4150
4151 err = create_umr_res(dev);
4152 if (err)
4153 goto err_dev;
4154
4155 init_delay_drop(dev);
4156
4157 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
4158 err = device_create_file(&dev->ib_dev.dev,
4159 mlx5_class_attributes[i]);
4160 if (err)
4161 goto err_delay_drop;
4162 }
4163
4164 if ((MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
4165 (MLX5_CAP_GEN(mdev, disable_local_lb_uc) ||
4166 MLX5_CAP_GEN(mdev, disable_local_lb_mc)))
4167 mutex_init(&dev->lb_mutex);
4168
4169 dev->ib_active = true;
4170
4171 return dev;
4172
4173 err_delay_drop:
4174 cancel_delay_drop(dev);
4175 destroy_umrc_res(dev);
4176
4177 err_dev:
4178 ib_unregister_device(&dev->ib_dev);
4179
4180 err_fp_bfreg:
4181 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4182
4183 err_bfreg:
4184 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4185
4186 err_uar_page:
4187 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4188
4189 err_cong:
4190 mlx5_ib_cleanup_cong_debugfs(dev);
4191 err_cnt:
4192 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
4193 mlx5_ib_dealloc_counters(dev);
4194
4195 err_odp:
4196 mlx5_ib_odp_remove_one(dev);
4197
4198 err_rsrc:
4199 destroy_dev_resources(&dev->devr);
4200
4201 err_disable_eth:
4202 if (ll == IB_LINK_LAYER_ETHERNET) {
4203 mlx5_disable_eth(dev);
4204 mlx5_remove_netdev_notifier(dev);
4205 }
4206
4207 err_free_port:
4208 kfree(dev->port);
4209
4210 err_dealloc:
4211 ib_dealloc_device((struct ib_device *)dev);
4212
4213 return NULL;
4214 }
4215
mlx5_ib_remove(struct mlx5_core_dev * mdev,void * context)4216 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
4217 {
4218 struct mlx5_ib_dev *dev = context;
4219 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
4220
4221 cancel_delay_drop(dev);
4222 mlx5_remove_netdev_notifier(dev);
4223 ib_unregister_device(&dev->ib_dev);
4224 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4225 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4226 mlx5_put_uars_page(dev->mdev, mdev->priv.uar);
4227 mlx5_ib_cleanup_cong_debugfs(dev);
4228 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
4229 mlx5_ib_dealloc_counters(dev);
4230 destroy_umrc_res(dev);
4231 mlx5_ib_odp_remove_one(dev);
4232 destroy_dev_resources(&dev->devr);
4233 if (ll == IB_LINK_LAYER_ETHERNET)
4234 mlx5_disable_eth(dev);
4235 kfree(dev->port);
4236 ib_dealloc_device(&dev->ib_dev);
4237 }
4238
4239 static struct mlx5_interface mlx5_ib_interface = {
4240 .add = mlx5_ib_add,
4241 .remove = mlx5_ib_remove,
4242 .event = mlx5_ib_event,
4243 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4244 .pfault = mlx5_ib_pfault,
4245 #endif
4246 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
4247 };
4248
mlx5_ib_init(void)4249 static int __init mlx5_ib_init(void)
4250 {
4251 int err;
4252
4253 mlx5_ib_odp_init();
4254
4255 err = mlx5_register_interface(&mlx5_ib_interface);
4256
4257 return err;
4258 }
4259
mlx5_ib_cleanup(void)4260 static void __exit mlx5_ib_cleanup(void)
4261 {
4262 mlx5_unregister_interface(&mlx5_ib_interface);
4263 }
4264
4265 module_init(mlx5_ib_init);
4266 module_exit(mlx5_ib_cleanup);
4267