1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
21 #define _ASM_X86_AMD_IOMMU_TYPES_H
22
23 #include <linux/types.h>
24 #include <linux/mutex.h>
25 #include <linux/msi.h>
26 #include <linux/list.h>
27 #include <linux/spinlock.h>
28 #include <linux/pci.h>
29 #include <linux/irqreturn.h>
30
31 /*
32 * Maximum number of IOMMUs supported
33 */
34 #define MAX_IOMMUS 32
35
36 /*
37 * some size calculation constants
38 */
39 #define DEV_TABLE_ENTRY_SIZE 32
40 #define ALIAS_TABLE_ENTRY_SIZE 2
41 #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *))
42
43 /* Capability offsets used by the driver */
44 #define MMIO_CAP_HDR_OFFSET 0x00
45 #define MMIO_RANGE_OFFSET 0x0c
46 #define MMIO_MISC_OFFSET 0x10
47
48 /* Masks, shifts and macros to parse the device range capability */
49 #define MMIO_RANGE_LD_MASK 0xff000000
50 #define MMIO_RANGE_FD_MASK 0x00ff0000
51 #define MMIO_RANGE_BUS_MASK 0x0000ff00
52 #define MMIO_RANGE_LD_SHIFT 24
53 #define MMIO_RANGE_FD_SHIFT 16
54 #define MMIO_RANGE_BUS_SHIFT 8
55 #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
56 #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
57 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
58 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
59
60 /* Flag masks for the AMD IOMMU exclusion range */
61 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
62 #define MMIO_EXCL_ALLOW_MASK 0x02ULL
63
64 /* Used offsets into the MMIO space */
65 #define MMIO_DEV_TABLE_OFFSET 0x0000
66 #define MMIO_CMD_BUF_OFFSET 0x0008
67 #define MMIO_EVT_BUF_OFFSET 0x0010
68 #define MMIO_CONTROL_OFFSET 0x0018
69 #define MMIO_EXCL_BASE_OFFSET 0x0020
70 #define MMIO_EXCL_LIMIT_OFFSET 0x0028
71 #define MMIO_EXT_FEATURES 0x0030
72 #define MMIO_PPR_LOG_OFFSET 0x0038
73 #define MMIO_GA_LOG_BASE_OFFSET 0x00e0
74 #define MMIO_GA_LOG_TAIL_OFFSET 0x00e8
75 #define MMIO_CMD_HEAD_OFFSET 0x2000
76 #define MMIO_CMD_TAIL_OFFSET 0x2008
77 #define MMIO_EVT_HEAD_OFFSET 0x2010
78 #define MMIO_EVT_TAIL_OFFSET 0x2018
79 #define MMIO_STATUS_OFFSET 0x2020
80 #define MMIO_PPR_HEAD_OFFSET 0x2030
81 #define MMIO_PPR_TAIL_OFFSET 0x2038
82 #define MMIO_GA_HEAD_OFFSET 0x2040
83 #define MMIO_GA_TAIL_OFFSET 0x2048
84 #define MMIO_CNTR_CONF_OFFSET 0x4000
85 #define MMIO_CNTR_REG_OFFSET 0x40000
86 #define MMIO_REG_END_OFFSET 0x80000
87
88
89
90 /* Extended Feature Bits */
91 #define FEATURE_PREFETCH (1ULL<<0)
92 #define FEATURE_PPR (1ULL<<1)
93 #define FEATURE_X2APIC (1ULL<<2)
94 #define FEATURE_NX (1ULL<<3)
95 #define FEATURE_GT (1ULL<<4)
96 #define FEATURE_IA (1ULL<<6)
97 #define FEATURE_GA (1ULL<<7)
98 #define FEATURE_HE (1ULL<<8)
99 #define FEATURE_PC (1ULL<<9)
100 #define FEATURE_GAM_VAPIC (1ULL<<21)
101
102 #define FEATURE_PASID_SHIFT 32
103 #define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT)
104
105 #define FEATURE_GLXVAL_SHIFT 14
106 #define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT)
107
108 /* Note:
109 * The current driver only support 16-bit PASID.
110 * Currently, hardware only implement upto 16-bit PASID
111 * even though the spec says it could have upto 20 bits.
112 */
113 #define PASID_MASK 0x0000ffff
114
115 /* MMIO status bits */
116 #define MMIO_STATUS_EVT_INT_MASK (1 << 1)
117 #define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2)
118 #define MMIO_STATUS_PPR_INT_MASK (1 << 6)
119 #define MMIO_STATUS_GALOG_RUN_MASK (1 << 8)
120 #define MMIO_STATUS_GALOG_OVERFLOW_MASK (1 << 9)
121 #define MMIO_STATUS_GALOG_INT_MASK (1 << 10)
122
123 /* event logging constants */
124 #define EVENT_ENTRY_SIZE 0x10
125 #define EVENT_TYPE_SHIFT 28
126 #define EVENT_TYPE_MASK 0xf
127 #define EVENT_TYPE_ILL_DEV 0x1
128 #define EVENT_TYPE_IO_FAULT 0x2
129 #define EVENT_TYPE_DEV_TAB_ERR 0x3
130 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
131 #define EVENT_TYPE_ILL_CMD 0x5
132 #define EVENT_TYPE_CMD_HARD_ERR 0x6
133 #define EVENT_TYPE_IOTLB_INV_TO 0x7
134 #define EVENT_TYPE_INV_DEV_REQ 0x8
135 #define EVENT_DEVID_MASK 0xffff
136 #define EVENT_DEVID_SHIFT 0
137 #define EVENT_DOMID_MASK 0xffff
138 #define EVENT_DOMID_SHIFT 0
139 #define EVENT_FLAGS_MASK 0xfff
140 #define EVENT_FLAGS_SHIFT 0x10
141
142 /* feature control bits */
143 #define CONTROL_IOMMU_EN 0x00ULL
144 #define CONTROL_HT_TUN_EN 0x01ULL
145 #define CONTROL_EVT_LOG_EN 0x02ULL
146 #define CONTROL_EVT_INT_EN 0x03ULL
147 #define CONTROL_COMWAIT_EN 0x04ULL
148 #define CONTROL_INV_TIMEOUT 0x05ULL
149 #define CONTROL_PASSPW_EN 0x08ULL
150 #define CONTROL_RESPASSPW_EN 0x09ULL
151 #define CONTROL_COHERENT_EN 0x0aULL
152 #define CONTROL_ISOC_EN 0x0bULL
153 #define CONTROL_CMDBUF_EN 0x0cULL
154 #define CONTROL_PPFLOG_EN 0x0dULL
155 #define CONTROL_PPFINT_EN 0x0eULL
156 #define CONTROL_PPR_EN 0x0fULL
157 #define CONTROL_GT_EN 0x10ULL
158 #define CONTROL_GA_EN 0x11ULL
159 #define CONTROL_GAM_EN 0x19ULL
160 #define CONTROL_GALOG_EN 0x1CULL
161 #define CONTROL_GAINT_EN 0x1DULL
162
163 #define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT)
164 #define CTRL_INV_TO_NONE 0
165 #define CTRL_INV_TO_1MS 1
166 #define CTRL_INV_TO_10MS 2
167 #define CTRL_INV_TO_100MS 3
168 #define CTRL_INV_TO_1S 4
169 #define CTRL_INV_TO_10S 5
170 #define CTRL_INV_TO_100S 6
171
172 /* command specific defines */
173 #define CMD_COMPL_WAIT 0x01
174 #define CMD_INV_DEV_ENTRY 0x02
175 #define CMD_INV_IOMMU_PAGES 0x03
176 #define CMD_INV_IOTLB_PAGES 0x04
177 #define CMD_INV_IRT 0x05
178 #define CMD_COMPLETE_PPR 0x07
179 #define CMD_INV_ALL 0x08
180
181 #define CMD_COMPL_WAIT_STORE_MASK 0x01
182 #define CMD_COMPL_WAIT_INT_MASK 0x02
183 #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
184 #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
185 #define CMD_INV_IOMMU_PAGES_GN_MASK 0x04
186
187 #define PPR_STATUS_MASK 0xf
188 #define PPR_STATUS_SHIFT 12
189
190 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
191
192 /* macros and definitions for device table entries */
193 #define DEV_ENTRY_VALID 0x00
194 #define DEV_ENTRY_TRANSLATION 0x01
195 #define DEV_ENTRY_IR 0x3d
196 #define DEV_ENTRY_IW 0x3e
197 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
198 #define DEV_ENTRY_EX 0x67
199 #define DEV_ENTRY_SYSMGT1 0x68
200 #define DEV_ENTRY_SYSMGT2 0x69
201 #define DEV_ENTRY_IRQ_TBL_EN 0x80
202 #define DEV_ENTRY_INIT_PASS 0xb8
203 #define DEV_ENTRY_EINT_PASS 0xb9
204 #define DEV_ENTRY_NMI_PASS 0xba
205 #define DEV_ENTRY_LINT0_PASS 0xbe
206 #define DEV_ENTRY_LINT1_PASS 0xbf
207 #define DEV_ENTRY_MODE_MASK 0x07
208 #define DEV_ENTRY_MODE_SHIFT 0x09
209
210 #define MAX_DEV_TABLE_ENTRIES 0xffff
211
212 /* constants to configure the command buffer */
213 #define CMD_BUFFER_SIZE 8192
214 #define CMD_BUFFER_UNINITIALIZED 1
215 #define CMD_BUFFER_ENTRIES 512
216 #define MMIO_CMD_SIZE_SHIFT 56
217 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
218
219 /* constants for event buffer handling */
220 #define EVT_BUFFER_SIZE 8192 /* 512 entries */
221 #define EVT_LEN_MASK (0x9ULL << 56)
222
223 /* Constants for PPR Log handling */
224 #define PPR_LOG_ENTRIES 512
225 #define PPR_LOG_SIZE_SHIFT 56
226 #define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT)
227 #define PPR_ENTRY_SIZE 16
228 #define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES)
229
230 #define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
231 #define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL)
232 #define PPR_DEVID(x) ((x) & 0xffffULL)
233 #define PPR_TAG(x) (((x) >> 32) & 0x3ffULL)
234 #define PPR_PASID1(x) (((x) >> 16) & 0xffffULL)
235 #define PPR_PASID2(x) (((x) >> 42) & 0xfULL)
236 #define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x))
237
238 #define PPR_REQ_FAULT 0x01
239
240 /* Constants for GA Log handling */
241 #define GA_LOG_ENTRIES 512
242 #define GA_LOG_SIZE_SHIFT 56
243 #define GA_LOG_SIZE_512 (0x8ULL << GA_LOG_SIZE_SHIFT)
244 #define GA_ENTRY_SIZE 8
245 #define GA_LOG_SIZE (GA_ENTRY_SIZE * GA_LOG_ENTRIES)
246
247 #define GA_TAG(x) (u32)(x & 0xffffffffULL)
248 #define GA_DEVID(x) (u16)(((x) >> 32) & 0xffffULL)
249 #define GA_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
250
251 #define GA_GUEST_NR 0x1
252
253 /* Bit value definition for dte irq remapping fields*/
254 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
255 #define DTE_IRQ_REMAP_INTCTL_MASK (0x3ULL << 60)
256 #define DTE_IRQ_TABLE_LEN_MASK (0xfULL << 1)
257 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
258 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
259 #define DTE_IRQ_REMAP_ENABLE 1ULL
260
261 #define PAGE_MODE_NONE 0x00
262 #define PAGE_MODE_1_LEVEL 0x01
263 #define PAGE_MODE_2_LEVEL 0x02
264 #define PAGE_MODE_3_LEVEL 0x03
265 #define PAGE_MODE_4_LEVEL 0x04
266 #define PAGE_MODE_5_LEVEL 0x05
267 #define PAGE_MODE_6_LEVEL 0x06
268
269 #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9))
270 #define PM_LEVEL_SIZE(x) (((x) < 6) ? \
271 ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
272 (0xffffffffffffffffULL))
273 #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
274 #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL)
275 #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \
276 IOMMU_PTE_PR | IOMMU_PTE_IR | IOMMU_PTE_IW)
277 #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL)
278
279 #define PM_MAP_4k 0
280 #define PM_ADDR_MASK 0x000ffffffffff000ULL
281 #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \
282 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
283 #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr))
284
285 /*
286 * Returns the page table level to use for a given page size
287 * Pagesize is expected to be a power-of-two
288 */
289 #define PAGE_SIZE_LEVEL(pagesize) \
290 ((__ffs(pagesize) - 12) / 9)
291 /*
292 * Returns the number of ptes to use for a given page size
293 * Pagesize is expected to be a power-of-two
294 */
295 #define PAGE_SIZE_PTE_COUNT(pagesize) \
296 (1ULL << ((__ffs(pagesize) - 12) % 9))
297
298 /*
299 * Aligns a given io-virtual address to a given page size
300 * Pagesize is expected to be a power-of-two
301 */
302 #define PAGE_SIZE_ALIGN(address, pagesize) \
303 ((address) & ~((pagesize) - 1))
304 /*
305 * Creates an IOMMU PTE for an address and a given pagesize
306 * The PTE has no permission bits set
307 * Pagesize is expected to be a power-of-two larger than 4096
308 */
309 #define PAGE_SIZE_PTE(address, pagesize) \
310 (((address) | ((pagesize) - 1)) & \
311 (~(pagesize >> 1)) & PM_ADDR_MASK)
312
313 /*
314 * Takes a PTE value with mode=0x07 and returns the page size it maps
315 */
316 #define PTE_PAGE_SIZE(pte) \
317 (1ULL << (1 + ffz(((pte) | 0xfffULL))))
318
319 /*
320 * Takes a page-table level and returns the default page-size for this level
321 */
322 #define PTE_LEVEL_PAGE_SIZE(level) \
323 (1ULL << (12 + (9 * (level))))
324
325 /*
326 * Bit value definition for I/O PTE fields
327 */
328 #define IOMMU_PTE_PR (1ULL << 0)
329 #define IOMMU_PTE_U (1ULL << 59)
330 #define IOMMU_PTE_FC (1ULL << 60)
331 #define IOMMU_PTE_IR (1ULL << 61)
332 #define IOMMU_PTE_IW (1ULL << 62)
333
334 /*
335 * Bit value definition for DTE fields
336 */
337 #define DTE_FLAG_V (1ULL << 0)
338 #define DTE_FLAG_TV (1ULL << 1)
339 #define DTE_FLAG_IR (1ULL << 61)
340 #define DTE_FLAG_IW (1ULL << 62)
341
342 #define DTE_FLAG_IOTLB (1ULL << 32)
343 #define DTE_FLAG_GV (1ULL << 55)
344 #define DTE_FLAG_MASK (0x3ffULL << 32)
345 #define DTE_GLX_SHIFT (56)
346 #define DTE_GLX_MASK (3)
347 #define DEV_DOMID_MASK 0xffffULL
348
349 #define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL)
350 #define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL)
351 #define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0xfffffULL)
352
353 #define DTE_GCR3_INDEX_A 0
354 #define DTE_GCR3_INDEX_B 1
355 #define DTE_GCR3_INDEX_C 1
356
357 #define DTE_GCR3_SHIFT_A 58
358 #define DTE_GCR3_SHIFT_B 16
359 #define DTE_GCR3_SHIFT_C 43
360
361 #define GCR3_VALID 0x01ULL
362
363 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
364 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_PR)
365 #define IOMMU_PTE_PAGE(pte) (iommu_phys_to_virt((pte) & IOMMU_PAGE_MASK))
366 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
367
368 #define IOMMU_PROT_MASK 0x03
369 #define IOMMU_PROT_IR 0x01
370 #define IOMMU_PROT_IW 0x02
371
372 #define IOMMU_UNITY_MAP_FLAG_EXCL_RANGE (1 << 2)
373
374 /* IOMMU capabilities */
375 #define IOMMU_CAP_IOTLB 24
376 #define IOMMU_CAP_NPCACHE 26
377 #define IOMMU_CAP_EFR 27
378
379 /* IOMMU Feature Reporting Field (for IVHD type 10h */
380 #define IOMMU_FEAT_GASUP_SHIFT 6
381
382 /* IOMMU Extended Feature Register (EFR) */
383 #define IOMMU_EFR_GASUP_SHIFT 7
384
385 #define MAX_DOMAIN_ID 65536
386
387 /* Protection domain flags */
388 #define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */
389 #define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops
390 domain for an IOMMU */
391 #define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page
392 translation */
393 #define PD_IOMMUV2_MASK (1UL << 3) /* domain has gcr3 table */
394
395 extern bool amd_iommu_dump;
396 #define DUMP_printk(format, arg...) \
397 do { \
398 if (amd_iommu_dump) \
399 printk(KERN_INFO "AMD-Vi: " format, ## arg); \
400 } while(0);
401
402 /* global flag if IOMMUs cache non-present entries */
403 extern bool amd_iommu_np_cache;
404 /* Only true if all IOMMUs support device IOTLBs */
405 extern bool amd_iommu_iotlb_sup;
406
407 #define MAX_IRQS_PER_TABLE 256
408 #define IRQ_TABLE_ALIGNMENT 128
409
410 struct irq_remap_table {
411 spinlock_t lock;
412 unsigned min_index;
413 u32 *table;
414 };
415
416 extern struct irq_remap_table **irq_lookup_table;
417
418 /* Interrupt remapping feature used? */
419 extern bool amd_iommu_irq_remap;
420
421 /* kmem_cache to get tables with 128 byte alignement */
422 extern struct kmem_cache *amd_iommu_irq_cache;
423
424 /*
425 * Make iterating over all IOMMUs easier
426 */
427 #define for_each_iommu(iommu) \
428 list_for_each_entry((iommu), &amd_iommu_list, list)
429 #define for_each_iommu_safe(iommu, next) \
430 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
431
432 #define APERTURE_RANGE_SHIFT 27 /* 128 MB */
433 #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT)
434 #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
435 #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */
436 #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
437 #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL)
438
439
440 /*
441 * This struct is used to pass information about
442 * incoming PPR faults around.
443 */
444 struct amd_iommu_fault {
445 u64 address; /* IO virtual address of the fault*/
446 u32 pasid; /* Address space identifier */
447 u16 device_id; /* Originating PCI device id */
448 u16 tag; /* PPR tag */
449 u16 flags; /* Fault flags */
450
451 };
452
453
454 struct iommu_domain;
455 struct irq_domain;
456 struct amd_irte_ops;
457
458 #define AMD_IOMMU_FLAG_TRANS_PRE_ENABLED (1 << 0)
459
460 /*
461 * This structure contains generic data for IOMMU protection domains
462 * independent of their use.
463 */
464 struct protection_domain {
465 struct list_head list; /* for list of all protection domains */
466 struct list_head dev_list; /* List of all devices in this domain */
467 struct iommu_domain domain; /* generic domain handle used by
468 iommu core code */
469 spinlock_t lock; /* mostly used to lock the page table*/
470 struct mutex api_lock; /* protect page tables in the iommu-api path */
471 u16 id; /* the domain id written to the device table */
472 int mode; /* paging mode (0-6 levels) */
473 u64 *pt_root; /* page table root pointer */
474 int glx; /* Number of levels for GCR3 table */
475 u64 *gcr3_tbl; /* Guest CR3 table */
476 unsigned long flags; /* flags to find out type of domain */
477 bool updated; /* complete domain flush required */
478 unsigned dev_cnt; /* devices assigned to this domain */
479 unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
480 };
481
482 /*
483 * Structure where we save information about one hardware AMD IOMMU in the
484 * system.
485 */
486 struct amd_iommu {
487 struct list_head list;
488
489 /* Index within the IOMMU array */
490 int index;
491
492 /* locks the accesses to the hardware */
493 spinlock_t lock;
494
495 /* Pointer to PCI device of this IOMMU */
496 struct pci_dev *dev;
497
498 /* Cache pdev to root device for resume quirks */
499 struct pci_dev *root_pdev;
500
501 /* physical address of MMIO space */
502 u64 mmio_phys;
503
504 /* physical end address of MMIO space */
505 u64 mmio_phys_end;
506
507 /* virtual address of MMIO space */
508 u8 __iomem *mmio_base;
509
510 /* capabilities of that IOMMU read from ACPI */
511 u32 cap;
512
513 /* flags read from acpi table */
514 u8 acpi_flags;
515
516 /* Extended features */
517 u64 features;
518
519 /* IOMMUv2 */
520 bool is_iommu_v2;
521
522 /* PCI device id of the IOMMU device */
523 u16 devid;
524
525 /*
526 * Capability pointer. There could be more than one IOMMU per PCI
527 * device function if there are more than one AMD IOMMU capability
528 * pointers.
529 */
530 u16 cap_ptr;
531
532 /* pci domain of this IOMMU */
533 u16 pci_seg;
534
535 /* start of exclusion range of that IOMMU */
536 u64 exclusion_start;
537 /* length of exclusion range of that IOMMU */
538 u64 exclusion_length;
539
540 /* command buffer virtual address */
541 u8 *cmd_buf;
542 u32 cmd_buf_head;
543 u32 cmd_buf_tail;
544
545 /* event buffer virtual address */
546 u8 *evt_buf;
547
548 /* Base of the PPR log, if present */
549 u8 *ppr_log;
550
551 /* Base of the GA log, if present */
552 u8 *ga_log;
553
554 /* Tail of the GA log, if present */
555 u8 *ga_log_tail;
556
557 /* true if interrupts for this IOMMU are already enabled */
558 bool int_enabled;
559
560 /* if one, we need to send a completion wait command */
561 bool need_sync;
562
563 /* Handle for IOMMU core code */
564 struct iommu_device iommu;
565
566 /*
567 * We can't rely on the BIOS to restore all values on reinit, so we
568 * need to stash them
569 */
570
571 /* The iommu BAR */
572 u32 stored_addr_lo;
573 u32 stored_addr_hi;
574
575 /*
576 * Each iommu has 6 l1s, each of which is documented as having 0x12
577 * registers
578 */
579 u32 stored_l1[6][0x12];
580
581 /* The l2 indirect registers */
582 u32 stored_l2[0x83];
583
584 /* The maximum PC banks and counters/bank (PCSup=1) */
585 u8 max_banks;
586 u8 max_counters;
587 #ifdef CONFIG_IRQ_REMAP
588 struct irq_domain *ir_domain;
589 struct irq_domain *msi_domain;
590
591 struct amd_irte_ops *irte_ops;
592 #endif
593
594 u32 flags;
595 volatile u64 __aligned(8) cmd_sem;
596 };
597
dev_to_amd_iommu(struct device * dev)598 static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev)
599 {
600 struct iommu_device *iommu = dev_to_iommu_device(dev);
601
602 return container_of(iommu, struct amd_iommu, iommu);
603 }
604
605 #define ACPIHID_UID_LEN 256
606 #define ACPIHID_HID_LEN 9
607
608 struct acpihid_map_entry {
609 struct list_head list;
610 u8 uid[ACPIHID_UID_LEN];
611 u8 hid[ACPIHID_HID_LEN];
612 u16 devid;
613 u16 root_devid;
614 bool cmd_line;
615 struct iommu_group *group;
616 };
617
618 struct devid_map {
619 struct list_head list;
620 u8 id;
621 u16 devid;
622 bool cmd_line;
623 };
624
625 /*
626 * This struct contains device specific data for the IOMMU
627 */
628 struct iommu_dev_data {
629 struct list_head list; /* For domain->dev_list */
630 struct list_head dev_data_list; /* For global dev_data_list */
631 struct protection_domain *domain; /* Domain the device is bound to */
632 u16 devid; /* PCI Device ID */
633 u16 alias; /* Alias Device ID */
634 bool iommu_v2; /* Device can make use of IOMMUv2 */
635 bool passthrough; /* Device is identity mapped */
636 struct {
637 bool enabled;
638 int qdep;
639 } ats; /* ATS state */
640 bool pri_tlp; /* PASID TLB required for
641 PPR completions */
642 u32 errata; /* Bitmap for errata to apply */
643 bool use_vapic; /* Enable device to use vapic mode */
644 bool defer_attach;
645
646 struct ratelimit_state rs; /* Ratelimit IOPF messages */
647 };
648
649 /* Map HPET and IOAPIC ids to the devid used by the IOMMU */
650 extern struct list_head ioapic_map;
651 extern struct list_head hpet_map;
652 extern struct list_head acpihid_map;
653
654 /*
655 * List with all IOMMUs in the system. This list is not locked because it is
656 * only written and read at driver initialization or suspend time
657 */
658 extern struct list_head amd_iommu_list;
659
660 /*
661 * Array with pointers to each IOMMU struct
662 * The indices are referenced in the protection domains
663 */
664 extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
665
666 /*
667 * Declarations for the global list of all protection domains
668 */
669 extern spinlock_t amd_iommu_pd_lock;
670 extern struct list_head amd_iommu_pd_list;
671
672 /*
673 * Structure defining one entry in the device table
674 */
675 struct dev_table_entry {
676 u64 data[4];
677 };
678
679 /*
680 * One entry for unity mappings parsed out of the ACPI table.
681 */
682 struct unity_map_entry {
683 struct list_head list;
684
685 /* starting device id this entry is used for (including) */
686 u16 devid_start;
687 /* end device id this entry is used for (including) */
688 u16 devid_end;
689
690 /* start address to unity map (including) */
691 u64 address_start;
692 /* end address to unity map (including) */
693 u64 address_end;
694
695 /* required protection */
696 int prot;
697 };
698
699 /*
700 * List of all unity mappings. It is not locked because as runtime it is only
701 * read. It is created at ACPI table parsing time.
702 */
703 extern struct list_head amd_iommu_unity_map;
704
705 /*
706 * Data structures for device handling
707 */
708
709 /*
710 * Device table used by hardware. Read and write accesses by software are
711 * locked with the amd_iommu_pd_table lock.
712 */
713 extern struct dev_table_entry *amd_iommu_dev_table;
714
715 /*
716 * Alias table to find requestor ids to device ids. Not locked because only
717 * read on runtime.
718 */
719 extern u16 *amd_iommu_alias_table;
720
721 /*
722 * Reverse lookup table to find the IOMMU which translates a specific device.
723 */
724 extern struct amd_iommu **amd_iommu_rlookup_table;
725
726 /* size of the dma_ops aperture as power of 2 */
727 extern unsigned amd_iommu_aperture_order;
728
729 /* largest PCI device id we expect translation requests for */
730 extern u16 amd_iommu_last_bdf;
731
732 /* allocation bitmap for domain ids */
733 extern unsigned long *amd_iommu_pd_alloc_bitmap;
734
735 /*
736 * If true, the addresses will be flushed on unmap time, not when
737 * they are reused
738 */
739 extern bool amd_iommu_unmap_flush;
740
741 /* Smallest max PASID supported by any IOMMU in the system */
742 extern u32 amd_iommu_max_pasid;
743
744 extern bool amd_iommu_v2_present;
745
746 extern bool amd_iommu_force_isolation;
747
748 /* Max levels of glxval supported */
749 extern int amd_iommu_max_glx_val;
750
751 /*
752 * This function flushes all internal caches of
753 * the IOMMU used by this driver.
754 */
755 extern void iommu_flush_all_caches(struct amd_iommu *iommu);
756
get_ioapic_devid(int id)757 static inline int get_ioapic_devid(int id)
758 {
759 struct devid_map *entry;
760
761 list_for_each_entry(entry, &ioapic_map, list) {
762 if (entry->id == id)
763 return entry->devid;
764 }
765
766 return -EINVAL;
767 }
768
get_hpet_devid(int id)769 static inline int get_hpet_devid(int id)
770 {
771 struct devid_map *entry;
772
773 list_for_each_entry(entry, &hpet_map, list) {
774 if (entry->id == id)
775 return entry->devid;
776 }
777
778 return -EINVAL;
779 }
780
781 enum amd_iommu_intr_mode_type {
782 AMD_IOMMU_GUEST_IR_LEGACY,
783
784 /* This mode is not visible to users. It is used when
785 * we cannot fully enable vAPIC and fallback to only support
786 * legacy interrupt remapping via 128-bit IRTE.
787 */
788 AMD_IOMMU_GUEST_IR_LEGACY_GA,
789 AMD_IOMMU_GUEST_IR_VAPIC,
790 };
791
792 #define AMD_IOMMU_GUEST_IR_GA(x) (x == AMD_IOMMU_GUEST_IR_VAPIC || \
793 x == AMD_IOMMU_GUEST_IR_LEGACY_GA)
794
795 #define AMD_IOMMU_GUEST_IR_VAPIC(x) (x == AMD_IOMMU_GUEST_IR_VAPIC)
796
797 union irte {
798 u32 val;
799 struct {
800 u32 valid : 1,
801 no_fault : 1,
802 int_type : 3,
803 rq_eoi : 1,
804 dm : 1,
805 rsvd_1 : 1,
806 destination : 8,
807 vector : 8,
808 rsvd_2 : 8;
809 } fields;
810 };
811
812 union irte_ga_lo {
813 u64 val;
814
815 /* For int remapping */
816 struct {
817 u64 valid : 1,
818 no_fault : 1,
819 /* ------ */
820 int_type : 3,
821 rq_eoi : 1,
822 dm : 1,
823 /* ------ */
824 guest_mode : 1,
825 destination : 8,
826 rsvd : 48;
827 } fields_remap;
828
829 /* For guest vAPIC */
830 struct {
831 u64 valid : 1,
832 no_fault : 1,
833 /* ------ */
834 ga_log_intr : 1,
835 rsvd1 : 3,
836 is_run : 1,
837 /* ------ */
838 guest_mode : 1,
839 destination : 8,
840 rsvd2 : 16,
841 ga_tag : 32;
842 } fields_vapic;
843 };
844
845 union irte_ga_hi {
846 u64 val;
847 struct {
848 u64 vector : 8,
849 rsvd_1 : 4,
850 ga_root_ptr : 40,
851 rsvd_2 : 12;
852 } fields;
853 };
854
855 struct irte_ga {
856 union irte_ga_lo lo;
857 union irte_ga_hi hi;
858 };
859
860 struct irq_2_irte {
861 u16 devid; /* Device ID for IRTE table */
862 u16 index; /* Index into IRTE table*/
863 };
864
865 struct amd_ir_data {
866 u32 cached_ga_tag;
867 struct irq_2_irte irq_2_irte;
868 struct msi_msg msi_entry;
869 void *entry; /* Pointer to union irte or struct irte_ga */
870 void *ref; /* Pointer to the actual irte */
871 };
872
873 struct amd_irte_ops {
874 void (*prepare)(void *, u32, u32, u8, u32, int);
875 void (*activate)(void *, u16, u16);
876 void (*deactivate)(void *, u16, u16);
877 void (*set_affinity)(void *, u16, u16, u8, u32);
878 void *(*get)(struct irq_remap_table *, int);
879 void (*set_allocated)(struct irq_remap_table *, int);
880 bool (*is_allocated)(struct irq_remap_table *, int);
881 void (*clear_allocated)(struct irq_remap_table *, int);
882 };
883
884 #ifdef CONFIG_IRQ_REMAP
885 extern struct amd_irte_ops irte_32_ops;
886 extern struct amd_irte_ops irte_128_ops;
887 #endif
888
889 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */
890