1 /*
2 * Copyright © 2015 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * Authors: David Woodhouse <dwmw2@infradead.org>
14 */
15
16 #include <linux/intel-iommu.h>
17 #include <linux/mmu_notifier.h>
18 #include <linux/sched.h>
19 #include <linux/sched/mm.h>
20 #include <linux/slab.h>
21 #include <linux/intel-svm.h>
22 #include <linux/rculist.h>
23 #include <linux/pci.h>
24 #include <linux/pci-ats.h>
25 #include <linux/dmar.h>
26 #include <linux/interrupt.h>
27 #include <asm/page.h>
28
29 static irqreturn_t prq_event_thread(int irq, void *d);
30
31 struct pasid_entry {
32 u64 val;
33 };
34
35 struct pasid_state_entry {
36 u64 val;
37 };
38
intel_svm_alloc_pasid_tables(struct intel_iommu * iommu)39 int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu)
40 {
41 struct page *pages;
42 int order;
43
44 /* Start at 2 because it's defined as 2^(1+PSS) */
45 iommu->pasid_max = 2 << ecap_pss(iommu->ecap);
46
47 /* Eventually I'm promised we will get a multi-level PASID table
48 * and it won't have to be physically contiguous. Until then,
49 * limit the size because 8MiB contiguous allocations can be hard
50 * to come by. The limit of 0x20000, which is 1MiB for each of
51 * the PASID and PASID-state tables, is somewhat arbitrary. */
52 if (iommu->pasid_max > 0x20000)
53 iommu->pasid_max = 0x20000;
54
55 order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max);
56 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
57 if (!pages) {
58 pr_warn("IOMMU: %s: Failed to allocate PASID table\n",
59 iommu->name);
60 return -ENOMEM;
61 }
62 iommu->pasid_table = page_address(pages);
63 pr_info("%s: Allocated order %d PASID table.\n", iommu->name, order);
64
65 if (ecap_dis(iommu->ecap)) {
66 /* Just making it explicit... */
67 BUILD_BUG_ON(sizeof(struct pasid_entry) != sizeof(struct pasid_state_entry));
68 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
69 if (pages)
70 iommu->pasid_state_table = page_address(pages);
71 else
72 pr_warn("IOMMU: %s: Failed to allocate PASID state table\n",
73 iommu->name);
74 }
75
76 idr_init(&iommu->pasid_idr);
77
78 return 0;
79 }
80
intel_svm_free_pasid_tables(struct intel_iommu * iommu)81 int intel_svm_free_pasid_tables(struct intel_iommu *iommu)
82 {
83 int order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max);
84
85 if (iommu->pasid_table) {
86 free_pages((unsigned long)iommu->pasid_table, order);
87 iommu->pasid_table = NULL;
88 }
89 if (iommu->pasid_state_table) {
90 free_pages((unsigned long)iommu->pasid_state_table, order);
91 iommu->pasid_state_table = NULL;
92 }
93 idr_destroy(&iommu->pasid_idr);
94 return 0;
95 }
96
97 #define PRQ_ORDER 0
98
intel_svm_enable_prq(struct intel_iommu * iommu)99 int intel_svm_enable_prq(struct intel_iommu *iommu)
100 {
101 struct page *pages;
102 int irq, ret;
103
104 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER);
105 if (!pages) {
106 pr_warn("IOMMU: %s: Failed to allocate page request queue\n",
107 iommu->name);
108 return -ENOMEM;
109 }
110 iommu->prq = page_address(pages);
111
112 irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu);
113 if (irq <= 0) {
114 pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n",
115 iommu->name);
116 ret = -EINVAL;
117 err:
118 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
119 iommu->prq = NULL;
120 return ret;
121 }
122 iommu->pr_irq = irq;
123
124 snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
125
126 ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT,
127 iommu->prq_name, iommu);
128 if (ret) {
129 pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
130 iommu->name);
131 dmar_free_hwirq(irq);
132 iommu->pr_irq = 0;
133 goto err;
134 }
135 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
136 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
137 dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
138
139 return 0;
140 }
141
intel_svm_finish_prq(struct intel_iommu * iommu)142 int intel_svm_finish_prq(struct intel_iommu *iommu)
143 {
144 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
145 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
146 dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
147
148 if (iommu->pr_irq) {
149 free_irq(iommu->pr_irq, iommu);
150 dmar_free_hwirq(iommu->pr_irq);
151 iommu->pr_irq = 0;
152 }
153
154 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
155 iommu->prq = NULL;
156
157 return 0;
158 }
159
intel_flush_svm_range_dev(struct intel_svm * svm,struct intel_svm_dev * sdev,unsigned long address,unsigned long pages,int ih,int gl)160 static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
161 unsigned long address, unsigned long pages, int ih, int gl)
162 {
163 struct qi_desc desc;
164
165 if (pages == -1) {
166 /* For global kernel pages we have to flush them in *all* PASIDs
167 * because that's the only option the hardware gives us. Despite
168 * the fact that they are actually only accessible through one. */
169 if (gl)
170 desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
171 QI_EIOTLB_GRAN(QI_GRAN_ALL_ALL) | QI_EIOTLB_TYPE;
172 else
173 desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
174 QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE;
175 desc.high = 0;
176 } else {
177 int mask = ilog2(__roundup_pow_of_two(pages));
178
179 desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
180 QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | QI_EIOTLB_TYPE;
181 desc.high = QI_EIOTLB_ADDR(address) | QI_EIOTLB_GL(gl) |
182 QI_EIOTLB_IH(ih) | QI_EIOTLB_AM(mask);
183 }
184 qi_submit_sync(&desc, svm->iommu);
185
186 if (sdev->dev_iotlb) {
187 desc.low = QI_DEV_EIOTLB_PASID(svm->pasid) | QI_DEV_EIOTLB_SID(sdev->sid) |
188 QI_DEV_EIOTLB_QDEP(sdev->qdep) | QI_DEIOTLB_TYPE;
189 if (pages == -1) {
190 desc.high = QI_DEV_EIOTLB_ADDR(-1ULL >> 1) | QI_DEV_EIOTLB_SIZE;
191 } else if (pages > 1) {
192 /* The least significant zero bit indicates the size. So,
193 * for example, an "address" value of 0x12345f000 will
194 * flush from 0x123440000 to 0x12347ffff (256KiB). */
195 unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT);
196 unsigned long mask = __rounddown_pow_of_two(address ^ last);;
197
198 desc.high = QI_DEV_EIOTLB_ADDR((address & ~mask) | (mask - 1)) | QI_DEV_EIOTLB_SIZE;
199 } else {
200 desc.high = QI_DEV_EIOTLB_ADDR(address);
201 }
202 qi_submit_sync(&desc, svm->iommu);
203 }
204 }
205
intel_flush_svm_range(struct intel_svm * svm,unsigned long address,unsigned long pages,int ih,int gl)206 static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
207 unsigned long pages, int ih, int gl)
208 {
209 struct intel_svm_dev *sdev;
210
211 /* Try deferred invalidate if available */
212 if (svm->iommu->pasid_state_table &&
213 !cmpxchg64(&svm->iommu->pasid_state_table[svm->pasid].val, 0, 1ULL << 63))
214 return;
215
216 rcu_read_lock();
217 list_for_each_entry_rcu(sdev, &svm->devs, list)
218 intel_flush_svm_range_dev(svm, sdev, address, pages, ih, gl);
219 rcu_read_unlock();
220 }
221
intel_change_pte(struct mmu_notifier * mn,struct mm_struct * mm,unsigned long address,pte_t pte)222 static void intel_change_pte(struct mmu_notifier *mn, struct mm_struct *mm,
223 unsigned long address, pte_t pte)
224 {
225 struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
226
227 intel_flush_svm_range(svm, address, 1, 1, 0);
228 }
229
230 /* Pages have been freed at this point */
intel_invalidate_range(struct mmu_notifier * mn,struct mm_struct * mm,unsigned long start,unsigned long end)231 static void intel_invalidate_range(struct mmu_notifier *mn,
232 struct mm_struct *mm,
233 unsigned long start, unsigned long end)
234 {
235 struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
236
237 intel_flush_svm_range(svm, start,
238 (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0, 0);
239 }
240
241
intel_flush_pasid_dev(struct intel_svm * svm,struct intel_svm_dev * sdev,int pasid)242 static void intel_flush_pasid_dev(struct intel_svm *svm, struct intel_svm_dev *sdev, int pasid)
243 {
244 struct qi_desc desc;
245
246 desc.high = 0;
247 desc.low = QI_PC_TYPE | QI_PC_DID(sdev->did) | QI_PC_PASID_SEL | QI_PC_PASID(pasid);
248
249 qi_submit_sync(&desc, svm->iommu);
250 }
251
intel_mm_release(struct mmu_notifier * mn,struct mm_struct * mm)252 static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
253 {
254 struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
255 struct intel_svm_dev *sdev;
256
257 /* This might end up being called from exit_mmap(), *before* the page
258 * tables are cleared. And __mmu_notifier_release() will delete us from
259 * the list of notifiers so that our invalidate_range() callback doesn't
260 * get called when the page tables are cleared. So we need to protect
261 * against hardware accessing those page tables.
262 *
263 * We do it by clearing the entry in the PASID table and then flushing
264 * the IOTLB and the PASID table caches. This might upset hardware;
265 * perhaps we'll want to point the PASID to a dummy PGD (like the zero
266 * page) so that we end up taking a fault that the hardware really
267 * *has* to handle gracefully without affecting other processes.
268 */
269 svm->iommu->pasid_table[svm->pasid].val = 0;
270 wmb();
271
272 rcu_read_lock();
273 list_for_each_entry_rcu(sdev, &svm->devs, list) {
274 intel_flush_pasid_dev(svm, sdev, svm->pasid);
275 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
276 }
277 rcu_read_unlock();
278
279 }
280
281 static const struct mmu_notifier_ops intel_mmuops = {
282 .release = intel_mm_release,
283 .change_pte = intel_change_pte,
284 .invalidate_range = intel_invalidate_range,
285 };
286
287 static DEFINE_MUTEX(pasid_mutex);
288
intel_svm_bind_mm(struct device * dev,int * pasid,int flags,struct svm_dev_ops * ops)289 int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops)
290 {
291 struct intel_iommu *iommu = intel_svm_device_to_iommu(dev);
292 struct intel_svm_dev *sdev;
293 struct intel_svm *svm = NULL;
294 struct mm_struct *mm = NULL;
295 int pasid_max;
296 int ret;
297
298 if (WARN_ON(!iommu))
299 return -EINVAL;
300
301 if (dev_is_pci(dev)) {
302 pasid_max = pci_max_pasids(to_pci_dev(dev));
303 if (pasid_max < 0)
304 return -EINVAL;
305 } else
306 pasid_max = 1 << 20;
307
308 if ((flags & SVM_FLAG_SUPERVISOR_MODE)) {
309 if (!ecap_srs(iommu->ecap))
310 return -EINVAL;
311 } else if (pasid) {
312 mm = get_task_mm(current);
313 BUG_ON(!mm);
314 }
315
316 mutex_lock(&pasid_mutex);
317 if (pasid && !(flags & SVM_FLAG_PRIVATE_PASID)) {
318 int i;
319
320 idr_for_each_entry(&iommu->pasid_idr, svm, i) {
321 if (svm->mm != mm ||
322 (svm->flags & SVM_FLAG_PRIVATE_PASID))
323 continue;
324
325 if (svm->pasid >= pasid_max) {
326 dev_warn(dev,
327 "Limited PASID width. Cannot use existing PASID %d\n",
328 svm->pasid);
329 ret = -ENOSPC;
330 goto out;
331 }
332
333 list_for_each_entry(sdev, &svm->devs, list) {
334 if (dev == sdev->dev) {
335 if (sdev->ops != ops) {
336 ret = -EBUSY;
337 goto out;
338 }
339 sdev->users++;
340 goto success;
341 }
342 }
343
344 break;
345 }
346 }
347
348 sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
349 if (!sdev) {
350 ret = -ENOMEM;
351 goto out;
352 }
353 sdev->dev = dev;
354
355 ret = intel_iommu_enable_pasid(iommu, sdev);
356 if (ret || !pasid) {
357 /* If they don't actually want to assign a PASID, this is
358 * just an enabling check/preparation. */
359 kfree(sdev);
360 goto out;
361 }
362 /* Finish the setup now we know we're keeping it */
363 sdev->users = 1;
364 sdev->ops = ops;
365 init_rcu_head(&sdev->rcu);
366
367 if (!svm) {
368 svm = kzalloc(sizeof(*svm), GFP_KERNEL);
369 if (!svm) {
370 ret = -ENOMEM;
371 kfree(sdev);
372 goto out;
373 }
374 svm->iommu = iommu;
375
376 if (pasid_max > iommu->pasid_max)
377 pasid_max = iommu->pasid_max;
378
379 /* Do not use PASID 0 in caching mode (virtualised IOMMU) */
380 ret = idr_alloc(&iommu->pasid_idr, svm,
381 !!cap_caching_mode(iommu->cap),
382 pasid_max - 1, GFP_KERNEL);
383 if (ret < 0) {
384 kfree(svm);
385 kfree(sdev);
386 goto out;
387 }
388 svm->pasid = ret;
389 svm->notifier.ops = &intel_mmuops;
390 svm->mm = mm;
391 svm->flags = flags;
392 INIT_LIST_HEAD_RCU(&svm->devs);
393 ret = -ENOMEM;
394 if (mm) {
395 ret = mmu_notifier_register(&svm->notifier, mm);
396 if (ret) {
397 idr_remove(&svm->iommu->pasid_idr, svm->pasid);
398 kfree(svm);
399 kfree(sdev);
400 goto out;
401 }
402 iommu->pasid_table[svm->pasid].val = (u64)__pa(mm->pgd) | 1;
403 } else
404 iommu->pasid_table[svm->pasid].val = (u64)__pa(init_mm.pgd) | 1 | (1ULL << 11);
405 wmb();
406 /* In caching mode, we still have to flush with PASID 0 when
407 * a PASID table entry becomes present. Not entirely clear
408 * *why* that would be the case — surely we could just issue
409 * a flush with the PASID value that we've changed? The PASID
410 * is the index into the table, after all. It's not like domain
411 * IDs in the case of the equivalent context-entry change in
412 * caching mode. And for that matter it's not entirely clear why
413 * a VMM would be in the business of caching the PASID table
414 * anyway. Surely that can be left entirely to the guest? */
415 if (cap_caching_mode(iommu->cap))
416 intel_flush_pasid_dev(svm, sdev, 0);
417 }
418 list_add_rcu(&sdev->list, &svm->devs);
419
420 success:
421 *pasid = svm->pasid;
422 ret = 0;
423 out:
424 mutex_unlock(&pasid_mutex);
425 if (mm)
426 mmput(mm);
427 return ret;
428 }
429 EXPORT_SYMBOL_GPL(intel_svm_bind_mm);
430
intel_svm_unbind_mm(struct device * dev,int pasid)431 int intel_svm_unbind_mm(struct device *dev, int pasid)
432 {
433 struct intel_svm_dev *sdev;
434 struct intel_iommu *iommu;
435 struct intel_svm *svm;
436 int ret = -EINVAL;
437
438 mutex_lock(&pasid_mutex);
439 iommu = intel_svm_device_to_iommu(dev);
440 if (!iommu || !iommu->pasid_table)
441 goto out;
442
443 svm = idr_find(&iommu->pasid_idr, pasid);
444 if (!svm)
445 goto out;
446
447 list_for_each_entry(sdev, &svm->devs, list) {
448 if (dev == sdev->dev) {
449 ret = 0;
450 sdev->users--;
451 if (!sdev->users) {
452 list_del_rcu(&sdev->list);
453 /* Flush the PASID cache and IOTLB for this device.
454 * Note that we do depend on the hardware *not* using
455 * the PASID any more. Just as we depend on other
456 * devices never using PASIDs that they have no right
457 * to use. We have a *shared* PASID table, because it's
458 * large and has to be physically contiguous. So it's
459 * hard to be as defensive as we might like. */
460 intel_flush_pasid_dev(svm, sdev, svm->pasid);
461 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
462 kfree_rcu(sdev, rcu);
463
464 if (list_empty(&svm->devs)) {
465
466 idr_remove(&svm->iommu->pasid_idr, svm->pasid);
467 if (svm->mm)
468 mmu_notifier_unregister(&svm->notifier, svm->mm);
469
470 /* We mandate that no page faults may be outstanding
471 * for the PASID when intel_svm_unbind_mm() is called.
472 * If that is not obeyed, subtle errors will happen.
473 * Let's make them less subtle... */
474 memset(svm, 0x6b, sizeof(*svm));
475 kfree(svm);
476 }
477 }
478 break;
479 }
480 }
481 out:
482 mutex_unlock(&pasid_mutex);
483
484 return ret;
485 }
486 EXPORT_SYMBOL_GPL(intel_svm_unbind_mm);
487
intel_svm_is_pasid_valid(struct device * dev,int pasid)488 int intel_svm_is_pasid_valid(struct device *dev, int pasid)
489 {
490 struct intel_iommu *iommu;
491 struct intel_svm *svm;
492 int ret = -EINVAL;
493
494 mutex_lock(&pasid_mutex);
495 iommu = intel_svm_device_to_iommu(dev);
496 if (!iommu || !iommu->pasid_table)
497 goto out;
498
499 svm = idr_find(&iommu->pasid_idr, pasid);
500 if (!svm)
501 goto out;
502
503 /* init_mm is used in this case */
504 if (!svm->mm)
505 ret = 1;
506 else if (atomic_read(&svm->mm->mm_users) > 0)
507 ret = 1;
508 else
509 ret = 0;
510
511 out:
512 mutex_unlock(&pasid_mutex);
513
514 return ret;
515 }
516 EXPORT_SYMBOL_GPL(intel_svm_is_pasid_valid);
517
518 /* Page request queue descriptor */
519 struct page_req_dsc {
520 u64 srr:1;
521 u64 bof:1;
522 u64 pasid_present:1;
523 u64 lpig:1;
524 u64 pasid:20;
525 u64 bus:8;
526 u64 private:23;
527 u64 prg_index:9;
528 u64 rd_req:1;
529 u64 wr_req:1;
530 u64 exe_req:1;
531 u64 priv_req:1;
532 u64 devfn:8;
533 u64 addr:52;
534 };
535
536 #define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x10)
537
access_error(struct vm_area_struct * vma,struct page_req_dsc * req)538 static bool access_error(struct vm_area_struct *vma, struct page_req_dsc *req)
539 {
540 unsigned long requested = 0;
541
542 if (req->exe_req)
543 requested |= VM_EXEC;
544
545 if (req->rd_req)
546 requested |= VM_READ;
547
548 if (req->wr_req)
549 requested |= VM_WRITE;
550
551 return (requested & ~vma->vm_flags) != 0;
552 }
553
is_canonical_address(u64 addr)554 static bool is_canonical_address(u64 addr)
555 {
556 int shift = 64 - (__VIRTUAL_MASK_SHIFT + 1);
557 long saddr = (long) addr;
558
559 return (((saddr << shift) >> shift) == saddr);
560 }
561
prq_event_thread(int irq,void * d)562 static irqreturn_t prq_event_thread(int irq, void *d)
563 {
564 struct intel_iommu *iommu = d;
565 struct intel_svm *svm = NULL;
566 int head, tail, handled = 0;
567
568 /* Clear PPR bit before reading head/tail registers, to
569 * ensure that we get a new interrupt if needed. */
570 writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
571
572 tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
573 head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
574 while (head != tail) {
575 struct intel_svm_dev *sdev;
576 struct vm_area_struct *vma;
577 struct page_req_dsc *req;
578 struct qi_desc resp;
579 int ret, result;
580 u64 address;
581
582 handled = 1;
583
584 req = &iommu->prq[head / sizeof(*req)];
585
586 result = QI_RESP_FAILURE;
587 address = (u64)req->addr << VTD_PAGE_SHIFT;
588 if (!req->pasid_present) {
589 pr_err("%s: Page request without PASID: %08llx %08llx\n",
590 iommu->name, ((unsigned long long *)req)[0],
591 ((unsigned long long *)req)[1]);
592 goto no_pasid;
593 }
594
595 if (!svm || svm->pasid != req->pasid) {
596 rcu_read_lock();
597 svm = idr_find(&iommu->pasid_idr, req->pasid);
598 /* It *can't* go away, because the driver is not permitted
599 * to unbind the mm while any page faults are outstanding.
600 * So we only need RCU to protect the internal idr code. */
601 rcu_read_unlock();
602
603 if (!svm) {
604 pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n",
605 iommu->name, req->pasid, ((unsigned long long *)req)[0],
606 ((unsigned long long *)req)[1]);
607 goto no_pasid;
608 }
609 }
610
611 result = QI_RESP_INVALID;
612 /* Since we're using init_mm.pgd directly, we should never take
613 * any faults on kernel addresses. */
614 if (!svm->mm)
615 goto bad_req;
616 /* If the mm is already defunct, don't handle faults. */
617 if (!mmget_not_zero(svm->mm))
618 goto bad_req;
619
620 /* If address is not canonical, return invalid response */
621 if (!is_canonical_address(address))
622 goto bad_req;
623
624 down_read(&svm->mm->mmap_sem);
625 vma = find_extend_vma(svm->mm, address);
626 if (!vma || address < vma->vm_start)
627 goto invalid;
628
629 if (access_error(vma, req))
630 goto invalid;
631
632 ret = handle_mm_fault(vma, address,
633 req->wr_req ? FAULT_FLAG_WRITE : 0);
634 if (ret & VM_FAULT_ERROR)
635 goto invalid;
636
637 result = QI_RESP_SUCCESS;
638 invalid:
639 up_read(&svm->mm->mmap_sem);
640 mmput(svm->mm);
641 bad_req:
642 /* Accounting for major/minor faults? */
643 rcu_read_lock();
644 list_for_each_entry_rcu(sdev, &svm->devs, list) {
645 if (sdev->sid == PCI_DEVID(req->bus, req->devfn))
646 break;
647 }
648 /* Other devices can go away, but the drivers are not permitted
649 * to unbind while any page faults might be in flight. So it's
650 * OK to drop the 'lock' here now we have it. */
651 rcu_read_unlock();
652
653 if (WARN_ON(&sdev->list == &svm->devs))
654 sdev = NULL;
655
656 if (sdev && sdev->ops && sdev->ops->fault_cb) {
657 int rwxp = (req->rd_req << 3) | (req->wr_req << 2) |
658 (req->exe_req << 1) | (req->priv_req);
659 sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr, req->private, rwxp, result);
660 }
661 /* We get here in the error case where the PASID lookup failed,
662 and these can be NULL. Do not use them below this point! */
663 sdev = NULL;
664 svm = NULL;
665 no_pasid:
666 if (req->lpig) {
667 /* Page Group Response */
668 resp.low = QI_PGRP_PASID(req->pasid) |
669 QI_PGRP_DID((req->bus << 8) | req->devfn) |
670 QI_PGRP_PASID_P(req->pasid_present) |
671 QI_PGRP_RESP_TYPE;
672 resp.high = QI_PGRP_IDX(req->prg_index) |
673 QI_PGRP_PRIV(req->private) | QI_PGRP_RESP_CODE(result);
674
675 qi_submit_sync(&resp, iommu);
676 } else if (req->srr) {
677 /* Page Stream Response */
678 resp.low = QI_PSTRM_IDX(req->prg_index) |
679 QI_PSTRM_PRIV(req->private) | QI_PSTRM_BUS(req->bus) |
680 QI_PSTRM_PASID(req->pasid) | QI_PSTRM_RESP_TYPE;
681 resp.high = QI_PSTRM_ADDR(address) | QI_PSTRM_DEVFN(req->devfn) |
682 QI_PSTRM_RESP_CODE(result);
683
684 qi_submit_sync(&resp, iommu);
685 }
686
687 head = (head + sizeof(*req)) & PRQ_RING_MASK;
688 }
689
690 dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
691
692 return IRQ_RETVAL(handled);
693 }
694