1 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 * You should have received a copy of the GNU General Public License 13 * along with this program; if not, write to the Free Software 14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 15 * 02110-1301, USA. 16 */ 17 18 #ifndef MSM_IOMMU_H 19 #define MSM_IOMMU_H 20 21 #include <linux/interrupt.h> 22 #include <linux/iommu.h> 23 #include <linux/clk.h> 24 25 /* Sharability attributes of MSM IOMMU mappings */ 26 #define MSM_IOMMU_ATTR_NON_SH 0x0 27 #define MSM_IOMMU_ATTR_SH 0x4 28 29 /* Cacheability attributes of MSM IOMMU mappings */ 30 #define MSM_IOMMU_ATTR_NONCACHED 0x0 31 #define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1 32 #define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2 33 #define MSM_IOMMU_ATTR_CACHED_WT 0x3 34 35 /* Mask for the cache policy attribute */ 36 #define MSM_IOMMU_CP_MASK 0x03 37 38 /* Maximum number of Machine IDs that we are allowing to be mapped to the same 39 * context bank. The number of MIDs mapped to the same CB does not affect 40 * performance, but there is a practical limit on how many distinct MIDs may 41 * be present. These mappings are typically determined at design time and are 42 * not expected to change at run time. 43 */ 44 #define MAX_NUM_MIDS 32 45 46 /* Maximum number of context banks that can be present in IOMMU */ 47 #define IOMMU_MAX_CBS 128 48 49 /** 50 * struct msm_iommu_dev - a single IOMMU hardware instance 51 * ncb Number of context banks present on this IOMMU HW instance 52 * dev: IOMMU device 53 * irq: Interrupt number 54 * clk: The bus clock for this IOMMU hardware instance 55 * pclk: The clock for the IOMMU bus interconnect 56 * dev_node: list head in qcom_iommu_device_list 57 * dom_node: list head for domain 58 * ctx_list: list of 'struct msm_iommu_ctx_dev' 59 * context_map: Bitmap to track allocated context banks 60 */ 61 struct msm_iommu_dev { 62 void __iomem *base; 63 int ncb; 64 struct device *dev; 65 int irq; 66 struct clk *clk; 67 struct clk *pclk; 68 struct list_head dev_node; 69 struct list_head dom_node; 70 struct list_head ctx_list; 71 DECLARE_BITMAP(context_map, IOMMU_MAX_CBS); 72 73 struct iommu_device iommu; 74 }; 75 76 /** 77 * struct msm_iommu_ctx_dev - an IOMMU context bank instance 78 * of_node node ptr of client device 79 * num Index of this context bank within the hardware 80 * mids List of Machine IDs that are to be mapped into this context 81 * bank, terminated by -1. The MID is a set of signals on the 82 * AXI bus that identifies the function associated with a specific 83 * memory request. (See ARM spec). 84 * num_mids Total number of mids 85 * node list head in ctx_list 86 */ 87 struct msm_iommu_ctx_dev { 88 struct device_node *of_node; 89 int num; 90 int mids[MAX_NUM_MIDS]; 91 int num_mids; 92 struct list_head list; 93 }; 94 95 /* 96 * Interrupt handler for the IOMMU context fault interrupt. Hooking the 97 * interrupt is not supported in the API yet, but this will print an error 98 * message and dump useful IOMMU registers. 99 */ 100 irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id); 101 102 #endif 103