1 /*
2 * Support for LGDT3306A - 8VSB/QAM-B
3 *
4 * Copyright (C) 2013 Fred Richter <frichter@hauppauge.com>
5 * - driver structure based on lgdt3305.[ch] by Michael Krufky
6 * - code based on LG3306_V0.35 API by LG Electronics Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
21 #include <asm/div64.h>
22 #include <linux/dvb/frontend.h>
23 #include "dvb_math.h"
24 #include "lgdt3306a.h"
25 #include <linux/i2c-mux.h>
26
27
28 static int debug;
29 module_param(debug, int, 0644);
30 MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
31
32 #define DBG_INFO 1
33 #define DBG_REG 2
34 #define DBG_DUMP 4 /* FGR - comment out to remove dump code */
35
36 #define lg_debug(fmt, arg...) \
37 printk(KERN_DEBUG pr_fmt(fmt), ## arg)
38
39 #define dbg_info(fmt, arg...) \
40 do { \
41 if (debug & DBG_INFO) \
42 lg_debug(fmt, ## arg); \
43 } while (0)
44
45 #define dbg_reg(fmt, arg...) \
46 do { \
47 if (debug & DBG_REG) \
48 lg_debug(fmt, ## arg); \
49 } while (0)
50
51 #define lg_chkerr(ret) \
52 ({ \
53 int __ret; \
54 __ret = (ret < 0); \
55 if (__ret) \
56 pr_err("error %d on line %d\n", ret, __LINE__); \
57 __ret; \
58 })
59
60 struct lgdt3306a_state {
61 struct i2c_adapter *i2c_adap;
62 const struct lgdt3306a_config *cfg;
63
64 struct dvb_frontend frontend;
65
66 enum fe_modulation current_modulation;
67 u32 current_frequency;
68 u32 snr;
69
70 struct i2c_mux_core *muxc;
71 };
72
73 /*
74 * LG3306A Register Usage
75 * (LG does not really name the registers, so this code does not either)
76 *
77 * 0000 -> 00FF Common control and status
78 * 1000 -> 10FF Synchronizer control and status
79 * 1F00 -> 1FFF Smart Antenna control and status
80 * 2100 -> 21FF VSB Equalizer control and status
81 * 2800 -> 28FF QAM Equalizer control and status
82 * 3000 -> 30FF FEC control and status
83 */
84
85 enum lgdt3306a_lock_status {
86 LG3306_UNLOCK = 0x00,
87 LG3306_LOCK = 0x01,
88 LG3306_UNKNOWN_LOCK = 0xff
89 };
90
91 enum lgdt3306a_neverlock_status {
92 LG3306_NL_INIT = 0x00,
93 LG3306_NL_PROCESS = 0x01,
94 LG3306_NL_LOCK = 0x02,
95 LG3306_NL_FAIL = 0x03,
96 LG3306_NL_UNKNOWN = 0xff
97 };
98
99 enum lgdt3306a_modulation {
100 LG3306_VSB = 0x00,
101 LG3306_QAM64 = 0x01,
102 LG3306_QAM256 = 0x02,
103 LG3306_UNKNOWN_MODE = 0xff
104 };
105
106 enum lgdt3306a_lock_check {
107 LG3306_SYNC_LOCK,
108 LG3306_FEC_LOCK,
109 LG3306_TR_LOCK,
110 LG3306_AGC_LOCK,
111 };
112
113
114 #ifdef DBG_DUMP
115 static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state);
116 static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state);
117 #endif
118
119
lgdt3306a_write_reg(struct lgdt3306a_state * state,u16 reg,u8 val)120 static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val)
121 {
122 int ret;
123 u8 buf[] = { reg >> 8, reg & 0xff, val };
124 struct i2c_msg msg = {
125 .addr = state->cfg->i2c_addr, .flags = 0,
126 .buf = buf, .len = 3,
127 };
128
129 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
130
131 ret = i2c_transfer(state->i2c_adap, &msg, 1);
132
133 if (ret != 1) {
134 pr_err("error (addr %02x %02x <- %02x, err = %i)\n",
135 msg.buf[0], msg.buf[1], msg.buf[2], ret);
136 if (ret < 0)
137 return ret;
138 else
139 return -EREMOTEIO;
140 }
141 return 0;
142 }
143
lgdt3306a_read_reg(struct lgdt3306a_state * state,u16 reg,u8 * val)144 static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val)
145 {
146 int ret;
147 u8 reg_buf[] = { reg >> 8, reg & 0xff };
148 struct i2c_msg msg[] = {
149 { .addr = state->cfg->i2c_addr,
150 .flags = 0, .buf = reg_buf, .len = 2 },
151 { .addr = state->cfg->i2c_addr,
152 .flags = I2C_M_RD, .buf = val, .len = 1 },
153 };
154
155 ret = i2c_transfer(state->i2c_adap, msg, 2);
156
157 if (ret != 2) {
158 pr_err("error (addr %02x reg %04x error (ret == %i)\n",
159 state->cfg->i2c_addr, reg, ret);
160 if (ret < 0)
161 return ret;
162 else
163 return -EREMOTEIO;
164 }
165 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val);
166
167 return 0;
168 }
169
170 #define read_reg(state, reg) \
171 ({ \
172 u8 __val; \
173 int ret = lgdt3306a_read_reg(state, reg, &__val); \
174 if (lg_chkerr(ret)) \
175 __val = 0; \
176 __val; \
177 })
178
lgdt3306a_set_reg_bit(struct lgdt3306a_state * state,u16 reg,int bit,int onoff)179 static int lgdt3306a_set_reg_bit(struct lgdt3306a_state *state,
180 u16 reg, int bit, int onoff)
181 {
182 u8 val;
183 int ret;
184
185 dbg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
186
187 ret = lgdt3306a_read_reg(state, reg, &val);
188 if (lg_chkerr(ret))
189 goto fail;
190
191 val &= ~(1 << bit);
192 val |= (onoff & 1) << bit;
193
194 ret = lgdt3306a_write_reg(state, reg, val);
195 lg_chkerr(ret);
196 fail:
197 return ret;
198 }
199
200 /* ------------------------------------------------------------------------ */
201
lgdt3306a_soft_reset(struct lgdt3306a_state * state)202 static int lgdt3306a_soft_reset(struct lgdt3306a_state *state)
203 {
204 int ret;
205
206 dbg_info("\n");
207
208 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
209 if (lg_chkerr(ret))
210 goto fail;
211
212 msleep(20);
213 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
214 lg_chkerr(ret);
215
216 fail:
217 return ret;
218 }
219
lgdt3306a_mpeg_mode(struct lgdt3306a_state * state,enum lgdt3306a_mpeg_mode mode)220 static int lgdt3306a_mpeg_mode(struct lgdt3306a_state *state,
221 enum lgdt3306a_mpeg_mode mode)
222 {
223 u8 val;
224 int ret;
225
226 dbg_info("(%d)\n", mode);
227 /* transport packet format - TPSENB=0x80 */
228 ret = lgdt3306a_set_reg_bit(state, 0x0071, 7,
229 mode == LGDT3306A_MPEG_PARALLEL ? 1 : 0);
230 if (lg_chkerr(ret))
231 goto fail;
232
233 /*
234 * start of packet signal duration
235 * TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration
236 */
237 ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0);
238 if (lg_chkerr(ret))
239 goto fail;
240
241 ret = lgdt3306a_read_reg(state, 0x0070, &val);
242 if (lg_chkerr(ret))
243 goto fail;
244
245 val |= 0x10; /* TPCLKSUPB=0x10 */
246
247 if (mode == LGDT3306A_MPEG_PARALLEL)
248 val &= ~0x10;
249
250 ret = lgdt3306a_write_reg(state, 0x0070, val);
251 lg_chkerr(ret);
252
253 fail:
254 return ret;
255 }
256
lgdt3306a_mpeg_mode_polarity(struct lgdt3306a_state * state,enum lgdt3306a_tp_clock_edge edge,enum lgdt3306a_tp_valid_polarity valid)257 static int lgdt3306a_mpeg_mode_polarity(struct lgdt3306a_state *state,
258 enum lgdt3306a_tp_clock_edge edge,
259 enum lgdt3306a_tp_valid_polarity valid)
260 {
261 u8 val;
262 int ret;
263
264 dbg_info("edge=%d, valid=%d\n", edge, valid);
265
266 ret = lgdt3306a_read_reg(state, 0x0070, &val);
267 if (lg_chkerr(ret))
268 goto fail;
269
270 val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */
271
272 if (edge == LGDT3306A_TPCLK_RISING_EDGE)
273 val |= 0x04;
274 if (valid == LGDT3306A_TP_VALID_HIGH)
275 val |= 0x02;
276
277 ret = lgdt3306a_write_reg(state, 0x0070, val);
278 lg_chkerr(ret);
279
280 fail:
281 return ret;
282 }
283
lgdt3306a_mpeg_tristate(struct lgdt3306a_state * state,int mode)284 static int lgdt3306a_mpeg_tristate(struct lgdt3306a_state *state,
285 int mode)
286 {
287 u8 val;
288 int ret;
289
290 dbg_info("(%d)\n", mode);
291
292 if (mode) {
293 ret = lgdt3306a_read_reg(state, 0x0070, &val);
294 if (lg_chkerr(ret))
295 goto fail;
296 /*
297 * Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20,
298 * TPDATAOUTEN=0x08
299 */
300 val &= ~0xa8;
301 ret = lgdt3306a_write_reg(state, 0x0070, val);
302 if (lg_chkerr(ret))
303 goto fail;
304
305 /* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */
306 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1);
307 if (lg_chkerr(ret))
308 goto fail;
309
310 } else {
311 /* enable IFAGC pin */
312 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0);
313 if (lg_chkerr(ret))
314 goto fail;
315
316 ret = lgdt3306a_read_reg(state, 0x0070, &val);
317 if (lg_chkerr(ret))
318 goto fail;
319
320 val |= 0xa8; /* enable bus */
321 ret = lgdt3306a_write_reg(state, 0x0070, val);
322 if (lg_chkerr(ret))
323 goto fail;
324 }
325
326 fail:
327 return ret;
328 }
329
lgdt3306a_ts_bus_ctrl(struct dvb_frontend * fe,int acquire)330 static int lgdt3306a_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
331 {
332 struct lgdt3306a_state *state = fe->demodulator_priv;
333
334 dbg_info("acquire=%d\n", acquire);
335
336 return lgdt3306a_mpeg_tristate(state, acquire ? 0 : 1);
337
338 }
339
lgdt3306a_power(struct lgdt3306a_state * state,int mode)340 static int lgdt3306a_power(struct lgdt3306a_state *state,
341 int mode)
342 {
343 int ret;
344
345 dbg_info("(%d)\n", mode);
346
347 if (mode == 0) {
348 /* into reset */
349 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
350 if (lg_chkerr(ret))
351 goto fail;
352
353 /* power down */
354 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0);
355 if (lg_chkerr(ret))
356 goto fail;
357
358 } else {
359 /* out of reset */
360 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
361 if (lg_chkerr(ret))
362 goto fail;
363
364 /* power up */
365 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1);
366 if (lg_chkerr(ret))
367 goto fail;
368 }
369
370 #ifdef DBG_DUMP
371 lgdt3306a_DumpAllRegs(state);
372 #endif
373 fail:
374 return ret;
375 }
376
377
lgdt3306a_set_vsb(struct lgdt3306a_state * state)378 static int lgdt3306a_set_vsb(struct lgdt3306a_state *state)
379 {
380 u8 val;
381 int ret;
382
383 dbg_info("\n");
384
385 /* 0. Spectrum inversion detection manual; spectrum inverted */
386 ret = lgdt3306a_read_reg(state, 0x0002, &val);
387 val &= 0xf7; /* SPECINVAUTO Off */
388 val |= 0x04; /* SPECINV On */
389 ret = lgdt3306a_write_reg(state, 0x0002, val);
390 if (lg_chkerr(ret))
391 goto fail;
392
393 /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
394 ret = lgdt3306a_write_reg(state, 0x0008, 0x80);
395 if (lg_chkerr(ret))
396 goto fail;
397
398 /* 2. Bandwidth mode for VSB(6MHz) */
399 ret = lgdt3306a_read_reg(state, 0x0009, &val);
400 val &= 0xe3;
401 val |= 0x0c; /* STDOPDETTMODE[2:0]=3 */
402 ret = lgdt3306a_write_reg(state, 0x0009, val);
403 if (lg_chkerr(ret))
404 goto fail;
405
406 /* 3. QAM mode detection mode(None) */
407 ret = lgdt3306a_read_reg(state, 0x0009, &val);
408 val &= 0xfc; /* STDOPDETCMODE[1:0]=0 */
409 ret = lgdt3306a_write_reg(state, 0x0009, val);
410 if (lg_chkerr(ret))
411 goto fail;
412
413 /* 4. ADC sampling frequency rate(2x sampling) */
414 ret = lgdt3306a_read_reg(state, 0x000d, &val);
415 val &= 0xbf; /* SAMPLING4XFEN=0 */
416 ret = lgdt3306a_write_reg(state, 0x000d, val);
417 if (lg_chkerr(ret))
418 goto fail;
419
420 #if 0
421 /* FGR - disable any AICC filtering, testing only */
422
423 ret = lgdt3306a_write_reg(state, 0x0024, 0x00);
424 if (lg_chkerr(ret))
425 goto fail;
426
427 /* AICCFIXFREQ0 NT N-1(Video rejection) */
428 ret = lgdt3306a_write_reg(state, 0x002e, 0x00);
429 ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
430 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
431
432 /* AICCFIXFREQ1 NT N-1(Audio rejection) */
433 ret = lgdt3306a_write_reg(state, 0x002b, 0x00);
434 ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
435 ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
436
437 /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
438 ret = lgdt3306a_write_reg(state, 0x0028, 0x00);
439 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
440 ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
441
442 /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
443 ret = lgdt3306a_write_reg(state, 0x0025, 0x00);
444 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
445 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
446
447 #else
448 /* FGR - this works well for HVR-1955,1975 */
449
450 /* 5. AICCOPMODE NT N-1 Adj. */
451 ret = lgdt3306a_write_reg(state, 0x0024, 0x5A);
452 if (lg_chkerr(ret))
453 goto fail;
454
455 /* AICCFIXFREQ0 NT N-1(Video rejection) */
456 ret = lgdt3306a_write_reg(state, 0x002e, 0x5A);
457 ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
458 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
459
460 /* AICCFIXFREQ1 NT N-1(Audio rejection) */
461 ret = lgdt3306a_write_reg(state, 0x002b, 0x36);
462 ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
463 ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
464
465 /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
466 ret = lgdt3306a_write_reg(state, 0x0028, 0x2A);
467 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
468 ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
469
470 /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
471 ret = lgdt3306a_write_reg(state, 0x0025, 0x06);
472 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
473 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
474 #endif
475
476 ret = lgdt3306a_read_reg(state, 0x001e, &val);
477 val &= 0x0f;
478 val |= 0xa0;
479 ret = lgdt3306a_write_reg(state, 0x001e, val);
480
481 ret = lgdt3306a_write_reg(state, 0x0022, 0x08);
482
483 ret = lgdt3306a_write_reg(state, 0x0023, 0xFF);
484
485 ret = lgdt3306a_read_reg(state, 0x211f, &val);
486 val &= 0xef;
487 ret = lgdt3306a_write_reg(state, 0x211f, val);
488
489 ret = lgdt3306a_write_reg(state, 0x2173, 0x01);
490
491 ret = lgdt3306a_read_reg(state, 0x1061, &val);
492 val &= 0xf8;
493 val |= 0x04;
494 ret = lgdt3306a_write_reg(state, 0x1061, val);
495
496 ret = lgdt3306a_read_reg(state, 0x103d, &val);
497 val &= 0xcf;
498 ret = lgdt3306a_write_reg(state, 0x103d, val);
499
500 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
501
502 ret = lgdt3306a_read_reg(state, 0x2141, &val);
503 val &= 0x3f;
504 ret = lgdt3306a_write_reg(state, 0x2141, val);
505
506 ret = lgdt3306a_read_reg(state, 0x2135, &val);
507 val &= 0x0f;
508 val |= 0x70;
509 ret = lgdt3306a_write_reg(state, 0x2135, val);
510
511 ret = lgdt3306a_read_reg(state, 0x0003, &val);
512 val &= 0xf7;
513 ret = lgdt3306a_write_reg(state, 0x0003, val);
514
515 ret = lgdt3306a_read_reg(state, 0x001c, &val);
516 val &= 0x7f;
517 ret = lgdt3306a_write_reg(state, 0x001c, val);
518
519 /* 6. EQ step size */
520 ret = lgdt3306a_read_reg(state, 0x2179, &val);
521 val &= 0xf8;
522 ret = lgdt3306a_write_reg(state, 0x2179, val);
523
524 ret = lgdt3306a_read_reg(state, 0x217a, &val);
525 val &= 0xf8;
526 ret = lgdt3306a_write_reg(state, 0x217a, val);
527
528 /* 7. Reset */
529 ret = lgdt3306a_soft_reset(state);
530 if (lg_chkerr(ret))
531 goto fail;
532
533 dbg_info("complete\n");
534 fail:
535 return ret;
536 }
537
lgdt3306a_set_qam(struct lgdt3306a_state * state,int modulation)538 static int lgdt3306a_set_qam(struct lgdt3306a_state *state, int modulation)
539 {
540 u8 val;
541 int ret;
542
543 dbg_info("modulation=%d\n", modulation);
544
545 /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
546 ret = lgdt3306a_write_reg(state, 0x0008, 0x08);
547 if (lg_chkerr(ret))
548 goto fail;
549
550 /* 1a. Spectrum inversion detection to Auto */
551 ret = lgdt3306a_read_reg(state, 0x0002, &val);
552 val &= 0xfb; /* SPECINV Off */
553 val |= 0x08; /* SPECINVAUTO On */
554 ret = lgdt3306a_write_reg(state, 0x0002, val);
555 if (lg_chkerr(ret))
556 goto fail;
557
558 /* 2. Bandwidth mode for QAM */
559 ret = lgdt3306a_read_reg(state, 0x0009, &val);
560 val &= 0xe3; /* STDOPDETTMODE[2:0]=0 VSB Off */
561 ret = lgdt3306a_write_reg(state, 0x0009, val);
562 if (lg_chkerr(ret))
563 goto fail;
564
565 /* 3. : 64QAM/256QAM detection(manual, auto) */
566 ret = lgdt3306a_read_reg(state, 0x0009, &val);
567 val &= 0xfc;
568 val |= 0x02; /* STDOPDETCMODE[1:0]=1=Manual 2=Auto */
569 ret = lgdt3306a_write_reg(state, 0x0009, val);
570 if (lg_chkerr(ret))
571 goto fail;
572
573 /* 3a. : 64QAM/256QAM selection for manual */
574 ret = lgdt3306a_read_reg(state, 0x101a, &val);
575 val &= 0xf8;
576 if (modulation == QAM_64)
577 val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */
578 else
579 val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */
580
581 ret = lgdt3306a_write_reg(state, 0x101a, val);
582 if (lg_chkerr(ret))
583 goto fail;
584
585 /* 4. ADC sampling frequency rate(4x sampling) */
586 ret = lgdt3306a_read_reg(state, 0x000d, &val);
587 val &= 0xbf;
588 val |= 0x40; /* SAMPLING4XFEN=1 */
589 ret = lgdt3306a_write_reg(state, 0x000d, val);
590 if (lg_chkerr(ret))
591 goto fail;
592
593 /* 5. No AICC operation in QAM mode */
594 ret = lgdt3306a_read_reg(state, 0x0024, &val);
595 val &= 0x00;
596 ret = lgdt3306a_write_reg(state, 0x0024, val);
597 if (lg_chkerr(ret))
598 goto fail;
599
600 /* 6. Reset */
601 ret = lgdt3306a_soft_reset(state);
602 if (lg_chkerr(ret))
603 goto fail;
604
605 dbg_info("complete\n");
606 fail:
607 return ret;
608 }
609
lgdt3306a_set_modulation(struct lgdt3306a_state * state,struct dtv_frontend_properties * p)610 static int lgdt3306a_set_modulation(struct lgdt3306a_state *state,
611 struct dtv_frontend_properties *p)
612 {
613 int ret;
614
615 dbg_info("\n");
616
617 switch (p->modulation) {
618 case VSB_8:
619 ret = lgdt3306a_set_vsb(state);
620 break;
621 case QAM_64:
622 ret = lgdt3306a_set_qam(state, QAM_64);
623 break;
624 case QAM_256:
625 ret = lgdt3306a_set_qam(state, QAM_256);
626 break;
627 default:
628 return -EINVAL;
629 }
630 if (lg_chkerr(ret))
631 goto fail;
632
633 state->current_modulation = p->modulation;
634
635 fail:
636 return ret;
637 }
638
639 /* ------------------------------------------------------------------------ */
640
lgdt3306a_agc_setup(struct lgdt3306a_state * state,struct dtv_frontend_properties * p)641 static int lgdt3306a_agc_setup(struct lgdt3306a_state *state,
642 struct dtv_frontend_properties *p)
643 {
644 /* TODO: anything we want to do here??? */
645 dbg_info("\n");
646
647 switch (p->modulation) {
648 case VSB_8:
649 break;
650 case QAM_64:
651 case QAM_256:
652 break;
653 default:
654 return -EINVAL;
655 }
656 return 0;
657 }
658
659 /* ------------------------------------------------------------------------ */
660
lgdt3306a_set_inversion(struct lgdt3306a_state * state,int inversion)661 static int lgdt3306a_set_inversion(struct lgdt3306a_state *state,
662 int inversion)
663 {
664 int ret;
665
666 dbg_info("(%d)\n", inversion);
667
668 ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0);
669 return ret;
670 }
671
lgdt3306a_set_inversion_auto(struct lgdt3306a_state * state,int enabled)672 static int lgdt3306a_set_inversion_auto(struct lgdt3306a_state *state,
673 int enabled)
674 {
675 int ret;
676
677 dbg_info("(%d)\n", enabled);
678
679 /* 0=Manual 1=Auto(QAM only) - SPECINVAUTO=0x04 */
680 ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);
681 return ret;
682 }
683
lgdt3306a_spectral_inversion(struct lgdt3306a_state * state,struct dtv_frontend_properties * p,int inversion)684 static int lgdt3306a_spectral_inversion(struct lgdt3306a_state *state,
685 struct dtv_frontend_properties *p,
686 int inversion)
687 {
688 int ret = 0;
689
690 dbg_info("(%d)\n", inversion);
691 #if 0
692 /*
693 * FGR - spectral_inversion defaults already set for VSB and QAM;
694 * can enable later if desired
695 */
696
697 ret = lgdt3306a_set_inversion(state, inversion);
698
699 switch (p->modulation) {
700 case VSB_8:
701 /* Manual only for VSB */
702 ret = lgdt3306a_set_inversion_auto(state, 0);
703 break;
704 case QAM_64:
705 case QAM_256:
706 /* Auto ok for QAM */
707 ret = lgdt3306a_set_inversion_auto(state, 1);
708 break;
709 default:
710 ret = -EINVAL;
711 }
712 #endif
713 return ret;
714 }
715
lgdt3306a_set_if(struct lgdt3306a_state * state,struct dtv_frontend_properties * p)716 static int lgdt3306a_set_if(struct lgdt3306a_state *state,
717 struct dtv_frontend_properties *p)
718 {
719 int ret;
720 u16 if_freq_khz;
721 u8 nco1, nco2;
722
723 switch (p->modulation) {
724 case VSB_8:
725 if_freq_khz = state->cfg->vsb_if_khz;
726 break;
727 case QAM_64:
728 case QAM_256:
729 if_freq_khz = state->cfg->qam_if_khz;
730 break;
731 default:
732 return -EINVAL;
733 }
734
735 switch (if_freq_khz) {
736 default:
737 pr_warn("IF=%d KHz is not supported, 3250 assumed\n",
738 if_freq_khz);
739 /* fallthrough */
740 case 3250: /* 3.25Mhz */
741 nco1 = 0x34;
742 nco2 = 0x00;
743 break;
744 case 3500: /* 3.50Mhz */
745 nco1 = 0x38;
746 nco2 = 0x00;
747 break;
748 case 4000: /* 4.00Mhz */
749 nco1 = 0x40;
750 nco2 = 0x00;
751 break;
752 case 5000: /* 5.00Mhz */
753 nco1 = 0x50;
754 nco2 = 0x00;
755 break;
756 case 5380: /* 5.38Mhz */
757 nco1 = 0x56;
758 nco2 = 0x14;
759 break;
760 }
761 ret = lgdt3306a_write_reg(state, 0x0010, nco1);
762 if (ret)
763 return ret;
764 ret = lgdt3306a_write_reg(state, 0x0011, nco2);
765 if (ret)
766 return ret;
767
768 dbg_info("if_freq=%d KHz->[%04x]\n", if_freq_khz, nco1<<8 | nco2);
769
770 return 0;
771 }
772
773 /* ------------------------------------------------------------------------ */
774
lgdt3306a_i2c_gate_ctrl(struct dvb_frontend * fe,int enable)775 static int lgdt3306a_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
776 {
777 struct lgdt3306a_state *state = fe->demodulator_priv;
778
779 if (state->cfg->deny_i2c_rptr) {
780 dbg_info("deny_i2c_rptr=%d\n", state->cfg->deny_i2c_rptr);
781 return 0;
782 }
783 dbg_info("(%d)\n", enable);
784
785 /* NI2CRPTEN=0x80 */
786 return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1);
787 }
788
lgdt3306a_sleep(struct lgdt3306a_state * state)789 static int lgdt3306a_sleep(struct lgdt3306a_state *state)
790 {
791 int ret;
792
793 dbg_info("\n");
794 state->current_frequency = -1; /* force re-tune, when we wake */
795
796 ret = lgdt3306a_mpeg_tristate(state, 1); /* disable data bus */
797 if (lg_chkerr(ret))
798 goto fail;
799
800 ret = lgdt3306a_power(state, 0); /* power down */
801 lg_chkerr(ret);
802
803 fail:
804 return 0;
805 }
806
lgdt3306a_fe_sleep(struct dvb_frontend * fe)807 static int lgdt3306a_fe_sleep(struct dvb_frontend *fe)
808 {
809 struct lgdt3306a_state *state = fe->demodulator_priv;
810
811 return lgdt3306a_sleep(state);
812 }
813
lgdt3306a_init(struct dvb_frontend * fe)814 static int lgdt3306a_init(struct dvb_frontend *fe)
815 {
816 struct lgdt3306a_state *state = fe->demodulator_priv;
817 u8 val;
818 int ret;
819
820 dbg_info("\n");
821
822 /* 1. Normal operation mode */
823 ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */
824 if (lg_chkerr(ret))
825 goto fail;
826
827 /* 2. Spectrum inversion auto detection (Not valid for VSB) */
828 ret = lgdt3306a_set_inversion_auto(state, 0);
829 if (lg_chkerr(ret))
830 goto fail;
831
832 /* 3. Spectrum inversion(According to the tuner configuration) */
833 ret = lgdt3306a_set_inversion(state, 1);
834 if (lg_chkerr(ret))
835 goto fail;
836
837 /* 4. Peak-to-peak voltage of ADC input signal */
838
839 /* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */
840 ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1);
841 if (lg_chkerr(ret))
842 goto fail;
843
844 /* 5. ADC output data capture clock phase */
845
846 /* 0=same phase as ADC clock */
847 ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0);
848 if (lg_chkerr(ret))
849 goto fail;
850
851 /* 5a. ADC sampling clock source */
852
853 /* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */
854 ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0);
855 if (lg_chkerr(ret))
856 goto fail;
857
858 /* 6. Automatic PLL set */
859
860 /* PLLSETAUTO=0x40; 0=off */
861 ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0);
862 if (lg_chkerr(ret))
863 goto fail;
864
865 if (state->cfg->xtalMHz == 24) { /* 24MHz */
866 /* 7. Frequency for PLL output(0x2564 for 192MHz for 24MHz) */
867 ret = lgdt3306a_read_reg(state, 0x0005, &val);
868 if (lg_chkerr(ret))
869 goto fail;
870 val &= 0xc0;
871 val |= 0x25;
872 ret = lgdt3306a_write_reg(state, 0x0005, val);
873 if (lg_chkerr(ret))
874 goto fail;
875 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
876 if (lg_chkerr(ret))
877 goto fail;
878
879 /* 8. ADC sampling frequency(0x180000 for 24MHz sampling) */
880 ret = lgdt3306a_read_reg(state, 0x000d, &val);
881 if (lg_chkerr(ret))
882 goto fail;
883 val &= 0xc0;
884 val |= 0x18;
885 ret = lgdt3306a_write_reg(state, 0x000d, val);
886 if (lg_chkerr(ret))
887 goto fail;
888
889 } else if (state->cfg->xtalMHz == 25) { /* 25MHz */
890 /* 7. Frequency for PLL output */
891 ret = lgdt3306a_read_reg(state, 0x0005, &val);
892 if (lg_chkerr(ret))
893 goto fail;
894 val &= 0xc0;
895 val |= 0x25;
896 ret = lgdt3306a_write_reg(state, 0x0005, val);
897 if (lg_chkerr(ret))
898 goto fail;
899 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
900 if (lg_chkerr(ret))
901 goto fail;
902
903 /* 8. ADC sampling frequency(0x190000 for 25MHz sampling) */
904 ret = lgdt3306a_read_reg(state, 0x000d, &val);
905 if (lg_chkerr(ret))
906 goto fail;
907 val &= 0xc0;
908 val |= 0x19;
909 ret = lgdt3306a_write_reg(state, 0x000d, val);
910 if (lg_chkerr(ret))
911 goto fail;
912 } else {
913 pr_err("Bad xtalMHz=%d\n", state->cfg->xtalMHz);
914 }
915 #if 0
916 ret = lgdt3306a_write_reg(state, 0x000e, 0x00);
917 ret = lgdt3306a_write_reg(state, 0x000f, 0x00);
918 #endif
919
920 /* 9. Center frequency of input signal of ADC */
921 ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */
922 ret = lgdt3306a_write_reg(state, 0x0011, 0x00);
923
924 /* 10. Fixed gain error value */
925 ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */
926
927 /* 10a. VSB TR BW gear shift initial step */
928 ret = lgdt3306a_read_reg(state, 0x103c, &val);
929 val &= 0x0f;
930 val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */
931 ret = lgdt3306a_write_reg(state, 0x103c, val);
932
933 /* 10b. Timing offset calibration in low temperature for VSB */
934 ret = lgdt3306a_read_reg(state, 0x103d, &val);
935 val &= 0xfc;
936 val |= 0x03;
937 ret = lgdt3306a_write_reg(state, 0x103d, val);
938
939 /* 10c. Timing offset calibration in low temperature for QAM */
940 ret = lgdt3306a_read_reg(state, 0x1036, &val);
941 val &= 0xf0;
942 val |= 0x0c;
943 ret = lgdt3306a_write_reg(state, 0x1036, val);
944
945 /* 11. Using the imaginary part of CIR in CIR loading */
946 ret = lgdt3306a_read_reg(state, 0x211f, &val);
947 val &= 0xef; /* do not use imaginary of CIR */
948 ret = lgdt3306a_write_reg(state, 0x211f, val);
949
950 /* 12. Control of no signal detector function */
951 ret = lgdt3306a_read_reg(state, 0x2849, &val);
952 val &= 0xef; /* NOUSENOSIGDET=0, enable no signal detector */
953 ret = lgdt3306a_write_reg(state, 0x2849, val);
954
955 /* FGR - put demod in some known mode */
956 ret = lgdt3306a_set_vsb(state);
957
958 /* 13. TP stream format */
959 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
960
961 /* 14. disable output buses */
962 ret = lgdt3306a_mpeg_tristate(state, 1);
963
964 /* 15. Sleep (in reset) */
965 ret = lgdt3306a_sleep(state);
966 lg_chkerr(ret);
967
968 fail:
969 return ret;
970 }
971
lgdt3306a_set_parameters(struct dvb_frontend * fe)972 static int lgdt3306a_set_parameters(struct dvb_frontend *fe)
973 {
974 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
975 struct lgdt3306a_state *state = fe->demodulator_priv;
976 int ret;
977
978 dbg_info("(%d, %d)\n", p->frequency, p->modulation);
979
980 if (state->current_frequency == p->frequency &&
981 state->current_modulation == p->modulation) {
982 dbg_info(" (already set, skipping ...)\n");
983 return 0;
984 }
985 state->current_frequency = -1;
986 state->current_modulation = -1;
987
988 ret = lgdt3306a_power(state, 1); /* power up */
989 if (lg_chkerr(ret))
990 goto fail;
991
992 if (fe->ops.tuner_ops.set_params) {
993 ret = fe->ops.tuner_ops.set_params(fe);
994 if (fe->ops.i2c_gate_ctrl)
995 fe->ops.i2c_gate_ctrl(fe, 0);
996 #if 0
997 if (lg_chkerr(ret))
998 goto fail;
999 state->current_frequency = p->frequency;
1000 #endif
1001 }
1002
1003 ret = lgdt3306a_set_modulation(state, p);
1004 if (lg_chkerr(ret))
1005 goto fail;
1006
1007 ret = lgdt3306a_agc_setup(state, p);
1008 if (lg_chkerr(ret))
1009 goto fail;
1010
1011 ret = lgdt3306a_set_if(state, p);
1012 if (lg_chkerr(ret))
1013 goto fail;
1014
1015 ret = lgdt3306a_spectral_inversion(state, p,
1016 state->cfg->spectral_inversion ? 1 : 0);
1017 if (lg_chkerr(ret))
1018 goto fail;
1019
1020 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
1021 if (lg_chkerr(ret))
1022 goto fail;
1023
1024 ret = lgdt3306a_mpeg_mode_polarity(state,
1025 state->cfg->tpclk_edge,
1026 state->cfg->tpvalid_polarity);
1027 if (lg_chkerr(ret))
1028 goto fail;
1029
1030 ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */
1031 if (lg_chkerr(ret))
1032 goto fail;
1033
1034 ret = lgdt3306a_soft_reset(state);
1035 if (lg_chkerr(ret))
1036 goto fail;
1037
1038 #ifdef DBG_DUMP
1039 lgdt3306a_DumpAllRegs(state);
1040 #endif
1041 state->current_frequency = p->frequency;
1042 fail:
1043 return ret;
1044 }
1045
lgdt3306a_get_frontend(struct dvb_frontend * fe,struct dtv_frontend_properties * p)1046 static int lgdt3306a_get_frontend(struct dvb_frontend *fe,
1047 struct dtv_frontend_properties *p)
1048 {
1049 struct lgdt3306a_state *state = fe->demodulator_priv;
1050
1051 dbg_info("(%u, %d)\n",
1052 state->current_frequency, state->current_modulation);
1053
1054 p->modulation = state->current_modulation;
1055 p->frequency = state->current_frequency;
1056 return 0;
1057 }
1058
lgdt3306a_get_frontend_algo(struct dvb_frontend * fe)1059 static enum dvbfe_algo lgdt3306a_get_frontend_algo(struct dvb_frontend *fe)
1060 {
1061 #if 1
1062 return DVBFE_ALGO_CUSTOM;
1063 #else
1064 return DVBFE_ALGO_HW;
1065 #endif
1066 }
1067
1068 /* ------------------------------------------------------------------------ */
lgdt3306a_monitor_vsb(struct lgdt3306a_state * state)1069 static int lgdt3306a_monitor_vsb(struct lgdt3306a_state *state)
1070 {
1071 u8 val;
1072 int ret;
1073 u8 snrRef, maxPowerMan, nCombDet;
1074 u16 fbDlyCir;
1075
1076 ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1077 if (ret)
1078 return ret;
1079 snrRef = val & 0x3f;
1080
1081 ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan);
1082 if (ret)
1083 return ret;
1084
1085 ret = lgdt3306a_read_reg(state, 0x2191, &val);
1086 if (ret)
1087 return ret;
1088 nCombDet = (val & 0x80) >> 7;
1089
1090 ret = lgdt3306a_read_reg(state, 0x2180, &val);
1091 if (ret)
1092 return ret;
1093 fbDlyCir = (val & 0x03) << 8;
1094
1095 ret = lgdt3306a_read_reg(state, 0x2181, &val);
1096 if (ret)
1097 return ret;
1098 fbDlyCir |= val;
1099
1100 dbg_info("snrRef=%d maxPowerMan=0x%x nCombDet=%d fbDlyCir=0x%x\n",
1101 snrRef, maxPowerMan, nCombDet, fbDlyCir);
1102
1103 /* Carrier offset sub loop bandwidth */
1104 ret = lgdt3306a_read_reg(state, 0x1061, &val);
1105 if (ret)
1106 return ret;
1107 val &= 0xf8;
1108 if ((snrRef > 18) && (maxPowerMan > 0x68)
1109 && (nCombDet == 0x01)
1110 && ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) {
1111 /* SNR is over 18dB and no ghosting */
1112 val |= 0x00; /* final bandwidth = 0 */
1113 } else {
1114 val |= 0x04; /* final bandwidth = 4 */
1115 }
1116 ret = lgdt3306a_write_reg(state, 0x1061, val);
1117 if (ret)
1118 return ret;
1119
1120 /* Adjust Notch Filter */
1121 ret = lgdt3306a_read_reg(state, 0x0024, &val);
1122 if (ret)
1123 return ret;
1124 val &= 0x0f;
1125 if (nCombDet == 0) { /* Turn on the Notch Filter */
1126 val |= 0x50;
1127 }
1128 ret = lgdt3306a_write_reg(state, 0x0024, val);
1129 if (ret)
1130 return ret;
1131
1132 /* VSB Timing Recovery output normalization */
1133 ret = lgdt3306a_read_reg(state, 0x103d, &val);
1134 if (ret)
1135 return ret;
1136 val &= 0xcf;
1137 val |= 0x20;
1138 ret = lgdt3306a_write_reg(state, 0x103d, val);
1139
1140 return ret;
1141 }
1142
1143 static enum lgdt3306a_modulation
lgdt3306a_check_oper_mode(struct lgdt3306a_state * state)1144 lgdt3306a_check_oper_mode(struct lgdt3306a_state *state)
1145 {
1146 u8 val = 0;
1147 int ret;
1148
1149 ret = lgdt3306a_read_reg(state, 0x0081, &val);
1150 if (ret)
1151 goto err;
1152
1153 if (val & 0x80) {
1154 dbg_info("VSB\n");
1155 return LG3306_VSB;
1156 }
1157 if (val & 0x08) {
1158 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1159 if (ret)
1160 goto err;
1161 val = val >> 2;
1162 if (val & 0x01) {
1163 dbg_info("QAM256\n");
1164 return LG3306_QAM256;
1165 }
1166 dbg_info("QAM64\n");
1167 return LG3306_QAM64;
1168 }
1169 err:
1170 pr_warn("UNKNOWN\n");
1171 return LG3306_UNKNOWN_MODE;
1172 }
1173
1174 static enum lgdt3306a_lock_status
lgdt3306a_check_lock_status(struct lgdt3306a_state * state,enum lgdt3306a_lock_check whatLock)1175 lgdt3306a_check_lock_status(struct lgdt3306a_state *state,
1176 enum lgdt3306a_lock_check whatLock)
1177 {
1178 u8 val = 0;
1179 int ret;
1180 enum lgdt3306a_modulation modeOper;
1181 enum lgdt3306a_lock_status lockStatus;
1182
1183 modeOper = LG3306_UNKNOWN_MODE;
1184
1185 switch (whatLock) {
1186 case LG3306_SYNC_LOCK:
1187 {
1188 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1189 if (ret)
1190 return ret;
1191
1192 if ((val & 0x80) == 0x80)
1193 lockStatus = LG3306_LOCK;
1194 else
1195 lockStatus = LG3306_UNLOCK;
1196
1197 dbg_info("SYNC_LOCK=%x\n", lockStatus);
1198 break;
1199 }
1200 case LG3306_AGC_LOCK:
1201 {
1202 ret = lgdt3306a_read_reg(state, 0x0080, &val);
1203 if (ret)
1204 return ret;
1205
1206 if ((val & 0x40) == 0x40)
1207 lockStatus = LG3306_LOCK;
1208 else
1209 lockStatus = LG3306_UNLOCK;
1210
1211 dbg_info("AGC_LOCK=%x\n", lockStatus);
1212 break;
1213 }
1214 case LG3306_TR_LOCK:
1215 {
1216 modeOper = lgdt3306a_check_oper_mode(state);
1217 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
1218 ret = lgdt3306a_read_reg(state, 0x1094, &val);
1219 if (ret)
1220 return ret;
1221
1222 if ((val & 0x80) == 0x80)
1223 lockStatus = LG3306_LOCK;
1224 else
1225 lockStatus = LG3306_UNLOCK;
1226 } else
1227 lockStatus = LG3306_UNKNOWN_LOCK;
1228
1229 dbg_info("TR_LOCK=%x\n", lockStatus);
1230 break;
1231 }
1232 case LG3306_FEC_LOCK:
1233 {
1234 modeOper = lgdt3306a_check_oper_mode(state);
1235 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
1236 ret = lgdt3306a_read_reg(state, 0x0080, &val);
1237 if (ret)
1238 return ret;
1239
1240 if ((val & 0x10) == 0x10)
1241 lockStatus = LG3306_LOCK;
1242 else
1243 lockStatus = LG3306_UNLOCK;
1244 } else
1245 lockStatus = LG3306_UNKNOWN_LOCK;
1246
1247 dbg_info("FEC_LOCK=%x\n", lockStatus);
1248 break;
1249 }
1250
1251 default:
1252 lockStatus = LG3306_UNKNOWN_LOCK;
1253 pr_warn("UNKNOWN whatLock=%d\n", whatLock);
1254 break;
1255 }
1256
1257 return lockStatus;
1258 }
1259
1260 static enum lgdt3306a_neverlock_status
lgdt3306a_check_neverlock_status(struct lgdt3306a_state * state)1261 lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state)
1262 {
1263 u8 val = 0;
1264 int ret;
1265 enum lgdt3306a_neverlock_status lockStatus;
1266
1267 ret = lgdt3306a_read_reg(state, 0x0080, &val);
1268 if (ret)
1269 return ret;
1270 lockStatus = (enum lgdt3306a_neverlock_status)(val & 0x03);
1271
1272 dbg_info("NeverLock=%d", lockStatus);
1273
1274 return lockStatus;
1275 }
1276
lgdt3306a_pre_monitoring(struct lgdt3306a_state * state)1277 static int lgdt3306a_pre_monitoring(struct lgdt3306a_state *state)
1278 {
1279 u8 val = 0;
1280 int ret;
1281 u8 currChDiffACQ, snrRef, mainStrong, aiccrejStatus;
1282
1283 /* Channel variation */
1284 ret = lgdt3306a_read_reg(state, 0x21bc, &currChDiffACQ);
1285 if (ret)
1286 return ret;
1287
1288 /* SNR of Frame sync */
1289 ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1290 if (ret)
1291 return ret;
1292 snrRef = val & 0x3f;
1293
1294 /* Strong Main CIR */
1295 ret = lgdt3306a_read_reg(state, 0x2199, &val);
1296 if (ret)
1297 return ret;
1298 mainStrong = (val & 0x40) >> 6;
1299
1300 ret = lgdt3306a_read_reg(state, 0x0090, &val);
1301 if (ret)
1302 return ret;
1303 aiccrejStatus = (val & 0xf0) >> 4;
1304
1305 dbg_info("snrRef=%d mainStrong=%d aiccrejStatus=%d currChDiffACQ=0x%x\n",
1306 snrRef, mainStrong, aiccrejStatus, currChDiffACQ);
1307
1308 #if 0
1309 /* Dynamic ghost exists */
1310 if ((mainStrong == 0) && (currChDiffACQ > 0x70))
1311 #endif
1312 if (mainStrong == 0) {
1313 ret = lgdt3306a_read_reg(state, 0x2135, &val);
1314 if (ret)
1315 return ret;
1316 val &= 0x0f;
1317 val |= 0xa0;
1318 ret = lgdt3306a_write_reg(state, 0x2135, val);
1319 if (ret)
1320 return ret;
1321
1322 ret = lgdt3306a_read_reg(state, 0x2141, &val);
1323 if (ret)
1324 return ret;
1325 val &= 0x3f;
1326 val |= 0x80;
1327 ret = lgdt3306a_write_reg(state, 0x2141, val);
1328 if (ret)
1329 return ret;
1330
1331 ret = lgdt3306a_write_reg(state, 0x2122, 0x70);
1332 if (ret)
1333 return ret;
1334 } else { /* Weak ghost or static channel */
1335 ret = lgdt3306a_read_reg(state, 0x2135, &val);
1336 if (ret)
1337 return ret;
1338 val &= 0x0f;
1339 val |= 0x70;
1340 ret = lgdt3306a_write_reg(state, 0x2135, val);
1341 if (ret)
1342 return ret;
1343
1344 ret = lgdt3306a_read_reg(state, 0x2141, &val);
1345 if (ret)
1346 return ret;
1347 val &= 0x3f;
1348 val |= 0x40;
1349 ret = lgdt3306a_write_reg(state, 0x2141, val);
1350 if (ret)
1351 return ret;
1352
1353 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
1354 if (ret)
1355 return ret;
1356 }
1357 return 0;
1358 }
1359
1360 static enum lgdt3306a_lock_status
lgdt3306a_sync_lock_poll(struct lgdt3306a_state * state)1361 lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state)
1362 {
1363 enum lgdt3306a_lock_status syncLockStatus = LG3306_UNLOCK;
1364 int i;
1365
1366 for (i = 0; i < 2; i++) {
1367 msleep(30);
1368
1369 syncLockStatus = lgdt3306a_check_lock_status(state,
1370 LG3306_SYNC_LOCK);
1371
1372 if (syncLockStatus == LG3306_LOCK) {
1373 dbg_info("locked(%d)\n", i);
1374 return LG3306_LOCK;
1375 }
1376 }
1377 dbg_info("not locked\n");
1378 return LG3306_UNLOCK;
1379 }
1380
1381 static enum lgdt3306a_lock_status
lgdt3306a_fec_lock_poll(struct lgdt3306a_state * state)1382 lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state)
1383 {
1384 enum lgdt3306a_lock_status FECLockStatus = LG3306_UNLOCK;
1385 int i;
1386
1387 for (i = 0; i < 2; i++) {
1388 msleep(30);
1389
1390 FECLockStatus = lgdt3306a_check_lock_status(state,
1391 LG3306_FEC_LOCK);
1392
1393 if (FECLockStatus == LG3306_LOCK) {
1394 dbg_info("locked(%d)\n", i);
1395 return FECLockStatus;
1396 }
1397 }
1398 dbg_info("not locked\n");
1399 return FECLockStatus;
1400 }
1401
1402 static enum lgdt3306a_neverlock_status
lgdt3306a_neverlock_poll(struct lgdt3306a_state * state)1403 lgdt3306a_neverlock_poll(struct lgdt3306a_state *state)
1404 {
1405 enum lgdt3306a_neverlock_status NLLockStatus = LG3306_NL_FAIL;
1406 int i;
1407
1408 for (i = 0; i < 5; i++) {
1409 msleep(30);
1410
1411 NLLockStatus = lgdt3306a_check_neverlock_status(state);
1412
1413 if (NLLockStatus == LG3306_NL_LOCK) {
1414 dbg_info("NL_LOCK(%d)\n", i);
1415 return NLLockStatus;
1416 }
1417 }
1418 dbg_info("NLLockStatus=%d\n", NLLockStatus);
1419 return NLLockStatus;
1420 }
1421
lgdt3306a_get_packet_error(struct lgdt3306a_state * state)1422 static u8 lgdt3306a_get_packet_error(struct lgdt3306a_state *state)
1423 {
1424 u8 val;
1425 int ret;
1426
1427 ret = lgdt3306a_read_reg(state, 0x00fa, &val);
1428 if (ret)
1429 return ret;
1430
1431 return val;
1432 }
1433
1434 static const u32 valx_x10[] = {
1435 10, 11, 13, 15, 17, 20, 25, 33, 41, 50, 59, 73, 87, 100
1436 };
1437 static const u32 log10x_x1000[] = {
1438 0, 41, 114, 176, 230, 301, 398, 518, 613, 699, 771, 863, 939, 1000
1439 };
1440
log10_x1000(u32 x)1441 static u32 log10_x1000(u32 x)
1442 {
1443 u32 diff_val, step_val, step_log10;
1444 u32 log_val = 0;
1445 u32 i;
1446
1447 if (x <= 0)
1448 return -1000000; /* signal error */
1449
1450 if (x == 10)
1451 return 0; /* log(1)=0 */
1452
1453 if (x < 10) {
1454 while (x < 10) {
1455 x = x * 10;
1456 log_val--;
1457 }
1458 } else { /* x > 10 */
1459 while (x >= 100) {
1460 x = x / 10;
1461 log_val++;
1462 }
1463 }
1464 log_val *= 1000;
1465
1466 if (x == 10) /* was our input an exact multiple of 10 */
1467 return log_val; /* don't need to interpolate */
1468
1469 /* find our place on the log curve */
1470 for (i = 1; i < ARRAY_SIZE(valx_x10); i++) {
1471 if (valx_x10[i] >= x)
1472 break;
1473 }
1474 if (i == ARRAY_SIZE(valx_x10))
1475 return log_val + log10x_x1000[i - 1];
1476
1477 diff_val = x - valx_x10[i-1];
1478 step_val = valx_x10[i] - valx_x10[i - 1];
1479 step_log10 = log10x_x1000[i] - log10x_x1000[i - 1];
1480
1481 /* do a linear interpolation to get in-between values */
1482 return log_val + log10x_x1000[i - 1] +
1483 ((diff_val*step_log10) / step_val);
1484 }
1485
lgdt3306a_calculate_snr_x100(struct lgdt3306a_state * state)1486 static u32 lgdt3306a_calculate_snr_x100(struct lgdt3306a_state *state)
1487 {
1488 u32 mse; /* Mean-Square Error */
1489 u32 pwr; /* Constelation power */
1490 u32 snr_x100;
1491
1492 mse = (read_reg(state, 0x00ec) << 8) |
1493 (read_reg(state, 0x00ed));
1494 pwr = (read_reg(state, 0x00e8) << 8) |
1495 (read_reg(state, 0x00e9));
1496
1497 if (mse == 0) /* no signal */
1498 return 0;
1499
1500 snr_x100 = log10_x1000((pwr * 10000) / mse) - 3000;
1501 dbg_info("mse=%u, pwr=%u, snr_x100=%d\n", mse, pwr, snr_x100);
1502
1503 return snr_x100;
1504 }
1505
1506 static enum lgdt3306a_lock_status
lgdt3306a_vsb_lock_poll(struct lgdt3306a_state * state)1507 lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state)
1508 {
1509 int ret;
1510 u8 cnt = 0;
1511 u8 packet_error;
1512 u32 snr;
1513
1514 for (cnt = 0; cnt < 10; cnt++) {
1515 if (lgdt3306a_sync_lock_poll(state) == LG3306_UNLOCK) {
1516 dbg_info("no sync lock!\n");
1517 return LG3306_UNLOCK;
1518 }
1519
1520 msleep(20);
1521 ret = lgdt3306a_pre_monitoring(state);
1522 if (ret)
1523 break;
1524
1525 packet_error = lgdt3306a_get_packet_error(state);
1526 snr = lgdt3306a_calculate_snr_x100(state);
1527 dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
1528
1529 if ((snr >= 1500) && (packet_error < 0xff))
1530 return LG3306_LOCK;
1531 }
1532
1533 dbg_info("not locked!\n");
1534 return LG3306_UNLOCK;
1535 }
1536
1537 static enum lgdt3306a_lock_status
lgdt3306a_qam_lock_poll(struct lgdt3306a_state * state)1538 lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state)
1539 {
1540 u8 cnt;
1541 u8 packet_error;
1542 u32 snr;
1543
1544 for (cnt = 0; cnt < 10; cnt++) {
1545 if (lgdt3306a_fec_lock_poll(state) == LG3306_UNLOCK) {
1546 dbg_info("no fec lock!\n");
1547 return LG3306_UNLOCK;
1548 }
1549
1550 msleep(20);
1551
1552 packet_error = lgdt3306a_get_packet_error(state);
1553 snr = lgdt3306a_calculate_snr_x100(state);
1554 dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
1555
1556 if ((snr >= 1500) && (packet_error < 0xff))
1557 return LG3306_LOCK;
1558 }
1559
1560 dbg_info("not locked!\n");
1561 return LG3306_UNLOCK;
1562 }
1563
lgdt3306a_read_status(struct dvb_frontend * fe,enum fe_status * status)1564 static int lgdt3306a_read_status(struct dvb_frontend *fe,
1565 enum fe_status *status)
1566 {
1567 struct lgdt3306a_state *state = fe->demodulator_priv;
1568 u16 strength = 0;
1569 int ret = 0;
1570
1571 if (fe->ops.tuner_ops.get_rf_strength) {
1572 ret = fe->ops.tuner_ops.get_rf_strength(fe, &strength);
1573 if (ret == 0)
1574 dbg_info("strength=%d\n", strength);
1575 else
1576 dbg_info("fe->ops.tuner_ops.get_rf_strength() failed\n");
1577 }
1578
1579 *status = 0;
1580 if (lgdt3306a_neverlock_poll(state) == LG3306_NL_LOCK) {
1581 *status |= FE_HAS_SIGNAL;
1582 *status |= FE_HAS_CARRIER;
1583
1584 switch (state->current_modulation) {
1585 case QAM_256:
1586 case QAM_64:
1587 if (lgdt3306a_qam_lock_poll(state) == LG3306_LOCK) {
1588 *status |= FE_HAS_VITERBI;
1589 *status |= FE_HAS_SYNC;
1590
1591 *status |= FE_HAS_LOCK;
1592 }
1593 break;
1594 case VSB_8:
1595 if (lgdt3306a_vsb_lock_poll(state) == LG3306_LOCK) {
1596 *status |= FE_HAS_VITERBI;
1597 *status |= FE_HAS_SYNC;
1598
1599 *status |= FE_HAS_LOCK;
1600
1601 ret = lgdt3306a_monitor_vsb(state);
1602 }
1603 break;
1604 default:
1605 ret = -EINVAL;
1606 }
1607 }
1608 return ret;
1609 }
1610
1611
lgdt3306a_read_snr(struct dvb_frontend * fe,u16 * snr)1612 static int lgdt3306a_read_snr(struct dvb_frontend *fe, u16 *snr)
1613 {
1614 struct lgdt3306a_state *state = fe->demodulator_priv;
1615
1616 state->snr = lgdt3306a_calculate_snr_x100(state);
1617 /* report SNR in dB * 10 */
1618 *snr = state->snr/10;
1619
1620 return 0;
1621 }
1622
lgdt3306a_read_signal_strength(struct dvb_frontend * fe,u16 * strength)1623 static int lgdt3306a_read_signal_strength(struct dvb_frontend *fe,
1624 u16 *strength)
1625 {
1626 /*
1627 * Calculate some sort of "strength" from SNR
1628 */
1629 struct lgdt3306a_state *state = fe->demodulator_priv;
1630 u16 snr; /* snr_x10 */
1631 int ret;
1632 u32 ref_snr; /* snr*100 */
1633 u32 str;
1634
1635 *strength = 0;
1636
1637 switch (state->current_modulation) {
1638 case VSB_8:
1639 ref_snr = 1600; /* 16dB */
1640 break;
1641 case QAM_64:
1642 ref_snr = 2200; /* 22dB */
1643 break;
1644 case QAM_256:
1645 ref_snr = 2800; /* 28dB */
1646 break;
1647 default:
1648 return -EINVAL;
1649 }
1650
1651 ret = fe->ops.read_snr(fe, &snr);
1652 if (lg_chkerr(ret))
1653 goto fail;
1654
1655 if (state->snr <= (ref_snr - 100))
1656 str = 0;
1657 else if (state->snr <= ref_snr)
1658 str = (0xffff * 65) / 100; /* 65% */
1659 else {
1660 str = state->snr - ref_snr;
1661 str /= 50;
1662 str += 78; /* 78%-100% */
1663 if (str > 100)
1664 str = 100;
1665 str = (0xffff * str) / 100;
1666 }
1667 *strength = (u16)str;
1668 dbg_info("strength=%u\n", *strength);
1669
1670 fail:
1671 return ret;
1672 }
1673
1674 /* ------------------------------------------------------------------------ */
1675
lgdt3306a_read_ber(struct dvb_frontend * fe,u32 * ber)1676 static int lgdt3306a_read_ber(struct dvb_frontend *fe, u32 *ber)
1677 {
1678 struct lgdt3306a_state *state = fe->demodulator_priv;
1679 u32 tmp;
1680
1681 *ber = 0;
1682 #if 1
1683 /* FGR - FIXME - I don't know what value is expected by dvb_core
1684 * what is the scale of the value?? */
1685 tmp = read_reg(state, 0x00fc); /* NBERVALUE[24-31] */
1686 tmp = (tmp << 8) | read_reg(state, 0x00fd); /* NBERVALUE[16-23] */
1687 tmp = (tmp << 8) | read_reg(state, 0x00fe); /* NBERVALUE[8-15] */
1688 tmp = (tmp << 8) | read_reg(state, 0x00ff); /* NBERVALUE[0-7] */
1689 *ber = tmp;
1690 dbg_info("ber=%u\n", tmp);
1691 #endif
1692 return 0;
1693 }
1694
lgdt3306a_read_ucblocks(struct dvb_frontend * fe,u32 * ucblocks)1695 static int lgdt3306a_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1696 {
1697 struct lgdt3306a_state *state = fe->demodulator_priv;
1698
1699 *ucblocks = 0;
1700 #if 1
1701 /* FGR - FIXME - I don't know what value is expected by dvb_core
1702 * what happens when value wraps? */
1703 *ucblocks = read_reg(state, 0x00f4); /* TPIFTPERRCNT[0-7] */
1704 dbg_info("ucblocks=%u\n", *ucblocks);
1705 #endif
1706
1707 return 0;
1708 }
1709
lgdt3306a_tune(struct dvb_frontend * fe,bool re_tune,unsigned int mode_flags,unsigned int * delay,enum fe_status * status)1710 static int lgdt3306a_tune(struct dvb_frontend *fe, bool re_tune,
1711 unsigned int mode_flags, unsigned int *delay,
1712 enum fe_status *status)
1713 {
1714 int ret = 0;
1715 struct lgdt3306a_state *state = fe->demodulator_priv;
1716
1717 dbg_info("re_tune=%u\n", re_tune);
1718
1719 if (re_tune) {
1720 state->current_frequency = -1; /* force re-tune */
1721 ret = lgdt3306a_set_parameters(fe);
1722 if (ret != 0)
1723 return ret;
1724 }
1725 *delay = 125;
1726 ret = lgdt3306a_read_status(fe, status);
1727
1728 return ret;
1729 }
1730
lgdt3306a_get_tune_settings(struct dvb_frontend * fe,struct dvb_frontend_tune_settings * fe_tune_settings)1731 static int lgdt3306a_get_tune_settings(struct dvb_frontend *fe,
1732 struct dvb_frontend_tune_settings
1733 *fe_tune_settings)
1734 {
1735 fe_tune_settings->min_delay_ms = 100;
1736 dbg_info("\n");
1737 return 0;
1738 }
1739
lgdt3306a_search(struct dvb_frontend * fe)1740 static int lgdt3306a_search(struct dvb_frontend *fe)
1741 {
1742 enum fe_status status = 0;
1743 int ret;
1744
1745 /* set frontend */
1746 ret = lgdt3306a_set_parameters(fe);
1747 if (ret)
1748 goto error;
1749
1750 ret = lgdt3306a_read_status(fe, &status);
1751 if (ret)
1752 goto error;
1753
1754 /* check if we have a valid signal */
1755 if (status & FE_HAS_LOCK)
1756 return DVBFE_ALGO_SEARCH_SUCCESS;
1757 else
1758 return DVBFE_ALGO_SEARCH_AGAIN;
1759
1760 error:
1761 dbg_info("failed (%d)\n", ret);
1762 return DVBFE_ALGO_SEARCH_ERROR;
1763 }
1764
lgdt3306a_release(struct dvb_frontend * fe)1765 static void lgdt3306a_release(struct dvb_frontend *fe)
1766 {
1767 struct lgdt3306a_state *state = fe->demodulator_priv;
1768
1769 dbg_info("\n");
1770
1771 /*
1772 * If state->muxc is not NULL, then we are an i2c device
1773 * and lgdt3306a_remove will clean up state
1774 */
1775 if (!state->muxc)
1776 kfree(state);
1777 }
1778
1779 static const struct dvb_frontend_ops lgdt3306a_ops;
1780
lgdt3306a_attach(const struct lgdt3306a_config * config,struct i2c_adapter * i2c_adap)1781 struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config,
1782 struct i2c_adapter *i2c_adap)
1783 {
1784 struct lgdt3306a_state *state = NULL;
1785 int ret;
1786 u8 val;
1787
1788 dbg_info("(%d-%04x)\n",
1789 i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
1790 config ? config->i2c_addr : 0);
1791
1792 state = kzalloc(sizeof(struct lgdt3306a_state), GFP_KERNEL);
1793 if (state == NULL)
1794 goto fail;
1795
1796 state->cfg = config;
1797 state->i2c_adap = i2c_adap;
1798
1799 memcpy(&state->frontend.ops, &lgdt3306a_ops,
1800 sizeof(struct dvb_frontend_ops));
1801 state->frontend.demodulator_priv = state;
1802
1803 /* verify that we're talking to a lg3306a */
1804 /* FGR - NOTE - there is no obvious ChipId to check; we check
1805 * some "known" bits after reset, but it's still just a guess */
1806 ret = lgdt3306a_read_reg(state, 0x0000, &val);
1807 if (lg_chkerr(ret))
1808 goto fail;
1809 if ((val & 0x74) != 0x74) {
1810 pr_warn("expected 0x74, got 0x%x\n", (val & 0x74));
1811 #if 0
1812 /* FIXME - re-enable when we know this is right */
1813 goto fail;
1814 #endif
1815 }
1816 ret = lgdt3306a_read_reg(state, 0x0001, &val);
1817 if (lg_chkerr(ret))
1818 goto fail;
1819 if ((val & 0xf6) != 0xc6) {
1820 pr_warn("expected 0xc6, got 0x%x\n", (val & 0xf6));
1821 #if 0
1822 /* FIXME - re-enable when we know this is right */
1823 goto fail;
1824 #endif
1825 }
1826 ret = lgdt3306a_read_reg(state, 0x0002, &val);
1827 if (lg_chkerr(ret))
1828 goto fail;
1829 if ((val & 0x73) != 0x03) {
1830 pr_warn("expected 0x03, got 0x%x\n", (val & 0x73));
1831 #if 0
1832 /* FIXME - re-enable when we know this is right */
1833 goto fail;
1834 #endif
1835 }
1836
1837 state->current_frequency = -1;
1838 state->current_modulation = -1;
1839
1840 lgdt3306a_sleep(state);
1841
1842 return &state->frontend;
1843
1844 fail:
1845 pr_warn("unable to detect LGDT3306A hardware\n");
1846 kfree(state);
1847 return NULL;
1848 }
1849 EXPORT_SYMBOL(lgdt3306a_attach);
1850
1851 #ifdef DBG_DUMP
1852
1853 static const short regtab[] = {
1854 0x0000, /* SOFTRSTB 1'b1 1'b1 1'b1 ADCPDB 1'b1 PLLPDB GBBPDB 11111111 */
1855 0x0001, /* 1'b1 1'b1 1'b0 1'b0 AUTORPTRS */
1856 0x0002, /* NI2CRPTEN 1'b0 1'b0 1'b0 SPECINVAUT */
1857 0x0003, /* AGCRFOUT */
1858 0x0004, /* ADCSEL1V ADCCNT ADCCNF ADCCNS ADCCLKPLL */
1859 0x0005, /* PLLINDIVSE */
1860 0x0006, /* PLLCTRL[7:0] 11100001 */
1861 0x0007, /* SYSINITWAITTIME[7:0] (msec) 00001000 */
1862 0x0008, /* STDOPMODE[7:0] 10000000 */
1863 0x0009, /* 1'b0 1'b0 1'b0 STDOPDETTMODE[2:0] STDOPDETCMODE[1:0] 00011110 */
1864 0x000a, /* DAFTEN 1'b1 x x SCSYSLOCK */
1865 0x000b, /* SCSYSLOCKCHKTIME[7:0] (10msec) 01100100 */
1866 0x000d, /* x SAMPLING4 */
1867 0x000e, /* SAMFREQ[15:8] 00000000 */
1868 0x000f, /* SAMFREQ[7:0] 00000000 */
1869 0x0010, /* IFFREQ[15:8] 01100000 */
1870 0x0011, /* IFFREQ[7:0] 00000000 */
1871 0x0012, /* AGCEN AGCREFMO */
1872 0x0013, /* AGCRFFIXB AGCIFFIXB AGCLOCKDETRNGSEL[1:0] 1'b1 1'b0 1'b0 1'b0 11101000 */
1873 0x0014, /* AGCFIXVALUE[7:0] 01111111 */
1874 0x0015, /* AGCREF[15:8] 00001010 */
1875 0x0016, /* AGCREF[7:0] 11100100 */
1876 0x0017, /* AGCDELAY[7:0] 00100000 */
1877 0x0018, /* AGCRFBW[3:0] AGCIFBW[3:0] 10001000 */
1878 0x0019, /* AGCUDOUTMODE[1:0] AGCUDCTRLLEN[1:0] AGCUDCTRL */
1879 0x001c, /* 1'b1 PFEN MFEN AICCVSYNC */
1880 0x001d, /* 1'b0 1'b1 1'b0 1'b1 AICCVSYNC */
1881 0x001e, /* AICCALPHA[3:0] 1'b1 1'b0 1'b1 1'b0 01111010 */
1882 0x001f, /* AICCDETTH[19:16] AICCOFFTH[19:16] 00000000 */
1883 0x0020, /* AICCDETTH[15:8] 01111100 */
1884 0x0021, /* AICCDETTH[7:0] 00000000 */
1885 0x0022, /* AICCOFFTH[15:8] 00000101 */
1886 0x0023, /* AICCOFFTH[7:0] 11100000 */
1887 0x0024, /* AICCOPMODE3[1:0] AICCOPMODE2[1:0] AICCOPMODE1[1:0] AICCOPMODE0[1:0] 00000000 */
1888 0x0025, /* AICCFIXFREQ3[23:16] 00000000 */
1889 0x0026, /* AICCFIXFREQ3[15:8] 00000000 */
1890 0x0027, /* AICCFIXFREQ3[7:0] 00000000 */
1891 0x0028, /* AICCFIXFREQ2[23:16] 00000000 */
1892 0x0029, /* AICCFIXFREQ2[15:8] 00000000 */
1893 0x002a, /* AICCFIXFREQ2[7:0] 00000000 */
1894 0x002b, /* AICCFIXFREQ1[23:16] 00000000 */
1895 0x002c, /* AICCFIXFREQ1[15:8] 00000000 */
1896 0x002d, /* AICCFIXFREQ1[7:0] 00000000 */
1897 0x002e, /* AICCFIXFREQ0[23:16] 00000000 */
1898 0x002f, /* AICCFIXFREQ0[15:8] 00000000 */
1899 0x0030, /* AICCFIXFREQ0[7:0] 00000000 */
1900 0x0031, /* 1'b0 1'b1 1'b0 1'b0 x DAGC1STER */
1901 0x0032, /* DAGC1STEN DAGC1STER */
1902 0x0033, /* DAGC1STREF[15:8] 00001010 */
1903 0x0034, /* DAGC1STREF[7:0] 11100100 */
1904 0x0035, /* DAGC2NDE */
1905 0x0036, /* DAGC2NDREF[15:8] 00001010 */
1906 0x0037, /* DAGC2NDREF[7:0] 10000000 */
1907 0x0038, /* DAGC2NDLOCKDETRNGSEL[1:0] */
1908 0x003d, /* 1'b1 SAMGEARS */
1909 0x0040, /* SAMLFGMA */
1910 0x0041, /* SAMLFBWM */
1911 0x0044, /* 1'b1 CRGEARSHE */
1912 0x0045, /* CRLFGMAN */
1913 0x0046, /* CFLFBWMA */
1914 0x0047, /* CRLFGMAN */
1915 0x0048, /* x x x x CRLFGSTEP_VS[3:0] xxxx1001 */
1916 0x0049, /* CRLFBWMA */
1917 0x004a, /* CRLFBWMA */
1918 0x0050, /* 1'b0 1'b1 1'b1 1'b0 MSECALCDA */
1919 0x0070, /* TPOUTEN TPIFEN TPCLKOUTE */
1920 0x0071, /* TPSENB TPSSOPBITE */
1921 0x0073, /* TP47HINS x x CHBERINT PERMODE[1:0] PERINT[1:0] 1xx11100 */
1922 0x0075, /* x x x x x IQSWAPCTRL[2:0] xxxxx000 */
1923 0x0076, /* NBERCON NBERST NBERPOL NBERWSYN */
1924 0x0077, /* x NBERLOSTTH[2:0] NBERACQTH[3:0] x0000000 */
1925 0x0078, /* NBERPOLY[31:24] 00000000 */
1926 0x0079, /* NBERPOLY[23:16] 00000000 */
1927 0x007a, /* NBERPOLY[15:8] 00000000 */
1928 0x007b, /* NBERPOLY[7:0] 00000000 */
1929 0x007c, /* NBERPED[31:24] 00000000 */
1930 0x007d, /* NBERPED[23:16] 00000000 */
1931 0x007e, /* NBERPED[15:8] 00000000 */
1932 0x007f, /* NBERPED[7:0] 00000000 */
1933 0x0080, /* x AGCLOCK DAGCLOCK SYSLOCK x x NEVERLOCK[1:0] */
1934 0x0085, /* SPECINVST */
1935 0x0088, /* SYSLOCKTIME[15:8] */
1936 0x0089, /* SYSLOCKTIME[7:0] */
1937 0x008c, /* FECLOCKTIME[15:8] */
1938 0x008d, /* FECLOCKTIME[7:0] */
1939 0x008e, /* AGCACCOUT[15:8] */
1940 0x008f, /* AGCACCOUT[7:0] */
1941 0x0090, /* AICCREJSTATUS[3:0] AICCREJBUSY[3:0] */
1942 0x0091, /* AICCVSYNC */
1943 0x009c, /* CARRFREQOFFSET[15:8] */
1944 0x009d, /* CARRFREQOFFSET[7:0] */
1945 0x00a1, /* SAMFREQOFFSET[23:16] */
1946 0x00a2, /* SAMFREQOFFSET[15:8] */
1947 0x00a3, /* SAMFREQOFFSET[7:0] */
1948 0x00a6, /* SYNCLOCK SYNCLOCKH */
1949 #if 0 /* covered elsewhere */
1950 0x00e8, /* CONSTPWR[15:8] */
1951 0x00e9, /* CONSTPWR[7:0] */
1952 0x00ea, /* BMSE[15:8] */
1953 0x00eb, /* BMSE[7:0] */
1954 0x00ec, /* MSE[15:8] */
1955 0x00ed, /* MSE[7:0] */
1956 0x00ee, /* CONSTI[7:0] */
1957 0x00ef, /* CONSTQ[7:0] */
1958 #endif
1959 0x00f4, /* TPIFTPERRCNT[7:0] */
1960 0x00f5, /* TPCORREC */
1961 0x00f6, /* VBBER[15:8] */
1962 0x00f7, /* VBBER[7:0] */
1963 0x00f8, /* VABER[15:8] */
1964 0x00f9, /* VABER[7:0] */
1965 0x00fa, /* TPERRCNT[7:0] */
1966 0x00fb, /* NBERLOCK x x x x x x x */
1967 0x00fc, /* NBERVALUE[31:24] */
1968 0x00fd, /* NBERVALUE[23:16] */
1969 0x00fe, /* NBERVALUE[15:8] */
1970 0x00ff, /* NBERVALUE[7:0] */
1971 0x1000, /* 1'b0 WODAGCOU */
1972 0x1005, /* x x 1'b1 1'b1 x SRD_Q_QM */
1973 0x1009, /* SRDWAITTIME[7:0] (10msec) 00100011 */
1974 0x100a, /* SRDWAITTIME_CQS[7:0] (msec) 01100100 */
1975 0x101a, /* x 1'b1 1'b0 1'b0 x QMDQAMMODE[2:0] x100x010 */
1976 0x1036, /* 1'b0 1'b1 1'b0 1'b0 SAMGSEND_CQS[3:0] 01001110 */
1977 0x103c, /* SAMGSAUTOSTL_V[3:0] SAMGSAUTOEDL_V[3:0] 01000110 */
1978 0x103d, /* 1'b1 1'b1 SAMCNORMBP_V[1:0] 1'b0 1'b0 SAMMODESEL_V[1:0] 11100001 */
1979 0x103f, /* SAMZTEDSE */
1980 0x105d, /* EQSTATUSE */
1981 0x105f, /* x PMAPG2_V[2:0] x DMAPG2_V[2:0] x001x011 */
1982 0x1060, /* 1'b1 EQSTATUSE */
1983 0x1061, /* CRMAPBWSTL_V[3:0] CRMAPBWEDL_V[3:0] 00000100 */
1984 0x1065, /* 1'b0 x CRMODE_V[1:0] 1'b1 x 1'b1 x 0x111x1x */
1985 0x1066, /* 1'b0 1'b0 1'b1 1'b0 1'b1 PNBOOSTSE */
1986 0x1068, /* CREPHNGAIN2_V[3:0] CREPHNPBW_V[3:0] 10010001 */
1987 0x106e, /* x x x x x CREPHNEN_ */
1988 0x106f, /* CREPHNTH_V[7:0] 00010101 */
1989 0x1072, /* CRSWEEPN */
1990 0x1073, /* CRPGAIN_V[3:0] x x 1'b1 1'b1 1001xx11 */
1991 0x1074, /* CRPBW_V[3:0] x x 1'b1 1'b1 0001xx11 */
1992 0x1080, /* DAFTSTATUS[1:0] x x x x x x */
1993 0x1081, /* SRDSTATUS[1:0] x x x x x SRDLOCK */
1994 0x10a9, /* EQSTATUS_CQS[1:0] x x x x x x */
1995 0x10b7, /* EQSTATUS_V[1:0] x x x x x x */
1996 #if 0 /* SMART_ANT */
1997 0x1f00, /* MODEDETE */
1998 0x1f01, /* x x x x x x x SFNRST xxxxxxx0 */
1999 0x1f03, /* NUMOFANT[7:0] 10000000 */
2000 0x1f04, /* x SELMASK[6:0] x0000000 */
2001 0x1f05, /* x SETMASK[6:0] x0000000 */
2002 0x1f06, /* x TXDATA[6:0] x0000000 */
2003 0x1f07, /* x CHNUMBER[6:0] x0000000 */
2004 0x1f09, /* AGCTIME[23:16] 10011000 */
2005 0x1f0a, /* AGCTIME[15:8] 10010110 */
2006 0x1f0b, /* AGCTIME[7:0] 10000000 */
2007 0x1f0c, /* ANTTIME[31:24] 00000000 */
2008 0x1f0d, /* ANTTIME[23:16] 00000011 */
2009 0x1f0e, /* ANTTIME[15:8] 10010000 */
2010 0x1f0f, /* ANTTIME[7:0] 10010000 */
2011 0x1f11, /* SYNCTIME[23:16] 10011000 */
2012 0x1f12, /* SYNCTIME[15:8] 10010110 */
2013 0x1f13, /* SYNCTIME[7:0] 10000000 */
2014 0x1f14, /* SNRTIME[31:24] 00000001 */
2015 0x1f15, /* SNRTIME[23:16] 01111101 */
2016 0x1f16, /* SNRTIME[15:8] 01111000 */
2017 0x1f17, /* SNRTIME[7:0] 01000000 */
2018 0x1f19, /* FECTIME[23:16] 00000000 */
2019 0x1f1a, /* FECTIME[15:8] 01110010 */
2020 0x1f1b, /* FECTIME[7:0] 01110000 */
2021 0x1f1d, /* FECTHD[7:0] 00000011 */
2022 0x1f1f, /* SNRTHD[23:16] 00001000 */
2023 0x1f20, /* SNRTHD[15:8] 01111111 */
2024 0x1f21, /* SNRTHD[7:0] 10000101 */
2025 0x1f80, /* IRQFLG x x SFSDRFLG MODEBFLG SAVEFLG SCANFLG TRACKFLG */
2026 0x1f81, /* x SYNCCON SNRCON FECCON x STDBUSY SYNCRST AGCFZCO */
2027 0x1f82, /* x x x SCANOPCD[4:0] */
2028 0x1f83, /* x x x x MAINOPCD[3:0] */
2029 0x1f84, /* x x RXDATA[13:8] */
2030 0x1f85, /* RXDATA[7:0] */
2031 0x1f86, /* x x SDTDATA[13:8] */
2032 0x1f87, /* SDTDATA[7:0] */
2033 0x1f89, /* ANTSNR[23:16] */
2034 0x1f8a, /* ANTSNR[15:8] */
2035 0x1f8b, /* ANTSNR[7:0] */
2036 0x1f8c, /* x x x x ANTFEC[13:8] */
2037 0x1f8d, /* ANTFEC[7:0] */
2038 0x1f8e, /* MAXCNT[7:0] */
2039 0x1f8f, /* SCANCNT[7:0] */
2040 0x1f91, /* MAXPW[23:16] */
2041 0x1f92, /* MAXPW[15:8] */
2042 0x1f93, /* MAXPW[7:0] */
2043 0x1f95, /* CURPWMSE[23:16] */
2044 0x1f96, /* CURPWMSE[15:8] */
2045 0x1f97, /* CURPWMSE[7:0] */
2046 #endif /* SMART_ANT */
2047 0x211f, /* 1'b1 1'b1 1'b1 CIRQEN x x 1'b0 1'b0 1111xx00 */
2048 0x212a, /* EQAUTOST */
2049 0x2122, /* CHFAST[7:0] 01100000 */
2050 0x212b, /* FFFSTEP_V[3:0] x FBFSTEP_V[2:0] 0001x001 */
2051 0x212c, /* PHDEROTBWSEL[3:0] 1'b1 1'b1 1'b1 1'b0 10001110 */
2052 0x212d, /* 1'b1 1'b1 1'b1 1'b1 x x TPIFLOCKS */
2053 0x2135, /* DYNTRACKFDEQ[3:0] x 1'b0 1'b0 1'b0 1010x000 */
2054 0x2141, /* TRMODE[1:0] 1'b1 1'b1 1'b0 1'b1 1'b1 1'b1 01110111 */
2055 0x2162, /* AICCCTRLE */
2056 0x2173, /* PHNCNFCNT[7:0] 00000100 */
2057 0x2179, /* 1'b0 1'b0 1'b0 1'b1 x BADSINGLEDYNTRACKFBF[2:0] 0001x001 */
2058 0x217a, /* 1'b0 1'b0 1'b0 1'b1 x BADSLOWSINGLEDYNTRACKFBF[2:0] 0001x001 */
2059 0x217e, /* CNFCNTTPIF[7:0] 00001000 */
2060 0x217f, /* TPERRCNTTPIF[7:0] 00000001 */
2061 0x2180, /* x x x x x x FBDLYCIR[9:8] */
2062 0x2181, /* FBDLYCIR[7:0] */
2063 0x2185, /* MAXPWRMAIN[7:0] */
2064 0x2191, /* NCOMBDET x x x x x x x */
2065 0x2199, /* x MAINSTRON */
2066 0x219a, /* FFFEQSTEPOUT_V[3:0] FBFSTEPOUT_V[2:0] */
2067 0x21a1, /* x x SNRREF[5:0] */
2068 0x2845, /* 1'b0 1'b1 x x FFFSTEP_CQS[1:0] FFFCENTERTAP[1:0] 01xx1110 */
2069 0x2846, /* 1'b0 x 1'b0 1'b1 FBFSTEP_CQS[1:0] 1'b1 1'b0 0x011110 */
2070 0x2847, /* ENNOSIGDE */
2071 0x2849, /* 1'b1 1'b1 NOUSENOSI */
2072 0x284a, /* EQINITWAITTIME[7:0] 01100100 */
2073 0x3000, /* 1'b1 1'b1 1'b1 x x x 1'b0 RPTRSTM */
2074 0x3001, /* RPTRSTWAITTIME[7:0] (100msec) 00110010 */
2075 0x3031, /* FRAMELOC */
2076 0x3032, /* 1'b1 1'b0 1'b0 1'b0 x x FRAMELOCKMODE_CQS[1:0] 1000xx11 */
2077 0x30a9, /* VDLOCK_Q FRAMELOCK */
2078 0x30aa, /* MPEGLOCK */
2079 };
2080
2081 #define numDumpRegs (sizeof(regtab)/sizeof(regtab[0]))
2082 static u8 regval1[numDumpRegs] = {0, };
2083 static u8 regval2[numDumpRegs] = {0, };
2084
lgdt3306a_DumpAllRegs(struct lgdt3306a_state * state)2085 static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state)
2086 {
2087 memset(regval2, 0xff, sizeof(regval2));
2088 lgdt3306a_DumpRegs(state);
2089 }
2090
lgdt3306a_DumpRegs(struct lgdt3306a_state * state)2091 static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state)
2092 {
2093 int i;
2094 int sav_debug = debug;
2095
2096 if ((debug & DBG_DUMP) == 0)
2097 return;
2098 debug &= ~DBG_REG; /* suppress DBG_REG during reg dump */
2099
2100 lg_debug("\n");
2101
2102 for (i = 0; i < numDumpRegs; i++) {
2103 lgdt3306a_read_reg(state, regtab[i], ®val1[i]);
2104 if (regval1[i] != regval2[i]) {
2105 lg_debug(" %04X = %02X\n", regtab[i], regval1[i]);
2106 regval2[i] = regval1[i];
2107 }
2108 }
2109 debug = sav_debug;
2110 }
2111 #endif /* DBG_DUMP */
2112
2113
2114
2115 static const struct dvb_frontend_ops lgdt3306a_ops = {
2116 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
2117 .info = {
2118 .name = "LG Electronics LGDT3306A VSB/QAM Frontend",
2119 .frequency_min = 54000000,
2120 .frequency_max = 858000000,
2121 .frequency_stepsize = 62500,
2122 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
2123 },
2124 .i2c_gate_ctrl = lgdt3306a_i2c_gate_ctrl,
2125 .init = lgdt3306a_init,
2126 .sleep = lgdt3306a_fe_sleep,
2127 /* if this is set, it overrides the default swzigzag */
2128 .tune = lgdt3306a_tune,
2129 .set_frontend = lgdt3306a_set_parameters,
2130 .get_frontend = lgdt3306a_get_frontend,
2131 .get_frontend_algo = lgdt3306a_get_frontend_algo,
2132 .get_tune_settings = lgdt3306a_get_tune_settings,
2133 .read_status = lgdt3306a_read_status,
2134 .read_ber = lgdt3306a_read_ber,
2135 .read_signal_strength = lgdt3306a_read_signal_strength,
2136 .read_snr = lgdt3306a_read_snr,
2137 .read_ucblocks = lgdt3306a_read_ucblocks,
2138 .release = lgdt3306a_release,
2139 .ts_bus_ctrl = lgdt3306a_ts_bus_ctrl,
2140 .search = lgdt3306a_search,
2141 };
2142
lgdt3306a_select(struct i2c_mux_core * muxc,u32 chan)2143 static int lgdt3306a_select(struct i2c_mux_core *muxc, u32 chan)
2144 {
2145 struct i2c_client *client = i2c_mux_priv(muxc);
2146 struct lgdt3306a_state *state = i2c_get_clientdata(client);
2147
2148 return lgdt3306a_i2c_gate_ctrl(&state->frontend, 1);
2149 }
2150
lgdt3306a_deselect(struct i2c_mux_core * muxc,u32 chan)2151 static int lgdt3306a_deselect(struct i2c_mux_core *muxc, u32 chan)
2152 {
2153 struct i2c_client *client = i2c_mux_priv(muxc);
2154 struct lgdt3306a_state *state = i2c_get_clientdata(client);
2155
2156 return lgdt3306a_i2c_gate_ctrl(&state->frontend, 0);
2157 }
2158
lgdt3306a_probe(struct i2c_client * client,const struct i2c_device_id * id)2159 static int lgdt3306a_probe(struct i2c_client *client,
2160 const struct i2c_device_id *id)
2161 {
2162 struct lgdt3306a_config *config;
2163 struct lgdt3306a_state *state;
2164 struct dvb_frontend *fe;
2165 int ret;
2166
2167 config = kzalloc(sizeof(struct lgdt3306a_config), GFP_KERNEL);
2168 if (config == NULL) {
2169 ret = -ENOMEM;
2170 goto fail;
2171 }
2172
2173 memcpy(config, client->dev.platform_data,
2174 sizeof(struct lgdt3306a_config));
2175
2176 config->i2c_addr = client->addr;
2177 fe = dvb_attach(lgdt3306a_attach, config, client->adapter);
2178 if (fe == NULL) {
2179 ret = -ENODEV;
2180 goto err_fe;
2181 }
2182
2183 i2c_set_clientdata(client, fe->demodulator_priv);
2184 state = fe->demodulator_priv;
2185
2186 /* create mux i2c adapter for tuner */
2187 state->muxc = i2c_mux_alloc(client->adapter, &client->dev,
2188 1, 0, I2C_MUX_LOCKED,
2189 lgdt3306a_select, lgdt3306a_deselect);
2190 if (!state->muxc) {
2191 ret = -ENOMEM;
2192 goto err_kfree;
2193 }
2194 state->muxc->priv = client;
2195 ret = i2c_mux_add_adapter(state->muxc, 0, 0, 0);
2196 if (ret)
2197 goto err_kfree;
2198
2199 /* create dvb_frontend */
2200 fe->ops.i2c_gate_ctrl = NULL;
2201 *config->i2c_adapter = state->muxc->adapter[0];
2202 *config->fe = fe;
2203
2204 return 0;
2205
2206 err_kfree:
2207 kfree(state);
2208 err_fe:
2209 kfree(config);
2210 fail:
2211 dev_dbg(&client->dev, "failed=%d\n", ret);
2212 return ret;
2213 }
2214
lgdt3306a_remove(struct i2c_client * client)2215 static int lgdt3306a_remove(struct i2c_client *client)
2216 {
2217 struct lgdt3306a_state *state = i2c_get_clientdata(client);
2218
2219 i2c_mux_del_adapters(state->muxc);
2220
2221 state->frontend.ops.release = NULL;
2222 state->frontend.demodulator_priv = NULL;
2223
2224 kfree(state->cfg);
2225 kfree(state);
2226
2227 return 0;
2228 }
2229
2230 static const struct i2c_device_id lgdt3306a_id_table[] = {
2231 {"lgdt3306a", 0},
2232 {}
2233 };
2234 MODULE_DEVICE_TABLE(i2c, lgdt3306a_id_table);
2235
2236 static struct i2c_driver lgdt3306a_driver = {
2237 .driver = {
2238 .name = "lgdt3306a",
2239 .suppress_bind_attrs = true,
2240 },
2241 .probe = lgdt3306a_probe,
2242 .remove = lgdt3306a_remove,
2243 .id_table = lgdt3306a_id_table,
2244 };
2245
2246 module_i2c_driver(lgdt3306a_driver);
2247
2248 MODULE_DESCRIPTION("LG Electronics LGDT3306A ATSC/QAM-B Demodulator Driver");
2249 MODULE_AUTHOR("Fred Richter <frichter@hauppauge.com>");
2250 MODULE_LICENSE("GPL");
2251 MODULE_VERSION("0.2");
2252