1 /*
2 * Driver for the MaxLinear MxL5xx family of tuners/demods
3 *
4 * Copyright (C) 2014-2015 Ralph Metzler <rjkm@metzlerbros.de>
5 * Marcus Metzler <mocm@metzlerbros.de>
6 * developed for Digital Devices GmbH
7 *
8 * based on code:
9 * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved
10 * which was released under GPL V2
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2, as published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 */
22
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/firmware.h>
29 #include <linux/i2c.h>
30 #include <linux/version.h>
31 #include <linux/mutex.h>
32 #include <linux/vmalloc.h>
33 #include <asm/div64.h>
34 #include <asm/unaligned.h>
35
36 #include "dvb_frontend.h"
37 #include "mxl5xx.h"
38 #include "mxl5xx_regs.h"
39 #include "mxl5xx_defs.h"
40
41 #define BYTE0(v) ((v >> 0) & 0xff)
42 #define BYTE1(v) ((v >> 8) & 0xff)
43 #define BYTE2(v) ((v >> 16) & 0xff)
44 #define BYTE3(v) ((v >> 24) & 0xff)
45
46 LIST_HEAD(mxllist);
47
48 struct mxl_base {
49 struct list_head mxllist;
50 struct list_head mxls;
51
52 u8 adr;
53 struct i2c_adapter *i2c;
54
55 u32 count;
56 u32 type;
57 u32 sku_type;
58 u32 chipversion;
59 u32 clock;
60 u32 fwversion;
61
62 u8 *ts_map;
63 u8 can_clkout;
64 u8 chan_bond;
65 u8 demod_num;
66 u8 tuner_num;
67
68 unsigned long next_tune;
69
70 struct mutex i2c_lock;
71 struct mutex status_lock;
72 struct mutex tune_lock;
73
74 u8 buf[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
75
76 u32 cmd_size;
77 u8 cmd_data[MAX_CMD_DATA];
78 };
79
80 struct mxl {
81 struct list_head mxl;
82
83 struct mxl_base *base;
84 struct dvb_frontend fe;
85 struct device *i2cdev;
86 u32 demod;
87 u32 tuner;
88 u32 tuner_in_use;
89 u8 xbar[3];
90
91 unsigned long tune_time;
92 };
93
convert_endian(u8 flag,u32 size,u8 * d)94 static void convert_endian(u8 flag, u32 size, u8 *d)
95 {
96 u32 i;
97
98 if (!flag)
99 return;
100 for (i = 0; i < (size & ~3); i += 4) {
101 d[i + 0] ^= d[i + 3];
102 d[i + 3] ^= d[i + 0];
103 d[i + 0] ^= d[i + 3];
104
105 d[i + 1] ^= d[i + 2];
106 d[i + 2] ^= d[i + 1];
107 d[i + 1] ^= d[i + 2];
108 }
109
110 switch (size & 3) {
111 case 0:
112 case 1:
113 /* do nothing */
114 break;
115 case 2:
116 d[i + 0] ^= d[i + 1];
117 d[i + 1] ^= d[i + 0];
118 d[i + 0] ^= d[i + 1];
119 break;
120
121 case 3:
122 d[i + 0] ^= d[i + 2];
123 d[i + 2] ^= d[i + 0];
124 d[i + 0] ^= d[i + 2];
125 break;
126 }
127
128 }
129
i2c_write(struct i2c_adapter * adap,u8 adr,u8 * data,u32 len)130 static int i2c_write(struct i2c_adapter *adap, u8 adr,
131 u8 *data, u32 len)
132 {
133 struct i2c_msg msg = {.addr = adr, .flags = 0,
134 .buf = data, .len = len};
135
136 return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1;
137 }
138
i2c_read(struct i2c_adapter * adap,u8 adr,u8 * data,u32 len)139 static int i2c_read(struct i2c_adapter *adap, u8 adr,
140 u8 *data, u32 len)
141 {
142 struct i2c_msg msg = {.addr = adr, .flags = I2C_M_RD,
143 .buf = data, .len = len};
144
145 return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1;
146 }
147
i2cread(struct mxl * state,u8 * data,int len)148 static int i2cread(struct mxl *state, u8 *data, int len)
149 {
150 return i2c_read(state->base->i2c, state->base->adr, data, len);
151 }
152
i2cwrite(struct mxl * state,u8 * data,int len)153 static int i2cwrite(struct mxl *state, u8 *data, int len)
154 {
155 return i2c_write(state->base->i2c, state->base->adr, data, len);
156 }
157
read_register_unlocked(struct mxl * state,u32 reg,u32 * val)158 static int read_register_unlocked(struct mxl *state, u32 reg, u32 *val)
159 {
160 int stat;
161 u8 data[MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE] = {
162 MXL_HYDRA_PLID_REG_READ, 0x04,
163 GET_BYTE(reg, 0), GET_BYTE(reg, 1),
164 GET_BYTE(reg, 2), GET_BYTE(reg, 3),
165 };
166
167 stat = i2cwrite(state, data,
168 MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE);
169 if (stat)
170 dev_err(state->i2cdev, "i2c read error 1\n");
171 if (!stat)
172 stat = i2cread(state, (u8 *) val,
173 MXL_HYDRA_REG_SIZE_IN_BYTES);
174 le32_to_cpus(val);
175 if (stat)
176 dev_err(state->i2cdev, "i2c read error 2\n");
177 return stat;
178 }
179
180 #define DMA_I2C_INTERRUPT_ADDR 0x8000011C
181 #define DMA_INTR_PROT_WR_CMP 0x08
182
send_command(struct mxl * state,u32 size,u8 * buf)183 static int send_command(struct mxl *state, u32 size, u8 *buf)
184 {
185 int stat;
186 u32 val, count = 10;
187
188 mutex_lock(&state->base->i2c_lock);
189 if (state->base->fwversion > 0x02010109) {
190 read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR, &val);
191 if (DMA_INTR_PROT_WR_CMP & val)
192 dev_info(state->i2cdev, "%s busy\n", __func__);
193 while ((DMA_INTR_PROT_WR_CMP & val) && --count) {
194 mutex_unlock(&state->base->i2c_lock);
195 usleep_range(1000, 2000);
196 mutex_lock(&state->base->i2c_lock);
197 read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR,
198 &val);
199 }
200 if (!count) {
201 dev_info(state->i2cdev, "%s busy\n", __func__);
202 mutex_unlock(&state->base->i2c_lock);
203 return -EBUSY;
204 }
205 }
206 stat = i2cwrite(state, buf, size);
207 mutex_unlock(&state->base->i2c_lock);
208 return stat;
209 }
210
write_register(struct mxl * state,u32 reg,u32 val)211 static int write_register(struct mxl *state, u32 reg, u32 val)
212 {
213 int stat;
214 u8 data[MXL_HYDRA_REG_WRITE_LEN] = {
215 MXL_HYDRA_PLID_REG_WRITE, 0x08,
216 BYTE0(reg), BYTE1(reg), BYTE2(reg), BYTE3(reg),
217 BYTE0(val), BYTE1(val), BYTE2(val), BYTE3(val),
218 };
219 mutex_lock(&state->base->i2c_lock);
220 stat = i2cwrite(state, data, sizeof(data));
221 mutex_unlock(&state->base->i2c_lock);
222 if (stat)
223 dev_err(state->i2cdev, "i2c write error\n");
224 return stat;
225 }
226
write_firmware_block(struct mxl * state,u32 reg,u32 size,u8 * reg_data_ptr)227 static int write_firmware_block(struct mxl *state,
228 u32 reg, u32 size, u8 *reg_data_ptr)
229 {
230 int stat;
231 u8 *buf = state->base->buf;
232
233 mutex_lock(&state->base->i2c_lock);
234 buf[0] = MXL_HYDRA_PLID_REG_WRITE;
235 buf[1] = size + 4;
236 buf[2] = GET_BYTE(reg, 0);
237 buf[3] = GET_BYTE(reg, 1);
238 buf[4] = GET_BYTE(reg, 2);
239 buf[5] = GET_BYTE(reg, 3);
240 memcpy(&buf[6], reg_data_ptr, size);
241 stat = i2cwrite(state, buf,
242 MXL_HYDRA_I2C_HDR_SIZE +
243 MXL_HYDRA_REG_SIZE_IN_BYTES + size);
244 mutex_unlock(&state->base->i2c_lock);
245 if (stat)
246 dev_err(state->i2cdev, "fw block write failed\n");
247 return stat;
248 }
249
read_register(struct mxl * state,u32 reg,u32 * val)250 static int read_register(struct mxl *state, u32 reg, u32 *val)
251 {
252 int stat;
253 u8 data[MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE] = {
254 MXL_HYDRA_PLID_REG_READ, 0x04,
255 GET_BYTE(reg, 0), GET_BYTE(reg, 1),
256 GET_BYTE(reg, 2), GET_BYTE(reg, 3),
257 };
258
259 mutex_lock(&state->base->i2c_lock);
260 stat = i2cwrite(state, data,
261 MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE);
262 if (stat)
263 dev_err(state->i2cdev, "i2c read error 1\n");
264 if (!stat)
265 stat = i2cread(state, (u8 *) val,
266 MXL_HYDRA_REG_SIZE_IN_BYTES);
267 mutex_unlock(&state->base->i2c_lock);
268 le32_to_cpus(val);
269 if (stat)
270 dev_err(state->i2cdev, "i2c read error 2\n");
271 return stat;
272 }
273
read_register_block(struct mxl * state,u32 reg,u32 size,u8 * data)274 static int read_register_block(struct mxl *state, u32 reg, u32 size, u8 *data)
275 {
276 int stat;
277 u8 *buf = state->base->buf;
278
279 mutex_lock(&state->base->i2c_lock);
280
281 buf[0] = MXL_HYDRA_PLID_REG_READ;
282 buf[1] = size + 4;
283 buf[2] = GET_BYTE(reg, 0);
284 buf[3] = GET_BYTE(reg, 1);
285 buf[4] = GET_BYTE(reg, 2);
286 buf[5] = GET_BYTE(reg, 3);
287 stat = i2cwrite(state, buf,
288 MXL_HYDRA_I2C_HDR_SIZE + MXL_HYDRA_REG_SIZE_IN_BYTES);
289 if (!stat) {
290 stat = i2cread(state, data, size);
291 convert_endian(MXL_ENABLE_BIG_ENDIAN, size, data);
292 }
293 mutex_unlock(&state->base->i2c_lock);
294 return stat;
295 }
296
read_by_mnemonic(struct mxl * state,u32 reg,u8 lsbloc,u8 numofbits,u32 * val)297 static int read_by_mnemonic(struct mxl *state,
298 u32 reg, u8 lsbloc, u8 numofbits, u32 *val)
299 {
300 u32 data = 0, mask = 0;
301 int stat;
302
303 stat = read_register(state, reg, &data);
304 if (stat)
305 return stat;
306 mask = MXL_GET_REG_MASK_32(lsbloc, numofbits);
307 data &= mask;
308 data >>= lsbloc;
309 *val = data;
310 return 0;
311 }
312
313
update_by_mnemonic(struct mxl * state,u32 reg,u8 lsbloc,u8 numofbits,u32 val)314 static int update_by_mnemonic(struct mxl *state,
315 u32 reg, u8 lsbloc, u8 numofbits, u32 val)
316 {
317 u32 data, mask;
318 int stat;
319
320 stat = read_register(state, reg, &data);
321 if (stat)
322 return stat;
323 mask = MXL_GET_REG_MASK_32(lsbloc, numofbits);
324 data = (data & ~mask) | ((val << lsbloc) & mask);
325 stat = write_register(state, reg, data);
326 return stat;
327 }
328
firmware_is_alive(struct mxl * state)329 static int firmware_is_alive(struct mxl *state)
330 {
331 u32 hb0, hb1;
332
333 if (read_register(state, HYDRA_HEAR_BEAT, &hb0))
334 return 0;
335 msleep(20);
336 if (read_register(state, HYDRA_HEAR_BEAT, &hb1))
337 return 0;
338 if (hb1 == hb0)
339 return 0;
340 return 1;
341 }
342
init(struct dvb_frontend * fe)343 static int init(struct dvb_frontend *fe)
344 {
345 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
346
347 /* init fe stats */
348 p->strength.len = 1;
349 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
350 p->cnr.len = 1;
351 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
352 p->pre_bit_error.len = 1;
353 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
354 p->pre_bit_count.len = 1;
355 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
356 p->post_bit_error.len = 1;
357 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
358 p->post_bit_count.len = 1;
359 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
360
361 return 0;
362 }
363
release(struct dvb_frontend * fe)364 static void release(struct dvb_frontend *fe)
365 {
366 struct mxl *state = fe->demodulator_priv;
367
368 list_del(&state->mxl);
369 /* Release one frontend, two more shall take its place! */
370 state->base->count--;
371 if (state->base->count == 0) {
372 list_del(&state->base->mxllist);
373 kfree(state->base);
374 }
375 kfree(state);
376 }
377
get_algo(struct dvb_frontend * fe)378 static int get_algo(struct dvb_frontend *fe)
379 {
380 return DVBFE_ALGO_HW;
381 }
382
cfg_demod_abort_tune(struct mxl * state)383 static int cfg_demod_abort_tune(struct mxl *state)
384 {
385 struct MXL_HYDRA_DEMOD_ABORT_TUNE_T abort_tune_cmd;
386 u8 cmd_size = sizeof(abort_tune_cmd);
387 u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
388
389 abort_tune_cmd.demod_id = state->demod;
390 BUILD_HYDRA_CMD(MXL_HYDRA_ABORT_TUNE_CMD, MXL_CMD_WRITE,
391 cmd_size, &abort_tune_cmd, cmd_buff);
392 return send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
393 &cmd_buff[0]);
394 }
395
send_master_cmd(struct dvb_frontend * fe,struct dvb_diseqc_master_cmd * cmd)396 static int send_master_cmd(struct dvb_frontend *fe,
397 struct dvb_diseqc_master_cmd *cmd)
398 {
399 /*struct mxl *state = fe->demodulator_priv;*/
400
401 return 0; /*CfgDemodAbortTune(state);*/
402 }
403
set_parameters(struct dvb_frontend * fe)404 static int set_parameters(struct dvb_frontend *fe)
405 {
406 struct mxl *state = fe->demodulator_priv;
407 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
408 struct MXL_HYDRA_DEMOD_PARAM_T demod_chan_cfg;
409 u8 cmd_size = sizeof(demod_chan_cfg);
410 u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
411 u32 srange = 10;
412 int stat;
413
414 if (p->frequency < 950000 || p->frequency > 2150000)
415 return -EINVAL;
416 if (p->symbol_rate < 1000000 || p->symbol_rate > 45000000)
417 return -EINVAL;
418
419 /* CfgDemodAbortTune(state); */
420
421 switch (p->delivery_system) {
422 case SYS_DSS:
423 demod_chan_cfg.standard = MXL_HYDRA_DSS;
424 demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_AUTO;
425 break;
426 case SYS_DVBS:
427 srange = p->symbol_rate / 1000000;
428 if (srange > 10)
429 srange = 10;
430 demod_chan_cfg.standard = MXL_HYDRA_DVBS;
431 demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_0_35;
432 demod_chan_cfg.modulation_scheme = MXL_HYDRA_MOD_QPSK;
433 demod_chan_cfg.pilots = MXL_HYDRA_PILOTS_OFF;
434 break;
435 case SYS_DVBS2:
436 demod_chan_cfg.standard = MXL_HYDRA_DVBS2;
437 demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_AUTO;
438 demod_chan_cfg.modulation_scheme = MXL_HYDRA_MOD_AUTO;
439 demod_chan_cfg.pilots = MXL_HYDRA_PILOTS_AUTO;
440 /* cfg_scrambler(state); */
441 break;
442 default:
443 return -EINVAL;
444 }
445 demod_chan_cfg.tuner_index = state->tuner;
446 demod_chan_cfg.demod_index = state->demod;
447 demod_chan_cfg.frequency_in_hz = p->frequency * 1000;
448 demod_chan_cfg.symbol_rate_in_hz = p->symbol_rate;
449 demod_chan_cfg.max_carrier_offset_in_mhz = srange;
450 demod_chan_cfg.spectrum_inversion = MXL_HYDRA_SPECTRUM_AUTO;
451 demod_chan_cfg.fec_code_rate = MXL_HYDRA_FEC_AUTO;
452
453 mutex_lock(&state->base->tune_lock);
454 if (time_after(jiffies + msecs_to_jiffies(200),
455 state->base->next_tune))
456 while (time_before(jiffies, state->base->next_tune))
457 usleep_range(10000, 11000);
458 state->base->next_tune = jiffies + msecs_to_jiffies(100);
459 state->tuner_in_use = state->tuner;
460 BUILD_HYDRA_CMD(MXL_HYDRA_DEMOD_SET_PARAM_CMD, MXL_CMD_WRITE,
461 cmd_size, &demod_chan_cfg, cmd_buff);
462 stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
463 &cmd_buff[0]);
464 mutex_unlock(&state->base->tune_lock);
465 return stat;
466 }
467
468 static int enable_tuner(struct mxl *state, u32 tuner, u32 enable);
469
sleep(struct dvb_frontend * fe)470 static int sleep(struct dvb_frontend *fe)
471 {
472 struct mxl *state = fe->demodulator_priv;
473 struct mxl *p;
474
475 cfg_demod_abort_tune(state);
476 if (state->tuner_in_use != 0xffffffff) {
477 mutex_lock(&state->base->tune_lock);
478 state->tuner_in_use = 0xffffffff;
479 list_for_each_entry(p, &state->base->mxls, mxl) {
480 if (p->tuner_in_use == state->tuner)
481 break;
482 }
483 if (&p->mxl == &state->base->mxls)
484 enable_tuner(state, state->tuner, 0);
485 mutex_unlock(&state->base->tune_lock);
486 }
487 return 0;
488 }
489
read_snr(struct dvb_frontend * fe)490 static int read_snr(struct dvb_frontend *fe)
491 {
492 struct mxl *state = fe->demodulator_priv;
493 int stat;
494 u32 reg_data = 0;
495 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
496
497 mutex_lock(&state->base->status_lock);
498 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
499 stat = read_register(state, (HYDRA_DMD_SNR_ADDR_OFFSET +
500 HYDRA_DMD_STATUS_OFFSET(state->demod)),
501 ®_data);
502 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
503 mutex_unlock(&state->base->status_lock);
504
505 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
506 p->cnr.stat[0].svalue = (s16)reg_data * 10;
507
508 return stat;
509 }
510
read_ber(struct dvb_frontend * fe)511 static int read_ber(struct dvb_frontend *fe)
512 {
513 struct mxl *state = fe->demodulator_priv;
514 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
515 u32 reg[8];
516
517 mutex_lock(&state->base->status_lock);
518 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
519 read_register_block(state,
520 (HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET +
521 HYDRA_DMD_STATUS_OFFSET(state->demod)),
522 (4 * sizeof(u32)),
523 (u8 *) ®[0]);
524 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
525
526 switch (p->delivery_system) {
527 case SYS_DSS:
528 case SYS_DVBS:
529 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
530 p->pre_bit_error.stat[0].uvalue = reg[2];
531 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
532 p->pre_bit_count.stat[0].uvalue = reg[3];
533 break;
534 default:
535 break;
536 }
537
538 read_register_block(state,
539 (HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET +
540 HYDRA_DMD_STATUS_OFFSET(state->demod)),
541 (7 * sizeof(u32)),
542 (u8 *) ®[0]);
543
544 switch (p->delivery_system) {
545 case SYS_DSS:
546 case SYS_DVBS:
547 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
548 p->post_bit_error.stat[0].uvalue = reg[5];
549 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
550 p->post_bit_count.stat[0].uvalue = reg[6];
551 break;
552 case SYS_DVBS2:
553 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
554 p->post_bit_error.stat[0].uvalue = reg[1];
555 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
556 p->post_bit_count.stat[0].uvalue = reg[2];
557 break;
558 default:
559 break;
560 }
561
562 mutex_unlock(&state->base->status_lock);
563
564 return 0;
565 }
566
read_signal_strength(struct dvb_frontend * fe)567 static int read_signal_strength(struct dvb_frontend *fe)
568 {
569 struct mxl *state = fe->demodulator_priv;
570 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
571 int stat;
572 u32 reg_data = 0;
573
574 mutex_lock(&state->base->status_lock);
575 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
576 stat = read_register(state, (HYDRA_DMD_STATUS_INPUT_POWER_ADDR +
577 HYDRA_DMD_STATUS_OFFSET(state->demod)),
578 ®_data);
579 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
580 mutex_unlock(&state->base->status_lock);
581
582 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
583 p->strength.stat[0].svalue = (s16) reg_data * 10; /* fix scale */
584
585 return stat;
586 }
587
read_status(struct dvb_frontend * fe,enum fe_status * status)588 static int read_status(struct dvb_frontend *fe, enum fe_status *status)
589 {
590 struct mxl *state = fe->demodulator_priv;
591 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
592 u32 reg_data = 0;
593
594 mutex_lock(&state->base->status_lock);
595 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
596 read_register(state, (HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET +
597 HYDRA_DMD_STATUS_OFFSET(state->demod)),
598 ®_data);
599 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
600 mutex_unlock(&state->base->status_lock);
601
602 *status = (reg_data == 1) ? 0x1f : 0;
603
604 /* signal statistics */
605
606 /* signal strength is always available */
607 read_signal_strength(fe);
608
609 if (*status & FE_HAS_CARRIER)
610 read_snr(fe);
611 else
612 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
613
614 if (*status & FE_HAS_SYNC)
615 read_ber(fe);
616 else {
617 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
618 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
619 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
620 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
621 }
622
623 return 0;
624 }
625
tune(struct dvb_frontend * fe,bool re_tune,unsigned int mode_flags,unsigned int * delay,enum fe_status * status)626 static int tune(struct dvb_frontend *fe, bool re_tune,
627 unsigned int mode_flags,
628 unsigned int *delay, enum fe_status *status)
629 {
630 struct mxl *state = fe->demodulator_priv;
631 int r = 0;
632
633 *delay = HZ / 2;
634 if (re_tune) {
635 r = set_parameters(fe);
636 if (r)
637 return r;
638 state->tune_time = jiffies;
639 return 0;
640 }
641 if (*status & FE_HAS_LOCK)
642 return 0;
643
644 r = read_status(fe, status);
645 if (r)
646 return r;
647
648 return 0;
649 }
650
conv_fec(enum MXL_HYDRA_FEC_E fec)651 static enum fe_code_rate conv_fec(enum MXL_HYDRA_FEC_E fec)
652 {
653 enum fe_code_rate fec2fec[11] = {
654 FEC_NONE, FEC_1_2, FEC_3_5, FEC_2_3,
655 FEC_3_4, FEC_4_5, FEC_5_6, FEC_6_7,
656 FEC_7_8, FEC_8_9, FEC_9_10
657 };
658
659 if (fec > MXL_HYDRA_FEC_9_10)
660 return FEC_NONE;
661 return fec2fec[fec];
662 }
663
get_frontend(struct dvb_frontend * fe,struct dtv_frontend_properties * p)664 static int get_frontend(struct dvb_frontend *fe,
665 struct dtv_frontend_properties *p)
666 {
667 struct mxl *state = fe->demodulator_priv;
668 u32 reg_data[MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE];
669 u32 freq;
670
671 mutex_lock(&state->base->status_lock);
672 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
673 read_register_block(state,
674 (HYDRA_DMD_STANDARD_ADDR_OFFSET +
675 HYDRA_DMD_STATUS_OFFSET(state->demod)),
676 (MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE * 4), /* 25 * 4 bytes */
677 (u8 *) ®_data[0]);
678 /* read demod channel parameters */
679 read_register_block(state,
680 (HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR +
681 HYDRA_DMD_STATUS_OFFSET(state->demod)),
682 (4), /* 4 bytes */
683 (u8 *) &freq);
684 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
685 mutex_unlock(&state->base->status_lock);
686
687 dev_dbg(state->i2cdev, "freq=%u delsys=%u srate=%u\n",
688 freq * 1000, reg_data[DMD_STANDARD_ADDR],
689 reg_data[DMD_SYMBOL_RATE_ADDR]);
690 p->symbol_rate = reg_data[DMD_SYMBOL_RATE_ADDR];
691 p->frequency = freq;
692 /*
693 * p->delivery_system =
694 * (MXL_HYDRA_BCAST_STD_E) regData[DMD_STANDARD_ADDR];
695 * p->inversion =
696 * (MXL_HYDRA_SPECTRUM_E) regData[DMD_SPECTRUM_INVERSION_ADDR];
697 * freqSearchRangeKHz =
698 * (regData[DMD_FREQ_SEARCH_RANGE_IN_KHZ_ADDR]);
699 */
700
701 p->fec_inner = conv_fec(reg_data[DMD_FEC_CODE_RATE_ADDR]);
702 switch (p->delivery_system) {
703 case SYS_DSS:
704 break;
705 case SYS_DVBS2:
706 switch ((enum MXL_HYDRA_PILOTS_E)
707 reg_data[DMD_DVBS2_PILOT_ON_OFF_ADDR]) {
708 case MXL_HYDRA_PILOTS_OFF:
709 p->pilot = PILOT_OFF;
710 break;
711 case MXL_HYDRA_PILOTS_ON:
712 p->pilot = PILOT_ON;
713 break;
714 default:
715 break;
716 }
717 case SYS_DVBS:
718 switch ((enum MXL_HYDRA_MODULATION_E)
719 reg_data[DMD_MODULATION_SCHEME_ADDR]) {
720 case MXL_HYDRA_MOD_QPSK:
721 p->modulation = QPSK;
722 break;
723 case MXL_HYDRA_MOD_8PSK:
724 p->modulation = PSK_8;
725 break;
726 default:
727 break;
728 }
729 switch ((enum MXL_HYDRA_ROLLOFF_E)
730 reg_data[DMD_SPECTRUM_ROLL_OFF_ADDR]) {
731 case MXL_HYDRA_ROLLOFF_0_20:
732 p->rolloff = ROLLOFF_20;
733 break;
734 case MXL_HYDRA_ROLLOFF_0_35:
735 p->rolloff = ROLLOFF_35;
736 break;
737 case MXL_HYDRA_ROLLOFF_0_25:
738 p->rolloff = ROLLOFF_25;
739 break;
740 default:
741 break;
742 }
743 break;
744 default:
745 return -EINVAL;
746 }
747 return 0;
748 }
749
set_input(struct dvb_frontend * fe,int input)750 static int set_input(struct dvb_frontend *fe, int input)
751 {
752 struct mxl *state = fe->demodulator_priv;
753
754 state->tuner = input;
755 return 0;
756 }
757
758 static struct dvb_frontend_ops mxl_ops = {
759 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
760 .info = {
761 .name = "MaxLinear MxL5xx DVB-S/S2 tuner-demodulator",
762 .frequency_min = 300000,
763 .frequency_max = 2350000,
764 .frequency_stepsize = 0,
765 .frequency_tolerance = 0,
766 .symbol_rate_min = 1000000,
767 .symbol_rate_max = 45000000,
768 .caps = FE_CAN_INVERSION_AUTO |
769 FE_CAN_FEC_AUTO |
770 FE_CAN_QPSK |
771 FE_CAN_2G_MODULATION
772 },
773 .init = init,
774 .release = release,
775 .get_frontend_algo = get_algo,
776 .tune = tune,
777 .read_status = read_status,
778 .sleep = sleep,
779 .get_frontend = get_frontend,
780 .diseqc_send_master_cmd = send_master_cmd,
781 };
782
match_base(struct i2c_adapter * i2c,u8 adr)783 static struct mxl_base *match_base(struct i2c_adapter *i2c, u8 adr)
784 {
785 struct mxl_base *p;
786
787 list_for_each_entry(p, &mxllist, mxllist)
788 if (p->i2c == i2c && p->adr == adr)
789 return p;
790 return NULL;
791 }
792
cfg_dev_xtal(struct mxl * state,u32 freq,u32 cap,u32 enable)793 static void cfg_dev_xtal(struct mxl *state, u32 freq, u32 cap, u32 enable)
794 {
795 if (state->base->can_clkout || !enable)
796 update_by_mnemonic(state, 0x90200054, 23, 1, enable);
797
798 if (freq == 24000000)
799 write_register(state, HYDRA_CRYSTAL_SETTING, 0);
800 else
801 write_register(state, HYDRA_CRYSTAL_SETTING, 1);
802
803 write_register(state, HYDRA_CRYSTAL_CAP, cap);
804 }
805
get_big_endian(u8 num_of_bits,const u8 buf[])806 static u32 get_big_endian(u8 num_of_bits, const u8 buf[])
807 {
808 u32 ret_value = 0;
809
810 switch (num_of_bits) {
811 case 24:
812 ret_value = (((u32) buf[0]) << 16) |
813 (((u32) buf[1]) << 8) | buf[2];
814 break;
815 case 32:
816 ret_value = (((u32) buf[0]) << 24) |
817 (((u32) buf[1]) << 16) |
818 (((u32) buf[2]) << 8) | buf[3];
819 break;
820 default:
821 break;
822 }
823
824 return ret_value;
825 }
826
write_fw_segment(struct mxl * state,u32 mem_addr,u32 total_size,u8 * data_ptr)827 static int write_fw_segment(struct mxl *state,
828 u32 mem_addr, u32 total_size, u8 *data_ptr)
829 {
830 int status;
831 u32 data_count = 0;
832 u32 size = 0;
833 u32 orig_size = 0;
834 u8 *w_buf_ptr = NULL;
835 u32 block_size = ((MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH -
836 (MXL_HYDRA_I2C_HDR_SIZE +
837 MXL_HYDRA_REG_SIZE_IN_BYTES)) / 4) * 4;
838 u8 w_msg_buffer[MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH -
839 (MXL_HYDRA_I2C_HDR_SIZE + MXL_HYDRA_REG_SIZE_IN_BYTES)];
840
841 do {
842 size = orig_size = (((u32)(data_count + block_size)) > total_size) ?
843 (total_size - data_count) : block_size;
844
845 if (orig_size & 3)
846 size = (orig_size + 4) & ~3;
847 w_buf_ptr = &w_msg_buffer[0];
848 memset((void *) w_buf_ptr, 0, size);
849 memcpy((void *) w_buf_ptr, (void *) data_ptr, orig_size);
850 convert_endian(1, size, w_buf_ptr);
851 status = write_firmware_block(state, mem_addr, size, w_buf_ptr);
852 if (status)
853 return status;
854 data_count += size;
855 mem_addr += size;
856 data_ptr += size;
857 } while (data_count < total_size);
858
859 return status;
860 }
861
do_firmware_download(struct mxl * state,u8 * mbin_buffer_ptr,u32 mbin_buffer_size)862 static int do_firmware_download(struct mxl *state, u8 *mbin_buffer_ptr,
863 u32 mbin_buffer_size)
864
865 {
866 int status;
867 u32 index = 0;
868 u32 seg_length = 0;
869 u32 seg_address = 0;
870 struct MBIN_FILE_T *mbin_ptr = (struct MBIN_FILE_T *)mbin_buffer_ptr;
871 struct MBIN_SEGMENT_T *segment_ptr;
872 enum MXL_BOOL_E xcpu_fw_flag = MXL_FALSE;
873
874 if (mbin_ptr->header.id != MBIN_FILE_HEADER_ID) {
875 dev_err(state->i2cdev, "%s: Invalid file header ID (%c)\n",
876 __func__, mbin_ptr->header.id);
877 return -EINVAL;
878 }
879 status = write_register(state, FW_DL_SIGN_ADDR, 0);
880 if (status)
881 return status;
882 segment_ptr = (struct MBIN_SEGMENT_T *) (&mbin_ptr->data[0]);
883 for (index = 0; index < mbin_ptr->header.num_segments; index++) {
884 if (segment_ptr->header.id != MBIN_SEGMENT_HEADER_ID) {
885 dev_err(state->i2cdev, "%s: Invalid segment header ID (%c)\n",
886 __func__, segment_ptr->header.id);
887 return -EINVAL;
888 }
889 seg_length = get_big_endian(24,
890 &(segment_ptr->header.len24[0]));
891 seg_address = get_big_endian(32,
892 &(segment_ptr->header.address[0]));
893
894 if (state->base->type == MXL_HYDRA_DEVICE_568) {
895 if ((((seg_address & 0x90760000) == 0x90760000) ||
896 ((seg_address & 0x90740000) == 0x90740000)) &&
897 (xcpu_fw_flag == MXL_FALSE)) {
898 update_by_mnemonic(state, 0x8003003C, 0, 1, 1);
899 msleep(200);
900 write_register(state, 0x90720000, 0);
901 usleep_range(10000, 11000);
902 xcpu_fw_flag = MXL_TRUE;
903 }
904 status = write_fw_segment(state, seg_address,
905 seg_length,
906 (u8 *) segment_ptr->data);
907 } else {
908 if (((seg_address & 0x90760000) != 0x90760000) &&
909 ((seg_address & 0x90740000) != 0x90740000))
910 status = write_fw_segment(state, seg_address,
911 seg_length, (u8 *) segment_ptr->data);
912 }
913 if (status)
914 return status;
915 segment_ptr = (struct MBIN_SEGMENT_T *)
916 &(segment_ptr->data[((seg_length + 3) / 4) * 4]);
917 }
918 return status;
919 }
920
check_fw(struct mxl * state,u8 * mbin,u32 mbin_len)921 static int check_fw(struct mxl *state, u8 *mbin, u32 mbin_len)
922 {
923 struct MBIN_FILE_HEADER_T *fh = (struct MBIN_FILE_HEADER_T *) mbin;
924 u32 flen = (fh->image_size24[0] << 16) |
925 (fh->image_size24[1] << 8) | fh->image_size24[2];
926 u8 *fw, cs = 0;
927 u32 i;
928
929 if (fh->id != 'M' || fh->fmt_version != '1' || flen > 0x3FFF0) {
930 dev_info(state->i2cdev, "Invalid FW Header\n");
931 return -1;
932 }
933 fw = mbin + sizeof(struct MBIN_FILE_HEADER_T);
934 for (i = 0; i < flen; i += 1)
935 cs += fw[i];
936 if (cs != fh->image_checksum) {
937 dev_info(state->i2cdev, "Invalid FW Checksum\n");
938 return -1;
939 }
940 return 0;
941 }
942
firmware_download(struct mxl * state,u8 * mbin,u32 mbin_len)943 static int firmware_download(struct mxl *state, u8 *mbin, u32 mbin_len)
944 {
945 int status;
946 u32 reg_data = 0;
947 struct MXL_HYDRA_SKU_COMMAND_T dev_sku_cfg;
948 u8 cmd_size = sizeof(struct MXL_HYDRA_SKU_COMMAND_T);
949 u8 cmd_buff[sizeof(struct MXL_HYDRA_SKU_COMMAND_T) + 6];
950
951 if (check_fw(state, mbin, mbin_len))
952 return -1;
953
954 /* put CPU into reset */
955 status = update_by_mnemonic(state, 0x8003003C, 0, 1, 0);
956 if (status)
957 return status;
958 usleep_range(1000, 2000);
959
960 /* Reset TX FIFO's, BBAND, XBAR */
961 status = write_register(state, HYDRA_RESET_TRANSPORT_FIFO_REG,
962 HYDRA_RESET_TRANSPORT_FIFO_DATA);
963 if (status)
964 return status;
965 status = write_register(state, HYDRA_RESET_BBAND_REG,
966 HYDRA_RESET_BBAND_DATA);
967 if (status)
968 return status;
969 status = write_register(state, HYDRA_RESET_XBAR_REG,
970 HYDRA_RESET_XBAR_DATA);
971 if (status)
972 return status;
973
974 /* Disable clock to Baseband, Wideband, SerDes,
975 * Alias ext & Transport modules
976 */
977 status = write_register(state, HYDRA_MODULES_CLK_2_REG,
978 HYDRA_DISABLE_CLK_2);
979 if (status)
980 return status;
981 /* Clear Software & Host interrupt status - (Clear on read) */
982 status = read_register(state, HYDRA_PRCM_ROOT_CLK_REG, ®_data);
983 if (status)
984 return status;
985 status = do_firmware_download(state, mbin, mbin_len);
986 if (status)
987 return status;
988
989 if (state->base->type == MXL_HYDRA_DEVICE_568) {
990 usleep_range(10000, 11000);
991
992 /* bring XCPU out of reset */
993 status = write_register(state, 0x90720000, 1);
994 if (status)
995 return status;
996 msleep(500);
997
998 /* Enable XCPU UART message processing in MCPU */
999 status = write_register(state, 0x9076B510, 1);
1000 if (status)
1001 return status;
1002 } else {
1003 /* Bring CPU out of reset */
1004 status = update_by_mnemonic(state, 0x8003003C, 0, 1, 1);
1005 if (status)
1006 return status;
1007 /* Wait until FW boots */
1008 msleep(150);
1009 }
1010
1011 /* Initialize XPT XBAR */
1012 status = write_register(state, XPT_DMD0_BASEADDR, 0x76543210);
1013 if (status)
1014 return status;
1015
1016 if (!firmware_is_alive(state))
1017 return -1;
1018
1019 dev_info(state->i2cdev, "Hydra FW alive. Hail!\n");
1020
1021 /* sometimes register values are wrong shortly
1022 * after first heart beats
1023 */
1024 msleep(50);
1025
1026 dev_sku_cfg.sku_type = state->base->sku_type;
1027 BUILD_HYDRA_CMD(MXL_HYDRA_DEV_CFG_SKU_CMD, MXL_CMD_WRITE,
1028 cmd_size, &dev_sku_cfg, cmd_buff);
1029 status = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
1030 &cmd_buff[0]);
1031
1032 return status;
1033 }
1034
cfg_ts_pad_mux(struct mxl * state,enum MXL_BOOL_E enable_serial_ts)1035 static int cfg_ts_pad_mux(struct mxl *state, enum MXL_BOOL_E enable_serial_ts)
1036 {
1037 int status = 0;
1038 u32 pad_mux_value = 0;
1039
1040 if (enable_serial_ts == MXL_TRUE) {
1041 pad_mux_value = 0;
1042 if ((state->base->type == MXL_HYDRA_DEVICE_541) ||
1043 (state->base->type == MXL_HYDRA_DEVICE_541S))
1044 pad_mux_value = 2;
1045 } else {
1046 if ((state->base->type == MXL_HYDRA_DEVICE_581) ||
1047 (state->base->type == MXL_HYDRA_DEVICE_581S))
1048 pad_mux_value = 2;
1049 else
1050 pad_mux_value = 3;
1051 }
1052
1053 switch (state->base->type) {
1054 case MXL_HYDRA_DEVICE_561:
1055 case MXL_HYDRA_DEVICE_581:
1056 case MXL_HYDRA_DEVICE_541:
1057 case MXL_HYDRA_DEVICE_541S:
1058 case MXL_HYDRA_DEVICE_561S:
1059 case MXL_HYDRA_DEVICE_581S:
1060 status |= update_by_mnemonic(state, 0x90000170, 24, 3,
1061 pad_mux_value);
1062 status |= update_by_mnemonic(state, 0x90000170, 28, 3,
1063 pad_mux_value);
1064 status |= update_by_mnemonic(state, 0x90000174, 0, 3,
1065 pad_mux_value);
1066 status |= update_by_mnemonic(state, 0x90000174, 4, 3,
1067 pad_mux_value);
1068 status |= update_by_mnemonic(state, 0x90000174, 8, 3,
1069 pad_mux_value);
1070 status |= update_by_mnemonic(state, 0x90000174, 12, 3,
1071 pad_mux_value);
1072 status |= update_by_mnemonic(state, 0x90000174, 16, 3,
1073 pad_mux_value);
1074 status |= update_by_mnemonic(state, 0x90000174, 20, 3,
1075 pad_mux_value);
1076 status |= update_by_mnemonic(state, 0x90000174, 24, 3,
1077 pad_mux_value);
1078 status |= update_by_mnemonic(state, 0x90000174, 28, 3,
1079 pad_mux_value);
1080 status |= update_by_mnemonic(state, 0x90000178, 0, 3,
1081 pad_mux_value);
1082 status |= update_by_mnemonic(state, 0x90000178, 4, 3,
1083 pad_mux_value);
1084 status |= update_by_mnemonic(state, 0x90000178, 8, 3,
1085 pad_mux_value);
1086 break;
1087
1088 case MXL_HYDRA_DEVICE_544:
1089 case MXL_HYDRA_DEVICE_542:
1090 status |= update_by_mnemonic(state, 0x9000016C, 4, 3, 1);
1091 status |= update_by_mnemonic(state, 0x9000016C, 8, 3, 0);
1092 status |= update_by_mnemonic(state, 0x9000016C, 12, 3, 0);
1093 status |= update_by_mnemonic(state, 0x9000016C, 16, 3, 0);
1094 status |= update_by_mnemonic(state, 0x90000170, 0, 3, 0);
1095 status |= update_by_mnemonic(state, 0x90000178, 12, 3, 1);
1096 status |= update_by_mnemonic(state, 0x90000178, 16, 3, 1);
1097 status |= update_by_mnemonic(state, 0x90000178, 20, 3, 1);
1098 status |= update_by_mnemonic(state, 0x90000178, 24, 3, 1);
1099 status |= update_by_mnemonic(state, 0x9000017C, 0, 3, 1);
1100 status |= update_by_mnemonic(state, 0x9000017C, 4, 3, 1);
1101 if (enable_serial_ts == MXL_ENABLE) {
1102 status |= update_by_mnemonic(state,
1103 0x90000170, 4, 3, 0);
1104 status |= update_by_mnemonic(state,
1105 0x90000170, 8, 3, 0);
1106 status |= update_by_mnemonic(state,
1107 0x90000170, 12, 3, 0);
1108 status |= update_by_mnemonic(state,
1109 0x90000170, 16, 3, 0);
1110 status |= update_by_mnemonic(state,
1111 0x90000170, 20, 3, 1);
1112 status |= update_by_mnemonic(state,
1113 0x90000170, 24, 3, 1);
1114 status |= update_by_mnemonic(state,
1115 0x90000170, 28, 3, 2);
1116 status |= update_by_mnemonic(state,
1117 0x90000174, 0, 3, 2);
1118 status |= update_by_mnemonic(state,
1119 0x90000174, 4, 3, 2);
1120 status |= update_by_mnemonic(state,
1121 0x90000174, 8, 3, 2);
1122 status |= update_by_mnemonic(state,
1123 0x90000174, 12, 3, 2);
1124 status |= update_by_mnemonic(state,
1125 0x90000174, 16, 3, 2);
1126 status |= update_by_mnemonic(state,
1127 0x90000174, 20, 3, 2);
1128 status |= update_by_mnemonic(state,
1129 0x90000174, 24, 3, 2);
1130 status |= update_by_mnemonic(state,
1131 0x90000174, 28, 3, 2);
1132 status |= update_by_mnemonic(state,
1133 0x90000178, 0, 3, 2);
1134 status |= update_by_mnemonic(state,
1135 0x90000178, 4, 3, 2);
1136 status |= update_by_mnemonic(state,
1137 0x90000178, 8, 3, 2);
1138 } else {
1139 status |= update_by_mnemonic(state,
1140 0x90000170, 4, 3, 3);
1141 status |= update_by_mnemonic(state,
1142 0x90000170, 8, 3, 3);
1143 status |= update_by_mnemonic(state,
1144 0x90000170, 12, 3, 3);
1145 status |= update_by_mnemonic(state,
1146 0x90000170, 16, 3, 3);
1147 status |= update_by_mnemonic(state,
1148 0x90000170, 20, 3, 3);
1149 status |= update_by_mnemonic(state,
1150 0x90000170, 24, 3, 3);
1151 status |= update_by_mnemonic(state,
1152 0x90000170, 28, 3, 3);
1153 status |= update_by_mnemonic(state,
1154 0x90000174, 0, 3, 3);
1155 status |= update_by_mnemonic(state,
1156 0x90000174, 4, 3, 3);
1157 status |= update_by_mnemonic(state,
1158 0x90000174, 8, 3, 3);
1159 status |= update_by_mnemonic(state,
1160 0x90000174, 12, 3, 3);
1161 status |= update_by_mnemonic(state,
1162 0x90000174, 16, 3, 3);
1163 status |= update_by_mnemonic(state,
1164 0x90000174, 20, 3, 1);
1165 status |= update_by_mnemonic(state,
1166 0x90000174, 24, 3, 1);
1167 status |= update_by_mnemonic(state,
1168 0x90000174, 28, 3, 1);
1169 status |= update_by_mnemonic(state,
1170 0x90000178, 0, 3, 1);
1171 status |= update_by_mnemonic(state,
1172 0x90000178, 4, 3, 1);
1173 status |= update_by_mnemonic(state,
1174 0x90000178, 8, 3, 1);
1175 }
1176 break;
1177
1178 case MXL_HYDRA_DEVICE_568:
1179 if (enable_serial_ts == MXL_FALSE) {
1180 status |= update_by_mnemonic(state,
1181 0x9000016C, 8, 3, 5);
1182 status |= update_by_mnemonic(state,
1183 0x9000016C, 12, 3, 5);
1184 status |= update_by_mnemonic(state,
1185 0x9000016C, 16, 3, 5);
1186 status |= update_by_mnemonic(state,
1187 0x9000016C, 20, 3, 5);
1188 status |= update_by_mnemonic(state,
1189 0x9000016C, 24, 3, 5);
1190 status |= update_by_mnemonic(state,
1191 0x9000016C, 28, 3, 5);
1192 status |= update_by_mnemonic(state,
1193 0x90000170, 0, 3, 5);
1194 status |= update_by_mnemonic(state,
1195 0x90000170, 4, 3, 5);
1196 status |= update_by_mnemonic(state,
1197 0x90000170, 8, 3, 5);
1198 status |= update_by_mnemonic(state,
1199 0x90000170, 12, 3, 5);
1200 status |= update_by_mnemonic(state,
1201 0x90000170, 16, 3, 5);
1202 status |= update_by_mnemonic(state,
1203 0x90000170, 20, 3, 5);
1204
1205 status |= update_by_mnemonic(state,
1206 0x90000170, 24, 3, pad_mux_value);
1207 status |= update_by_mnemonic(state,
1208 0x90000174, 0, 3, pad_mux_value);
1209 status |= update_by_mnemonic(state,
1210 0x90000174, 4, 3, pad_mux_value);
1211 status |= update_by_mnemonic(state,
1212 0x90000174, 8, 3, pad_mux_value);
1213 status |= update_by_mnemonic(state,
1214 0x90000174, 12, 3, pad_mux_value);
1215 status |= update_by_mnemonic(state,
1216 0x90000174, 16, 3, pad_mux_value);
1217 status |= update_by_mnemonic(state,
1218 0x90000174, 20, 3, pad_mux_value);
1219 status |= update_by_mnemonic(state,
1220 0x90000174, 24, 3, pad_mux_value);
1221 status |= update_by_mnemonic(state,
1222 0x90000174, 28, 3, pad_mux_value);
1223 status |= update_by_mnemonic(state,
1224 0x90000178, 0, 3, pad_mux_value);
1225 status |= update_by_mnemonic(state,
1226 0x90000178, 4, 3, pad_mux_value);
1227
1228 status |= update_by_mnemonic(state,
1229 0x90000178, 8, 3, 5);
1230 status |= update_by_mnemonic(state,
1231 0x90000178, 12, 3, 5);
1232 status |= update_by_mnemonic(state,
1233 0x90000178, 16, 3, 5);
1234 status |= update_by_mnemonic(state,
1235 0x90000178, 20, 3, 5);
1236 status |= update_by_mnemonic(state,
1237 0x90000178, 24, 3, 5);
1238 status |= update_by_mnemonic(state,
1239 0x90000178, 28, 3, 5);
1240 status |= update_by_mnemonic(state,
1241 0x9000017C, 0, 3, 5);
1242 status |= update_by_mnemonic(state,
1243 0x9000017C, 4, 3, 5);
1244 } else {
1245 status |= update_by_mnemonic(state,
1246 0x90000170, 4, 3, pad_mux_value);
1247 status |= update_by_mnemonic(state,
1248 0x90000170, 8, 3, pad_mux_value);
1249 status |= update_by_mnemonic(state,
1250 0x90000170, 12, 3, pad_mux_value);
1251 status |= update_by_mnemonic(state,
1252 0x90000170, 16, 3, pad_mux_value);
1253 status |= update_by_mnemonic(state,
1254 0x90000170, 20, 3, pad_mux_value);
1255 status |= update_by_mnemonic(state,
1256 0x90000170, 24, 3, pad_mux_value);
1257 status |= update_by_mnemonic(state,
1258 0x90000170, 28, 3, pad_mux_value);
1259 status |= update_by_mnemonic(state,
1260 0x90000174, 0, 3, pad_mux_value);
1261 status |= update_by_mnemonic(state,
1262 0x90000174, 4, 3, pad_mux_value);
1263 status |= update_by_mnemonic(state,
1264 0x90000174, 8, 3, pad_mux_value);
1265 status |= update_by_mnemonic(state,
1266 0x90000174, 12, 3, pad_mux_value);
1267 }
1268 break;
1269
1270
1271 case MXL_HYDRA_DEVICE_584:
1272 default:
1273 status |= update_by_mnemonic(state,
1274 0x90000170, 4, 3, pad_mux_value);
1275 status |= update_by_mnemonic(state,
1276 0x90000170, 8, 3, pad_mux_value);
1277 status |= update_by_mnemonic(state,
1278 0x90000170, 12, 3, pad_mux_value);
1279 status |= update_by_mnemonic(state,
1280 0x90000170, 16, 3, pad_mux_value);
1281 status |= update_by_mnemonic(state,
1282 0x90000170, 20, 3, pad_mux_value);
1283 status |= update_by_mnemonic(state,
1284 0x90000170, 24, 3, pad_mux_value);
1285 status |= update_by_mnemonic(state,
1286 0x90000170, 28, 3, pad_mux_value);
1287 status |= update_by_mnemonic(state,
1288 0x90000174, 0, 3, pad_mux_value);
1289 status |= update_by_mnemonic(state,
1290 0x90000174, 4, 3, pad_mux_value);
1291 status |= update_by_mnemonic(state,
1292 0x90000174, 8, 3, pad_mux_value);
1293 status |= update_by_mnemonic(state,
1294 0x90000174, 12, 3, pad_mux_value);
1295 break;
1296 }
1297 return status;
1298 }
1299
set_drive_strength(struct mxl * state,enum MXL_HYDRA_TS_DRIVE_STRENGTH_E ts_drive_strength)1300 static int set_drive_strength(struct mxl *state,
1301 enum MXL_HYDRA_TS_DRIVE_STRENGTH_E ts_drive_strength)
1302 {
1303 int stat = 0;
1304 u32 val;
1305
1306 read_register(state, 0x90000194, &val);
1307 dev_info(state->i2cdev, "DIGIO = %08x\n", val);
1308 dev_info(state->i2cdev, "set drive_strength = %u\n", ts_drive_strength);
1309
1310
1311 stat |= update_by_mnemonic(state, 0x90000194, 0, 3, ts_drive_strength);
1312 stat |= update_by_mnemonic(state, 0x90000194, 20, 3, ts_drive_strength);
1313 stat |= update_by_mnemonic(state, 0x90000194, 24, 3, ts_drive_strength);
1314 stat |= update_by_mnemonic(state, 0x90000198, 12, 3, ts_drive_strength);
1315 stat |= update_by_mnemonic(state, 0x90000198, 16, 3, ts_drive_strength);
1316 stat |= update_by_mnemonic(state, 0x90000198, 20, 3, ts_drive_strength);
1317 stat |= update_by_mnemonic(state, 0x90000198, 24, 3, ts_drive_strength);
1318 stat |= update_by_mnemonic(state, 0x9000019C, 0, 3, ts_drive_strength);
1319 stat |= update_by_mnemonic(state, 0x9000019C, 4, 3, ts_drive_strength);
1320 stat |= update_by_mnemonic(state, 0x9000019C, 8, 3, ts_drive_strength);
1321 stat |= update_by_mnemonic(state, 0x9000019C, 24, 3, ts_drive_strength);
1322 stat |= update_by_mnemonic(state, 0x9000019C, 28, 3, ts_drive_strength);
1323 stat |= update_by_mnemonic(state, 0x900001A0, 0, 3, ts_drive_strength);
1324 stat |= update_by_mnemonic(state, 0x900001A0, 4, 3, ts_drive_strength);
1325 stat |= update_by_mnemonic(state, 0x900001A0, 20, 3, ts_drive_strength);
1326 stat |= update_by_mnemonic(state, 0x900001A0, 24, 3, ts_drive_strength);
1327 stat |= update_by_mnemonic(state, 0x900001A0, 28, 3, ts_drive_strength);
1328
1329 return stat;
1330 }
1331
enable_tuner(struct mxl * state,u32 tuner,u32 enable)1332 static int enable_tuner(struct mxl *state, u32 tuner, u32 enable)
1333 {
1334 int stat = 0;
1335 struct MXL_HYDRA_TUNER_CMD ctrl_tuner_cmd;
1336 u8 cmd_size = sizeof(ctrl_tuner_cmd);
1337 u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
1338 u32 val, count = 10;
1339
1340 ctrl_tuner_cmd.tuner_id = tuner;
1341 ctrl_tuner_cmd.enable = enable;
1342 BUILD_HYDRA_CMD(MXL_HYDRA_TUNER_ACTIVATE_CMD, MXL_CMD_WRITE,
1343 cmd_size, &ctrl_tuner_cmd, cmd_buff);
1344 stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
1345 &cmd_buff[0]);
1346 if (stat)
1347 return stat;
1348 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
1349 while (--count && ((val >> tuner) & 1) != enable) {
1350 msleep(20);
1351 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
1352 }
1353 if (!count)
1354 return -1;
1355 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
1356 dev_dbg(state->i2cdev, "tuner %u ready = %u\n",
1357 tuner, (val >> tuner) & 1);
1358
1359 return 0;
1360 }
1361
1362
config_ts(struct mxl * state,enum MXL_HYDRA_DEMOD_ID_E demod_id,struct MXL_HYDRA_MPEGOUT_PARAM_T * mpeg_out_param_ptr)1363 static int config_ts(struct mxl *state, enum MXL_HYDRA_DEMOD_ID_E demod_id,
1364 struct MXL_HYDRA_MPEGOUT_PARAM_T *mpeg_out_param_ptr)
1365 {
1366 int status = 0;
1367 u32 nco_count_min = 0;
1368 u32 clk_type = 0;
1369
1370 struct MXL_REG_FIELD_T xpt_sync_polarity[MXL_HYDRA_DEMOD_MAX] = {
1371 {0x90700010, 8, 1}, {0x90700010, 9, 1},
1372 {0x90700010, 10, 1}, {0x90700010, 11, 1},
1373 {0x90700010, 12, 1}, {0x90700010, 13, 1},
1374 {0x90700010, 14, 1}, {0x90700010, 15, 1} };
1375 struct MXL_REG_FIELD_T xpt_clock_polarity[MXL_HYDRA_DEMOD_MAX] = {
1376 {0x90700010, 16, 1}, {0x90700010, 17, 1},
1377 {0x90700010, 18, 1}, {0x90700010, 19, 1},
1378 {0x90700010, 20, 1}, {0x90700010, 21, 1},
1379 {0x90700010, 22, 1}, {0x90700010, 23, 1} };
1380 struct MXL_REG_FIELD_T xpt_valid_polarity[MXL_HYDRA_DEMOD_MAX] = {
1381 {0x90700014, 0, 1}, {0x90700014, 1, 1},
1382 {0x90700014, 2, 1}, {0x90700014, 3, 1},
1383 {0x90700014, 4, 1}, {0x90700014, 5, 1},
1384 {0x90700014, 6, 1}, {0x90700014, 7, 1} };
1385 struct MXL_REG_FIELD_T xpt_ts_clock_phase[MXL_HYDRA_DEMOD_MAX] = {
1386 {0x90700018, 0, 3}, {0x90700018, 4, 3},
1387 {0x90700018, 8, 3}, {0x90700018, 12, 3},
1388 {0x90700018, 16, 3}, {0x90700018, 20, 3},
1389 {0x90700018, 24, 3}, {0x90700018, 28, 3} };
1390 struct MXL_REG_FIELD_T xpt_lsb_first[MXL_HYDRA_DEMOD_MAX] = {
1391 {0x9070000C, 16, 1}, {0x9070000C, 17, 1},
1392 {0x9070000C, 18, 1}, {0x9070000C, 19, 1},
1393 {0x9070000C, 20, 1}, {0x9070000C, 21, 1},
1394 {0x9070000C, 22, 1}, {0x9070000C, 23, 1} };
1395 struct MXL_REG_FIELD_T xpt_sync_byte[MXL_HYDRA_DEMOD_MAX] = {
1396 {0x90700010, 0, 1}, {0x90700010, 1, 1},
1397 {0x90700010, 2, 1}, {0x90700010, 3, 1},
1398 {0x90700010, 4, 1}, {0x90700010, 5, 1},
1399 {0x90700010, 6, 1}, {0x90700010, 7, 1} };
1400 struct MXL_REG_FIELD_T xpt_enable_output[MXL_HYDRA_DEMOD_MAX] = {
1401 {0x9070000C, 0, 1}, {0x9070000C, 1, 1},
1402 {0x9070000C, 2, 1}, {0x9070000C, 3, 1},
1403 {0x9070000C, 4, 1}, {0x9070000C, 5, 1},
1404 {0x9070000C, 6, 1}, {0x9070000C, 7, 1} };
1405 struct MXL_REG_FIELD_T xpt_err_replace_sync[MXL_HYDRA_DEMOD_MAX] = {
1406 {0x9070000C, 24, 1}, {0x9070000C, 25, 1},
1407 {0x9070000C, 26, 1}, {0x9070000C, 27, 1},
1408 {0x9070000C, 28, 1}, {0x9070000C, 29, 1},
1409 {0x9070000C, 30, 1}, {0x9070000C, 31, 1} };
1410 struct MXL_REG_FIELD_T xpt_err_replace_valid[MXL_HYDRA_DEMOD_MAX] = {
1411 {0x90700014, 8, 1}, {0x90700014, 9, 1},
1412 {0x90700014, 10, 1}, {0x90700014, 11, 1},
1413 {0x90700014, 12, 1}, {0x90700014, 13, 1},
1414 {0x90700014, 14, 1}, {0x90700014, 15, 1} };
1415 struct MXL_REG_FIELD_T xpt_continuous_clock[MXL_HYDRA_DEMOD_MAX] = {
1416 {0x907001D4, 0, 1}, {0x907001D4, 1, 1},
1417 {0x907001D4, 2, 1}, {0x907001D4, 3, 1},
1418 {0x907001D4, 4, 1}, {0x907001D4, 5, 1},
1419 {0x907001D4, 6, 1}, {0x907001D4, 7, 1} };
1420 struct MXL_REG_FIELD_T xpt_nco_clock_rate[MXL_HYDRA_DEMOD_MAX] = {
1421 {0x90700044, 16, 80}, {0x90700044, 16, 81},
1422 {0x90700044, 16, 82}, {0x90700044, 16, 83},
1423 {0x90700044, 16, 84}, {0x90700044, 16, 85},
1424 {0x90700044, 16, 86}, {0x90700044, 16, 87} };
1425
1426 demod_id = state->base->ts_map[demod_id];
1427
1428 if (mpeg_out_param_ptr->enable == MXL_ENABLE) {
1429 if (mpeg_out_param_ptr->mpeg_mode ==
1430 MXL_HYDRA_MPEG_MODE_PARALLEL) {
1431 } else {
1432 cfg_ts_pad_mux(state, MXL_TRUE);
1433 update_by_mnemonic(state,
1434 0x90700010, 27, 1, MXL_FALSE);
1435 }
1436 }
1437
1438 nco_count_min =
1439 (u32)(MXL_HYDRA_NCO_CLK / mpeg_out_param_ptr->max_mpeg_clk_rate);
1440
1441 if (state->base->chipversion >= 2) {
1442 status |= update_by_mnemonic(state,
1443 xpt_nco_clock_rate[demod_id].reg_addr, /* Reg Addr */
1444 xpt_nco_clock_rate[demod_id].lsb_pos, /* LSB pos */
1445 xpt_nco_clock_rate[demod_id].num_of_bits, /* Num of bits */
1446 nco_count_min); /* Data */
1447 } else
1448 update_by_mnemonic(state, 0x90700044, 16, 8, nco_count_min);
1449
1450 if (mpeg_out_param_ptr->mpeg_clk_type == MXL_HYDRA_MPEG_CLK_CONTINUOUS)
1451 clk_type = 1;
1452
1453 if (mpeg_out_param_ptr->mpeg_mode < MXL_HYDRA_MPEG_MODE_PARALLEL) {
1454 status |= update_by_mnemonic(state,
1455 xpt_continuous_clock[demod_id].reg_addr,
1456 xpt_continuous_clock[demod_id].lsb_pos,
1457 xpt_continuous_clock[demod_id].num_of_bits,
1458 clk_type);
1459 } else
1460 update_by_mnemonic(state, 0x907001D4, 8, 1, clk_type);
1461
1462 status |= update_by_mnemonic(state,
1463 xpt_sync_polarity[demod_id].reg_addr,
1464 xpt_sync_polarity[demod_id].lsb_pos,
1465 xpt_sync_polarity[demod_id].num_of_bits,
1466 mpeg_out_param_ptr->mpeg_sync_pol);
1467
1468 status |= update_by_mnemonic(state,
1469 xpt_valid_polarity[demod_id].reg_addr,
1470 xpt_valid_polarity[demod_id].lsb_pos,
1471 xpt_valid_polarity[demod_id].num_of_bits,
1472 mpeg_out_param_ptr->mpeg_valid_pol);
1473
1474 status |= update_by_mnemonic(state,
1475 xpt_clock_polarity[demod_id].reg_addr,
1476 xpt_clock_polarity[demod_id].lsb_pos,
1477 xpt_clock_polarity[demod_id].num_of_bits,
1478 mpeg_out_param_ptr->mpeg_clk_pol);
1479
1480 status |= update_by_mnemonic(state,
1481 xpt_sync_byte[demod_id].reg_addr,
1482 xpt_sync_byte[demod_id].lsb_pos,
1483 xpt_sync_byte[demod_id].num_of_bits,
1484 mpeg_out_param_ptr->mpeg_sync_pulse_width);
1485
1486 status |= update_by_mnemonic(state,
1487 xpt_ts_clock_phase[demod_id].reg_addr,
1488 xpt_ts_clock_phase[demod_id].lsb_pos,
1489 xpt_ts_clock_phase[demod_id].num_of_bits,
1490 mpeg_out_param_ptr->mpeg_clk_phase);
1491
1492 status |= update_by_mnemonic(state,
1493 xpt_lsb_first[demod_id].reg_addr,
1494 xpt_lsb_first[demod_id].lsb_pos,
1495 xpt_lsb_first[demod_id].num_of_bits,
1496 mpeg_out_param_ptr->lsb_or_msb_first);
1497
1498 switch (mpeg_out_param_ptr->mpeg_error_indication) {
1499 case MXL_HYDRA_MPEG_ERR_REPLACE_SYNC:
1500 status |= update_by_mnemonic(state,
1501 xpt_err_replace_sync[demod_id].reg_addr,
1502 xpt_err_replace_sync[demod_id].lsb_pos,
1503 xpt_err_replace_sync[demod_id].num_of_bits,
1504 MXL_TRUE);
1505 status |= update_by_mnemonic(state,
1506 xpt_err_replace_valid[demod_id].reg_addr,
1507 xpt_err_replace_valid[demod_id].lsb_pos,
1508 xpt_err_replace_valid[demod_id].num_of_bits,
1509 MXL_FALSE);
1510 break;
1511
1512 case MXL_HYDRA_MPEG_ERR_REPLACE_VALID:
1513 status |= update_by_mnemonic(state,
1514 xpt_err_replace_sync[demod_id].reg_addr,
1515 xpt_err_replace_sync[demod_id].lsb_pos,
1516 xpt_err_replace_sync[demod_id].num_of_bits,
1517 MXL_FALSE);
1518
1519 status |= update_by_mnemonic(state,
1520 xpt_err_replace_valid[demod_id].reg_addr,
1521 xpt_err_replace_valid[demod_id].lsb_pos,
1522 xpt_err_replace_valid[demod_id].num_of_bits,
1523 MXL_TRUE);
1524 break;
1525
1526 case MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED:
1527 default:
1528 status |= update_by_mnemonic(state,
1529 xpt_err_replace_sync[demod_id].reg_addr,
1530 xpt_err_replace_sync[demod_id].lsb_pos,
1531 xpt_err_replace_sync[demod_id].num_of_bits,
1532 MXL_FALSE);
1533
1534 status |= update_by_mnemonic(state,
1535 xpt_err_replace_valid[demod_id].reg_addr,
1536 xpt_err_replace_valid[demod_id].lsb_pos,
1537 xpt_err_replace_valid[demod_id].num_of_bits,
1538 MXL_FALSE);
1539
1540 break;
1541
1542 }
1543
1544 if (mpeg_out_param_ptr->mpeg_mode != MXL_HYDRA_MPEG_MODE_PARALLEL) {
1545 status |= update_by_mnemonic(state,
1546 xpt_enable_output[demod_id].reg_addr,
1547 xpt_enable_output[demod_id].lsb_pos,
1548 xpt_enable_output[demod_id].num_of_bits,
1549 mpeg_out_param_ptr->enable);
1550 }
1551 return status;
1552 }
1553
config_mux(struct mxl * state)1554 static int config_mux(struct mxl *state)
1555 {
1556 update_by_mnemonic(state, 0x9070000C, 0, 1, 0);
1557 update_by_mnemonic(state, 0x9070000C, 1, 1, 0);
1558 update_by_mnemonic(state, 0x9070000C, 2, 1, 0);
1559 update_by_mnemonic(state, 0x9070000C, 3, 1, 0);
1560 update_by_mnemonic(state, 0x9070000C, 4, 1, 0);
1561 update_by_mnemonic(state, 0x9070000C, 5, 1, 0);
1562 update_by_mnemonic(state, 0x9070000C, 6, 1, 0);
1563 update_by_mnemonic(state, 0x9070000C, 7, 1, 0);
1564 update_by_mnemonic(state, 0x90700008, 0, 2, 1);
1565 update_by_mnemonic(state, 0x90700008, 2, 2, 1);
1566 return 0;
1567 }
1568
load_fw(struct mxl * state,struct mxl5xx_cfg * cfg)1569 static int load_fw(struct mxl *state, struct mxl5xx_cfg *cfg)
1570 {
1571 int stat = 0;
1572 u8 *buf;
1573
1574 if (cfg->fw)
1575 return firmware_download(state, cfg->fw, cfg->fw_len);
1576
1577 if (!cfg->fw_read)
1578 return -1;
1579
1580 buf = vmalloc(0x40000);
1581 if (!buf)
1582 return -ENOMEM;
1583
1584 cfg->fw_read(cfg->fw_priv, buf, 0x40000);
1585 stat = firmware_download(state, buf, 0x40000);
1586 vfree(buf);
1587
1588 return stat;
1589 }
1590
validate_sku(struct mxl * state)1591 static int validate_sku(struct mxl *state)
1592 {
1593 u32 pad_mux_bond = 0, prcm_chip_id = 0, prcm_so_cid = 0;
1594 int status;
1595 u32 type = state->base->type;
1596
1597 status = read_by_mnemonic(state, 0x90000190, 0, 3, &pad_mux_bond);
1598 status |= read_by_mnemonic(state, 0x80030000, 0, 12, &prcm_chip_id);
1599 status |= read_by_mnemonic(state, 0x80030004, 24, 8, &prcm_so_cid);
1600 if (status)
1601 return -1;
1602
1603 dev_info(state->i2cdev, "padMuxBond=%08x, prcmChipId=%08x, prcmSoCId=%08x\n",
1604 pad_mux_bond, prcm_chip_id, prcm_so_cid);
1605
1606 if (prcm_chip_id != 0x560) {
1607 switch (pad_mux_bond) {
1608 case MXL_HYDRA_SKU_ID_581:
1609 if (type == MXL_HYDRA_DEVICE_581)
1610 return 0;
1611 if (type == MXL_HYDRA_DEVICE_581S) {
1612 state->base->type = MXL_HYDRA_DEVICE_581;
1613 return 0;
1614 }
1615 break;
1616 case MXL_HYDRA_SKU_ID_584:
1617 if (type == MXL_HYDRA_DEVICE_584)
1618 return 0;
1619 break;
1620 case MXL_HYDRA_SKU_ID_544:
1621 if (type == MXL_HYDRA_DEVICE_544)
1622 return 0;
1623 if (type == MXL_HYDRA_DEVICE_542)
1624 return 0;
1625 break;
1626 case MXL_HYDRA_SKU_ID_582:
1627 if (type == MXL_HYDRA_DEVICE_582)
1628 return 0;
1629 break;
1630 default:
1631 return -1;
1632 }
1633 } else {
1634
1635 }
1636 return -1;
1637 }
1638
get_fwinfo(struct mxl * state)1639 static int get_fwinfo(struct mxl *state)
1640 {
1641 int status;
1642 u32 val = 0;
1643
1644 status = read_by_mnemonic(state, 0x90000190, 0, 3, &val);
1645 if (status)
1646 return status;
1647 dev_info(state->i2cdev, "chipID=%08x\n", val);
1648
1649 status = read_by_mnemonic(state, 0x80030004, 8, 8, &val);
1650 if (status)
1651 return status;
1652 dev_info(state->i2cdev, "chipVer=%08x\n", val);
1653
1654 status = read_register(state, HYDRA_FIRMWARE_VERSION, &val);
1655 if (status)
1656 return status;
1657 dev_info(state->i2cdev, "FWVer=%08x\n", val);
1658
1659 state->base->fwversion = val;
1660 return status;
1661 }
1662
1663
1664 static u8 ts_map1_to_1[MXL_HYDRA_DEMOD_MAX] = {
1665 MXL_HYDRA_DEMOD_ID_0,
1666 MXL_HYDRA_DEMOD_ID_1,
1667 MXL_HYDRA_DEMOD_ID_2,
1668 MXL_HYDRA_DEMOD_ID_3,
1669 MXL_HYDRA_DEMOD_ID_4,
1670 MXL_HYDRA_DEMOD_ID_5,
1671 MXL_HYDRA_DEMOD_ID_6,
1672 MXL_HYDRA_DEMOD_ID_7,
1673 };
1674
1675 static u8 ts_map54x[MXL_HYDRA_DEMOD_MAX] = {
1676 MXL_HYDRA_DEMOD_ID_2,
1677 MXL_HYDRA_DEMOD_ID_3,
1678 MXL_HYDRA_DEMOD_ID_4,
1679 MXL_HYDRA_DEMOD_ID_5,
1680 MXL_HYDRA_DEMOD_MAX,
1681 MXL_HYDRA_DEMOD_MAX,
1682 MXL_HYDRA_DEMOD_MAX,
1683 MXL_HYDRA_DEMOD_MAX,
1684 };
1685
probe(struct mxl * state,struct mxl5xx_cfg * cfg)1686 static int probe(struct mxl *state, struct mxl5xx_cfg *cfg)
1687 {
1688 u32 chipver;
1689 int fw, status, j;
1690 struct MXL_HYDRA_MPEGOUT_PARAM_T mpeg_interface_cfg;
1691
1692 state->base->ts_map = ts_map1_to_1;
1693
1694 switch (state->base->type) {
1695 case MXL_HYDRA_DEVICE_581:
1696 case MXL_HYDRA_DEVICE_581S:
1697 state->base->can_clkout = 1;
1698 state->base->demod_num = 8;
1699 state->base->tuner_num = 1;
1700 state->base->sku_type = MXL_HYDRA_SKU_TYPE_581;
1701 break;
1702 case MXL_HYDRA_DEVICE_582:
1703 state->base->can_clkout = 1;
1704 state->base->demod_num = 8;
1705 state->base->tuner_num = 3;
1706 state->base->sku_type = MXL_HYDRA_SKU_TYPE_582;
1707 break;
1708 case MXL_HYDRA_DEVICE_585:
1709 state->base->can_clkout = 0;
1710 state->base->demod_num = 8;
1711 state->base->tuner_num = 4;
1712 state->base->sku_type = MXL_HYDRA_SKU_TYPE_585;
1713 break;
1714 case MXL_HYDRA_DEVICE_544:
1715 state->base->can_clkout = 0;
1716 state->base->demod_num = 4;
1717 state->base->tuner_num = 4;
1718 state->base->sku_type = MXL_HYDRA_SKU_TYPE_544;
1719 state->base->ts_map = ts_map54x;
1720 break;
1721 case MXL_HYDRA_DEVICE_541:
1722 case MXL_HYDRA_DEVICE_541S:
1723 state->base->can_clkout = 0;
1724 state->base->demod_num = 4;
1725 state->base->tuner_num = 1;
1726 state->base->sku_type = MXL_HYDRA_SKU_TYPE_541;
1727 state->base->ts_map = ts_map54x;
1728 break;
1729 case MXL_HYDRA_DEVICE_561:
1730 case MXL_HYDRA_DEVICE_561S:
1731 state->base->can_clkout = 0;
1732 state->base->demod_num = 6;
1733 state->base->tuner_num = 1;
1734 state->base->sku_type = MXL_HYDRA_SKU_TYPE_561;
1735 break;
1736 case MXL_HYDRA_DEVICE_568:
1737 state->base->can_clkout = 0;
1738 state->base->demod_num = 8;
1739 state->base->tuner_num = 1;
1740 state->base->chan_bond = 1;
1741 state->base->sku_type = MXL_HYDRA_SKU_TYPE_568;
1742 break;
1743 case MXL_HYDRA_DEVICE_542:
1744 state->base->can_clkout = 1;
1745 state->base->demod_num = 4;
1746 state->base->tuner_num = 3;
1747 state->base->sku_type = MXL_HYDRA_SKU_TYPE_542;
1748 state->base->ts_map = ts_map54x;
1749 break;
1750 case MXL_HYDRA_DEVICE_TEST:
1751 case MXL_HYDRA_DEVICE_584:
1752 default:
1753 state->base->can_clkout = 0;
1754 state->base->demod_num = 8;
1755 state->base->tuner_num = 4;
1756 state->base->sku_type = MXL_HYDRA_SKU_TYPE_584;
1757 break;
1758 }
1759
1760 status = validate_sku(state);
1761 if (status)
1762 return status;
1763
1764 update_by_mnemonic(state, 0x80030014, 9, 1, 1);
1765 update_by_mnemonic(state, 0x8003003C, 12, 1, 1);
1766 status = read_by_mnemonic(state, 0x80030000, 12, 4, &chipver);
1767 if (status)
1768 state->base->chipversion = 0;
1769 else
1770 state->base->chipversion = (chipver == 2) ? 2 : 1;
1771 dev_info(state->i2cdev, "Hydra chip version %u\n",
1772 state->base->chipversion);
1773
1774 cfg_dev_xtal(state, cfg->clk, cfg->cap, 0);
1775
1776 fw = firmware_is_alive(state);
1777 if (!fw) {
1778 status = load_fw(state, cfg);
1779 if (status)
1780 return status;
1781 }
1782 get_fwinfo(state);
1783
1784 config_mux(state);
1785 mpeg_interface_cfg.enable = MXL_ENABLE;
1786 mpeg_interface_cfg.lsb_or_msb_first = MXL_HYDRA_MPEG_SERIAL_MSB_1ST;
1787 /* supports only (0-104&139)MHz */
1788 if (cfg->ts_clk)
1789 mpeg_interface_cfg.max_mpeg_clk_rate = cfg->ts_clk;
1790 else
1791 mpeg_interface_cfg.max_mpeg_clk_rate = 69; /* 139; */
1792 mpeg_interface_cfg.mpeg_clk_phase = MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_0_DEG;
1793 mpeg_interface_cfg.mpeg_clk_pol = MXL_HYDRA_MPEG_CLK_IN_PHASE;
1794 /* MXL_HYDRA_MPEG_CLK_GAPPED; */
1795 mpeg_interface_cfg.mpeg_clk_type = MXL_HYDRA_MPEG_CLK_CONTINUOUS;
1796 mpeg_interface_cfg.mpeg_error_indication =
1797 MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED;
1798 mpeg_interface_cfg.mpeg_mode = MXL_HYDRA_MPEG_MODE_SERIAL_3_WIRE;
1799 mpeg_interface_cfg.mpeg_sync_pol = MXL_HYDRA_MPEG_ACTIVE_HIGH;
1800 mpeg_interface_cfg.mpeg_sync_pulse_width = MXL_HYDRA_MPEG_SYNC_WIDTH_BIT;
1801 mpeg_interface_cfg.mpeg_valid_pol = MXL_HYDRA_MPEG_ACTIVE_HIGH;
1802
1803 for (j = 0; j < state->base->demod_num; j++) {
1804 status = config_ts(state, (enum MXL_HYDRA_DEMOD_ID_E) j,
1805 &mpeg_interface_cfg);
1806 if (status)
1807 return status;
1808 }
1809 set_drive_strength(state, 1);
1810 return 0;
1811 }
1812
mxl5xx_attach(struct i2c_adapter * i2c,struct mxl5xx_cfg * cfg,u32 demod,u32 tuner,int (** fn_set_input)(struct dvb_frontend *,int))1813 struct dvb_frontend *mxl5xx_attach(struct i2c_adapter *i2c,
1814 struct mxl5xx_cfg *cfg, u32 demod, u32 tuner,
1815 int (**fn_set_input)(struct dvb_frontend *, int))
1816 {
1817 struct mxl *state;
1818 struct mxl_base *base;
1819
1820 state = kzalloc(sizeof(struct mxl), GFP_KERNEL);
1821 if (!state)
1822 return NULL;
1823
1824 state->demod = demod;
1825 state->tuner = tuner;
1826 state->tuner_in_use = 0xffffffff;
1827 state->i2cdev = &i2c->dev;
1828
1829 base = match_base(i2c, cfg->adr);
1830 if (base) {
1831 base->count++;
1832 if (base->count > base->demod_num)
1833 goto fail;
1834 state->base = base;
1835 } else {
1836 base = kzalloc(sizeof(struct mxl_base), GFP_KERNEL);
1837 if (!base)
1838 goto fail;
1839 base->i2c = i2c;
1840 base->adr = cfg->adr;
1841 base->type = cfg->type;
1842 base->count = 1;
1843 mutex_init(&base->i2c_lock);
1844 mutex_init(&base->status_lock);
1845 mutex_init(&base->tune_lock);
1846 INIT_LIST_HEAD(&base->mxls);
1847
1848 state->base = base;
1849 if (probe(state, cfg) < 0) {
1850 kfree(base);
1851 goto fail;
1852 }
1853 list_add(&base->mxllist, &mxllist);
1854 }
1855 state->fe.ops = mxl_ops;
1856 state->xbar[0] = 4;
1857 state->xbar[1] = demod;
1858 state->xbar[2] = 8;
1859 state->fe.demodulator_priv = state;
1860 *fn_set_input = set_input;
1861
1862 list_add(&state->mxl, &base->mxls);
1863 return &state->fe;
1864
1865 fail:
1866 kfree(state);
1867 return NULL;
1868 }
1869 EXPORT_SYMBOL_GPL(mxl5xx_attach);
1870
1871 MODULE_DESCRIPTION("MaxLinear MxL5xx DVB-S/S2 tuner-demodulator driver");
1872 MODULE_AUTHOR("Ralph and Marcus Metzler, Metzler Brothers Systementwicklung GbR");
1873 MODULE_LICENSE("GPL");
1874