1 /*
2 * STIH4xx CEC driver
3 * Copyright (C) STMicroelectronics SA 2016
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10 #include <linux/clk.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_platform.h>
17 #include <linux/platform_device.h>
18
19 #include <media/cec.h>
20 #include <media/cec-notifier.h>
21
22 #define CEC_NAME "stih-cec"
23
24 /* CEC registers */
25 #define CEC_CLK_DIV 0x0
26 #define CEC_CTRL 0x4
27 #define CEC_IRQ_CTRL 0x8
28 #define CEC_STATUS 0xC
29 #define CEC_EXT_STATUS 0x10
30 #define CEC_TX_CTRL 0x14
31 #define CEC_FREE_TIME_THRESH 0x18
32 #define CEC_BIT_TOUT_THRESH 0x1C
33 #define CEC_BIT_PULSE_THRESH 0x20
34 #define CEC_DATA 0x24
35 #define CEC_TX_ARRAY_CTRL 0x28
36 #define CEC_CTRL2 0x2C
37 #define CEC_TX_ERROR_STS 0x30
38 #define CEC_ADDR_TABLE 0x34
39 #define CEC_DATA_ARRAY_CTRL 0x38
40 #define CEC_DATA_ARRAY_STATUS 0x3C
41 #define CEC_TX_DATA_BASE 0x40
42 #define CEC_TX_DATA_TOP 0x50
43 #define CEC_TX_DATA_SIZE 0x1
44 #define CEC_RX_DATA_BASE 0x54
45 #define CEC_RX_DATA_TOP 0x64
46 #define CEC_RX_DATA_SIZE 0x1
47
48 /* CEC_CTRL2 */
49 #define CEC_LINE_INACTIVE_EN BIT(0)
50 #define CEC_AUTO_BUS_ERR_EN BIT(1)
51 #define CEC_STOP_ON_ARB_ERR_EN BIT(2)
52 #define CEC_TX_REQ_WAIT_EN BIT(3)
53
54 /* CEC_DATA_ARRAY_CTRL */
55 #define CEC_TX_ARRAY_EN BIT(0)
56 #define CEC_RX_ARRAY_EN BIT(1)
57 #define CEC_TX_ARRAY_RESET BIT(2)
58 #define CEC_RX_ARRAY_RESET BIT(3)
59 #define CEC_TX_N_OF_BYTES_IRQ_EN BIT(4)
60 #define CEC_TX_STOP_ON_NACK BIT(7)
61
62 /* CEC_TX_ARRAY_CTRL */
63 #define CEC_TX_N_OF_BYTES 0x1F
64 #define CEC_TX_START BIT(5)
65 #define CEC_TX_AUTO_SOM_EN BIT(6)
66 #define CEC_TX_AUTO_EOM_EN BIT(7)
67
68 /* CEC_IRQ_CTRL */
69 #define CEC_TX_DONE_IRQ_EN BIT(0)
70 #define CEC_ERROR_IRQ_EN BIT(2)
71 #define CEC_RX_DONE_IRQ_EN BIT(3)
72 #define CEC_RX_SOM_IRQ_EN BIT(4)
73 #define CEC_RX_EOM_IRQ_EN BIT(5)
74 #define CEC_FREE_TIME_IRQ_EN BIT(6)
75 #define CEC_PIN_STS_IRQ_EN BIT(7)
76
77 /* CEC_CTRL */
78 #define CEC_IN_FILTER_EN BIT(0)
79 #define CEC_PWR_SAVE_EN BIT(1)
80 #define CEC_EN BIT(4)
81 #define CEC_ACK_CTRL BIT(5)
82 #define CEC_RX_RESET_EN BIT(6)
83 #define CEC_IGNORE_RX_ERROR BIT(7)
84
85 /* CEC_STATUS */
86 #define CEC_TX_DONE_STS BIT(0)
87 #define CEC_TX_ACK_GET_STS BIT(1)
88 #define CEC_ERROR_STS BIT(2)
89 #define CEC_RX_DONE_STS BIT(3)
90 #define CEC_RX_SOM_STS BIT(4)
91 #define CEC_RX_EOM_STS BIT(5)
92 #define CEC_FREE_TIME_IRQ_STS BIT(6)
93 #define CEC_PIN_STS BIT(7)
94 #define CEC_SBIT_TOUT_STS BIT(8)
95 #define CEC_DBIT_TOUT_STS BIT(9)
96 #define CEC_LPULSE_ERROR_STS BIT(10)
97 #define CEC_HPULSE_ERROR_STS BIT(11)
98 #define CEC_TX_ERROR BIT(12)
99 #define CEC_TX_ARB_ERROR BIT(13)
100 #define CEC_RX_ERROR_MIN BIT(14)
101 #define CEC_RX_ERROR_MAX BIT(15)
102
103 /* Signal free time in bit periods (2.4ms) */
104 #define CEC_PRESENT_INIT_SFT 7
105 #define CEC_NEW_INIT_SFT 5
106 #define CEC_RETRANSMIT_SFT 3
107
108 /* Constants for CEC_BIT_TOUT_THRESH register */
109 #define CEC_SBIT_TOUT_47MS BIT(1)
110 #define CEC_SBIT_TOUT_48MS (BIT(0) | BIT(1))
111 #define CEC_SBIT_TOUT_50MS BIT(2)
112 #define CEC_DBIT_TOUT_27MS BIT(0)
113 #define CEC_DBIT_TOUT_28MS BIT(1)
114 #define CEC_DBIT_TOUT_29MS (BIT(0) | BIT(1))
115
116 /* Constants for CEC_BIT_PULSE_THRESH register */
117 #define CEC_BIT_LPULSE_03MS BIT(1)
118 #define CEC_BIT_HPULSE_03MS BIT(3)
119
120 /* Constants for CEC_DATA_ARRAY_STATUS register */
121 #define CEC_RX_N_OF_BYTES 0x1F
122 #define CEC_TX_N_OF_BYTES_SENT BIT(5)
123 #define CEC_RX_OVERRUN BIT(6)
124
125 struct stih_cec {
126 struct cec_adapter *adap;
127 struct device *dev;
128 struct clk *clk;
129 void __iomem *regs;
130 int irq;
131 u32 irq_status;
132 struct cec_notifier *notifier;
133 };
134
stih_cec_adap_enable(struct cec_adapter * adap,bool enable)135 static int stih_cec_adap_enable(struct cec_adapter *adap, bool enable)
136 {
137 struct stih_cec *cec = cec_get_drvdata(adap);
138
139 if (enable) {
140 /* The doc says (input TCLK_PERIOD * CEC_CLK_DIV) = 0.1ms */
141 unsigned long clk_freq = clk_get_rate(cec->clk);
142 u32 cec_clk_div = clk_freq / 10000;
143
144 writel(cec_clk_div, cec->regs + CEC_CLK_DIV);
145
146 /* Configuration of the durations activating a timeout */
147 writel(CEC_SBIT_TOUT_47MS | (CEC_DBIT_TOUT_28MS << 4),
148 cec->regs + CEC_BIT_TOUT_THRESH);
149
150 /* Configuration of the smallest allowed duration for pulses */
151 writel(CEC_BIT_LPULSE_03MS | CEC_BIT_HPULSE_03MS,
152 cec->regs + CEC_BIT_PULSE_THRESH);
153
154 /* Minimum received bit period threshold */
155 writel(BIT(5) | BIT(7), cec->regs + CEC_TX_CTRL);
156
157 /* Configuration of transceiver data arrays */
158 writel(CEC_TX_ARRAY_EN | CEC_RX_ARRAY_EN | CEC_TX_STOP_ON_NACK,
159 cec->regs + CEC_DATA_ARRAY_CTRL);
160
161 /* Configuration of the control bits for CEC Transceiver */
162 writel(CEC_IN_FILTER_EN | CEC_EN | CEC_RX_RESET_EN,
163 cec->regs + CEC_CTRL);
164
165 /* Clear logical addresses */
166 writel(0, cec->regs + CEC_ADDR_TABLE);
167
168 /* Clear the status register */
169 writel(0x0, cec->regs + CEC_STATUS);
170
171 /* Enable the interrupts */
172 writel(CEC_TX_DONE_IRQ_EN | CEC_RX_DONE_IRQ_EN |
173 CEC_RX_SOM_IRQ_EN | CEC_RX_EOM_IRQ_EN |
174 CEC_ERROR_IRQ_EN,
175 cec->regs + CEC_IRQ_CTRL);
176
177 } else {
178 /* Clear logical addresses */
179 writel(0, cec->regs + CEC_ADDR_TABLE);
180
181 /* Clear the status register */
182 writel(0x0, cec->regs + CEC_STATUS);
183
184 /* Disable the interrupts */
185 writel(0, cec->regs + CEC_IRQ_CTRL);
186 }
187
188 return 0;
189 }
190
stih_cec_adap_log_addr(struct cec_adapter * adap,u8 logical_addr)191 static int stih_cec_adap_log_addr(struct cec_adapter *adap, u8 logical_addr)
192 {
193 struct stih_cec *cec = cec_get_drvdata(adap);
194 u32 reg = readl(cec->regs + CEC_ADDR_TABLE);
195
196 reg |= 1 << logical_addr;
197
198 if (logical_addr == CEC_LOG_ADDR_INVALID)
199 reg = 0;
200
201 writel(reg, cec->regs + CEC_ADDR_TABLE);
202
203 return 0;
204 }
205
stih_cec_adap_transmit(struct cec_adapter * adap,u8 attempts,u32 signal_free_time,struct cec_msg * msg)206 static int stih_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
207 u32 signal_free_time, struct cec_msg *msg)
208 {
209 struct stih_cec *cec = cec_get_drvdata(adap);
210 int i;
211
212 /* Copy message into registers */
213 for (i = 0; i < msg->len; i++)
214 writeb(msg->msg[i], cec->regs + CEC_TX_DATA_BASE + i);
215
216 /*
217 * Start transmission, configure hardware to add start and stop bits
218 * Signal free time is handled by the hardware
219 */
220 writel(CEC_TX_AUTO_SOM_EN | CEC_TX_AUTO_EOM_EN | CEC_TX_START |
221 msg->len, cec->regs + CEC_TX_ARRAY_CTRL);
222
223 return 0;
224 }
225
stih_tx_done(struct stih_cec * cec,u32 status)226 static void stih_tx_done(struct stih_cec *cec, u32 status)
227 {
228 if (status & CEC_TX_ERROR) {
229 cec_transmit_attempt_done(cec->adap, CEC_TX_STATUS_ERROR);
230 return;
231 }
232
233 if (status & CEC_TX_ARB_ERROR) {
234 cec_transmit_attempt_done(cec->adap, CEC_TX_STATUS_ARB_LOST);
235 return;
236 }
237
238 if (!(status & CEC_TX_ACK_GET_STS)) {
239 cec_transmit_attempt_done(cec->adap, CEC_TX_STATUS_NACK);
240 return;
241 }
242
243 cec_transmit_attempt_done(cec->adap, CEC_TX_STATUS_OK);
244 }
245
stih_rx_done(struct stih_cec * cec,u32 status)246 static void stih_rx_done(struct stih_cec *cec, u32 status)
247 {
248 struct cec_msg msg = {};
249 u8 i;
250
251 if (status & CEC_RX_ERROR_MIN)
252 return;
253
254 if (status & CEC_RX_ERROR_MAX)
255 return;
256
257 msg.len = readl(cec->regs + CEC_DATA_ARRAY_STATUS) & 0x1f;
258
259 if (!msg.len)
260 return;
261
262 if (msg.len > 16)
263 msg.len = 16;
264
265 for (i = 0; i < msg.len; i++)
266 msg.msg[i] = readl(cec->regs + CEC_RX_DATA_BASE + i);
267
268 cec_received_msg(cec->adap, &msg);
269 }
270
stih_cec_irq_handler_thread(int irq,void * priv)271 static irqreturn_t stih_cec_irq_handler_thread(int irq, void *priv)
272 {
273 struct stih_cec *cec = priv;
274
275 if (cec->irq_status & CEC_TX_DONE_STS)
276 stih_tx_done(cec, cec->irq_status);
277
278 if (cec->irq_status & CEC_RX_DONE_STS)
279 stih_rx_done(cec, cec->irq_status);
280
281 cec->irq_status = 0;
282
283 return IRQ_HANDLED;
284 }
285
stih_cec_irq_handler(int irq,void * priv)286 static irqreturn_t stih_cec_irq_handler(int irq, void *priv)
287 {
288 struct stih_cec *cec = priv;
289
290 cec->irq_status = readl(cec->regs + CEC_STATUS);
291 writel(cec->irq_status, cec->regs + CEC_STATUS);
292
293 return IRQ_WAKE_THREAD;
294 }
295
296 static const struct cec_adap_ops sti_cec_adap_ops = {
297 .adap_enable = stih_cec_adap_enable,
298 .adap_log_addr = stih_cec_adap_log_addr,
299 .adap_transmit = stih_cec_adap_transmit,
300 };
301
stih_cec_probe(struct platform_device * pdev)302 static int stih_cec_probe(struct platform_device *pdev)
303 {
304 struct device *dev = &pdev->dev;
305 struct resource *res;
306 struct stih_cec *cec;
307 struct device_node *np;
308 struct platform_device *hdmi_dev;
309 int ret;
310
311 cec = devm_kzalloc(dev, sizeof(*cec), GFP_KERNEL);
312 if (!cec)
313 return -ENOMEM;
314
315 np = of_parse_phandle(pdev->dev.of_node, "hdmi-phandle", 0);
316
317 if (!np) {
318 dev_err(&pdev->dev, "Failed to find hdmi node in device tree\n");
319 return -ENODEV;
320 }
321
322 hdmi_dev = of_find_device_by_node(np);
323 if (!hdmi_dev)
324 return -EPROBE_DEFER;
325
326 cec->notifier = cec_notifier_get(&hdmi_dev->dev);
327 if (!cec->notifier)
328 return -ENOMEM;
329
330 cec->dev = dev;
331
332 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
333 cec->regs = devm_ioremap_resource(dev, res);
334 if (IS_ERR(cec->regs))
335 return PTR_ERR(cec->regs);
336
337 cec->irq = platform_get_irq(pdev, 0);
338 if (cec->irq < 0)
339 return cec->irq;
340
341 ret = devm_request_threaded_irq(dev, cec->irq, stih_cec_irq_handler,
342 stih_cec_irq_handler_thread, 0,
343 pdev->name, cec);
344 if (ret)
345 return ret;
346
347 cec->clk = devm_clk_get(dev, "cec-clk");
348 if (IS_ERR(cec->clk)) {
349 dev_err(dev, "Cannot get cec clock\n");
350 return PTR_ERR(cec->clk);
351 }
352
353 cec->adap = cec_allocate_adapter(&sti_cec_adap_ops, cec,
354 CEC_NAME, CEC_CAP_DEFAULTS, CEC_MAX_LOG_ADDRS);
355 ret = PTR_ERR_OR_ZERO(cec->adap);
356 if (ret)
357 return ret;
358
359 ret = cec_register_adapter(cec->adap, &pdev->dev);
360 if (ret) {
361 cec_delete_adapter(cec->adap);
362 return ret;
363 }
364
365 cec_register_cec_notifier(cec->adap, cec->notifier);
366
367 platform_set_drvdata(pdev, cec);
368 return 0;
369 }
370
stih_cec_remove(struct platform_device * pdev)371 static int stih_cec_remove(struct platform_device *pdev)
372 {
373 struct stih_cec *cec = platform_get_drvdata(pdev);
374
375 cec_unregister_adapter(cec->adap);
376 cec_notifier_put(cec->notifier);
377
378 return 0;
379 }
380
381 static const struct of_device_id stih_cec_match[] = {
382 {
383 .compatible = "st,stih-cec",
384 },
385 {},
386 };
387 MODULE_DEVICE_TABLE(of, stih_cec_match);
388
389 static struct platform_driver stih_cec_pdrv = {
390 .probe = stih_cec_probe,
391 .remove = stih_cec_remove,
392 .driver = {
393 .name = CEC_NAME,
394 .of_match_table = stih_cec_match,
395 },
396 };
397
398 module_platform_driver(stih_cec_pdrv);
399
400 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@linaro.org>");
401 MODULE_LICENSE("GPL");
402 MODULE_DESCRIPTION("STIH4xx CEC driver");
403