1 /*
2 * Driver for Mediatek IR Receiver Controller
3 *
4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/clk.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/of_platform.h>
21 #include <linux/reset.h>
22 #include <media/rc-core.h>
23
24 #define MTK_IR_DEV KBUILD_MODNAME
25
26 /* Register to enable PWM and IR */
27 #define MTK_CONFIG_HIGH_REG 0x0c
28
29 /* Bit to enable IR pulse width detection */
30 #define MTK_PWM_EN BIT(13)
31
32 /*
33 * Register to setting ok count whose unit based on hardware sampling period
34 * indicating IR receiving completion and then making IRQ fires
35 */
36 #define MTK_OK_COUNT(x) (((x) & GENMASK(23, 16)) << 16)
37
38 /* Bit to enable IR hardware function */
39 #define MTK_IR_EN BIT(0)
40
41 /* Bit to restart IR receiving */
42 #define MTK_IRCLR BIT(0)
43
44 /* Fields containing pulse width data */
45 #define MTK_WIDTH_MASK (GENMASK(7, 0))
46
47 /* IR threshold */
48 #define MTK_IRTHD 0x14
49 #define MTK_DG_CNT_MASK (GENMASK(12, 8))
50 #define MTK_DG_CNT(x) ((x) << 8)
51
52 /* Bit to enable interrupt */
53 #define MTK_IRINT_EN BIT(0)
54
55 /* Bit to clear interrupt status */
56 #define MTK_IRINT_CLR BIT(0)
57
58 /* Maximum count of samples */
59 #define MTK_MAX_SAMPLES 0xff
60 /* Indicate the end of IR message */
61 #define MTK_IR_END(v, p) ((v) == MTK_MAX_SAMPLES && (p) == 0)
62 /* Number of registers to record the pulse width */
63 #define MTK_CHKDATA_SZ 17
64 /* Sample period in ns */
65 #define MTK_IR_SAMPLE 46000
66
67 enum mtk_fields {
68 /* Register to setting software sampling period */
69 MTK_CHK_PERIOD,
70 /* Register to setting hardware sampling period */
71 MTK_HW_PERIOD,
72 };
73
74 enum mtk_regs {
75 /* Register to clear state of state machine */
76 MTK_IRCLR_REG,
77 /* Register containing pulse width data */
78 MTK_CHKDATA_REG,
79 /* Register to enable IR interrupt */
80 MTK_IRINT_EN_REG,
81 /* Register to ack IR interrupt */
82 MTK_IRINT_CLR_REG
83 };
84
85 static const u32 mt7623_regs[] = {
86 [MTK_IRCLR_REG] = 0x20,
87 [MTK_CHKDATA_REG] = 0x88,
88 [MTK_IRINT_EN_REG] = 0xcc,
89 [MTK_IRINT_CLR_REG] = 0xd0,
90 };
91
92 static const u32 mt7622_regs[] = {
93 [MTK_IRCLR_REG] = 0x18,
94 [MTK_CHKDATA_REG] = 0x30,
95 [MTK_IRINT_EN_REG] = 0x1c,
96 [MTK_IRINT_CLR_REG] = 0x20,
97 };
98
99 struct mtk_field_type {
100 u32 reg;
101 u8 offset;
102 u32 mask;
103 };
104
105 /*
106 * struct mtk_ir_data - This is the structure holding all differences among
107 various hardwares
108 * @regs: The pointer to the array holding registers offset
109 * @fields: The pointer to the array holding fields location
110 * @div: The internal divisor for the based reference clock
111 * @ok_count: The count indicating the completion of IR data
112 * receiving when count is reached
113 * @hw_period: The value indicating the hardware sampling period
114 */
115 struct mtk_ir_data {
116 const u32 *regs;
117 const struct mtk_field_type *fields;
118 u8 div;
119 u8 ok_count;
120 u32 hw_period;
121 };
122
123 static const struct mtk_field_type mt7623_fields[] = {
124 [MTK_CHK_PERIOD] = {0x10, 8, GENMASK(20, 8)},
125 [MTK_HW_PERIOD] = {0x10, 0, GENMASK(7, 0)},
126 };
127
128 static const struct mtk_field_type mt7622_fields[] = {
129 [MTK_CHK_PERIOD] = {0x24, 0, GENMASK(24, 0)},
130 [MTK_HW_PERIOD] = {0x10, 0, GENMASK(24, 0)},
131 };
132
133 /*
134 * struct mtk_ir - This is the main datasructure for holding the state
135 * of the driver
136 * @dev: The device pointer
137 * @rc: The rc instrance
138 * @base: The mapped register i/o base
139 * @irq: The IRQ that we are using
140 * @clk: The clock that IR internal is using
141 * @bus: The clock that software decoder is using
142 * @data: Holding specific data for vaious platform
143 */
144 struct mtk_ir {
145 struct device *dev;
146 struct rc_dev *rc;
147 void __iomem *base;
148 int irq;
149 struct clk *clk;
150 struct clk *bus;
151 const struct mtk_ir_data *data;
152 };
153
mtk_chkdata_reg(struct mtk_ir * ir,u32 i)154 static inline u32 mtk_chkdata_reg(struct mtk_ir *ir, u32 i)
155 {
156 return ir->data->regs[MTK_CHKDATA_REG] + 4 * i;
157 }
158
mtk_chk_period(struct mtk_ir * ir)159 static inline u32 mtk_chk_period(struct mtk_ir *ir)
160 {
161 u32 val;
162
163 /* Period of raw software sampling in ns */
164 val = DIV_ROUND_CLOSEST(1000000000ul,
165 clk_get_rate(ir->bus) / ir->data->div);
166
167 /*
168 * Period for software decoder used in the
169 * unit of raw software sampling
170 */
171 val = DIV_ROUND_CLOSEST(MTK_IR_SAMPLE, val);
172
173 dev_dbg(ir->dev, "@pwm clk = \t%lu\n",
174 clk_get_rate(ir->bus) / ir->data->div);
175 dev_dbg(ir->dev, "@chkperiod = %08x\n", val);
176
177 return val;
178 }
179
mtk_w32_mask(struct mtk_ir * ir,u32 val,u32 mask,unsigned int reg)180 static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg)
181 {
182 u32 tmp;
183
184 tmp = __raw_readl(ir->base + reg);
185 tmp = (tmp & ~mask) | val;
186 __raw_writel(tmp, ir->base + reg);
187 }
188
mtk_w32(struct mtk_ir * ir,u32 val,unsigned int reg)189 static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg)
190 {
191 __raw_writel(val, ir->base + reg);
192 }
193
mtk_r32(struct mtk_ir * ir,unsigned int reg)194 static u32 mtk_r32(struct mtk_ir *ir, unsigned int reg)
195 {
196 return __raw_readl(ir->base + reg);
197 }
198
mtk_irq_disable(struct mtk_ir * ir,u32 mask)199 static inline void mtk_irq_disable(struct mtk_ir *ir, u32 mask)
200 {
201 u32 val;
202
203 val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
204 mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]);
205 }
206
mtk_irq_enable(struct mtk_ir * ir,u32 mask)207 static inline void mtk_irq_enable(struct mtk_ir *ir, u32 mask)
208 {
209 u32 val;
210
211 val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
212 mtk_w32(ir, val | mask, ir->data->regs[MTK_IRINT_EN_REG]);
213 }
214
mtk_ir_irq(int irqno,void * dev_id)215 static irqreturn_t mtk_ir_irq(int irqno, void *dev_id)
216 {
217 struct mtk_ir *ir = dev_id;
218 u8 wid = 0;
219 u32 i, j, val;
220 DEFINE_IR_RAW_EVENT(rawir);
221
222 /*
223 * Reset decoder state machine explicitly is required
224 * because 1) the longest duration for space MTK IR hardware
225 * could record is not safely long. e.g 12ms if rx resolution
226 * is 46us by default. There is still the risk to satisfying
227 * every decoder to reset themselves through long enough
228 * trailing spaces and 2) the IRQ handler guarantees that
229 * start of IR message is always contained in and starting
230 * from register mtk_chkdata_reg(ir, i).
231 */
232 ir_raw_event_reset(ir->rc);
233
234 /* First message must be pulse */
235 rawir.pulse = false;
236
237 /* Handle all pulse and space IR controller captures */
238 for (i = 0 ; i < MTK_CHKDATA_SZ ; i++) {
239 val = mtk_r32(ir, mtk_chkdata_reg(ir, i));
240 dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val);
241
242 for (j = 0 ; j < 4 ; j++) {
243 wid = (val & (MTK_WIDTH_MASK << j * 8)) >> j * 8;
244 rawir.pulse = !rawir.pulse;
245 rawir.duration = wid * (MTK_IR_SAMPLE + 1);
246 ir_raw_event_store_with_filter(ir->rc, &rawir);
247 }
248 }
249
250 /*
251 * The maximum number of edges the IR controller can
252 * hold is MTK_CHKDATA_SZ * 4. So if received IR messages
253 * is over the limit, the last incomplete IR message would
254 * be appended trailing space and still would be sent into
255 * ir-rc-raw to decode. That helps it is possible that it
256 * has enough information to decode a scancode even if the
257 * trailing end of the message is missing.
258 */
259 if (!MTK_IR_END(wid, rawir.pulse)) {
260 rawir.pulse = false;
261 rawir.duration = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
262 ir_raw_event_store_with_filter(ir->rc, &rawir);
263 }
264
265 ir_raw_event_handle(ir->rc);
266
267 /*
268 * Restart controller for the next receive that would
269 * clear up all CHKDATA registers
270 */
271 mtk_w32_mask(ir, 0x1, MTK_IRCLR, ir->data->regs[MTK_IRCLR_REG]);
272
273 /* Clear interrupt status */
274 mtk_w32_mask(ir, 0x1, MTK_IRINT_CLR,
275 ir->data->regs[MTK_IRINT_CLR_REG]);
276
277 return IRQ_HANDLED;
278 }
279
280 static const struct mtk_ir_data mt7623_data = {
281 .regs = mt7623_regs,
282 .fields = mt7623_fields,
283 .ok_count = 0xf,
284 .hw_period = 0xff,
285 .div = 4,
286 };
287
288 static const struct mtk_ir_data mt7622_data = {
289 .regs = mt7622_regs,
290 .fields = mt7622_fields,
291 .ok_count = 0xf,
292 .hw_period = 0xffff,
293 .div = 32,
294 };
295
296 static const struct of_device_id mtk_ir_match[] = {
297 { .compatible = "mediatek,mt7623-cir", .data = &mt7623_data},
298 { .compatible = "mediatek,mt7622-cir", .data = &mt7622_data},
299 {},
300 };
301 MODULE_DEVICE_TABLE(of, mtk_ir_match);
302
mtk_ir_probe(struct platform_device * pdev)303 static int mtk_ir_probe(struct platform_device *pdev)
304 {
305 struct device *dev = &pdev->dev;
306 struct device_node *dn = dev->of_node;
307 const struct of_device_id *of_id =
308 of_match_device(mtk_ir_match, &pdev->dev);
309 struct resource *res;
310 struct mtk_ir *ir;
311 u32 val;
312 int ret = 0;
313 const char *map_name;
314
315 ir = devm_kzalloc(dev, sizeof(struct mtk_ir), GFP_KERNEL);
316 if (!ir)
317 return -ENOMEM;
318
319 ir->dev = dev;
320 ir->data = of_id->data;
321
322 ir->clk = devm_clk_get(dev, "clk");
323 if (IS_ERR(ir->clk)) {
324 dev_err(dev, "failed to get a ir clock.\n");
325 return PTR_ERR(ir->clk);
326 }
327
328 ir->bus = devm_clk_get(dev, "bus");
329 if (IS_ERR(ir->bus)) {
330 /*
331 * For compatibility with older device trees try unnamed
332 * ir->bus uses the same clock as ir->clock.
333 */
334 ir->bus = ir->clk;
335 }
336
337 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
338 ir->base = devm_ioremap_resource(dev, res);
339 if (IS_ERR(ir->base)) {
340 dev_err(dev, "failed to map registers\n");
341 return PTR_ERR(ir->base);
342 }
343
344 ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
345 if (!ir->rc) {
346 dev_err(dev, "failed to allocate device\n");
347 return -ENOMEM;
348 }
349
350 ir->rc->priv = ir;
351 ir->rc->device_name = MTK_IR_DEV;
352 ir->rc->input_phys = MTK_IR_DEV "/input0";
353 ir->rc->input_id.bustype = BUS_HOST;
354 ir->rc->input_id.vendor = 0x0001;
355 ir->rc->input_id.product = 0x0001;
356 ir->rc->input_id.version = 0x0001;
357 map_name = of_get_property(dn, "linux,rc-map-name", NULL);
358 ir->rc->map_name = map_name ?: RC_MAP_EMPTY;
359 ir->rc->dev.parent = dev;
360 ir->rc->driver_name = MTK_IR_DEV;
361 ir->rc->allowed_protocols = RC_PROTO_BIT_ALL;
362 ir->rc->rx_resolution = MTK_IR_SAMPLE;
363 ir->rc->timeout = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
364
365 ret = devm_rc_register_device(dev, ir->rc);
366 if (ret) {
367 dev_err(dev, "failed to register rc device\n");
368 return ret;
369 }
370
371 platform_set_drvdata(pdev, ir);
372
373 ir->irq = platform_get_irq(pdev, 0);
374 if (ir->irq < 0) {
375 dev_err(dev, "no irq resource\n");
376 return -ENODEV;
377 }
378
379 if (clk_prepare_enable(ir->clk)) {
380 dev_err(dev, "try to enable ir_clk failed\n");
381 return -EINVAL;
382 }
383
384 if (clk_prepare_enable(ir->bus)) {
385 dev_err(dev, "try to enable ir_clk failed\n");
386 ret = -EINVAL;
387 goto exit_clkdisable_clk;
388 }
389
390 /*
391 * Enable interrupt after proper hardware
392 * setup and IRQ handler registration
393 */
394 mtk_irq_disable(ir, MTK_IRINT_EN);
395
396 ret = devm_request_irq(dev, ir->irq, mtk_ir_irq, 0, MTK_IR_DEV, ir);
397 if (ret) {
398 dev_err(dev, "failed request irq\n");
399 goto exit_clkdisable_bus;
400 }
401
402 /*
403 * Setup software sample period as the reference of software decoder
404 */
405 val = (mtk_chk_period(ir) << ir->data->fields[MTK_CHK_PERIOD].offset) &
406 ir->data->fields[MTK_CHK_PERIOD].mask;
407 mtk_w32_mask(ir, val, ir->data->fields[MTK_CHK_PERIOD].mask,
408 ir->data->fields[MTK_CHK_PERIOD].reg);
409
410 /*
411 * Setup hardware sampling period used to setup the proper timeout for
412 * indicating end of IR receiving completion
413 */
414 val = (ir->data->hw_period << ir->data->fields[MTK_HW_PERIOD].offset) &
415 ir->data->fields[MTK_HW_PERIOD].mask;
416 mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask,
417 ir->data->fields[MTK_HW_PERIOD].reg);
418
419 /* Set de-glitch counter */
420 mtk_w32_mask(ir, MTK_DG_CNT(1), MTK_DG_CNT_MASK, MTK_IRTHD);
421
422 /* Enable IR and PWM */
423 val = mtk_r32(ir, MTK_CONFIG_HIGH_REG);
424 val |= MTK_OK_COUNT(ir->data->ok_count) | MTK_PWM_EN | MTK_IR_EN;
425 mtk_w32(ir, val, MTK_CONFIG_HIGH_REG);
426
427 mtk_irq_enable(ir, MTK_IRINT_EN);
428
429 dev_info(dev, "Initialized MT7623 IR driver, sample period = %dus\n",
430 DIV_ROUND_CLOSEST(MTK_IR_SAMPLE, 1000));
431
432 return 0;
433
434 exit_clkdisable_bus:
435 clk_disable_unprepare(ir->bus);
436 exit_clkdisable_clk:
437 clk_disable_unprepare(ir->clk);
438
439 return ret;
440 }
441
mtk_ir_remove(struct platform_device * pdev)442 static int mtk_ir_remove(struct platform_device *pdev)
443 {
444 struct mtk_ir *ir = platform_get_drvdata(pdev);
445
446 /*
447 * Avoid contention between remove handler and
448 * IRQ handler so that disabling IR interrupt and
449 * waiting for pending IRQ handler to complete
450 */
451 mtk_irq_disable(ir, MTK_IRINT_EN);
452 synchronize_irq(ir->irq);
453
454 clk_disable_unprepare(ir->bus);
455 clk_disable_unprepare(ir->clk);
456
457 return 0;
458 }
459
460 static struct platform_driver mtk_ir_driver = {
461 .probe = mtk_ir_probe,
462 .remove = mtk_ir_remove,
463 .driver = {
464 .name = MTK_IR_DEV,
465 .of_match_table = mtk_ir_match,
466 },
467 };
468
469 module_platform_driver(mtk_ir_driver);
470
471 MODULE_DESCRIPTION("Mediatek IR Receiver Controller Driver");
472 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
473 MODULE_LICENSE("GPL");
474