1 /*
2 *
3 * Intel Management Engine Interface (Intel MEI) Linux driver
4 * Copyright (c) 2003-2012, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 */
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/fs.h>
21 #include <linux/errno.h>
22 #include <linux/types.h>
23 #include <linux/fcntl.h>
24 #include <linux/pci.h>
25 #include <linux/poll.h>
26 #include <linux/ioctl.h>
27 #include <linux/cdev.h>
28 #include <linux/sched.h>
29 #include <linux/uuid.h>
30 #include <linux/compat.h>
31 #include <linux/jiffies.h>
32 #include <linux/interrupt.h>
33
34 #include <linux/pm_domain.h>
35 #include <linux/pm_runtime.h>
36
37 #include <linux/mei.h>
38
39 #include "mei_dev.h"
40 #include "client.h"
41 #include "hw-me-regs.h"
42 #include "hw-me.h"
43
44 /* mei_pci_tbl - PCI Device ID Table */
45 static const struct pci_device_id mei_me_pci_tbl[] = {
46 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
47 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
48 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
49 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
50 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
51 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
54 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
55 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
56 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
57
58 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
59 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
60 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
61 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
62 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
63 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
64 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
65 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
66 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
67
68 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
69 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
70 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
71 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
72
73 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH_CFG)},
74 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH_CFG)},
75 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
76 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
77 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH_CFG)},
78 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH_CFG)},
79 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH_CFG)},
80 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)},
81 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)},
82 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
83 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)},
84 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
85 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
86
87 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
88 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
89 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)},
90 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)},
91 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH8_CFG)},
92
93 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
94 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
95
96 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
97
98 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
99
100 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
101 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
102
103 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH8_CFG)},
104 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_4, MEI_ME_PCH8_CFG)},
105 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH8_CFG)},
106 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_4, MEI_ME_PCH8_CFG)},
107
108 /* required last entry */
109 {0, }
110 };
111
112 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
113
114 #ifdef CONFIG_PM
115 static inline void mei_me_set_pm_domain(struct mei_device *dev);
116 static inline void mei_me_unset_pm_domain(struct mei_device *dev);
117 #else
mei_me_set_pm_domain(struct mei_device * dev)118 static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
mei_me_unset_pm_domain(struct mei_device * dev)119 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
120 #endif /* CONFIG_PM */
121
122 /**
123 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
124 *
125 * @pdev: PCI device structure
126 * @cfg: per generation config
127 *
128 * Return: true if ME Interface is valid, false otherwise
129 */
mei_me_quirk_probe(struct pci_dev * pdev,const struct mei_cfg * cfg)130 static bool mei_me_quirk_probe(struct pci_dev *pdev,
131 const struct mei_cfg *cfg)
132 {
133 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
134 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
135 return false;
136 }
137
138 return true;
139 }
140
141 /**
142 * mei_me_probe - Device Initialization Routine
143 *
144 * @pdev: PCI device structure
145 * @ent: entry in kcs_pci_tbl
146 *
147 * Return: 0 on success, <0 on failure.
148 */
mei_me_probe(struct pci_dev * pdev,const struct pci_device_id * ent)149 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
150 {
151 const struct mei_cfg *cfg;
152 struct mei_device *dev;
153 struct mei_me_hw *hw;
154 unsigned int irqflags;
155 int err;
156
157 cfg = mei_me_get_cfg(ent->driver_data);
158 if (!cfg)
159 return -ENODEV;
160
161 if (!mei_me_quirk_probe(pdev, cfg))
162 return -ENODEV;
163
164 /* enable pci dev */
165 err = pcim_enable_device(pdev);
166 if (err) {
167 dev_err(&pdev->dev, "failed to enable pci device.\n");
168 goto end;
169 }
170 /* set PCI host mastering */
171 pci_set_master(pdev);
172 /* pci request regions and mapping IO device memory for mei driver */
173 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
174 if (err) {
175 dev_err(&pdev->dev, "failed to get pci regions.\n");
176 goto end;
177 }
178
179 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
180 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
181
182 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
183 if (err)
184 err = dma_set_coherent_mask(&pdev->dev,
185 DMA_BIT_MASK(32));
186 }
187 if (err) {
188 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
189 goto end;
190 }
191
192 /* allocates and initializes the mei dev structure */
193 dev = mei_me_dev_init(pdev, cfg);
194 if (!dev) {
195 err = -ENOMEM;
196 goto end;
197 }
198 hw = to_me_hw(dev);
199 hw->mem_addr = pcim_iomap_table(pdev)[0];
200
201 pci_enable_msi(pdev);
202
203 /* request and enable interrupt */
204 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
205
206 err = request_threaded_irq(pdev->irq,
207 mei_me_irq_quick_handler,
208 mei_me_irq_thread_handler,
209 irqflags, KBUILD_MODNAME, dev);
210 if (err) {
211 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
212 pdev->irq);
213 goto end;
214 }
215
216 if (mei_start(dev)) {
217 dev_err(&pdev->dev, "init hw failure.\n");
218 err = -ENODEV;
219 goto release_irq;
220 }
221
222 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
223 pm_runtime_use_autosuspend(&pdev->dev);
224
225 err = mei_register(dev, &pdev->dev);
226 if (err)
227 goto stop;
228
229 pci_set_drvdata(pdev, dev);
230
231 /*
232 * MEI requires to resume from runtime suspend mode
233 * in order to perform link reset flow upon system suspend.
234 */
235 pdev->dev_flags |= PCI_DEV_FLAGS_NEEDS_RESUME;
236
237 /*
238 * ME maps runtime suspend/resume to D0i states,
239 * hence we need to go around native PCI runtime service which
240 * eventually brings the device into D3cold/hot state,
241 * but the mei device cannot wake up from D3 unlike from D0i3.
242 * To get around the PCI device native runtime pm,
243 * ME uses runtime pm domain handlers which take precedence
244 * over the driver's pm handlers.
245 */
246 mei_me_set_pm_domain(dev);
247
248 if (mei_pg_is_enabled(dev)) {
249 pm_runtime_put_noidle(&pdev->dev);
250 if (hw->d0i3_supported)
251 pm_runtime_allow(&pdev->dev);
252 }
253
254 dev_dbg(&pdev->dev, "initialization successful.\n");
255
256 return 0;
257
258 stop:
259 mei_stop(dev);
260 release_irq:
261 mei_cancel_work(dev);
262 mei_disable_interrupts(dev);
263 free_irq(pdev->irq, dev);
264 end:
265 dev_err(&pdev->dev, "initialization failed.\n");
266 return err;
267 }
268
269 /**
270 * mei_me_shutdown - Device Removal Routine
271 *
272 * @pdev: PCI device structure
273 *
274 * mei_me_shutdown is called from the reboot notifier
275 * it's a simplified version of remove so we go down
276 * faster.
277 */
mei_me_shutdown(struct pci_dev * pdev)278 static void mei_me_shutdown(struct pci_dev *pdev)
279 {
280 struct mei_device *dev;
281
282 dev = pci_get_drvdata(pdev);
283 if (!dev)
284 return;
285
286 dev_dbg(&pdev->dev, "shutdown\n");
287 mei_stop(dev);
288
289 mei_me_unset_pm_domain(dev);
290
291 mei_disable_interrupts(dev);
292 free_irq(pdev->irq, dev);
293 }
294
295 /**
296 * mei_me_remove - Device Removal Routine
297 *
298 * @pdev: PCI device structure
299 *
300 * mei_me_remove is called by the PCI subsystem to alert the driver
301 * that it should release a PCI device.
302 */
mei_me_remove(struct pci_dev * pdev)303 static void mei_me_remove(struct pci_dev *pdev)
304 {
305 struct mei_device *dev;
306
307 dev = pci_get_drvdata(pdev);
308 if (!dev)
309 return;
310
311 if (mei_pg_is_enabled(dev))
312 pm_runtime_get_noresume(&pdev->dev);
313
314 dev_dbg(&pdev->dev, "stop\n");
315 mei_stop(dev);
316
317 mei_me_unset_pm_domain(dev);
318
319 mei_disable_interrupts(dev);
320
321 free_irq(pdev->irq, dev);
322
323 mei_deregister(dev);
324 }
325
326 #ifdef CONFIG_PM_SLEEP
mei_me_pci_suspend(struct device * device)327 static int mei_me_pci_suspend(struct device *device)
328 {
329 struct pci_dev *pdev = to_pci_dev(device);
330 struct mei_device *dev = pci_get_drvdata(pdev);
331
332 if (!dev)
333 return -ENODEV;
334
335 dev_dbg(&pdev->dev, "suspend\n");
336
337 mei_stop(dev);
338
339 mei_disable_interrupts(dev);
340
341 free_irq(pdev->irq, dev);
342 pci_disable_msi(pdev);
343
344 return 0;
345 }
346
mei_me_pci_resume(struct device * device)347 static int mei_me_pci_resume(struct device *device)
348 {
349 struct pci_dev *pdev = to_pci_dev(device);
350 struct mei_device *dev;
351 unsigned int irqflags;
352 int err;
353
354 dev = pci_get_drvdata(pdev);
355 if (!dev)
356 return -ENODEV;
357
358 pci_enable_msi(pdev);
359
360 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
361
362 /* request and enable interrupt */
363 err = request_threaded_irq(pdev->irq,
364 mei_me_irq_quick_handler,
365 mei_me_irq_thread_handler,
366 irqflags, KBUILD_MODNAME, dev);
367
368 if (err) {
369 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
370 pdev->irq);
371 return err;
372 }
373
374 err = mei_restart(dev);
375 if (err)
376 return err;
377
378 /* Start timer if stopped in suspend */
379 schedule_delayed_work(&dev->timer_work, HZ);
380
381 return 0;
382 }
383 #endif /* CONFIG_PM_SLEEP */
384
385 #ifdef CONFIG_PM
mei_me_pm_runtime_idle(struct device * device)386 static int mei_me_pm_runtime_idle(struct device *device)
387 {
388 struct pci_dev *pdev = to_pci_dev(device);
389 struct mei_device *dev;
390
391 dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");
392
393 dev = pci_get_drvdata(pdev);
394 if (!dev)
395 return -ENODEV;
396 if (mei_write_is_idle(dev))
397 pm_runtime_autosuspend(device);
398
399 return -EBUSY;
400 }
401
mei_me_pm_runtime_suspend(struct device * device)402 static int mei_me_pm_runtime_suspend(struct device *device)
403 {
404 struct pci_dev *pdev = to_pci_dev(device);
405 struct mei_device *dev;
406 int ret;
407
408 dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");
409
410 dev = pci_get_drvdata(pdev);
411 if (!dev)
412 return -ENODEV;
413
414 mutex_lock(&dev->device_lock);
415
416 if (mei_write_is_idle(dev))
417 ret = mei_me_pg_enter_sync(dev);
418 else
419 ret = -EAGAIN;
420
421 mutex_unlock(&dev->device_lock);
422
423 dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);
424
425 if (ret && ret != -EAGAIN)
426 schedule_work(&dev->reset_work);
427
428 return ret;
429 }
430
mei_me_pm_runtime_resume(struct device * device)431 static int mei_me_pm_runtime_resume(struct device *device)
432 {
433 struct pci_dev *pdev = to_pci_dev(device);
434 struct mei_device *dev;
435 int ret;
436
437 dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");
438
439 dev = pci_get_drvdata(pdev);
440 if (!dev)
441 return -ENODEV;
442
443 mutex_lock(&dev->device_lock);
444
445 ret = mei_me_pg_exit_sync(dev);
446
447 mutex_unlock(&dev->device_lock);
448
449 dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);
450
451 if (ret)
452 schedule_work(&dev->reset_work);
453
454 return ret;
455 }
456
457 /**
458 * mei_me_set_pm_domain - fill and set pm domain structure for device
459 *
460 * @dev: mei_device
461 */
mei_me_set_pm_domain(struct mei_device * dev)462 static inline void mei_me_set_pm_domain(struct mei_device *dev)
463 {
464 struct pci_dev *pdev = to_pci_dev(dev->dev);
465
466 if (pdev->dev.bus && pdev->dev.bus->pm) {
467 dev->pg_domain.ops = *pdev->dev.bus->pm;
468
469 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
470 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
471 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
472
473 dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
474 }
475 }
476
477 /**
478 * mei_me_unset_pm_domain - clean pm domain structure for device
479 *
480 * @dev: mei_device
481 */
mei_me_unset_pm_domain(struct mei_device * dev)482 static inline void mei_me_unset_pm_domain(struct mei_device *dev)
483 {
484 /* stop using pm callbacks if any */
485 dev_pm_domain_set(dev->dev, NULL);
486 }
487
488 static const struct dev_pm_ops mei_me_pm_ops = {
489 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
490 mei_me_pci_resume)
491 SET_RUNTIME_PM_OPS(
492 mei_me_pm_runtime_suspend,
493 mei_me_pm_runtime_resume,
494 mei_me_pm_runtime_idle)
495 };
496
497 #define MEI_ME_PM_OPS (&mei_me_pm_ops)
498 #else
499 #define MEI_ME_PM_OPS NULL
500 #endif /* CONFIG_PM */
501 /*
502 * PCI driver structure
503 */
504 static struct pci_driver mei_me_driver = {
505 .name = KBUILD_MODNAME,
506 .id_table = mei_me_pci_tbl,
507 .probe = mei_me_probe,
508 .remove = mei_me_remove,
509 .shutdown = mei_me_shutdown,
510 .driver.pm = MEI_ME_PM_OPS,
511 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
512 };
513
514 module_pci_driver(mei_me_driver);
515
516 MODULE_AUTHOR("Intel Corporation");
517 MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
518 MODULE_LICENSE("GPL v2");
519