1 /*
2 * Copyright (c) 2014-2015 MediaTek Inc.
3 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/module.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/ioport.h>
20 #include <linux/irq.h>
21 #include <linux/of_address.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_gpio.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/interrupt.h>
32
33 #include <linux/mmc/card.h>
34 #include <linux/mmc/core.h>
35 #include <linux/mmc/host.h>
36 #include <linux/mmc/mmc.h>
37 #include <linux/mmc/sd.h>
38 #include <linux/mmc/sdio.h>
39 #include <linux/mmc/slot-gpio.h>
40
41 #define MAX_BD_NUM 1024
42
43 /*--------------------------------------------------------------------------*/
44 /* Common Definition */
45 /*--------------------------------------------------------------------------*/
46 #define MSDC_BUS_1BITS 0x0
47 #define MSDC_BUS_4BITS 0x1
48 #define MSDC_BUS_8BITS 0x2
49
50 #define MSDC_BURST_64B 0x6
51
52 /*--------------------------------------------------------------------------*/
53 /* Register Offset */
54 /*--------------------------------------------------------------------------*/
55 #define MSDC_CFG 0x0
56 #define MSDC_IOCON 0x04
57 #define MSDC_PS 0x08
58 #define MSDC_INT 0x0c
59 #define MSDC_INTEN 0x10
60 #define MSDC_FIFOCS 0x14
61 #define SDC_CFG 0x30
62 #define SDC_CMD 0x34
63 #define SDC_ARG 0x38
64 #define SDC_STS 0x3c
65 #define SDC_RESP0 0x40
66 #define SDC_RESP1 0x44
67 #define SDC_RESP2 0x48
68 #define SDC_RESP3 0x4c
69 #define SDC_BLK_NUM 0x50
70 #define EMMC_IOCON 0x7c
71 #define SDC_ACMD_RESP 0x80
72 #define MSDC_DMA_SA 0x90
73 #define MSDC_DMA_CTRL 0x98
74 #define MSDC_DMA_CFG 0x9c
75 #define MSDC_PATCH_BIT 0xb0
76 #define MSDC_PATCH_BIT1 0xb4
77 #define MSDC_PAD_TUNE 0xec
78 #define PAD_DS_TUNE 0x188
79 #define PAD_CMD_TUNE 0x18c
80 #define EMMC50_CFG0 0x208
81
82 /*--------------------------------------------------------------------------*/
83 /* Register Mask */
84 /*--------------------------------------------------------------------------*/
85
86 /* MSDC_CFG mask */
87 #define MSDC_CFG_MODE (0x1 << 0) /* RW */
88 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
89 #define MSDC_CFG_RST (0x1 << 2) /* RW */
90 #define MSDC_CFG_PIO (0x1 << 3) /* RW */
91 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
92 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
93 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
94 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */
95 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */
96 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
97 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */
98
99 /* MSDC_IOCON mask */
100 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
101 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
102 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
103 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
104 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
105 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
106 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */
107 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
108 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
109 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
110 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
111 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
112 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
113 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
114 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
115 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
116
117 /* MSDC_PS mask */
118 #define MSDC_PS_CDEN (0x1 << 0) /* RW */
119 #define MSDC_PS_CDSTS (0x1 << 1) /* R */
120 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
121 #define MSDC_PS_DAT (0xff << 16) /* R */
122 #define MSDC_PS_CMD (0x1 << 24) /* R */
123 #define MSDC_PS_WP (0x1 << 31) /* R */
124
125 /* MSDC_INT mask */
126 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
127 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */
128 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
129 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
130 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
131 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
132 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
133 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
134 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
135 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
136 #define MSDC_INT_CSTA (0x1 << 11) /* R */
137 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
138 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
139 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
140 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
141 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
142 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */
143 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */
144 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */
145
146 /* MSDC_INTEN mask */
147 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
148 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
149 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
150 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
151 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
152 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
153 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
154 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
155 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
156 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
157 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
158 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
159 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
160 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
161 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
162 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
163 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */
164 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */
165 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */
166
167 /* MSDC_FIFOCS mask */
168 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
169 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
170 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */
171
172 /* SDC_CFG mask */
173 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
174 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
175 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
176 #define SDC_CFG_SDIO (0x1 << 19) /* RW */
177 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
178 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
179 #define SDC_CFG_DTOC (0xff << 24) /* RW */
180
181 /* SDC_STS mask */
182 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
183 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
184 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
185
186 /* MSDC_DMA_CTRL mask */
187 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
188 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
189 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
190 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
191 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
192 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
193
194 /* MSDC_DMA_CFG mask */
195 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
196 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
197 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */
198 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */
199 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */
200
201 /* MSDC_PATCH_BIT mask */
202 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
203 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
204 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10)
205 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
206 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
207 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
208 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
209 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
210 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
211 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
212 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
213 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
214
215 #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */
216
217 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */
218 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */
219 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */
220 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */
221 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */
222
223 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */
224 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */
225 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */
226
227 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */
228
229 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */
230 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */
231 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */
232
233 #define REQ_CMD_EIO (0x1 << 0)
234 #define REQ_CMD_TMO (0x1 << 1)
235 #define REQ_DAT_ERR (0x1 << 2)
236 #define REQ_STOP_EIO (0x1 << 3)
237 #define REQ_STOP_TMO (0x1 << 4)
238 #define REQ_CMD_BUSY (0x1 << 5)
239
240 #define MSDC_PREPARE_FLAG (0x1 << 0)
241 #define MSDC_ASYNC_FLAG (0x1 << 1)
242 #define MSDC_MMAP_FLAG (0x1 << 2)
243
244 #define MTK_MMC_AUTOSUSPEND_DELAY 50
245 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
246 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
247
248 #define PAD_DELAY_MAX 32 /* PAD delay cells */
249 /*--------------------------------------------------------------------------*/
250 /* Descriptor Structure */
251 /*--------------------------------------------------------------------------*/
252 struct mt_gpdma_desc {
253 u32 gpd_info;
254 #define GPDMA_DESC_HWO (0x1 << 0)
255 #define GPDMA_DESC_BDP (0x1 << 1)
256 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
257 #define GPDMA_DESC_INT (0x1 << 16)
258 u32 next;
259 u32 ptr;
260 u32 gpd_data_len;
261 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
262 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */
263 u32 arg;
264 u32 blknum;
265 u32 cmd;
266 };
267
268 struct mt_bdma_desc {
269 u32 bd_info;
270 #define BDMA_DESC_EOL (0x1 << 0)
271 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
272 #define BDMA_DESC_BLKPAD (0x1 << 17)
273 #define BDMA_DESC_DWPAD (0x1 << 18)
274 u32 next;
275 u32 ptr;
276 u32 bd_data_len;
277 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
278 };
279
280 struct msdc_dma {
281 struct scatterlist *sg; /* I/O scatter list */
282 struct mt_gpdma_desc *gpd; /* pointer to gpd array */
283 struct mt_bdma_desc *bd; /* pointer to bd array */
284 dma_addr_t gpd_addr; /* the physical address of gpd array */
285 dma_addr_t bd_addr; /* the physical address of bd array */
286 };
287
288 struct msdc_save_para {
289 u32 msdc_cfg;
290 u32 iocon;
291 u32 sdc_cfg;
292 u32 pad_tune;
293 u32 patch_bit0;
294 u32 patch_bit1;
295 u32 pad_ds_tune;
296 u32 pad_cmd_tune;
297 u32 emmc50_cfg0;
298 };
299
300 struct msdc_tune_para {
301 u32 iocon;
302 u32 pad_tune;
303 u32 pad_cmd_tune;
304 };
305
306 struct msdc_delay_phase {
307 u8 maxlen;
308 u8 start;
309 u8 final_phase;
310 };
311
312 struct msdc_host {
313 struct device *dev;
314 struct mmc_host *mmc; /* mmc structure */
315 int cmd_rsp;
316
317 spinlock_t lock;
318 struct mmc_request *mrq;
319 struct mmc_command *cmd;
320 struct mmc_data *data;
321 int error;
322
323 void __iomem *base; /* host base address */
324
325 struct msdc_dma dma; /* dma channel */
326 u64 dma_mask;
327
328 u32 timeout_ns; /* data timeout ns */
329 u32 timeout_clks; /* data timeout clks */
330
331 struct pinctrl *pinctrl;
332 struct pinctrl_state *pins_default;
333 struct pinctrl_state *pins_uhs;
334 struct delayed_work req_timeout;
335 int irq; /* host interrupt */
336
337 struct clk *src_clk; /* msdc source clock */
338 struct clk *h_clk; /* msdc h_clk */
339 u32 mclk; /* mmc subsystem clock frequency */
340 u32 src_clk_freq; /* source clock frequency */
341 u32 sclk; /* SD/MS bus clock frequency */
342 unsigned char timing;
343 bool vqmmc_enabled;
344 u32 hs400_ds_delay;
345 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
346 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
347 bool hs400_cmd_resp_sel_rising;
348 /* cmd response sample selection for HS400 */
349 bool hs400_mode; /* current eMMC will run at hs400 mode */
350 struct msdc_save_para save_para; /* used when gate HCLK */
351 struct msdc_tune_para def_tune_para; /* default tune setting */
352 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
353 };
354
sdr_set_bits(void __iomem * reg,u32 bs)355 static void sdr_set_bits(void __iomem *reg, u32 bs)
356 {
357 u32 val = readl(reg);
358
359 val |= bs;
360 writel(val, reg);
361 }
362
sdr_clr_bits(void __iomem * reg,u32 bs)363 static void sdr_clr_bits(void __iomem *reg, u32 bs)
364 {
365 u32 val = readl(reg);
366
367 val &= ~bs;
368 writel(val, reg);
369 }
370
sdr_set_field(void __iomem * reg,u32 field,u32 val)371 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
372 {
373 unsigned int tv = readl(reg);
374
375 tv &= ~field;
376 tv |= ((val) << (ffs((unsigned int)field) - 1));
377 writel(tv, reg);
378 }
379
sdr_get_field(void __iomem * reg,u32 field,u32 * val)380 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
381 {
382 unsigned int tv = readl(reg);
383
384 *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
385 }
386
msdc_reset_hw(struct msdc_host * host)387 static void msdc_reset_hw(struct msdc_host *host)
388 {
389 u32 val;
390
391 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
392 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST)
393 cpu_relax();
394
395 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
396 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR)
397 cpu_relax();
398
399 val = readl(host->base + MSDC_INT);
400 writel(val, host->base + MSDC_INT);
401 }
402
403 static void msdc_cmd_next(struct msdc_host *host,
404 struct mmc_request *mrq, struct mmc_command *cmd);
405
406 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
407 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
408 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
409 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
410 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
411 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
412
msdc_dma_calcs(u8 * buf,u32 len)413 static u8 msdc_dma_calcs(u8 *buf, u32 len)
414 {
415 u32 i, sum = 0;
416
417 for (i = 0; i < len; i++)
418 sum += buf[i];
419 return 0xff - (u8) sum;
420 }
421
msdc_dma_setup(struct msdc_host * host,struct msdc_dma * dma,struct mmc_data * data)422 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
423 struct mmc_data *data)
424 {
425 unsigned int j, dma_len;
426 dma_addr_t dma_address;
427 u32 dma_ctrl;
428 struct scatterlist *sg;
429 struct mt_gpdma_desc *gpd;
430 struct mt_bdma_desc *bd;
431
432 sg = data->sg;
433
434 gpd = dma->gpd;
435 bd = dma->bd;
436
437 /* modify gpd */
438 gpd->gpd_info |= GPDMA_DESC_HWO;
439 gpd->gpd_info |= GPDMA_DESC_BDP;
440 /* need to clear first. use these bits to calc checksum */
441 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
442 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
443
444 /* modify bd */
445 for_each_sg(data->sg, sg, data->sg_count, j) {
446 dma_address = sg_dma_address(sg);
447 dma_len = sg_dma_len(sg);
448
449 /* init bd */
450 bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
451 bd[j].bd_info &= ~BDMA_DESC_DWPAD;
452 bd[j].ptr = (u32)dma_address;
453 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
454 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
455
456 if (j == data->sg_count - 1) /* the last bd */
457 bd[j].bd_info |= BDMA_DESC_EOL;
458 else
459 bd[j].bd_info &= ~BDMA_DESC_EOL;
460
461 /* checksume need to clear first */
462 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
463 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
464 }
465
466 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
467 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
468 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
469 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8);
470 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
471 writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA);
472 }
473
msdc_prepare_data(struct msdc_host * host,struct mmc_request * mrq)474 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq)
475 {
476 struct mmc_data *data = mrq->data;
477
478 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
479 data->host_cookie |= MSDC_PREPARE_FLAG;
480 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
481 mmc_get_dma_dir(data));
482 }
483 }
484
msdc_unprepare_data(struct msdc_host * host,struct mmc_request * mrq)485 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq)
486 {
487 struct mmc_data *data = mrq->data;
488
489 if (data->host_cookie & MSDC_ASYNC_FLAG)
490 return;
491
492 if (data->host_cookie & MSDC_PREPARE_FLAG) {
493 dma_unmap_sg(host->dev, data->sg, data->sg_len,
494 mmc_get_dma_dir(data));
495 data->host_cookie &= ~MSDC_PREPARE_FLAG;
496 }
497 }
498
499 /* clock control primitives */
msdc_set_timeout(struct msdc_host * host,u32 ns,u32 clks)500 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
501 {
502 u32 timeout, clk_ns;
503 u32 mode = 0;
504
505 host->timeout_ns = ns;
506 host->timeout_clks = clks;
507 if (host->sclk == 0) {
508 timeout = 0;
509 } else {
510 clk_ns = 1000000000UL / host->sclk;
511 timeout = (ns + clk_ns - 1) / clk_ns + clks;
512 /* in 1048576 sclk cycle unit */
513 timeout = (timeout + (0x1 << 20) - 1) >> 20;
514 sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode);
515 /*DDR mode will double the clk cycles for data timeout */
516 timeout = mode >= 2 ? timeout * 2 : timeout;
517 timeout = timeout > 1 ? timeout - 1 : 0;
518 timeout = timeout > 255 ? 255 : timeout;
519 }
520 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout);
521 }
522
msdc_gate_clock(struct msdc_host * host)523 static void msdc_gate_clock(struct msdc_host *host)
524 {
525 clk_disable_unprepare(host->src_clk);
526 clk_disable_unprepare(host->h_clk);
527 }
528
msdc_ungate_clock(struct msdc_host * host)529 static void msdc_ungate_clock(struct msdc_host *host)
530 {
531 clk_prepare_enable(host->h_clk);
532 clk_prepare_enable(host->src_clk);
533 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
534 cpu_relax();
535 }
536
msdc_set_mclk(struct msdc_host * host,unsigned char timing,u32 hz)537 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
538 {
539 u32 mode;
540 u32 flags;
541 u32 div;
542 u32 sclk;
543
544 if (!hz) {
545 dev_dbg(host->dev, "set mclk to 0\n");
546 host->mclk = 0;
547 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
548 return;
549 }
550
551 flags = readl(host->base + MSDC_INTEN);
552 sdr_clr_bits(host->base + MSDC_INTEN, flags);
553 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
554 if (timing == MMC_TIMING_UHS_DDR50 ||
555 timing == MMC_TIMING_MMC_DDR52 ||
556 timing == MMC_TIMING_MMC_HS400) {
557 if (timing == MMC_TIMING_MMC_HS400)
558 mode = 0x3;
559 else
560 mode = 0x2; /* ddr mode and use divisor */
561
562 if (hz >= (host->src_clk_freq >> 2)) {
563 div = 0; /* mean div = 1/4 */
564 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
565 } else {
566 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
567 sclk = (host->src_clk_freq >> 2) / div;
568 div = (div >> 1);
569 }
570
571 if (timing == MMC_TIMING_MMC_HS400 &&
572 hz >= (host->src_clk_freq >> 1)) {
573 sdr_set_bits(host->base + MSDC_CFG,
574 MSDC_CFG_HS400_CK_MODE);
575 sclk = host->src_clk_freq >> 1;
576 div = 0; /* div is ignore when bit18 is set */
577 }
578 } else if (hz >= host->src_clk_freq) {
579 mode = 0x1; /* no divisor */
580 div = 0;
581 sclk = host->src_clk_freq;
582 } else {
583 mode = 0x0; /* use divisor */
584 if (hz >= (host->src_clk_freq >> 1)) {
585 div = 0; /* mean div = 1/2 */
586 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
587 } else {
588 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
589 sclk = (host->src_clk_freq >> 2) / div;
590 }
591 }
592 sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
593 (mode << 8) | div);
594 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
595 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
596 cpu_relax();
597 host->sclk = sclk;
598 host->mclk = hz;
599 host->timing = timing;
600 /* need because clk changed. */
601 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
602 sdr_set_bits(host->base + MSDC_INTEN, flags);
603
604 /*
605 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
606 * tune result of hs200/200Mhz is not suitable for 50Mhz
607 */
608 if (host->sclk <= 52000000) {
609 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
610 writel(host->def_tune_para.pad_tune, host->base + MSDC_PAD_TUNE);
611 } else {
612 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
613 writel(host->saved_tune_para.pad_tune, host->base + MSDC_PAD_TUNE);
614 writel(host->saved_tune_para.pad_cmd_tune,
615 host->base + PAD_CMD_TUNE);
616 }
617
618 if (timing == MMC_TIMING_MMC_HS400)
619 sdr_set_field(host->base + PAD_CMD_TUNE,
620 MSDC_PAD_TUNE_CMDRRDLY,
621 host->hs400_cmd_int_delay);
622 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->sclk, timing);
623 }
624
msdc_cmd_find_resp(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)625 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
626 struct mmc_request *mrq, struct mmc_command *cmd)
627 {
628 u32 resp;
629
630 switch (mmc_resp_type(cmd)) {
631 /* Actually, R1, R5, R6, R7 are the same */
632 case MMC_RSP_R1:
633 resp = 0x1;
634 break;
635 case MMC_RSP_R1B:
636 resp = 0x7;
637 break;
638 case MMC_RSP_R2:
639 resp = 0x2;
640 break;
641 case MMC_RSP_R3:
642 resp = 0x3;
643 break;
644 case MMC_RSP_NONE:
645 default:
646 resp = 0x0;
647 break;
648 }
649
650 return resp;
651 }
652
msdc_cmd_prepare_raw_cmd(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)653 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
654 struct mmc_request *mrq, struct mmc_command *cmd)
655 {
656 /* rawcmd :
657 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
658 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
659 */
660 u32 opcode = cmd->opcode;
661 u32 resp = msdc_cmd_find_resp(host, mrq, cmd);
662 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
663
664 host->cmd_rsp = resp;
665
666 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
667 opcode == MMC_STOP_TRANSMISSION)
668 rawcmd |= (0x1 << 14);
669 else if (opcode == SD_SWITCH_VOLTAGE)
670 rawcmd |= (0x1 << 30);
671 else if (opcode == SD_APP_SEND_SCR ||
672 opcode == SD_APP_SEND_NUM_WR_BLKS ||
673 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
674 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
675 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
676 rawcmd |= (0x1 << 11);
677
678 if (cmd->data) {
679 struct mmc_data *data = cmd->data;
680
681 if (mmc_op_multi(opcode)) {
682 if (mmc_card_mmc(host->mmc->card) && mrq->sbc &&
683 !(mrq->sbc->arg & 0xFFFF0000))
684 rawcmd |= 0x2 << 28; /* AutoCMD23 */
685 }
686
687 rawcmd |= ((data->blksz & 0xFFF) << 16);
688 if (data->flags & MMC_DATA_WRITE)
689 rawcmd |= (0x1 << 13);
690 if (data->blocks > 1)
691 rawcmd |= (0x2 << 11);
692 else
693 rawcmd |= (0x1 << 11);
694 /* Always use dma mode */
695 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
696
697 if (host->timeout_ns != data->timeout_ns ||
698 host->timeout_clks != data->timeout_clks)
699 msdc_set_timeout(host, data->timeout_ns,
700 data->timeout_clks);
701
702 writel(data->blocks, host->base + SDC_BLK_NUM);
703 }
704 return rawcmd;
705 }
706
msdc_start_data(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd,struct mmc_data * data)707 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq,
708 struct mmc_command *cmd, struct mmc_data *data)
709 {
710 bool read;
711
712 WARN_ON(host->data);
713 host->data = data;
714 read = data->flags & MMC_DATA_READ;
715
716 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
717 msdc_dma_setup(host, &host->dma, data);
718 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
719 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
720 dev_dbg(host->dev, "DMA start\n");
721 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
722 __func__, cmd->opcode, data->blocks, read);
723 }
724
msdc_auto_cmd_done(struct msdc_host * host,int events,struct mmc_command * cmd)725 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
726 struct mmc_command *cmd)
727 {
728 u32 *rsp = cmd->resp;
729
730 rsp[0] = readl(host->base + SDC_ACMD_RESP);
731
732 if (events & MSDC_INT_ACMDRDY) {
733 cmd->error = 0;
734 } else {
735 msdc_reset_hw(host);
736 if (events & MSDC_INT_ACMDCRCERR) {
737 cmd->error = -EILSEQ;
738 host->error |= REQ_STOP_EIO;
739 } else if (events & MSDC_INT_ACMDTMO) {
740 cmd->error = -ETIMEDOUT;
741 host->error |= REQ_STOP_TMO;
742 }
743 dev_err(host->dev,
744 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
745 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
746 }
747 return cmd->error;
748 }
749
msdc_track_cmd_data(struct msdc_host * host,struct mmc_command * cmd,struct mmc_data * data)750 static void msdc_track_cmd_data(struct msdc_host *host,
751 struct mmc_command *cmd, struct mmc_data *data)
752 {
753 if (host->error)
754 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
755 __func__, cmd->opcode, cmd->arg, host->error);
756 }
757
msdc_request_done(struct msdc_host * host,struct mmc_request * mrq)758 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
759 {
760 unsigned long flags;
761 bool ret;
762
763 ret = cancel_delayed_work(&host->req_timeout);
764 if (!ret) {
765 /* delay work already running */
766 return;
767 }
768 spin_lock_irqsave(&host->lock, flags);
769 host->mrq = NULL;
770 spin_unlock_irqrestore(&host->lock, flags);
771
772 msdc_track_cmd_data(host, mrq->cmd, mrq->data);
773 if (mrq->data)
774 msdc_unprepare_data(host, mrq);
775 mmc_request_done(host->mmc, mrq);
776 }
777
778 /* returns true if command is fully handled; returns false otherwise */
msdc_cmd_done(struct msdc_host * host,int events,struct mmc_request * mrq,struct mmc_command * cmd)779 static bool msdc_cmd_done(struct msdc_host *host, int events,
780 struct mmc_request *mrq, struct mmc_command *cmd)
781 {
782 bool done = false;
783 bool sbc_error;
784 unsigned long flags;
785 u32 *rsp = cmd->resp;
786
787 if (mrq->sbc && cmd == mrq->cmd &&
788 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
789 | MSDC_INT_ACMDTMO)))
790 msdc_auto_cmd_done(host, events, mrq->sbc);
791
792 sbc_error = mrq->sbc && mrq->sbc->error;
793
794 if (!sbc_error && !(events & (MSDC_INT_CMDRDY
795 | MSDC_INT_RSPCRCERR
796 | MSDC_INT_CMDTMO)))
797 return done;
798
799 spin_lock_irqsave(&host->lock, flags);
800 done = !host->cmd;
801 host->cmd = NULL;
802 spin_unlock_irqrestore(&host->lock, flags);
803
804 if (done)
805 return true;
806
807 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
808
809 if (cmd->flags & MMC_RSP_PRESENT) {
810 if (cmd->flags & MMC_RSP_136) {
811 rsp[0] = readl(host->base + SDC_RESP3);
812 rsp[1] = readl(host->base + SDC_RESP2);
813 rsp[2] = readl(host->base + SDC_RESP1);
814 rsp[3] = readl(host->base + SDC_RESP0);
815 } else {
816 rsp[0] = readl(host->base + SDC_RESP0);
817 }
818 }
819
820 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
821 if (cmd->opcode != MMC_SEND_TUNING_BLOCK &&
822 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
823 /*
824 * should not clear fifo/interrupt as the tune data
825 * may have alreay come.
826 */
827 msdc_reset_hw(host);
828 if (events & MSDC_INT_RSPCRCERR) {
829 cmd->error = -EILSEQ;
830 host->error |= REQ_CMD_EIO;
831 } else if (events & MSDC_INT_CMDTMO) {
832 cmd->error = -ETIMEDOUT;
833 host->error |= REQ_CMD_TMO;
834 }
835 }
836 if (cmd->error)
837 dev_dbg(host->dev,
838 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
839 __func__, cmd->opcode, cmd->arg, rsp[0],
840 cmd->error);
841
842 msdc_cmd_next(host, mrq, cmd);
843 return true;
844 }
845
846 /* It is the core layer's responsibility to ensure card status
847 * is correct before issue a request. but host design do below
848 * checks recommended.
849 */
msdc_cmd_is_ready(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)850 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
851 struct mmc_request *mrq, struct mmc_command *cmd)
852 {
853 /* The max busy time we can endure is 20ms */
854 unsigned long tmo = jiffies + msecs_to_jiffies(20);
855
856 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) &&
857 time_before(jiffies, tmo))
858 cpu_relax();
859 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) {
860 dev_err(host->dev, "CMD bus busy detected\n");
861 host->error |= REQ_CMD_BUSY;
862 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
863 return false;
864 }
865
866 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
867 tmo = jiffies + msecs_to_jiffies(20);
868 /* R1B or with data, should check SDCBUSY */
869 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) &&
870 time_before(jiffies, tmo))
871 cpu_relax();
872 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) {
873 dev_err(host->dev, "Controller busy detected\n");
874 host->error |= REQ_CMD_BUSY;
875 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
876 return false;
877 }
878 }
879 return true;
880 }
881
msdc_start_command(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)882 static void msdc_start_command(struct msdc_host *host,
883 struct mmc_request *mrq, struct mmc_command *cmd)
884 {
885 u32 rawcmd;
886
887 WARN_ON(host->cmd);
888 host->cmd = cmd;
889
890 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
891 if (!msdc_cmd_is_ready(host, mrq, cmd))
892 return;
893
894 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
895 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
896 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
897 msdc_reset_hw(host);
898 }
899
900 cmd->error = 0;
901 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
902
903 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
904 writel(cmd->arg, host->base + SDC_ARG);
905 writel(rawcmd, host->base + SDC_CMD);
906 }
907
msdc_cmd_next(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)908 static void msdc_cmd_next(struct msdc_host *host,
909 struct mmc_request *mrq, struct mmc_command *cmd)
910 {
911 if ((cmd->error &&
912 !(cmd->error == -EILSEQ &&
913 (cmd->opcode == MMC_SEND_TUNING_BLOCK ||
914 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) ||
915 (mrq->sbc && mrq->sbc->error))
916 msdc_request_done(host, mrq);
917 else if (cmd == mrq->sbc)
918 msdc_start_command(host, mrq, mrq->cmd);
919 else if (!cmd->data)
920 msdc_request_done(host, mrq);
921 else
922 msdc_start_data(host, mrq, cmd, cmd->data);
923 }
924
msdc_ops_request(struct mmc_host * mmc,struct mmc_request * mrq)925 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
926 {
927 struct msdc_host *host = mmc_priv(mmc);
928
929 host->error = 0;
930 WARN_ON(host->mrq);
931 host->mrq = mrq;
932
933 if (mrq->data)
934 msdc_prepare_data(host, mrq);
935
936 /* if SBC is required, we have HW option and SW option.
937 * if HW option is enabled, and SBC does not have "special" flags,
938 * use HW option, otherwise use SW option
939 */
940 if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
941 (mrq->sbc->arg & 0xFFFF0000)))
942 msdc_start_command(host, mrq, mrq->sbc);
943 else
944 msdc_start_command(host, mrq, mrq->cmd);
945 }
946
msdc_pre_req(struct mmc_host * mmc,struct mmc_request * mrq)947 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
948 {
949 struct msdc_host *host = mmc_priv(mmc);
950 struct mmc_data *data = mrq->data;
951
952 if (!data)
953 return;
954
955 msdc_prepare_data(host, mrq);
956 data->host_cookie |= MSDC_ASYNC_FLAG;
957 }
958
msdc_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)959 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
960 int err)
961 {
962 struct msdc_host *host = mmc_priv(mmc);
963 struct mmc_data *data;
964
965 data = mrq->data;
966 if (!data)
967 return;
968 if (data->host_cookie) {
969 data->host_cookie &= ~MSDC_ASYNC_FLAG;
970 msdc_unprepare_data(host, mrq);
971 }
972 }
973
msdc_data_xfer_next(struct msdc_host * host,struct mmc_request * mrq,struct mmc_data * data)974 static void msdc_data_xfer_next(struct msdc_host *host,
975 struct mmc_request *mrq, struct mmc_data *data)
976 {
977 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
978 !mrq->sbc)
979 msdc_start_command(host, mrq, mrq->stop);
980 else
981 msdc_request_done(host, mrq);
982 }
983
msdc_data_xfer_done(struct msdc_host * host,u32 events,struct mmc_request * mrq,struct mmc_data * data)984 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
985 struct mmc_request *mrq, struct mmc_data *data)
986 {
987 struct mmc_command *stop = data->stop;
988 unsigned long flags;
989 bool done;
990 unsigned int check_data = events &
991 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
992 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
993 | MSDC_INT_DMA_PROTECT);
994
995 spin_lock_irqsave(&host->lock, flags);
996 done = !host->data;
997 if (check_data)
998 host->data = NULL;
999 spin_unlock_irqrestore(&host->lock, flags);
1000
1001 if (done)
1002 return true;
1003
1004 if (check_data || (stop && stop->error)) {
1005 dev_dbg(host->dev, "DMA status: 0x%8X\n",
1006 readl(host->base + MSDC_DMA_CFG));
1007 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1008 1);
1009 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
1010 cpu_relax();
1011 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1012 dev_dbg(host->dev, "DMA stop\n");
1013
1014 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1015 data->bytes_xfered = data->blocks * data->blksz;
1016 } else {
1017 dev_dbg(host->dev, "interrupt events: %x\n", events);
1018 msdc_reset_hw(host);
1019 host->error |= REQ_DAT_ERR;
1020 data->bytes_xfered = 0;
1021
1022 if (events & MSDC_INT_DATTMO)
1023 data->error = -ETIMEDOUT;
1024 else if (events & MSDC_INT_DATCRCERR)
1025 data->error = -EILSEQ;
1026
1027 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1028 __func__, mrq->cmd->opcode, data->blocks);
1029 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1030 (int)data->error, data->bytes_xfered);
1031 }
1032
1033 msdc_data_xfer_next(host, mrq, data);
1034 done = true;
1035 }
1036 return done;
1037 }
1038
msdc_set_buswidth(struct msdc_host * host,u32 width)1039 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1040 {
1041 u32 val = readl(host->base + SDC_CFG);
1042
1043 val &= ~SDC_CFG_BUSWIDTH;
1044
1045 switch (width) {
1046 default:
1047 case MMC_BUS_WIDTH_1:
1048 val |= (MSDC_BUS_1BITS << 16);
1049 break;
1050 case MMC_BUS_WIDTH_4:
1051 val |= (MSDC_BUS_4BITS << 16);
1052 break;
1053 case MMC_BUS_WIDTH_8:
1054 val |= (MSDC_BUS_8BITS << 16);
1055 break;
1056 }
1057
1058 writel(val, host->base + SDC_CFG);
1059 dev_dbg(host->dev, "Bus Width = %d", width);
1060 }
1061
msdc_ops_switch_volt(struct mmc_host * mmc,struct mmc_ios * ios)1062 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1063 {
1064 struct msdc_host *host = mmc_priv(mmc);
1065 int ret = 0;
1066
1067 if (!IS_ERR(mmc->supply.vqmmc)) {
1068 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1069 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1070 dev_err(host->dev, "Unsupported signal voltage!\n");
1071 return -EINVAL;
1072 }
1073
1074 ret = mmc_regulator_set_vqmmc(mmc, ios);
1075 if (ret) {
1076 dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1077 ret, ios->signal_voltage);
1078 } else {
1079 /* Apply different pinctrl settings for different signal voltage */
1080 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1081 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1082 else
1083 pinctrl_select_state(host->pinctrl, host->pins_default);
1084 }
1085 }
1086 return ret;
1087 }
1088
msdc_card_busy(struct mmc_host * mmc)1089 static int msdc_card_busy(struct mmc_host *mmc)
1090 {
1091 struct msdc_host *host = mmc_priv(mmc);
1092 u32 status = readl(host->base + MSDC_PS);
1093
1094 /* only check if data0 is low */
1095 return !(status & BIT(16));
1096 }
1097
msdc_request_timeout(struct work_struct * work)1098 static void msdc_request_timeout(struct work_struct *work)
1099 {
1100 struct msdc_host *host = container_of(work, struct msdc_host,
1101 req_timeout.work);
1102
1103 /* simulate HW timeout status */
1104 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1105 if (host->mrq) {
1106 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1107 host->mrq, host->mrq->cmd->opcode);
1108 if (host->cmd) {
1109 dev_err(host->dev, "%s: aborting cmd=%d\n",
1110 __func__, host->cmd->opcode);
1111 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1112 host->cmd);
1113 } else if (host->data) {
1114 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1115 __func__, host->mrq->cmd->opcode,
1116 host->data->blocks);
1117 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1118 host->data);
1119 }
1120 }
1121 }
1122
msdc_irq(int irq,void * dev_id)1123 static irqreturn_t msdc_irq(int irq, void *dev_id)
1124 {
1125 struct msdc_host *host = (struct msdc_host *) dev_id;
1126
1127 while (true) {
1128 unsigned long flags;
1129 struct mmc_request *mrq;
1130 struct mmc_command *cmd;
1131 struct mmc_data *data;
1132 u32 events, event_mask;
1133
1134 spin_lock_irqsave(&host->lock, flags);
1135 events = readl(host->base + MSDC_INT);
1136 event_mask = readl(host->base + MSDC_INTEN);
1137 /* clear interrupts */
1138 writel(events & event_mask, host->base + MSDC_INT);
1139
1140 mrq = host->mrq;
1141 cmd = host->cmd;
1142 data = host->data;
1143 spin_unlock_irqrestore(&host->lock, flags);
1144
1145 if (!(events & event_mask))
1146 break;
1147
1148 if (!mrq) {
1149 dev_err(host->dev,
1150 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1151 __func__, events, event_mask);
1152 WARN_ON(1);
1153 break;
1154 }
1155
1156 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1157
1158 if (cmd)
1159 msdc_cmd_done(host, events, mrq, cmd);
1160 else if (data)
1161 msdc_data_xfer_done(host, events, mrq, data);
1162 }
1163
1164 return IRQ_HANDLED;
1165 }
1166
msdc_init_hw(struct msdc_host * host)1167 static void msdc_init_hw(struct msdc_host *host)
1168 {
1169 u32 val;
1170
1171 /* Configure to MMC/SD mode, clock free running */
1172 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1173
1174 /* Reset */
1175 msdc_reset_hw(host);
1176
1177 /* Disable card detection */
1178 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1179
1180 /* Disable and clear all interrupts */
1181 writel(0, host->base + MSDC_INTEN);
1182 val = readl(host->base + MSDC_INT);
1183 writel(val, host->base + MSDC_INT);
1184
1185 writel(0, host->base + MSDC_PAD_TUNE);
1186 writel(0, host->base + MSDC_IOCON);
1187 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1188 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1189 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1190 writel(0xffff0089, host->base + MSDC_PATCH_BIT1);
1191 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1192
1193 /* Configure to enable SDIO mode.
1194 * it's must otherwise sdio cmd5 failed
1195 */
1196 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1197
1198 /* disable detect SDIO device interrupt function */
1199 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1200
1201 /* Configure to default data timeout */
1202 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1203
1204 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1205 host->def_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
1206 dev_dbg(host->dev, "init hardware done!");
1207 }
1208
msdc_deinit_hw(struct msdc_host * host)1209 static void msdc_deinit_hw(struct msdc_host *host)
1210 {
1211 u32 val;
1212 /* Disable and clear all interrupts */
1213 writel(0, host->base + MSDC_INTEN);
1214
1215 val = readl(host->base + MSDC_INT);
1216 writel(val, host->base + MSDC_INT);
1217 }
1218
1219 /* init gpd and bd list in msdc_drv_probe */
msdc_init_gpd_bd(struct msdc_host * host,struct msdc_dma * dma)1220 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1221 {
1222 struct mt_gpdma_desc *gpd = dma->gpd;
1223 struct mt_bdma_desc *bd = dma->bd;
1224 int i;
1225
1226 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1227
1228 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1229 gpd->ptr = (u32)dma->bd_addr; /* physical address */
1230 /* gpd->next is must set for desc DMA
1231 * That's why must alloc 2 gpd structure.
1232 */
1233 gpd->next = (u32)dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1234 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1235 for (i = 0; i < (MAX_BD_NUM - 1); i++)
1236 bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1);
1237 }
1238
msdc_ops_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1239 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1240 {
1241 struct msdc_host *host = mmc_priv(mmc);
1242 int ret;
1243
1244 msdc_set_buswidth(host, ios->bus_width);
1245
1246 /* Suspend/Resume will do power off/on */
1247 switch (ios->power_mode) {
1248 case MMC_POWER_UP:
1249 if (!IS_ERR(mmc->supply.vmmc)) {
1250 msdc_init_hw(host);
1251 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1252 ios->vdd);
1253 if (ret) {
1254 dev_err(host->dev, "Failed to set vmmc power!\n");
1255 return;
1256 }
1257 }
1258 break;
1259 case MMC_POWER_ON:
1260 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1261 ret = regulator_enable(mmc->supply.vqmmc);
1262 if (ret)
1263 dev_err(host->dev, "Failed to set vqmmc power!\n");
1264 else
1265 host->vqmmc_enabled = true;
1266 }
1267 break;
1268 case MMC_POWER_OFF:
1269 if (!IS_ERR(mmc->supply.vmmc))
1270 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1271
1272 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1273 regulator_disable(mmc->supply.vqmmc);
1274 host->vqmmc_enabled = false;
1275 }
1276 break;
1277 default:
1278 break;
1279 }
1280
1281 if (host->mclk != ios->clock || host->timing != ios->timing)
1282 msdc_set_mclk(host, ios->timing, ios->clock);
1283 }
1284
test_delay_bit(u32 delay,u32 bit)1285 static u32 test_delay_bit(u32 delay, u32 bit)
1286 {
1287 bit %= PAD_DELAY_MAX;
1288 return delay & (1 << bit);
1289 }
1290
get_delay_len(u32 delay,u32 start_bit)1291 static int get_delay_len(u32 delay, u32 start_bit)
1292 {
1293 int i;
1294
1295 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
1296 if (test_delay_bit(delay, start_bit + i) == 0)
1297 return i;
1298 }
1299 return PAD_DELAY_MAX - start_bit;
1300 }
1301
get_best_delay(struct msdc_host * host,u32 delay)1302 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1303 {
1304 int start = 0, len = 0;
1305 int start_final = 0, len_final = 0;
1306 u8 final_phase = 0xff;
1307 struct msdc_delay_phase delay_phase = { 0, };
1308
1309 if (delay == 0) {
1310 dev_err(host->dev, "phase error: [map:%x]\n", delay);
1311 delay_phase.final_phase = final_phase;
1312 return delay_phase;
1313 }
1314
1315 while (start < PAD_DELAY_MAX) {
1316 len = get_delay_len(delay, start);
1317 if (len_final < len) {
1318 start_final = start;
1319 len_final = len;
1320 }
1321 start += len ? len : 1;
1322 if (len >= 12 && start_final < 4)
1323 break;
1324 }
1325
1326 /* The rule is that to find the smallest delay cell */
1327 if (start_final == 0)
1328 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
1329 else
1330 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
1331 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1332 delay, len_final, final_phase);
1333
1334 delay_phase.maxlen = len_final;
1335 delay_phase.start = start_final;
1336 delay_phase.final_phase = final_phase;
1337 return delay_phase;
1338 }
1339
msdc_tune_response(struct mmc_host * mmc,u32 opcode)1340 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
1341 {
1342 struct msdc_host *host = mmc_priv(mmc);
1343 u32 rise_delay = 0, fall_delay = 0;
1344 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1345 struct msdc_delay_phase internal_delay_phase;
1346 u8 final_delay, final_maxlen;
1347 u32 internal_delay = 0;
1348 int cmd_err;
1349 int i, j;
1350
1351 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
1352 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
1353 sdr_set_field(host->base + MSDC_PAD_TUNE,
1354 MSDC_PAD_TUNE_CMDRRDLY,
1355 host->hs200_cmd_int_delay);
1356
1357 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1358 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1359 sdr_set_field(host->base + MSDC_PAD_TUNE,
1360 MSDC_PAD_TUNE_CMDRDLY, i);
1361 /*
1362 * Using the same parameters, it may sometimes pass the test,
1363 * but sometimes it may fail. To make sure the parameters are
1364 * more stable, we test each set of parameters 3 times.
1365 */
1366 for (j = 0; j < 3; j++) {
1367 mmc_send_tuning(mmc, opcode, &cmd_err);
1368 if (!cmd_err) {
1369 rise_delay |= (1 << i);
1370 } else {
1371 rise_delay &= ~(1 << i);
1372 break;
1373 }
1374 }
1375 }
1376 final_rise_delay = get_best_delay(host, rise_delay);
1377 /* if rising edge has enough margin, then do not scan falling edge */
1378 if (final_rise_delay.maxlen >= 12 && final_rise_delay.start < 4)
1379 goto skip_fall;
1380
1381 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1382 for (i = 0; i < PAD_DELAY_MAX; i++) {
1383 sdr_set_field(host->base + MSDC_PAD_TUNE,
1384 MSDC_PAD_TUNE_CMDRDLY, i);
1385 /*
1386 * Using the same parameters, it may sometimes pass the test,
1387 * but sometimes it may fail. To make sure the parameters are
1388 * more stable, we test each set of parameters 3 times.
1389 */
1390 for (j = 0; j < 3; j++) {
1391 mmc_send_tuning(mmc, opcode, &cmd_err);
1392 if (!cmd_err) {
1393 fall_delay |= (1 << i);
1394 } else {
1395 fall_delay &= ~(1 << i);
1396 break;
1397 }
1398 }
1399 }
1400 final_fall_delay = get_best_delay(host, fall_delay);
1401
1402 skip_fall:
1403 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1404 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
1405 final_maxlen = final_fall_delay.maxlen;
1406 if (final_maxlen == final_rise_delay.maxlen) {
1407 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1408 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
1409 final_rise_delay.final_phase);
1410 final_delay = final_rise_delay.final_phase;
1411 } else {
1412 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1413 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
1414 final_fall_delay.final_phase);
1415 final_delay = final_fall_delay.final_phase;
1416 }
1417 if (host->hs200_cmd_int_delay)
1418 goto skip_internal;
1419
1420 for (i = 0; i < PAD_DELAY_MAX; i++) {
1421 sdr_set_field(host->base + MSDC_PAD_TUNE,
1422 MSDC_PAD_TUNE_CMDRRDLY, i);
1423 mmc_send_tuning(mmc, opcode, &cmd_err);
1424 if (!cmd_err)
1425 internal_delay |= (1 << i);
1426 }
1427 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
1428 internal_delay_phase = get_best_delay(host, internal_delay);
1429 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY,
1430 internal_delay_phase.final_phase);
1431 skip_internal:
1432 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
1433 return final_delay == 0xff ? -EIO : 0;
1434 }
1435
hs400_tune_response(struct mmc_host * mmc,u32 opcode)1436 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
1437 {
1438 struct msdc_host *host = mmc_priv(mmc);
1439 u32 cmd_delay = 0;
1440 struct msdc_delay_phase final_cmd_delay = { 0,};
1441 u8 final_delay;
1442 int cmd_err;
1443 int i, j;
1444
1445 /* select EMMC50 PAD CMD tune */
1446 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
1447 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
1448
1449 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
1450 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
1451 sdr_set_field(host->base + MSDC_PAD_TUNE,
1452 MSDC_PAD_TUNE_CMDRRDLY,
1453 host->hs200_cmd_int_delay);
1454
1455 if (host->hs400_cmd_resp_sel_rising)
1456 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1457 else
1458 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1459 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1460 sdr_set_field(host->base + PAD_CMD_TUNE,
1461 PAD_CMD_TUNE_RX_DLY3, i);
1462 /*
1463 * Using the same parameters, it may sometimes pass the test,
1464 * but sometimes it may fail. To make sure the parameters are
1465 * more stable, we test each set of parameters 3 times.
1466 */
1467 for (j = 0; j < 3; j++) {
1468 mmc_send_tuning(mmc, opcode, &cmd_err);
1469 if (!cmd_err) {
1470 cmd_delay |= (1 << i);
1471 } else {
1472 cmd_delay &= ~(1 << i);
1473 break;
1474 }
1475 }
1476 }
1477 final_cmd_delay = get_best_delay(host, cmd_delay);
1478 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
1479 final_cmd_delay.final_phase);
1480 final_delay = final_cmd_delay.final_phase;
1481
1482 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
1483 return final_delay == 0xff ? -EIO : 0;
1484 }
1485
msdc_tune_data(struct mmc_host * mmc,u32 opcode)1486 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
1487 {
1488 struct msdc_host *host = mmc_priv(mmc);
1489 u32 rise_delay = 0, fall_delay = 0;
1490 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1491 u8 final_delay, final_maxlen;
1492 int i, ret;
1493
1494 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1495 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1496 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1497 sdr_set_field(host->base + MSDC_PAD_TUNE,
1498 MSDC_PAD_TUNE_DATRRDLY, i);
1499 ret = mmc_send_tuning(mmc, opcode, NULL);
1500 if (!ret)
1501 rise_delay |= (1 << i);
1502 }
1503 final_rise_delay = get_best_delay(host, rise_delay);
1504 /* if rising edge has enough margin, then do not scan falling edge */
1505 if (final_rise_delay.maxlen >= 12 ||
1506 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1507 goto skip_fall;
1508
1509 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1510 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1511 for (i = 0; i < PAD_DELAY_MAX; i++) {
1512 sdr_set_field(host->base + MSDC_PAD_TUNE,
1513 MSDC_PAD_TUNE_DATRRDLY, i);
1514 ret = mmc_send_tuning(mmc, opcode, NULL);
1515 if (!ret)
1516 fall_delay |= (1 << i);
1517 }
1518 final_fall_delay = get_best_delay(host, fall_delay);
1519
1520 skip_fall:
1521 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1522 if (final_maxlen == final_rise_delay.maxlen) {
1523 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1524 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1525 sdr_set_field(host->base + MSDC_PAD_TUNE,
1526 MSDC_PAD_TUNE_DATRRDLY,
1527 final_rise_delay.final_phase);
1528 final_delay = final_rise_delay.final_phase;
1529 } else {
1530 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1531 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1532 sdr_set_field(host->base + MSDC_PAD_TUNE,
1533 MSDC_PAD_TUNE_DATRRDLY,
1534 final_fall_delay.final_phase);
1535 final_delay = final_fall_delay.final_phase;
1536 }
1537
1538 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
1539 return final_delay == 0xff ? -EIO : 0;
1540 }
1541
msdc_execute_tuning(struct mmc_host * mmc,u32 opcode)1542 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1543 {
1544 struct msdc_host *host = mmc_priv(mmc);
1545 int ret;
1546
1547 if (host->hs400_mode)
1548 ret = hs400_tune_response(mmc, opcode);
1549 else
1550 ret = msdc_tune_response(mmc, opcode);
1551 if (ret == -EIO) {
1552 dev_err(host->dev, "Tune response fail!\n");
1553 return ret;
1554 }
1555 if (host->hs400_mode == false) {
1556 ret = msdc_tune_data(mmc, opcode);
1557 if (ret == -EIO)
1558 dev_err(host->dev, "Tune data fail!\n");
1559 }
1560
1561 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1562 host->saved_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
1563 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
1564 return ret;
1565 }
1566
msdc_prepare_hs400_tuning(struct mmc_host * mmc,struct mmc_ios * ios)1567 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1568 {
1569 struct msdc_host *host = mmc_priv(mmc);
1570 host->hs400_mode = true;
1571
1572 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
1573 return 0;
1574 }
1575
msdc_hw_reset(struct mmc_host * mmc)1576 static void msdc_hw_reset(struct mmc_host *mmc)
1577 {
1578 struct msdc_host *host = mmc_priv(mmc);
1579
1580 sdr_set_bits(host->base + EMMC_IOCON, 1);
1581 udelay(10); /* 10us is enough */
1582 sdr_clr_bits(host->base + EMMC_IOCON, 1);
1583 }
1584
1585 static const struct mmc_host_ops mt_msdc_ops = {
1586 .post_req = msdc_post_req,
1587 .pre_req = msdc_pre_req,
1588 .request = msdc_ops_request,
1589 .set_ios = msdc_ops_set_ios,
1590 .get_ro = mmc_gpio_get_ro,
1591 .get_cd = mmc_gpio_get_cd,
1592 .start_signal_voltage_switch = msdc_ops_switch_volt,
1593 .card_busy = msdc_card_busy,
1594 .execute_tuning = msdc_execute_tuning,
1595 .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
1596 .hw_reset = msdc_hw_reset,
1597 };
1598
msdc_of_property_parse(struct platform_device * pdev,struct msdc_host * host)1599 static void msdc_of_property_parse(struct platform_device *pdev,
1600 struct msdc_host *host)
1601 {
1602 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
1603 &host->hs400_ds_delay);
1604
1605 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
1606 &host->hs200_cmd_int_delay);
1607
1608 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
1609 &host->hs400_cmd_int_delay);
1610
1611 if (of_property_read_bool(pdev->dev.of_node,
1612 "mediatek,hs400-cmd-resp-sel-rising"))
1613 host->hs400_cmd_resp_sel_rising = true;
1614 else
1615 host->hs400_cmd_resp_sel_rising = false;
1616 }
1617
msdc_drv_probe(struct platform_device * pdev)1618 static int msdc_drv_probe(struct platform_device *pdev)
1619 {
1620 struct mmc_host *mmc;
1621 struct msdc_host *host;
1622 struct resource *res;
1623 int ret;
1624
1625 if (!pdev->dev.of_node) {
1626 dev_err(&pdev->dev, "No DT found\n");
1627 return -EINVAL;
1628 }
1629 /* Allocate MMC host for this device */
1630 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
1631 if (!mmc)
1632 return -ENOMEM;
1633
1634 host = mmc_priv(mmc);
1635 ret = mmc_of_parse(mmc);
1636 if (ret)
1637 goto host_free;
1638
1639 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1640 host->base = devm_ioremap_resource(&pdev->dev, res);
1641 if (IS_ERR(host->base)) {
1642 ret = PTR_ERR(host->base);
1643 goto host_free;
1644 }
1645
1646 ret = mmc_regulator_get_supply(mmc);
1647 if (ret == -EPROBE_DEFER)
1648 goto host_free;
1649
1650 host->src_clk = devm_clk_get(&pdev->dev, "source");
1651 if (IS_ERR(host->src_clk)) {
1652 ret = PTR_ERR(host->src_clk);
1653 goto host_free;
1654 }
1655
1656 host->h_clk = devm_clk_get(&pdev->dev, "hclk");
1657 if (IS_ERR(host->h_clk)) {
1658 ret = PTR_ERR(host->h_clk);
1659 goto host_free;
1660 }
1661
1662 host->irq = platform_get_irq(pdev, 0);
1663 if (host->irq < 0) {
1664 ret = -EINVAL;
1665 goto host_free;
1666 }
1667
1668 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1669 if (IS_ERR(host->pinctrl)) {
1670 ret = PTR_ERR(host->pinctrl);
1671 dev_err(&pdev->dev, "Cannot find pinctrl!\n");
1672 goto host_free;
1673 }
1674
1675 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
1676 if (IS_ERR(host->pins_default)) {
1677 ret = PTR_ERR(host->pins_default);
1678 dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
1679 goto host_free;
1680 }
1681
1682 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
1683 if (IS_ERR(host->pins_uhs)) {
1684 ret = PTR_ERR(host->pins_uhs);
1685 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
1686 goto host_free;
1687 }
1688
1689 msdc_of_property_parse(pdev, host);
1690
1691 host->dev = &pdev->dev;
1692 host->mmc = mmc;
1693 host->src_clk_freq = clk_get_rate(host->src_clk);
1694 /* Set host parameters to mmc */
1695 mmc->ops = &mt_msdc_ops;
1696 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
1697
1698 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
1699 /* MMC core transfer sizes tunable parameters */
1700 mmc->max_segs = MAX_BD_NUM;
1701 mmc->max_seg_size = BDMA_DESC_BUFLEN;
1702 mmc->max_blk_size = 2048;
1703 mmc->max_req_size = 512 * 1024;
1704 mmc->max_blk_count = mmc->max_req_size / 512;
1705 host->dma_mask = DMA_BIT_MASK(32);
1706 mmc_dev(mmc)->dma_mask = &host->dma_mask;
1707
1708 host->timeout_clks = 3 * 1048576;
1709 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
1710 2 * sizeof(struct mt_gpdma_desc),
1711 &host->dma.gpd_addr, GFP_KERNEL);
1712 host->dma.bd = dma_alloc_coherent(&pdev->dev,
1713 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1714 &host->dma.bd_addr, GFP_KERNEL);
1715 if (!host->dma.gpd || !host->dma.bd) {
1716 ret = -ENOMEM;
1717 goto release_mem;
1718 }
1719 msdc_init_gpd_bd(host, &host->dma);
1720 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
1721 spin_lock_init(&host->lock);
1722
1723 platform_set_drvdata(pdev, mmc);
1724 msdc_ungate_clock(host);
1725 msdc_init_hw(host);
1726
1727 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
1728 IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host);
1729 if (ret)
1730 goto release;
1731
1732 pm_runtime_set_active(host->dev);
1733 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
1734 pm_runtime_use_autosuspend(host->dev);
1735 pm_runtime_enable(host->dev);
1736 ret = mmc_add_host(mmc);
1737
1738 if (ret)
1739 goto end;
1740
1741 return 0;
1742 end:
1743 pm_runtime_disable(host->dev);
1744 release:
1745 platform_set_drvdata(pdev, NULL);
1746 msdc_deinit_hw(host);
1747 msdc_gate_clock(host);
1748 release_mem:
1749 if (host->dma.gpd)
1750 dma_free_coherent(&pdev->dev,
1751 2 * sizeof(struct mt_gpdma_desc),
1752 host->dma.gpd, host->dma.gpd_addr);
1753 if (host->dma.bd)
1754 dma_free_coherent(&pdev->dev,
1755 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1756 host->dma.bd, host->dma.bd_addr);
1757 host_free:
1758 mmc_free_host(mmc);
1759
1760 return ret;
1761 }
1762
msdc_drv_remove(struct platform_device * pdev)1763 static int msdc_drv_remove(struct platform_device *pdev)
1764 {
1765 struct mmc_host *mmc;
1766 struct msdc_host *host;
1767
1768 mmc = platform_get_drvdata(pdev);
1769 host = mmc_priv(mmc);
1770
1771 pm_runtime_get_sync(host->dev);
1772
1773 platform_set_drvdata(pdev, NULL);
1774 mmc_remove_host(host->mmc);
1775 msdc_deinit_hw(host);
1776 msdc_gate_clock(host);
1777
1778 pm_runtime_disable(host->dev);
1779 pm_runtime_put_noidle(host->dev);
1780 dma_free_coherent(&pdev->dev,
1781 2 * sizeof(struct mt_gpdma_desc),
1782 host->dma.gpd, host->dma.gpd_addr);
1783 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1784 host->dma.bd, host->dma.bd_addr);
1785
1786 mmc_free_host(host->mmc);
1787
1788 return 0;
1789 }
1790
1791 #ifdef CONFIG_PM
msdc_save_reg(struct msdc_host * host)1792 static void msdc_save_reg(struct msdc_host *host)
1793 {
1794 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
1795 host->save_para.iocon = readl(host->base + MSDC_IOCON);
1796 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
1797 host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
1798 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
1799 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
1800 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
1801 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
1802 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
1803 }
1804
msdc_restore_reg(struct msdc_host * host)1805 static void msdc_restore_reg(struct msdc_host *host)
1806 {
1807 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
1808 writel(host->save_para.iocon, host->base + MSDC_IOCON);
1809 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
1810 writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE);
1811 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
1812 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
1813 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
1814 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
1815 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
1816 }
1817
msdc_runtime_suspend(struct device * dev)1818 static int msdc_runtime_suspend(struct device *dev)
1819 {
1820 struct mmc_host *mmc = dev_get_drvdata(dev);
1821 struct msdc_host *host = mmc_priv(mmc);
1822
1823 msdc_save_reg(host);
1824 msdc_gate_clock(host);
1825 return 0;
1826 }
1827
msdc_runtime_resume(struct device * dev)1828 static int msdc_runtime_resume(struct device *dev)
1829 {
1830 struct mmc_host *mmc = dev_get_drvdata(dev);
1831 struct msdc_host *host = mmc_priv(mmc);
1832
1833 msdc_ungate_clock(host);
1834 msdc_restore_reg(host);
1835 return 0;
1836 }
1837 #endif
1838
1839 static const struct dev_pm_ops msdc_dev_pm_ops = {
1840 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1841 pm_runtime_force_resume)
1842 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
1843 };
1844
1845 static const struct of_device_id msdc_of_ids[] = {
1846 { .compatible = "mediatek,mt8135-mmc", },
1847 {}
1848 };
1849 MODULE_DEVICE_TABLE(of, msdc_of_ids);
1850
1851 static struct platform_driver mt_msdc_driver = {
1852 .probe = msdc_drv_probe,
1853 .remove = msdc_drv_remove,
1854 .driver = {
1855 .name = "mtk-msdc",
1856 .of_match_table = msdc_of_ids,
1857 .pm = &msdc_dev_pm_ops,
1858 },
1859 };
1860
1861 module_platform_driver(mt_msdc_driver);
1862 MODULE_LICENSE("GPL v2");
1863 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
1864