1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15 #include <linux/string.h>
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/device.h>
23 #include <linux/mmc/host.h>
24 #include <linux/mmc/mmc.h>
25 #include <linux/scatterlist.h>
26 #include <linux/io.h>
27 #include <linux/gpio.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/mmc/slot-gpio.h>
30 #include <linux/mmc/sdhci-pci-data.h>
31 #include <linux/acpi.h>
32
33 #include "sdhci.h"
34 #include "sdhci-pci.h"
35 #include "sdhci-pci-o2micro.h"
36
37 static int sdhci_pci_enable_dma(struct sdhci_host *host);
38 static void sdhci_pci_hw_reset(struct sdhci_host *host);
39
40 #ifdef CONFIG_PM_SLEEP
__sdhci_pci_suspend_host(struct sdhci_pci_chip * chip)41 static int __sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
42 {
43 int i, ret;
44
45 for (i = 0; i < chip->num_slots; i++) {
46 struct sdhci_pci_slot *slot = chip->slots[i];
47 struct sdhci_host *host;
48
49 if (!slot)
50 continue;
51
52 host = slot->host;
53
54 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
55 mmc_retune_needed(host->mmc);
56
57 ret = sdhci_suspend_host(host);
58 if (ret)
59 goto err_pci_suspend;
60
61 if (host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ)
62 sdhci_enable_irq_wakeups(host);
63 }
64
65 return 0;
66
67 err_pci_suspend:
68 while (--i >= 0)
69 sdhci_resume_host(chip->slots[i]->host);
70 return ret;
71 }
72
sdhci_pci_init_wakeup(struct sdhci_pci_chip * chip)73 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
74 {
75 mmc_pm_flag_t pm_flags = 0;
76 int i;
77
78 for (i = 0; i < chip->num_slots; i++) {
79 struct sdhci_pci_slot *slot = chip->slots[i];
80
81 if (slot)
82 pm_flags |= slot->host->mmc->pm_flags;
83 }
84
85 return device_init_wakeup(&chip->pdev->dev,
86 (pm_flags & MMC_PM_KEEP_POWER) &&
87 (pm_flags & MMC_PM_WAKE_SDIO_IRQ));
88 }
89
sdhci_pci_suspend_host(struct sdhci_pci_chip * chip)90 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
91 {
92 int ret;
93
94 ret = __sdhci_pci_suspend_host(chip);
95 if (ret)
96 return ret;
97
98 sdhci_pci_init_wakeup(chip);
99
100 return 0;
101 }
102
sdhci_pci_resume_host(struct sdhci_pci_chip * chip)103 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
104 {
105 struct sdhci_pci_slot *slot;
106 int i, ret;
107
108 for (i = 0; i < chip->num_slots; i++) {
109 slot = chip->slots[i];
110 if (!slot)
111 continue;
112
113 ret = sdhci_resume_host(slot->host);
114 if (ret)
115 return ret;
116 }
117
118 return 0;
119 }
120 #endif
121
122 #ifdef CONFIG_PM
sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip * chip)123 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
124 {
125 struct sdhci_pci_slot *slot;
126 struct sdhci_host *host;
127 int i, ret;
128
129 for (i = 0; i < chip->num_slots; i++) {
130 slot = chip->slots[i];
131 if (!slot)
132 continue;
133
134 host = slot->host;
135
136 ret = sdhci_runtime_suspend_host(host);
137 if (ret)
138 goto err_pci_runtime_suspend;
139
140 if (chip->rpm_retune &&
141 host->tuning_mode != SDHCI_TUNING_MODE_3)
142 mmc_retune_needed(host->mmc);
143 }
144
145 return 0;
146
147 err_pci_runtime_suspend:
148 while (--i >= 0)
149 sdhci_runtime_resume_host(chip->slots[i]->host);
150 return ret;
151 }
152
sdhci_pci_runtime_resume_host(struct sdhci_pci_chip * chip)153 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
154 {
155 struct sdhci_pci_slot *slot;
156 int i, ret;
157
158 for (i = 0; i < chip->num_slots; i++) {
159 slot = chip->slots[i];
160 if (!slot)
161 continue;
162
163 ret = sdhci_runtime_resume_host(slot->host);
164 if (ret)
165 return ret;
166 }
167
168 return 0;
169 }
170 #endif
171
172 /*****************************************************************************\
173 * *
174 * Hardware specific quirk handling *
175 * *
176 \*****************************************************************************/
177
ricoh_probe(struct sdhci_pci_chip * chip)178 static int ricoh_probe(struct sdhci_pci_chip *chip)
179 {
180 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
181 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
182 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
183 return 0;
184 }
185
ricoh_mmc_probe_slot(struct sdhci_pci_slot * slot)186 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
187 {
188 slot->host->caps =
189 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
190 & SDHCI_TIMEOUT_CLK_MASK) |
191
192 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
193 & SDHCI_CLOCK_BASE_MASK) |
194
195 SDHCI_TIMEOUT_CLK_UNIT |
196 SDHCI_CAN_VDD_330 |
197 SDHCI_CAN_DO_HISPD |
198 SDHCI_CAN_DO_SDMA;
199 return 0;
200 }
201
202 #ifdef CONFIG_PM_SLEEP
ricoh_mmc_resume(struct sdhci_pci_chip * chip)203 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
204 {
205 /* Apply a delay to allow controller to settle */
206 /* Otherwise it becomes confused if card state changed
207 during suspend */
208 msleep(500);
209 return sdhci_pci_resume_host(chip);
210 }
211 #endif
212
213 static const struct sdhci_pci_fixes sdhci_ricoh = {
214 .probe = ricoh_probe,
215 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
216 SDHCI_QUIRK_FORCE_DMA |
217 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
218 };
219
220 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
221 .probe_slot = ricoh_mmc_probe_slot,
222 #ifdef CONFIG_PM_SLEEP
223 .resume = ricoh_mmc_resume,
224 #endif
225 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
226 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
227 SDHCI_QUIRK_NO_CARD_NO_RESET |
228 SDHCI_QUIRK_MISSING_CAPS
229 };
230
231 static const struct sdhci_pci_fixes sdhci_ene_712 = {
232 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
233 SDHCI_QUIRK_BROKEN_DMA,
234 };
235
236 static const struct sdhci_pci_fixes sdhci_ene_714 = {
237 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
238 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
239 SDHCI_QUIRK_BROKEN_DMA,
240 };
241
242 static const struct sdhci_pci_fixes sdhci_cafe = {
243 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
244 SDHCI_QUIRK_NO_BUSY_IRQ |
245 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
246 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
247 };
248
249 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
250 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
251 };
252
mrst_hc_probe_slot(struct sdhci_pci_slot * slot)253 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
254 {
255 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
256 return 0;
257 }
258
259 /*
260 * ADMA operation is disabled for Moorestown platform due to
261 * hardware bugs.
262 */
mrst_hc_probe(struct sdhci_pci_chip * chip)263 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
264 {
265 /*
266 * slots number is fixed here for MRST as SDIO3/5 are never used and
267 * have hardware bugs.
268 */
269 chip->num_slots = 1;
270 return 0;
271 }
272
pch_hc_probe_slot(struct sdhci_pci_slot * slot)273 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
274 {
275 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
276 return 0;
277 }
278
279 #ifdef CONFIG_PM
280
sdhci_pci_sd_cd(int irq,void * dev_id)281 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
282 {
283 struct sdhci_pci_slot *slot = dev_id;
284 struct sdhci_host *host = slot->host;
285
286 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
287 return IRQ_HANDLED;
288 }
289
sdhci_pci_add_own_cd(struct sdhci_pci_slot * slot)290 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
291 {
292 int err, irq, gpio = slot->cd_gpio;
293
294 slot->cd_gpio = -EINVAL;
295 slot->cd_irq = -EINVAL;
296
297 if (!gpio_is_valid(gpio))
298 return;
299
300 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
301 if (err < 0)
302 goto out;
303
304 err = gpio_direction_input(gpio);
305 if (err < 0)
306 goto out_free;
307
308 irq = gpio_to_irq(gpio);
309 if (irq < 0)
310 goto out_free;
311
312 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
313 IRQF_TRIGGER_FALLING, "sd_cd", slot);
314 if (err)
315 goto out_free;
316
317 slot->cd_gpio = gpio;
318 slot->cd_irq = irq;
319
320 return;
321
322 out_free:
323 devm_gpio_free(&slot->chip->pdev->dev, gpio);
324 out:
325 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
326 }
327
sdhci_pci_remove_own_cd(struct sdhci_pci_slot * slot)328 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
329 {
330 if (slot->cd_irq >= 0)
331 free_irq(slot->cd_irq, slot);
332 }
333
334 #else
335
sdhci_pci_add_own_cd(struct sdhci_pci_slot * slot)336 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
337 {
338 }
339
sdhci_pci_remove_own_cd(struct sdhci_pci_slot * slot)340 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
341 {
342 }
343
344 #endif
345
mfd_emmc_probe_slot(struct sdhci_pci_slot * slot)346 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
347 {
348 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
349 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
350 return 0;
351 }
352
mfd_sdio_probe_slot(struct sdhci_pci_slot * slot)353 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
354 {
355 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
356 return 0;
357 }
358
359 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
360 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
361 .probe_slot = mrst_hc_probe_slot,
362 };
363
364 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
365 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
366 .probe = mrst_hc_probe,
367 };
368
369 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
370 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
371 .allow_runtime_pm = true,
372 .own_cd_for_runtime_pm = true,
373 };
374
375 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
376 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
377 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
378 .allow_runtime_pm = true,
379 .probe_slot = mfd_sdio_probe_slot,
380 };
381
382 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
383 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
384 .allow_runtime_pm = true,
385 .probe_slot = mfd_emmc_probe_slot,
386 };
387
388 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
389 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
390 .probe_slot = pch_hc_probe_slot,
391 };
392
393 enum {
394 INTEL_DSM_FNS = 0,
395 INTEL_DSM_V18_SWITCH = 3,
396 INTEL_DSM_DRV_STRENGTH = 9,
397 INTEL_DSM_D3_RETUNE = 10,
398 };
399
400 struct intel_host {
401 u32 dsm_fns;
402 int drv_strength;
403 bool d3_retune;
404 };
405
406 static const guid_t intel_dsm_guid =
407 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
408 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
409
__intel_dsm(struct intel_host * intel_host,struct device * dev,unsigned int fn,u32 * result)410 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
411 unsigned int fn, u32 *result)
412 {
413 union acpi_object *obj;
414 int err = 0;
415 size_t len;
416
417 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
418 if (!obj)
419 return -EOPNOTSUPP;
420
421 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
422 err = -EINVAL;
423 goto out;
424 }
425
426 len = min_t(size_t, obj->buffer.length, 4);
427
428 *result = 0;
429 memcpy(result, obj->buffer.pointer, len);
430 out:
431 ACPI_FREE(obj);
432
433 return err;
434 }
435
intel_dsm(struct intel_host * intel_host,struct device * dev,unsigned int fn,u32 * result)436 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
437 unsigned int fn, u32 *result)
438 {
439 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
440 return -EOPNOTSUPP;
441
442 return __intel_dsm(intel_host, dev, fn, result);
443 }
444
intel_dsm_init(struct intel_host * intel_host,struct device * dev,struct mmc_host * mmc)445 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
446 struct mmc_host *mmc)
447 {
448 int err;
449 u32 val;
450
451 intel_host->d3_retune = true;
452
453 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
454 if (err) {
455 pr_debug("%s: DSM not supported, error %d\n",
456 mmc_hostname(mmc), err);
457 return;
458 }
459
460 pr_debug("%s: DSM function mask %#x\n",
461 mmc_hostname(mmc), intel_host->dsm_fns);
462
463 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
464 intel_host->drv_strength = err ? 0 : val;
465
466 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
467 intel_host->d3_retune = err ? true : !!val;
468 }
469
sdhci_pci_int_hw_reset(struct sdhci_host * host)470 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
471 {
472 u8 reg;
473
474 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
475 reg |= 0x10;
476 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
477 /* For eMMC, minimum is 1us but give it 9us for good measure */
478 udelay(9);
479 reg &= ~0x10;
480 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
481 /* For eMMC, minimum is 200us but give it 300us for good measure */
482 usleep_range(300, 1000);
483 }
484
intel_select_drive_strength(struct mmc_card * card,unsigned int max_dtr,int host_drv,int card_drv,int * drv_type)485 static int intel_select_drive_strength(struct mmc_card *card,
486 unsigned int max_dtr, int host_drv,
487 int card_drv, int *drv_type)
488 {
489 struct sdhci_host *host = mmc_priv(card->host);
490 struct sdhci_pci_slot *slot = sdhci_priv(host);
491 struct intel_host *intel_host = sdhci_pci_priv(slot);
492
493 return intel_host->drv_strength;
494 }
495
bxt_get_cd(struct mmc_host * mmc)496 static int bxt_get_cd(struct mmc_host *mmc)
497 {
498 int gpio_cd = mmc_gpio_get_cd(mmc);
499 struct sdhci_host *host = mmc_priv(mmc);
500 unsigned long flags;
501 int ret = 0;
502
503 if (!gpio_cd)
504 return 0;
505
506 spin_lock_irqsave(&host->lock, flags);
507
508 if (host->flags & SDHCI_DEVICE_DEAD)
509 goto out;
510
511 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
512 out:
513 spin_unlock_irqrestore(&host->lock, flags);
514
515 return ret;
516 }
517
518 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
519 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
520
sdhci_intel_set_power(struct sdhci_host * host,unsigned char mode,unsigned short vdd)521 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
522 unsigned short vdd)
523 {
524 int cntr;
525 u8 reg;
526
527 sdhci_set_power(host, mode, vdd);
528
529 if (mode == MMC_POWER_OFF)
530 return;
531
532 /*
533 * Bus power might not enable after D3 -> D0 transition due to the
534 * present state not yet having propagated. Retry for up to 2ms.
535 */
536 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
537 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
538 if (reg & SDHCI_POWER_ON)
539 break;
540 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
541 reg |= SDHCI_POWER_ON;
542 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
543 }
544 }
545
546 #define INTEL_HS400_ES_REG 0x78
547 #define INTEL_HS400_ES_BIT BIT(0)
548
intel_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)549 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
550 struct mmc_ios *ios)
551 {
552 struct sdhci_host *host = mmc_priv(mmc);
553 u32 val;
554
555 val = sdhci_readl(host, INTEL_HS400_ES_REG);
556 if (ios->enhanced_strobe)
557 val |= INTEL_HS400_ES_BIT;
558 else
559 val &= ~INTEL_HS400_ES_BIT;
560 sdhci_writel(host, val, INTEL_HS400_ES_REG);
561 }
562
sdhci_intel_voltage_switch(struct sdhci_host * host)563 static void sdhci_intel_voltage_switch(struct sdhci_host *host)
564 {
565 struct sdhci_pci_slot *slot = sdhci_priv(host);
566 struct intel_host *intel_host = sdhci_pci_priv(slot);
567 struct device *dev = &slot->chip->pdev->dev;
568 u32 result = 0;
569 int err;
570
571 err = intel_dsm(intel_host, dev, INTEL_DSM_V18_SWITCH, &result);
572 pr_debug("%s: %s DSM error %d result %u\n",
573 mmc_hostname(host->mmc), __func__, err, result);
574 }
575
576 static const struct sdhci_ops sdhci_intel_byt_ops = {
577 .set_clock = sdhci_set_clock,
578 .set_power = sdhci_intel_set_power,
579 .enable_dma = sdhci_pci_enable_dma,
580 .set_bus_width = sdhci_set_bus_width,
581 .reset = sdhci_reset,
582 .set_uhs_signaling = sdhci_set_uhs_signaling,
583 .hw_reset = sdhci_pci_hw_reset,
584 .voltage_switch = sdhci_intel_voltage_switch,
585 };
586
byt_read_dsm(struct sdhci_pci_slot * slot)587 static void byt_read_dsm(struct sdhci_pci_slot *slot)
588 {
589 struct intel_host *intel_host = sdhci_pci_priv(slot);
590 struct device *dev = &slot->chip->pdev->dev;
591 struct mmc_host *mmc = slot->host->mmc;
592
593 intel_dsm_init(intel_host, dev, mmc);
594 slot->chip->rpm_retune = intel_host->d3_retune;
595 }
596
intel_execute_tuning(struct mmc_host * mmc,u32 opcode)597 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode)
598 {
599 int err = sdhci_execute_tuning(mmc, opcode);
600 struct sdhci_host *host = mmc_priv(mmc);
601
602 if (err)
603 return err;
604
605 /*
606 * Tuning can leave the IP in an active state (Buffer Read Enable bit
607 * set) which prevents the entry to low power states (i.e. S0i3). Data
608 * reset will clear it.
609 */
610 sdhci_reset(host, SDHCI_RESET_DATA);
611
612 return 0;
613 }
614
byt_probe_slot(struct sdhci_pci_slot * slot)615 static void byt_probe_slot(struct sdhci_pci_slot *slot)
616 {
617 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
618
619 byt_read_dsm(slot);
620
621 ops->execute_tuning = intel_execute_tuning;
622 }
623
byt_emmc_probe_slot(struct sdhci_pci_slot * slot)624 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
625 {
626 byt_probe_slot(slot);
627 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
628 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
629 MMC_CAP_CMD_DURING_TFR |
630 MMC_CAP_WAIT_WHILE_BUSY;
631 slot->hw_reset = sdhci_pci_int_hw_reset;
632 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
633 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
634 slot->host->mmc_host_ops.select_drive_strength =
635 intel_select_drive_strength;
636 return 0;
637 }
638
glk_emmc_probe_slot(struct sdhci_pci_slot * slot)639 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
640 {
641 int ret = byt_emmc_probe_slot(slot);
642
643 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
644 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
645 slot->host->mmc_host_ops.hs400_enhanced_strobe =
646 intel_hs400_enhanced_strobe;
647 }
648
649 return ret;
650 }
651
652 #ifdef CONFIG_ACPI
ni_set_max_freq(struct sdhci_pci_slot * slot)653 static int ni_set_max_freq(struct sdhci_pci_slot *slot)
654 {
655 acpi_status status;
656 unsigned long long max_freq;
657
658 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
659 "MXFQ", NULL, &max_freq);
660 if (ACPI_FAILURE(status)) {
661 dev_err(&slot->chip->pdev->dev,
662 "MXFQ not found in acpi table\n");
663 return -EINVAL;
664 }
665
666 slot->host->mmc->f_max = max_freq * 1000000;
667
668 return 0;
669 }
670 #else
ni_set_max_freq(struct sdhci_pci_slot * slot)671 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
672 {
673 return 0;
674 }
675 #endif
676
ni_byt_sdio_probe_slot(struct sdhci_pci_slot * slot)677 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
678 {
679 int err;
680
681 byt_probe_slot(slot);
682
683 err = ni_set_max_freq(slot);
684 if (err)
685 return err;
686
687 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
688 MMC_CAP_WAIT_WHILE_BUSY;
689 return 0;
690 }
691
byt_sdio_probe_slot(struct sdhci_pci_slot * slot)692 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
693 {
694 byt_probe_slot(slot);
695 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
696 MMC_CAP_WAIT_WHILE_BUSY;
697 return 0;
698 }
699
byt_sd_probe_slot(struct sdhci_pci_slot * slot)700 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
701 {
702 byt_probe_slot(slot);
703 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
704 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
705 slot->cd_idx = 0;
706 slot->cd_override_level = true;
707 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
708 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
709 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
710 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
711 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
712
713 return 0;
714 }
715
716 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
717 .allow_runtime_pm = true,
718 .probe_slot = byt_emmc_probe_slot,
719 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
720 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
721 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
722 SDHCI_QUIRK2_STOP_WITH_TC,
723 .ops = &sdhci_intel_byt_ops,
724 .priv_size = sizeof(struct intel_host),
725 };
726
727 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
728 .allow_runtime_pm = true,
729 .probe_slot = glk_emmc_probe_slot,
730 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
731 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
732 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
733 SDHCI_QUIRK2_STOP_WITH_TC,
734 .ops = &sdhci_intel_byt_ops,
735 .priv_size = sizeof(struct intel_host),
736 };
737
738 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
739 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
740 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
741 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
742 .allow_runtime_pm = true,
743 .probe_slot = ni_byt_sdio_probe_slot,
744 .ops = &sdhci_intel_byt_ops,
745 .priv_size = sizeof(struct intel_host),
746 };
747
748 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
749 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
750 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
751 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
752 .allow_runtime_pm = true,
753 .probe_slot = byt_sdio_probe_slot,
754 .ops = &sdhci_intel_byt_ops,
755 .priv_size = sizeof(struct intel_host),
756 };
757
758 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
759 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
760 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
761 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
762 SDHCI_QUIRK2_STOP_WITH_TC,
763 .allow_runtime_pm = true,
764 .own_cd_for_runtime_pm = true,
765 .probe_slot = byt_sd_probe_slot,
766 .ops = &sdhci_intel_byt_ops,
767 .priv_size = sizeof(struct intel_host),
768 };
769
770 /* Define Host controllers for Intel Merrifield platform */
771 #define INTEL_MRFLD_EMMC_0 0
772 #define INTEL_MRFLD_EMMC_1 1
773 #define INTEL_MRFLD_SD 2
774 #define INTEL_MRFLD_SDIO 3
775
776 #ifdef CONFIG_ACPI
intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot * slot)777 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
778 {
779 struct acpi_device *device, *child;
780
781 device = ACPI_COMPANION(&slot->chip->pdev->dev);
782 if (!device)
783 return;
784
785 acpi_device_fix_up_power(device);
786 list_for_each_entry(child, &device->children, node)
787 if (child->status.present && child->status.enabled)
788 acpi_device_fix_up_power(child);
789 }
790 #else
intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot * slot)791 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
792 #endif
793
intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot * slot)794 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
795 {
796 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
797
798 switch (func) {
799 case INTEL_MRFLD_EMMC_0:
800 case INTEL_MRFLD_EMMC_1:
801 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
802 MMC_CAP_8_BIT_DATA |
803 MMC_CAP_1_8V_DDR;
804 break;
805 case INTEL_MRFLD_SD:
806 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
807 break;
808 case INTEL_MRFLD_SDIO:
809 /* Advertise 2.0v for compatibility with the SDIO card's OCR */
810 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195;
811 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
812 MMC_CAP_POWER_OFF_CARD;
813 break;
814 default:
815 return -ENODEV;
816 }
817
818 intel_mrfld_mmc_fix_up_power_slot(slot);
819 return 0;
820 }
821
822 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
823 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
824 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
825 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
826 .allow_runtime_pm = true,
827 .probe_slot = intel_mrfld_mmc_probe_slot,
828 };
829
830 /* O2Micro extra registers */
831 #define O2_SD_LOCK_WP 0xD3
832 #define O2_SD_MULTI_VCC3V 0xEE
833 #define O2_SD_CLKREQ 0xEC
834 #define O2_SD_CAPS 0xE0
835 #define O2_SD_ADMA1 0xE2
836 #define O2_SD_ADMA2 0xE7
837 #define O2_SD_INF_MOD 0xF1
838
jmicron_pmos(struct sdhci_pci_chip * chip,int on)839 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
840 {
841 u8 scratch;
842 int ret;
843
844 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
845 if (ret)
846 return ret;
847
848 /*
849 * Turn PMOS on [bit 0], set over current detection to 2.4 V
850 * [bit 1:2] and enable over current debouncing [bit 6].
851 */
852 if (on)
853 scratch |= 0x47;
854 else
855 scratch &= ~0x47;
856
857 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
858 }
859
jmicron_probe(struct sdhci_pci_chip * chip)860 static int jmicron_probe(struct sdhci_pci_chip *chip)
861 {
862 int ret;
863 u16 mmcdev = 0;
864
865 if (chip->pdev->revision == 0) {
866 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
867 SDHCI_QUIRK_32BIT_DMA_SIZE |
868 SDHCI_QUIRK_32BIT_ADMA_SIZE |
869 SDHCI_QUIRK_RESET_AFTER_REQUEST |
870 SDHCI_QUIRK_BROKEN_SMALL_PIO;
871 }
872
873 /*
874 * JMicron chips can have two interfaces to the same hardware
875 * in order to work around limitations in Microsoft's driver.
876 * We need to make sure we only bind to one of them.
877 *
878 * This code assumes two things:
879 *
880 * 1. The PCI code adds subfunctions in order.
881 *
882 * 2. The MMC interface has a lower subfunction number
883 * than the SD interface.
884 */
885 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
886 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
887 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
888 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
889
890 if (mmcdev) {
891 struct pci_dev *sd_dev;
892
893 sd_dev = NULL;
894 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
895 mmcdev, sd_dev)) != NULL) {
896 if ((PCI_SLOT(chip->pdev->devfn) ==
897 PCI_SLOT(sd_dev->devfn)) &&
898 (chip->pdev->bus == sd_dev->bus))
899 break;
900 }
901
902 if (sd_dev) {
903 pci_dev_put(sd_dev);
904 dev_info(&chip->pdev->dev, "Refusing to bind to "
905 "secondary interface.\n");
906 return -ENODEV;
907 }
908 }
909
910 /*
911 * JMicron chips need a bit of a nudge to enable the power
912 * output pins.
913 */
914 ret = jmicron_pmos(chip, 1);
915 if (ret) {
916 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
917 return ret;
918 }
919
920 /* quirk for unsable RO-detection on JM388 chips */
921 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
922 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
923 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
924
925 return 0;
926 }
927
jmicron_enable_mmc(struct sdhci_host * host,int on)928 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
929 {
930 u8 scratch;
931
932 scratch = readb(host->ioaddr + 0xC0);
933
934 if (on)
935 scratch |= 0x01;
936 else
937 scratch &= ~0x01;
938
939 writeb(scratch, host->ioaddr + 0xC0);
940 }
941
jmicron_probe_slot(struct sdhci_pci_slot * slot)942 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
943 {
944 if (slot->chip->pdev->revision == 0) {
945 u16 version;
946
947 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
948 version = (version & SDHCI_VENDOR_VER_MASK) >>
949 SDHCI_VENDOR_VER_SHIFT;
950
951 /*
952 * Older versions of the chip have lots of nasty glitches
953 * in the ADMA engine. It's best just to avoid it
954 * completely.
955 */
956 if (version < 0xAC)
957 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
958 }
959
960 /* JM388 MMC doesn't support 1.8V while SD supports it */
961 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
962 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
963 MMC_VDD_29_30 | MMC_VDD_30_31 |
964 MMC_VDD_165_195; /* allow 1.8V */
965 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
966 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
967 }
968
969 /*
970 * The secondary interface requires a bit set to get the
971 * interrupts.
972 */
973 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
974 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
975 jmicron_enable_mmc(slot->host, 1);
976
977 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
978
979 return 0;
980 }
981
jmicron_remove_slot(struct sdhci_pci_slot * slot,int dead)982 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
983 {
984 if (dead)
985 return;
986
987 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
988 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
989 jmicron_enable_mmc(slot->host, 0);
990 }
991
992 #ifdef CONFIG_PM_SLEEP
jmicron_suspend(struct sdhci_pci_chip * chip)993 static int jmicron_suspend(struct sdhci_pci_chip *chip)
994 {
995 int i, ret;
996
997 ret = __sdhci_pci_suspend_host(chip);
998 if (ret)
999 return ret;
1000
1001 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1002 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1003 for (i = 0; i < chip->num_slots; i++)
1004 jmicron_enable_mmc(chip->slots[i]->host, 0);
1005 }
1006
1007 sdhci_pci_init_wakeup(chip);
1008
1009 return 0;
1010 }
1011
jmicron_resume(struct sdhci_pci_chip * chip)1012 static int jmicron_resume(struct sdhci_pci_chip *chip)
1013 {
1014 int ret, i;
1015
1016 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1017 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1018 for (i = 0; i < chip->num_slots; i++)
1019 jmicron_enable_mmc(chip->slots[i]->host, 1);
1020 }
1021
1022 ret = jmicron_pmos(chip, 1);
1023 if (ret) {
1024 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1025 return ret;
1026 }
1027
1028 return sdhci_pci_resume_host(chip);
1029 }
1030 #endif
1031
1032 static const struct sdhci_pci_fixes sdhci_o2 = {
1033 .probe = sdhci_pci_o2_probe,
1034 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1035 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
1036 .probe_slot = sdhci_pci_o2_probe_slot,
1037 #ifdef CONFIG_PM_SLEEP
1038 .resume = sdhci_pci_o2_resume,
1039 #endif
1040 };
1041
1042 static const struct sdhci_pci_fixes sdhci_jmicron = {
1043 .probe = jmicron_probe,
1044
1045 .probe_slot = jmicron_probe_slot,
1046 .remove_slot = jmicron_remove_slot,
1047
1048 #ifdef CONFIG_PM_SLEEP
1049 .suspend = jmicron_suspend,
1050 .resume = jmicron_resume,
1051 #endif
1052 };
1053
1054 /* SysKonnect CardBus2SDIO extra registers */
1055 #define SYSKT_CTRL 0x200
1056 #define SYSKT_RDFIFO_STAT 0x204
1057 #define SYSKT_WRFIFO_STAT 0x208
1058 #define SYSKT_POWER_DATA 0x20c
1059 #define SYSKT_POWER_330 0xef
1060 #define SYSKT_POWER_300 0xf8
1061 #define SYSKT_POWER_184 0xcc
1062 #define SYSKT_POWER_CMD 0x20d
1063 #define SYSKT_POWER_START (1 << 7)
1064 #define SYSKT_POWER_STATUS 0x20e
1065 #define SYSKT_POWER_STATUS_OK (1 << 0)
1066 #define SYSKT_BOARD_REV 0x210
1067 #define SYSKT_CHIP_REV 0x211
1068 #define SYSKT_CONF_DATA 0x212
1069 #define SYSKT_CONF_DATA_1V8 (1 << 2)
1070 #define SYSKT_CONF_DATA_2V5 (1 << 1)
1071 #define SYSKT_CONF_DATA_3V3 (1 << 0)
1072
syskt_probe(struct sdhci_pci_chip * chip)1073 static int syskt_probe(struct sdhci_pci_chip *chip)
1074 {
1075 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1076 chip->pdev->class &= ~0x0000FF;
1077 chip->pdev->class |= PCI_SDHCI_IFDMA;
1078 }
1079 return 0;
1080 }
1081
syskt_probe_slot(struct sdhci_pci_slot * slot)1082 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1083 {
1084 int tm, ps;
1085
1086 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1087 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1088 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1089 "board rev %d.%d, chip rev %d.%d\n",
1090 board_rev >> 4, board_rev & 0xf,
1091 chip_rev >> 4, chip_rev & 0xf);
1092 if (chip_rev >= 0x20)
1093 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1094
1095 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1096 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1097 udelay(50);
1098 tm = 10; /* Wait max 1 ms */
1099 do {
1100 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1101 if (ps & SYSKT_POWER_STATUS_OK)
1102 break;
1103 udelay(100);
1104 } while (--tm);
1105 if (!tm) {
1106 dev_err(&slot->chip->pdev->dev,
1107 "power regulator never stabilized");
1108 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1109 return -ENODEV;
1110 }
1111
1112 return 0;
1113 }
1114
1115 static const struct sdhci_pci_fixes sdhci_syskt = {
1116 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1117 .probe = syskt_probe,
1118 .probe_slot = syskt_probe_slot,
1119 };
1120
via_probe(struct sdhci_pci_chip * chip)1121 static int via_probe(struct sdhci_pci_chip *chip)
1122 {
1123 if (chip->pdev->revision == 0x10)
1124 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1125
1126 return 0;
1127 }
1128
1129 static const struct sdhci_pci_fixes sdhci_via = {
1130 .probe = via_probe,
1131 };
1132
rtsx_probe_slot(struct sdhci_pci_slot * slot)1133 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1134 {
1135 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1136 return 0;
1137 }
1138
1139 static const struct sdhci_pci_fixes sdhci_rtsx = {
1140 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1141 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
1142 SDHCI_QUIRK2_BROKEN_DDR50,
1143 .probe_slot = rtsx_probe_slot,
1144 };
1145
1146 /*AMD chipset generation*/
1147 enum amd_chipset_gen {
1148 AMD_CHIPSET_BEFORE_ML,
1149 AMD_CHIPSET_CZ,
1150 AMD_CHIPSET_NL,
1151 AMD_CHIPSET_UNKNOWN,
1152 };
1153
1154 /* AMD registers */
1155 #define AMD_SD_AUTO_PATTERN 0xB8
1156 #define AMD_MSLEEP_DURATION 4
1157 #define AMD_SD_MISC_CONTROL 0xD0
1158 #define AMD_MAX_TUNE_VALUE 0x0B
1159 #define AMD_AUTO_TUNE_SEL 0x10800
1160 #define AMD_FIFO_PTR 0x30
1161 #define AMD_BIT_MASK 0x1F
1162
amd_tuning_reset(struct sdhci_host * host)1163 static void amd_tuning_reset(struct sdhci_host *host)
1164 {
1165 unsigned int val;
1166
1167 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1168 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1169 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1170
1171 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1172 val &= ~SDHCI_CTRL_EXEC_TUNING;
1173 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1174 }
1175
amd_config_tuning_phase(struct pci_dev * pdev,u8 phase)1176 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1177 {
1178 unsigned int val;
1179
1180 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1181 val &= ~AMD_BIT_MASK;
1182 val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1183 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1184 }
1185
amd_enable_manual_tuning(struct pci_dev * pdev)1186 static void amd_enable_manual_tuning(struct pci_dev *pdev)
1187 {
1188 unsigned int val;
1189
1190 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1191 val |= AMD_FIFO_PTR;
1192 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1193 }
1194
amd_execute_tuning_hs200(struct sdhci_host * host,u32 opcode)1195 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode)
1196 {
1197 struct sdhci_pci_slot *slot = sdhci_priv(host);
1198 struct pci_dev *pdev = slot->chip->pdev;
1199 u8 valid_win = 0;
1200 u8 valid_win_max = 0;
1201 u8 valid_win_end = 0;
1202 u8 ctrl, tune_around;
1203
1204 amd_tuning_reset(host);
1205
1206 for (tune_around = 0; tune_around < 12; tune_around++) {
1207 amd_config_tuning_phase(pdev, tune_around);
1208
1209 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1210 valid_win = 0;
1211 msleep(AMD_MSLEEP_DURATION);
1212 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1213 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1214 } else if (++valid_win > valid_win_max) {
1215 valid_win_max = valid_win;
1216 valid_win_end = tune_around;
1217 }
1218 }
1219
1220 if (!valid_win_max) {
1221 dev_err(&pdev->dev, "no tuning point found\n");
1222 return -EIO;
1223 }
1224
1225 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1226
1227 amd_enable_manual_tuning(pdev);
1228
1229 host->mmc->retune_period = 0;
1230
1231 return 0;
1232 }
1233
amd_execute_tuning(struct mmc_host * mmc,u32 opcode)1234 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode)
1235 {
1236 struct sdhci_host *host = mmc_priv(mmc);
1237
1238 /* AMD requires custom HS200 tuning */
1239 if (host->timing == MMC_TIMING_MMC_HS200)
1240 return amd_execute_tuning_hs200(host, opcode);
1241
1242 /* Otherwise perform standard SDHCI tuning */
1243 return sdhci_execute_tuning(mmc, opcode);
1244 }
1245
amd_probe_slot(struct sdhci_pci_slot * slot)1246 static int amd_probe_slot(struct sdhci_pci_slot *slot)
1247 {
1248 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
1249
1250 ops->execute_tuning = amd_execute_tuning;
1251
1252 return 0;
1253 }
1254
amd_probe(struct sdhci_pci_chip * chip)1255 static int amd_probe(struct sdhci_pci_chip *chip)
1256 {
1257 struct pci_dev *smbus_dev;
1258 enum amd_chipset_gen gen;
1259
1260 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1261 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
1262 if (smbus_dev) {
1263 gen = AMD_CHIPSET_BEFORE_ML;
1264 } else {
1265 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1266 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1267 if (smbus_dev) {
1268 if (smbus_dev->revision < 0x51)
1269 gen = AMD_CHIPSET_CZ;
1270 else
1271 gen = AMD_CHIPSET_NL;
1272 } else {
1273 gen = AMD_CHIPSET_UNKNOWN;
1274 }
1275 }
1276
1277 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
1278 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1279
1280 return 0;
1281 }
1282
1283 static const struct sdhci_ops amd_sdhci_pci_ops = {
1284 .set_clock = sdhci_set_clock,
1285 .enable_dma = sdhci_pci_enable_dma,
1286 .set_bus_width = sdhci_set_bus_width,
1287 .reset = sdhci_reset,
1288 .set_uhs_signaling = sdhci_set_uhs_signaling,
1289 };
1290
1291 static const struct sdhci_pci_fixes sdhci_amd = {
1292 .probe = amd_probe,
1293 .ops = &amd_sdhci_pci_ops,
1294 .probe_slot = amd_probe_slot,
1295 };
1296
1297 static const struct pci_device_id pci_ids[] = {
1298 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh),
1299 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc),
1300 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1301 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1302 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712),
1303 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1304 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714),
1305 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1306 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1307 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron),
1308 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1309 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron),
1310 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1311 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1312 SDHCI_PCI_DEVICE(VIA, 95D0, via),
1313 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1314 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk),
1315 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0),
1316 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2),
1317 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2),
1318 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd),
1319 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1320 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1321 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1322 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1323 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1324 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1325 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc),
1326 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1327 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio),
1328 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd),
1329 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1330 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc),
1331 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio),
1332 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd),
1333 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1334 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1335 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1336 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1337 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1338 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1339 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc),
1340 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio),
1341 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd),
1342 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc),
1343 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc),
1344 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio),
1345 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd),
1346 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1347 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1348 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd),
1349 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc),
1350 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio),
1351 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd),
1352 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc),
1353 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio),
1354 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd),
1355 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc),
1356 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd),
1357 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd),
1358 SDHCI_PCI_DEVICE(O2, 8120, o2),
1359 SDHCI_PCI_DEVICE(O2, 8220, o2),
1360 SDHCI_PCI_DEVICE(O2, 8221, o2),
1361 SDHCI_PCI_DEVICE(O2, 8320, o2),
1362 SDHCI_PCI_DEVICE(O2, 8321, o2),
1363 SDHCI_PCI_DEVICE(O2, FUJIN2, o2),
1364 SDHCI_PCI_DEVICE(O2, SDS0, o2),
1365 SDHCI_PCI_DEVICE(O2, SDS1, o2),
1366 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1367 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
1368 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1369 /* Generic SD host controller */
1370 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
1371 { /* end: all zeroes */ },
1372 };
1373
1374 MODULE_DEVICE_TABLE(pci, pci_ids);
1375
1376 /*****************************************************************************\
1377 * *
1378 * SDHCI core callbacks *
1379 * *
1380 \*****************************************************************************/
1381
sdhci_pci_enable_dma(struct sdhci_host * host)1382 static int sdhci_pci_enable_dma(struct sdhci_host *host)
1383 {
1384 struct sdhci_pci_slot *slot;
1385 struct pci_dev *pdev;
1386
1387 slot = sdhci_priv(host);
1388 pdev = slot->chip->pdev;
1389
1390 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1391 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1392 (host->flags & SDHCI_USE_SDMA)) {
1393 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1394 "doesn't fully claim to support it.\n");
1395 }
1396
1397 pci_set_master(pdev);
1398
1399 return 0;
1400 }
1401
sdhci_pci_gpio_hw_reset(struct sdhci_host * host)1402 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1403 {
1404 struct sdhci_pci_slot *slot = sdhci_priv(host);
1405 int rst_n_gpio = slot->rst_n_gpio;
1406
1407 if (!gpio_is_valid(rst_n_gpio))
1408 return;
1409 gpio_set_value_cansleep(rst_n_gpio, 0);
1410 /* For eMMC, minimum is 1us but give it 10us for good measure */
1411 udelay(10);
1412 gpio_set_value_cansleep(rst_n_gpio, 1);
1413 /* For eMMC, minimum is 200us but give it 300us for good measure */
1414 usleep_range(300, 1000);
1415 }
1416
sdhci_pci_hw_reset(struct sdhci_host * host)1417 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1418 {
1419 struct sdhci_pci_slot *slot = sdhci_priv(host);
1420
1421 if (slot->hw_reset)
1422 slot->hw_reset(host);
1423 }
1424
1425 static const struct sdhci_ops sdhci_pci_ops = {
1426 .set_clock = sdhci_set_clock,
1427 .enable_dma = sdhci_pci_enable_dma,
1428 .set_bus_width = sdhci_set_bus_width,
1429 .reset = sdhci_reset,
1430 .set_uhs_signaling = sdhci_set_uhs_signaling,
1431 .hw_reset = sdhci_pci_hw_reset,
1432 };
1433
1434 /*****************************************************************************\
1435 * *
1436 * Suspend/resume *
1437 * *
1438 \*****************************************************************************/
1439
1440 #ifdef CONFIG_PM_SLEEP
sdhci_pci_suspend(struct device * dev)1441 static int sdhci_pci_suspend(struct device *dev)
1442 {
1443 struct pci_dev *pdev = to_pci_dev(dev);
1444 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1445
1446 if (!chip)
1447 return 0;
1448
1449 if (chip->fixes && chip->fixes->suspend)
1450 return chip->fixes->suspend(chip);
1451
1452 return sdhci_pci_suspend_host(chip);
1453 }
1454
sdhci_pci_resume(struct device * dev)1455 static int sdhci_pci_resume(struct device *dev)
1456 {
1457 struct pci_dev *pdev = to_pci_dev(dev);
1458 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1459
1460 if (!chip)
1461 return 0;
1462
1463 if (chip->fixes && chip->fixes->resume)
1464 return chip->fixes->resume(chip);
1465
1466 return sdhci_pci_resume_host(chip);
1467 }
1468 #endif
1469
1470 #ifdef CONFIG_PM
sdhci_pci_runtime_suspend(struct device * dev)1471 static int sdhci_pci_runtime_suspend(struct device *dev)
1472 {
1473 struct pci_dev *pdev = to_pci_dev(dev);
1474 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1475
1476 if (!chip)
1477 return 0;
1478
1479 if (chip->fixes && chip->fixes->runtime_suspend)
1480 return chip->fixes->runtime_suspend(chip);
1481
1482 return sdhci_pci_runtime_suspend_host(chip);
1483 }
1484
sdhci_pci_runtime_resume(struct device * dev)1485 static int sdhci_pci_runtime_resume(struct device *dev)
1486 {
1487 struct pci_dev *pdev = to_pci_dev(dev);
1488 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1489
1490 if (!chip)
1491 return 0;
1492
1493 if (chip->fixes && chip->fixes->runtime_resume)
1494 return chip->fixes->runtime_resume(chip);
1495
1496 return sdhci_pci_runtime_resume_host(chip);
1497 }
1498 #endif
1499
1500 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1501 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
1502 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1503 sdhci_pci_runtime_resume, NULL)
1504 };
1505
1506 /*****************************************************************************\
1507 * *
1508 * Device probing/removal *
1509 * *
1510 \*****************************************************************************/
1511
sdhci_pci_probe_slot(struct pci_dev * pdev,struct sdhci_pci_chip * chip,int first_bar,int slotno)1512 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1513 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1514 int slotno)
1515 {
1516 struct sdhci_pci_slot *slot;
1517 struct sdhci_host *host;
1518 int ret, bar = first_bar + slotno;
1519 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
1520
1521 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1522 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1523 return ERR_PTR(-ENODEV);
1524 }
1525
1526 if (pci_resource_len(pdev, bar) < 0x100) {
1527 dev_err(&pdev->dev, "Invalid iomem size. You may "
1528 "experience problems.\n");
1529 }
1530
1531 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1532 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1533 return ERR_PTR(-ENODEV);
1534 }
1535
1536 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1537 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1538 return ERR_PTR(-ENODEV);
1539 }
1540
1541 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
1542 if (IS_ERR(host)) {
1543 dev_err(&pdev->dev, "cannot allocate host\n");
1544 return ERR_CAST(host);
1545 }
1546
1547 slot = sdhci_priv(host);
1548
1549 slot->chip = chip;
1550 slot->host = host;
1551 slot->rst_n_gpio = -EINVAL;
1552 slot->cd_gpio = -EINVAL;
1553 slot->cd_idx = -1;
1554
1555 /* Retrieve platform data if there is any */
1556 if (*sdhci_pci_get_data)
1557 slot->data = sdhci_pci_get_data(pdev, slotno);
1558
1559 if (slot->data) {
1560 if (slot->data->setup) {
1561 ret = slot->data->setup(slot->data);
1562 if (ret) {
1563 dev_err(&pdev->dev, "platform setup failed\n");
1564 goto free;
1565 }
1566 }
1567 slot->rst_n_gpio = slot->data->rst_n_gpio;
1568 slot->cd_gpio = slot->data->cd_gpio;
1569 }
1570
1571 host->hw_name = "PCI";
1572 host->ops = chip->fixes && chip->fixes->ops ?
1573 chip->fixes->ops :
1574 &sdhci_pci_ops;
1575 host->quirks = chip->quirks;
1576 host->quirks2 = chip->quirks2;
1577
1578 host->irq = pdev->irq;
1579
1580 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
1581 if (ret) {
1582 dev_err(&pdev->dev, "cannot request region\n");
1583 goto cleanup;
1584 }
1585
1586 host->ioaddr = pcim_iomap_table(pdev)[bar];
1587
1588 if (chip->fixes && chip->fixes->probe_slot) {
1589 ret = chip->fixes->probe_slot(slot);
1590 if (ret)
1591 goto cleanup;
1592 }
1593
1594 if (gpio_is_valid(slot->rst_n_gpio)) {
1595 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
1596 gpio_direction_output(slot->rst_n_gpio, 1);
1597 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1598 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1599 } else {
1600 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1601 slot->rst_n_gpio = -EINVAL;
1602 }
1603 }
1604
1605 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1606 host->mmc->slotno = slotno;
1607 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1608
1609 if (slot->cd_idx >= 0) {
1610 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx,
1611 slot->cd_override_level, 0, NULL);
1612 if (ret && ret != -EPROBE_DEFER)
1613 ret = mmc_gpiod_request_cd(host->mmc, NULL,
1614 slot->cd_idx,
1615 slot->cd_override_level,
1616 0, NULL);
1617 if (ret == -EPROBE_DEFER)
1618 goto remove;
1619
1620 if (ret) {
1621 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1622 slot->cd_idx = -1;
1623 }
1624 }
1625
1626 if (chip->fixes && chip->fixes->add_host)
1627 ret = chip->fixes->add_host(slot);
1628 else
1629 ret = sdhci_add_host(host);
1630 if (ret)
1631 goto remove;
1632
1633 sdhci_pci_add_own_cd(slot);
1634
1635 /*
1636 * Check if the chip needs a separate GPIO for card detect to wake up
1637 * from runtime suspend. If it is not there, don't allow runtime PM.
1638 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1639 */
1640 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1641 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1642 chip->allow_runtime_pm = false;
1643
1644 return slot;
1645
1646 remove:
1647 if (chip->fixes && chip->fixes->remove_slot)
1648 chip->fixes->remove_slot(slot, 0);
1649
1650 cleanup:
1651 if (slot->data && slot->data->cleanup)
1652 slot->data->cleanup(slot->data);
1653
1654 free:
1655 sdhci_free_host(host);
1656
1657 return ERR_PTR(ret);
1658 }
1659
sdhci_pci_remove_slot(struct sdhci_pci_slot * slot)1660 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1661 {
1662 int dead;
1663 u32 scratch;
1664
1665 sdhci_pci_remove_own_cd(slot);
1666
1667 dead = 0;
1668 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1669 if (scratch == (u32)-1)
1670 dead = 1;
1671
1672 sdhci_remove_host(slot->host, dead);
1673
1674 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1675 slot->chip->fixes->remove_slot(slot, dead);
1676
1677 if (slot->data && slot->data->cleanup)
1678 slot->data->cleanup(slot->data);
1679
1680 sdhci_free_host(slot->host);
1681 }
1682
sdhci_pci_runtime_pm_allow(struct device * dev)1683 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1684 {
1685 pm_suspend_ignore_children(dev, 1);
1686 pm_runtime_set_autosuspend_delay(dev, 50);
1687 pm_runtime_use_autosuspend(dev);
1688 pm_runtime_allow(dev);
1689 /* Stay active until mmc core scans for a card */
1690 pm_runtime_put_noidle(dev);
1691 }
1692
sdhci_pci_runtime_pm_forbid(struct device * dev)1693 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1694 {
1695 pm_runtime_forbid(dev);
1696 pm_runtime_get_noresume(dev);
1697 }
1698
sdhci_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1699 static int sdhci_pci_probe(struct pci_dev *pdev,
1700 const struct pci_device_id *ent)
1701 {
1702 struct sdhci_pci_chip *chip;
1703 struct sdhci_pci_slot *slot;
1704
1705 u8 slots, first_bar;
1706 int ret, i;
1707
1708 BUG_ON(pdev == NULL);
1709 BUG_ON(ent == NULL);
1710
1711 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1712 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1713
1714 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1715 if (ret)
1716 return ret;
1717
1718 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1719 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1720 if (slots == 0)
1721 return -ENODEV;
1722
1723 BUG_ON(slots > MAX_SLOTS);
1724
1725 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1726 if (ret)
1727 return ret;
1728
1729 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1730
1731 if (first_bar > 5) {
1732 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1733 return -ENODEV;
1734 }
1735
1736 ret = pcim_enable_device(pdev);
1737 if (ret)
1738 return ret;
1739
1740 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1741 if (!chip)
1742 return -ENOMEM;
1743
1744 chip->pdev = pdev;
1745 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1746 if (chip->fixes) {
1747 chip->quirks = chip->fixes->quirks;
1748 chip->quirks2 = chip->fixes->quirks2;
1749 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1750 }
1751 chip->num_slots = slots;
1752 chip->pm_retune = true;
1753 chip->rpm_retune = true;
1754
1755 pci_set_drvdata(pdev, chip);
1756
1757 if (chip->fixes && chip->fixes->probe) {
1758 ret = chip->fixes->probe(chip);
1759 if (ret)
1760 return ret;
1761 }
1762
1763 slots = chip->num_slots; /* Quirk may have changed this */
1764
1765 for (i = 0; i < slots; i++) {
1766 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1767 if (IS_ERR(slot)) {
1768 for (i--; i >= 0; i--)
1769 sdhci_pci_remove_slot(chip->slots[i]);
1770 return PTR_ERR(slot);
1771 }
1772
1773 chip->slots[i] = slot;
1774 }
1775
1776 if (chip->allow_runtime_pm)
1777 sdhci_pci_runtime_pm_allow(&pdev->dev);
1778
1779 return 0;
1780 }
1781
sdhci_pci_remove(struct pci_dev * pdev)1782 static void sdhci_pci_remove(struct pci_dev *pdev)
1783 {
1784 int i;
1785 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1786
1787 if (chip->allow_runtime_pm)
1788 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1789
1790 for (i = 0; i < chip->num_slots; i++)
1791 sdhci_pci_remove_slot(chip->slots[i]);
1792 }
1793
1794 static struct pci_driver sdhci_driver = {
1795 .name = "sdhci-pci",
1796 .id_table = pci_ids,
1797 .probe = sdhci_pci_probe,
1798 .remove = sdhci_pci_remove,
1799 .driver = {
1800 .pm = &sdhci_pci_pm_ops
1801 },
1802 };
1803
1804 module_pci_driver(sdhci_driver);
1805
1806 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1807 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1808 MODULE_LICENSE("GPL");
1809