1 /*
2 * drivers/mtd/nand/fsmc_nand.c
3 *
4 * ST Microelectronics
5 * Flexible Static Memory Controller (FSMC)
6 * Driver for NAND portions
7 *
8 * Copyright © 2010 ST Microelectronics
9 * Vipin Kumar <vipin.kumar@st.com>
10 * Ashish Priyadarshi
11 *
12 * Based on drivers/mtd/nand/nomadik_nand.c
13 *
14 * This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
17 */
18
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/dmaengine.h>
22 #include <linux/dma-direction.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/err.h>
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/resource.h>
28 #include <linux/sched.h>
29 #include <linux/types.h>
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/rawnand.h>
32 #include <linux/mtd/nand_ecc.h>
33 #include <linux/platform_device.h>
34 #include <linux/of.h>
35 #include <linux/mtd/partitions.h>
36 #include <linux/io.h>
37 #include <linux/slab.h>
38 #include <linux/amba/bus.h>
39 #include <mtd/mtd-abi.h>
40
41 /* fsmc controller registers for NOR flash */
42 #define CTRL 0x0
43 /* ctrl register definitions */
44 #define BANK_ENABLE (1 << 0)
45 #define MUXED (1 << 1)
46 #define NOR_DEV (2 << 2)
47 #define WIDTH_8 (0 << 4)
48 #define WIDTH_16 (1 << 4)
49 #define RSTPWRDWN (1 << 6)
50 #define WPROT (1 << 7)
51 #define WRT_ENABLE (1 << 12)
52 #define WAIT_ENB (1 << 13)
53
54 #define CTRL_TIM 0x4
55 /* ctrl_tim register definitions */
56
57 #define FSMC_NOR_BANK_SZ 0x8
58 #define FSMC_NOR_REG_SIZE 0x40
59
60 #define FSMC_NOR_REG(base, bank, reg) (base + \
61 FSMC_NOR_BANK_SZ * (bank) + \
62 reg)
63
64 /* fsmc controller registers for NAND flash */
65 #define PC 0x00
66 /* pc register definitions */
67 #define FSMC_RESET (1 << 0)
68 #define FSMC_WAITON (1 << 1)
69 #define FSMC_ENABLE (1 << 2)
70 #define FSMC_DEVTYPE_NAND (1 << 3)
71 #define FSMC_DEVWID_8 (0 << 4)
72 #define FSMC_DEVWID_16 (1 << 4)
73 #define FSMC_ECCEN (1 << 6)
74 #define FSMC_ECCPLEN_512 (0 << 7)
75 #define FSMC_ECCPLEN_256 (1 << 7)
76 #define FSMC_TCLR_1 (1)
77 #define FSMC_TCLR_SHIFT (9)
78 #define FSMC_TCLR_MASK (0xF)
79 #define FSMC_TAR_1 (1)
80 #define FSMC_TAR_SHIFT (13)
81 #define FSMC_TAR_MASK (0xF)
82 #define STS 0x04
83 /* sts register definitions */
84 #define FSMC_CODE_RDY (1 << 15)
85 #define COMM 0x08
86 /* comm register definitions */
87 #define FSMC_TSET_0 0
88 #define FSMC_TSET_SHIFT 0
89 #define FSMC_TSET_MASK 0xFF
90 #define FSMC_TWAIT_6 6
91 #define FSMC_TWAIT_SHIFT 8
92 #define FSMC_TWAIT_MASK 0xFF
93 #define FSMC_THOLD_4 4
94 #define FSMC_THOLD_SHIFT 16
95 #define FSMC_THOLD_MASK 0xFF
96 #define FSMC_THIZ_1 1
97 #define FSMC_THIZ_SHIFT 24
98 #define FSMC_THIZ_MASK 0xFF
99 #define ATTRIB 0x0C
100 #define IOATA 0x10
101 #define ECC1 0x14
102 #define ECC2 0x18
103 #define ECC3 0x1C
104 #define FSMC_NAND_BANK_SZ 0x20
105
106 #define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \
107 (FSMC_NAND_BANK_SZ * (bank)) + \
108 reg)
109
110 #define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
111
112 struct fsmc_nand_timings {
113 uint8_t tclr;
114 uint8_t tar;
115 uint8_t thiz;
116 uint8_t thold;
117 uint8_t twait;
118 uint8_t tset;
119 };
120
121 enum access_mode {
122 USE_DMA_ACCESS = 1,
123 USE_WORD_ACCESS,
124 };
125
126 /**
127 * struct fsmc_nand_data - structure for FSMC NAND device state
128 *
129 * @pid: Part ID on the AMBA PrimeCell format
130 * @mtd: MTD info for a NAND flash.
131 * @nand: Chip related info for a NAND flash.
132 * @partitions: Partition info for a NAND Flash.
133 * @nr_partitions: Total number of partition of a NAND flash.
134 *
135 * @bank: Bank number for probed device.
136 * @clk: Clock structure for FSMC.
137 *
138 * @read_dma_chan: DMA channel for read access
139 * @write_dma_chan: DMA channel for write access to NAND
140 * @dma_access_complete: Completion structure
141 *
142 * @data_pa: NAND Physical port for Data.
143 * @data_va: NAND port for Data.
144 * @cmd_va: NAND port for Command.
145 * @addr_va: NAND port for Address.
146 * @regs_va: FSMC regs base address.
147 */
148 struct fsmc_nand_data {
149 u32 pid;
150 struct nand_chip nand;
151
152 unsigned int bank;
153 struct device *dev;
154 enum access_mode mode;
155 struct clk *clk;
156
157 /* DMA related objects */
158 struct dma_chan *read_dma_chan;
159 struct dma_chan *write_dma_chan;
160 struct completion dma_access_complete;
161
162 struct fsmc_nand_timings *dev_timings;
163
164 dma_addr_t data_pa;
165 void __iomem *data_va;
166 void __iomem *cmd_va;
167 void __iomem *addr_va;
168 void __iomem *regs_va;
169 };
170
fsmc_ecc1_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)171 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
172 struct mtd_oob_region *oobregion)
173 {
174 struct nand_chip *chip = mtd_to_nand(mtd);
175
176 if (section >= chip->ecc.steps)
177 return -ERANGE;
178
179 oobregion->offset = (section * 16) + 2;
180 oobregion->length = 3;
181
182 return 0;
183 }
184
fsmc_ecc1_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)185 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
186 struct mtd_oob_region *oobregion)
187 {
188 struct nand_chip *chip = mtd_to_nand(mtd);
189
190 if (section >= chip->ecc.steps)
191 return -ERANGE;
192
193 oobregion->offset = (section * 16) + 8;
194
195 if (section < chip->ecc.steps - 1)
196 oobregion->length = 8;
197 else
198 oobregion->length = mtd->oobsize - oobregion->offset;
199
200 return 0;
201 }
202
203 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
204 .ecc = fsmc_ecc1_ooblayout_ecc,
205 .free = fsmc_ecc1_ooblayout_free,
206 };
207
208 /*
209 * ECC placement definitions in oobfree type format.
210 * There are 13 bytes of ecc for every 512 byte block and it has to be read
211 * consecutively and immediately after the 512 byte data block for hardware to
212 * generate the error bit offsets in 512 byte data.
213 */
fsmc_ecc4_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)214 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
215 struct mtd_oob_region *oobregion)
216 {
217 struct nand_chip *chip = mtd_to_nand(mtd);
218
219 if (section >= chip->ecc.steps)
220 return -ERANGE;
221
222 oobregion->length = chip->ecc.bytes;
223
224 if (!section && mtd->writesize <= 512)
225 oobregion->offset = 0;
226 else
227 oobregion->offset = (section * 16) + 2;
228
229 return 0;
230 }
231
fsmc_ecc4_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)232 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
233 struct mtd_oob_region *oobregion)
234 {
235 struct nand_chip *chip = mtd_to_nand(mtd);
236
237 if (section >= chip->ecc.steps)
238 return -ERANGE;
239
240 oobregion->offset = (section * 16) + 15;
241
242 if (section < chip->ecc.steps - 1)
243 oobregion->length = 3;
244 else
245 oobregion->length = mtd->oobsize - oobregion->offset;
246
247 return 0;
248 }
249
250 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
251 .ecc = fsmc_ecc4_ooblayout_ecc,
252 .free = fsmc_ecc4_ooblayout_free,
253 };
254
mtd_to_fsmc(struct mtd_info * mtd)255 static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd)
256 {
257 return container_of(mtd_to_nand(mtd), struct fsmc_nand_data, nand);
258 }
259
260 /*
261 * fsmc_cmd_ctrl - For facilitaing Hardware access
262 * This routine allows hardware specific access to control-lines(ALE,CLE)
263 */
fsmc_cmd_ctrl(struct mtd_info * mtd,int cmd,unsigned int ctrl)264 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
265 {
266 struct nand_chip *this = mtd_to_nand(mtd);
267 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
268 void __iomem *regs = host->regs_va;
269 unsigned int bank = host->bank;
270
271 if (ctrl & NAND_CTRL_CHANGE) {
272 u32 pc;
273
274 if (ctrl & NAND_CLE) {
275 this->IO_ADDR_R = host->cmd_va;
276 this->IO_ADDR_W = host->cmd_va;
277 } else if (ctrl & NAND_ALE) {
278 this->IO_ADDR_R = host->addr_va;
279 this->IO_ADDR_W = host->addr_va;
280 } else {
281 this->IO_ADDR_R = host->data_va;
282 this->IO_ADDR_W = host->data_va;
283 }
284
285 pc = readl(FSMC_NAND_REG(regs, bank, PC));
286 if (ctrl & NAND_NCE)
287 pc |= FSMC_ENABLE;
288 else
289 pc &= ~FSMC_ENABLE;
290 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));
291 }
292
293 mb();
294
295 if (cmd != NAND_CMD_NONE)
296 writeb_relaxed(cmd, this->IO_ADDR_W);
297 }
298
299 /*
300 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
301 *
302 * This routine initializes timing parameters related to NAND memory access in
303 * FSMC registers
304 */
fsmc_nand_setup(struct fsmc_nand_data * host,struct fsmc_nand_timings * tims)305 static void fsmc_nand_setup(struct fsmc_nand_data *host,
306 struct fsmc_nand_timings *tims)
307 {
308 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
309 uint32_t tclr, tar, thiz, thold, twait, tset;
310 unsigned int bank = host->bank;
311 void __iomem *regs = host->regs_va;
312
313 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
314 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
315 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
316 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
317 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
318 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
319
320 if (host->nand.options & NAND_BUSWIDTH_16)
321 writel_relaxed(value | FSMC_DEVWID_16,
322 FSMC_NAND_REG(regs, bank, PC));
323 else
324 writel_relaxed(value | FSMC_DEVWID_8,
325 FSMC_NAND_REG(regs, bank, PC));
326
327 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
328 FSMC_NAND_REG(regs, bank, PC));
329 writel_relaxed(thiz | thold | twait | tset,
330 FSMC_NAND_REG(regs, bank, COMM));
331 writel_relaxed(thiz | thold | twait | tset,
332 FSMC_NAND_REG(regs, bank, ATTRIB));
333 }
334
fsmc_calc_timings(struct fsmc_nand_data * host,const struct nand_sdr_timings * sdrt,struct fsmc_nand_timings * tims)335 static int fsmc_calc_timings(struct fsmc_nand_data *host,
336 const struct nand_sdr_timings *sdrt,
337 struct fsmc_nand_timings *tims)
338 {
339 unsigned long hclk = clk_get_rate(host->clk);
340 unsigned long hclkn = NSEC_PER_SEC / hclk;
341 uint32_t thiz, thold, twait, tset;
342
343 if (sdrt->tRC_min < 30000)
344 return -EOPNOTSUPP;
345
346 tims->tar = DIV_ROUND_UP(sdrt->tAR_min / 1000, hclkn) - 1;
347 if (tims->tar > FSMC_TAR_MASK)
348 tims->tar = FSMC_TAR_MASK;
349 tims->tclr = DIV_ROUND_UP(sdrt->tCLR_min / 1000, hclkn) - 1;
350 if (tims->tclr > FSMC_TCLR_MASK)
351 tims->tclr = FSMC_TCLR_MASK;
352
353 thiz = sdrt->tCS_min - sdrt->tWP_min;
354 tims->thiz = DIV_ROUND_UP(thiz / 1000, hclkn);
355
356 thold = sdrt->tDH_min;
357 if (thold < sdrt->tCH_min)
358 thold = sdrt->tCH_min;
359 if (thold < sdrt->tCLH_min)
360 thold = sdrt->tCLH_min;
361 if (thold < sdrt->tWH_min)
362 thold = sdrt->tWH_min;
363 if (thold < sdrt->tALH_min)
364 thold = sdrt->tALH_min;
365 if (thold < sdrt->tREH_min)
366 thold = sdrt->tREH_min;
367 tims->thold = DIV_ROUND_UP(thold / 1000, hclkn);
368 if (tims->thold == 0)
369 tims->thold = 1;
370 else if (tims->thold > FSMC_THOLD_MASK)
371 tims->thold = FSMC_THOLD_MASK;
372
373 twait = max(sdrt->tRP_min, sdrt->tWP_min);
374 tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1;
375 if (tims->twait == 0)
376 tims->twait = 1;
377 else if (tims->twait > FSMC_TWAIT_MASK)
378 tims->twait = FSMC_TWAIT_MASK;
379
380 tset = max(sdrt->tCS_min - sdrt->tWP_min,
381 sdrt->tCEA_max - sdrt->tREA_max);
382 tims->tset = DIV_ROUND_UP(tset / 1000, hclkn) - 1;
383 if (tims->tset == 0)
384 tims->tset = 1;
385 else if (tims->tset > FSMC_TSET_MASK)
386 tims->tset = FSMC_TSET_MASK;
387
388 return 0;
389 }
390
fsmc_setup_data_interface(struct mtd_info * mtd,int csline,const struct nand_data_interface * conf)391 static int fsmc_setup_data_interface(struct mtd_info *mtd, int csline,
392 const struct nand_data_interface *conf)
393 {
394 struct nand_chip *nand = mtd_to_nand(mtd);
395 struct fsmc_nand_data *host = nand_get_controller_data(nand);
396 struct fsmc_nand_timings tims;
397 const struct nand_sdr_timings *sdrt;
398 int ret;
399
400 sdrt = nand_get_sdr_timings(conf);
401 if (IS_ERR(sdrt))
402 return PTR_ERR(sdrt);
403
404 ret = fsmc_calc_timings(host, sdrt, &tims);
405 if (ret)
406 return ret;
407
408 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
409 return 0;
410
411 fsmc_nand_setup(host, &tims);
412
413 return 0;
414 }
415
416 /*
417 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
418 */
fsmc_enable_hwecc(struct mtd_info * mtd,int mode)419 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
420 {
421 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
422 void __iomem *regs = host->regs_va;
423 uint32_t bank = host->bank;
424
425 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
426 FSMC_NAND_REG(regs, bank, PC));
427 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
428 FSMC_NAND_REG(regs, bank, PC));
429 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
430 FSMC_NAND_REG(regs, bank, PC));
431 }
432
433 /*
434 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
435 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
436 * max of 8-bits)
437 */
fsmc_read_hwecc_ecc4(struct mtd_info * mtd,const uint8_t * data,uint8_t * ecc)438 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
439 uint8_t *ecc)
440 {
441 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
442 void __iomem *regs = host->regs_va;
443 uint32_t bank = host->bank;
444 uint32_t ecc_tmp;
445 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
446
447 do {
448 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
449 break;
450 else
451 cond_resched();
452 } while (!time_after_eq(jiffies, deadline));
453
454 if (time_after_eq(jiffies, deadline)) {
455 dev_err(host->dev, "calculate ecc timed out\n");
456 return -ETIMEDOUT;
457 }
458
459 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
460 ecc[0] = (uint8_t) (ecc_tmp >> 0);
461 ecc[1] = (uint8_t) (ecc_tmp >> 8);
462 ecc[2] = (uint8_t) (ecc_tmp >> 16);
463 ecc[3] = (uint8_t) (ecc_tmp >> 24);
464
465 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
466 ecc[4] = (uint8_t) (ecc_tmp >> 0);
467 ecc[5] = (uint8_t) (ecc_tmp >> 8);
468 ecc[6] = (uint8_t) (ecc_tmp >> 16);
469 ecc[7] = (uint8_t) (ecc_tmp >> 24);
470
471 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
472 ecc[8] = (uint8_t) (ecc_tmp >> 0);
473 ecc[9] = (uint8_t) (ecc_tmp >> 8);
474 ecc[10] = (uint8_t) (ecc_tmp >> 16);
475 ecc[11] = (uint8_t) (ecc_tmp >> 24);
476
477 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
478 ecc[12] = (uint8_t) (ecc_tmp >> 16);
479
480 return 0;
481 }
482
483 /*
484 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
485 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
486 * max of 1-bit)
487 */
fsmc_read_hwecc_ecc1(struct mtd_info * mtd,const uint8_t * data,uint8_t * ecc)488 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
489 uint8_t *ecc)
490 {
491 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
492 void __iomem *regs = host->regs_va;
493 uint32_t bank = host->bank;
494 uint32_t ecc_tmp;
495
496 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
497 ecc[0] = (uint8_t) (ecc_tmp >> 0);
498 ecc[1] = (uint8_t) (ecc_tmp >> 8);
499 ecc[2] = (uint8_t) (ecc_tmp >> 16);
500
501 return 0;
502 }
503
504 /* Count the number of 0's in buff upto a max of max_bits */
count_written_bits(uint8_t * buff,int size,int max_bits)505 static int count_written_bits(uint8_t *buff, int size, int max_bits)
506 {
507 int k, written_bits = 0;
508
509 for (k = 0; k < size; k++) {
510 written_bits += hweight8(~buff[k]);
511 if (written_bits > max_bits)
512 break;
513 }
514
515 return written_bits;
516 }
517
dma_complete(void * param)518 static void dma_complete(void *param)
519 {
520 struct fsmc_nand_data *host = param;
521
522 complete(&host->dma_access_complete);
523 }
524
dma_xfer(struct fsmc_nand_data * host,void * buffer,int len,enum dma_data_direction direction)525 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
526 enum dma_data_direction direction)
527 {
528 struct dma_chan *chan;
529 struct dma_device *dma_dev;
530 struct dma_async_tx_descriptor *tx;
531 dma_addr_t dma_dst, dma_src, dma_addr;
532 dma_cookie_t cookie;
533 unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
534 int ret;
535 unsigned long time_left;
536
537 if (direction == DMA_TO_DEVICE)
538 chan = host->write_dma_chan;
539 else if (direction == DMA_FROM_DEVICE)
540 chan = host->read_dma_chan;
541 else
542 return -EINVAL;
543
544 dma_dev = chan->device;
545 dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
546
547 if (direction == DMA_TO_DEVICE) {
548 dma_src = dma_addr;
549 dma_dst = host->data_pa;
550 } else {
551 dma_src = host->data_pa;
552 dma_dst = dma_addr;
553 }
554
555 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
556 len, flags);
557 if (!tx) {
558 dev_err(host->dev, "device_prep_dma_memcpy error\n");
559 ret = -EIO;
560 goto unmap_dma;
561 }
562
563 tx->callback = dma_complete;
564 tx->callback_param = host;
565 cookie = tx->tx_submit(tx);
566
567 ret = dma_submit_error(cookie);
568 if (ret) {
569 dev_err(host->dev, "dma_submit_error %d\n", cookie);
570 goto unmap_dma;
571 }
572
573 dma_async_issue_pending(chan);
574
575 time_left =
576 wait_for_completion_timeout(&host->dma_access_complete,
577 msecs_to_jiffies(3000));
578 if (time_left == 0) {
579 dmaengine_terminate_all(chan);
580 dev_err(host->dev, "wait_for_completion_timeout\n");
581 ret = -ETIMEDOUT;
582 goto unmap_dma;
583 }
584
585 ret = 0;
586
587 unmap_dma:
588 dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
589
590 return ret;
591 }
592
593 /*
594 * fsmc_write_buf - write buffer to chip
595 * @mtd: MTD device structure
596 * @buf: data buffer
597 * @len: number of bytes to write
598 */
fsmc_write_buf(struct mtd_info * mtd,const uint8_t * buf,int len)599 static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
600 {
601 int i;
602 struct nand_chip *chip = mtd_to_nand(mtd);
603
604 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
605 IS_ALIGNED(len, sizeof(uint32_t))) {
606 uint32_t *p = (uint32_t *)buf;
607 len = len >> 2;
608 for (i = 0; i < len; i++)
609 writel_relaxed(p[i], chip->IO_ADDR_W);
610 } else {
611 for (i = 0; i < len; i++)
612 writeb_relaxed(buf[i], chip->IO_ADDR_W);
613 }
614 }
615
616 /*
617 * fsmc_read_buf - read chip data into buffer
618 * @mtd: MTD device structure
619 * @buf: buffer to store date
620 * @len: number of bytes to read
621 */
fsmc_read_buf(struct mtd_info * mtd,uint8_t * buf,int len)622 static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
623 {
624 int i;
625 struct nand_chip *chip = mtd_to_nand(mtd);
626
627 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
628 IS_ALIGNED(len, sizeof(uint32_t))) {
629 uint32_t *p = (uint32_t *)buf;
630 len = len >> 2;
631 for (i = 0; i < len; i++)
632 p[i] = readl_relaxed(chip->IO_ADDR_R);
633 } else {
634 for (i = 0; i < len; i++)
635 buf[i] = readb_relaxed(chip->IO_ADDR_R);
636 }
637 }
638
639 /*
640 * fsmc_read_buf_dma - read chip data into buffer
641 * @mtd: MTD device structure
642 * @buf: buffer to store date
643 * @len: number of bytes to read
644 */
fsmc_read_buf_dma(struct mtd_info * mtd,uint8_t * buf,int len)645 static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
646 {
647 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
648
649 dma_xfer(host, buf, len, DMA_FROM_DEVICE);
650 }
651
652 /*
653 * fsmc_write_buf_dma - write buffer to chip
654 * @mtd: MTD device structure
655 * @buf: data buffer
656 * @len: number of bytes to write
657 */
fsmc_write_buf_dma(struct mtd_info * mtd,const uint8_t * buf,int len)658 static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
659 int len)
660 {
661 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
662
663 dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
664 }
665
666 /*
667 * fsmc_read_page_hwecc
668 * @mtd: mtd info structure
669 * @chip: nand chip info structure
670 * @buf: buffer to store read data
671 * @oob_required: caller expects OOB data read to chip->oob_poi
672 * @page: page number to read
673 *
674 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
675 * performed in a strict sequence as follows:
676 * data(512 byte) -> ecc(13 byte)
677 * After this read, fsmc hardware generates and reports error data bits(up to a
678 * max of 8 bits)
679 */
fsmc_read_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)680 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
681 uint8_t *buf, int oob_required, int page)
682 {
683 int i, j, s, stat, eccsize = chip->ecc.size;
684 int eccbytes = chip->ecc.bytes;
685 int eccsteps = chip->ecc.steps;
686 uint8_t *p = buf;
687 uint8_t *ecc_calc = chip->buffers->ecccalc;
688 uint8_t *ecc_code = chip->buffers->ecccode;
689 int off, len, group = 0;
690 /*
691 * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
692 * end up reading 14 bytes (7 words) from oob. The local array is
693 * to maintain word alignment
694 */
695 uint16_t ecc_oob[7];
696 uint8_t *oob = (uint8_t *)&ecc_oob[0];
697 unsigned int max_bitflips = 0;
698
699 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
700 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
701 chip->ecc.hwctl(mtd, NAND_ECC_READ);
702 chip->read_buf(mtd, p, eccsize);
703
704 for (j = 0; j < eccbytes;) {
705 struct mtd_oob_region oobregion;
706 int ret;
707
708 ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
709 if (ret)
710 return ret;
711
712 off = oobregion.offset;
713 len = oobregion.length;
714
715 /*
716 * length is intentionally kept a higher multiple of 2
717 * to read at least 13 bytes even in case of 16 bit NAND
718 * devices
719 */
720 if (chip->options & NAND_BUSWIDTH_16)
721 len = roundup(len, 2);
722
723 chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
724 chip->read_buf(mtd, oob + j, len);
725 j += len;
726 }
727
728 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
729 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
730
731 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
732 if (stat < 0) {
733 mtd->ecc_stats.failed++;
734 } else {
735 mtd->ecc_stats.corrected += stat;
736 max_bitflips = max_t(unsigned int, max_bitflips, stat);
737 }
738 }
739
740 return max_bitflips;
741 }
742
743 /*
744 * fsmc_bch8_correct_data
745 * @mtd: mtd info structure
746 * @dat: buffer of read data
747 * @read_ecc: ecc read from device spare area
748 * @calc_ecc: ecc calculated from read data
749 *
750 * calc_ecc is a 104 bit information containing maximum of 8 error
751 * offset informations of 13 bits each in 512 bytes of read data.
752 */
fsmc_bch8_correct_data(struct mtd_info * mtd,uint8_t * dat,uint8_t * read_ecc,uint8_t * calc_ecc)753 static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
754 uint8_t *read_ecc, uint8_t *calc_ecc)
755 {
756 struct nand_chip *chip = mtd_to_nand(mtd);
757 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
758 void __iomem *regs = host->regs_va;
759 unsigned int bank = host->bank;
760 uint32_t err_idx[8];
761 uint32_t num_err, i;
762 uint32_t ecc1, ecc2, ecc3, ecc4;
763
764 num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
765
766 /* no bit flipping */
767 if (likely(num_err == 0))
768 return 0;
769
770 /* too many errors */
771 if (unlikely(num_err > 8)) {
772 /*
773 * This is a temporary erase check. A newly erased page read
774 * would result in an ecc error because the oob data is also
775 * erased to FF and the calculated ecc for an FF data is not
776 * FF..FF.
777 * This is a workaround to skip performing correction in case
778 * data is FF..FF
779 *
780 * Logic:
781 * For every page, each bit written as 0 is counted until these
782 * number of bits are greater than 8 (the maximum correction
783 * capability of FSMC for each 512 + 13 bytes)
784 */
785
786 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
787 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
788
789 if ((bits_ecc + bits_data) <= 8) {
790 if (bits_data)
791 memset(dat, 0xff, chip->ecc.size);
792 return bits_data;
793 }
794
795 return -EBADMSG;
796 }
797
798 /*
799 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
800 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
801 *
802 * calc_ecc is a 104 bit information containing maximum of 8 error
803 * offset informations of 13 bits each. calc_ecc is copied into a
804 * uint64_t array and error offset indexes are populated in err_idx
805 * array
806 */
807 ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
808 ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
809 ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
810 ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
811
812 err_idx[0] = (ecc1 >> 0) & 0x1FFF;
813 err_idx[1] = (ecc1 >> 13) & 0x1FFF;
814 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
815 err_idx[3] = (ecc2 >> 7) & 0x1FFF;
816 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
817 err_idx[5] = (ecc3 >> 1) & 0x1FFF;
818 err_idx[6] = (ecc3 >> 14) & 0x1FFF;
819 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
820
821 i = 0;
822 while (num_err--) {
823 change_bit(0, (unsigned long *)&err_idx[i]);
824 change_bit(1, (unsigned long *)&err_idx[i]);
825
826 if (err_idx[i] < chip->ecc.size * 8) {
827 change_bit(err_idx[i], (unsigned long *)dat);
828 i++;
829 }
830 }
831 return i;
832 }
833
filter(struct dma_chan * chan,void * slave)834 static bool filter(struct dma_chan *chan, void *slave)
835 {
836 chan->private = slave;
837 return true;
838 }
839
fsmc_nand_probe_config_dt(struct platform_device * pdev,struct fsmc_nand_data * host,struct nand_chip * nand)840 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
841 struct fsmc_nand_data *host,
842 struct nand_chip *nand)
843 {
844 struct device_node *np = pdev->dev.of_node;
845 u32 val;
846 int ret;
847
848 nand->options = 0;
849
850 if (!of_property_read_u32(np, "bank-width", &val)) {
851 if (val == 2) {
852 nand->options |= NAND_BUSWIDTH_16;
853 } else if (val != 1) {
854 dev_err(&pdev->dev, "invalid bank-width %u\n", val);
855 return -EINVAL;
856 }
857 }
858
859 if (of_get_property(np, "nand-skip-bbtscan", NULL))
860 nand->options |= NAND_SKIP_BBTSCAN;
861
862 host->dev_timings = devm_kzalloc(&pdev->dev,
863 sizeof(*host->dev_timings), GFP_KERNEL);
864 if (!host->dev_timings)
865 return -ENOMEM;
866 ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings,
867 sizeof(*host->dev_timings));
868 if (ret)
869 host->dev_timings = NULL;
870
871 /* Set default NAND bank to 0 */
872 host->bank = 0;
873 if (!of_property_read_u32(np, "bank", &val)) {
874 if (val > 3) {
875 dev_err(&pdev->dev, "invalid bank %u\n", val);
876 return -EINVAL;
877 }
878 host->bank = val;
879 }
880 return 0;
881 }
882
883 /*
884 * fsmc_nand_probe - Probe function
885 * @pdev: platform device structure
886 */
fsmc_nand_probe(struct platform_device * pdev)887 static int __init fsmc_nand_probe(struct platform_device *pdev)
888 {
889 struct fsmc_nand_data *host;
890 struct mtd_info *mtd;
891 struct nand_chip *nand;
892 struct resource *res;
893 dma_cap_mask_t mask;
894 int ret = 0;
895 u32 pid;
896 int i;
897
898 /* Allocate memory for the device structure (and zero it) */
899 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
900 if (!host)
901 return -ENOMEM;
902
903 nand = &host->nand;
904
905 ret = fsmc_nand_probe_config_dt(pdev, host, nand);
906 if (ret)
907 return ret;
908
909 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
910 host->data_va = devm_ioremap_resource(&pdev->dev, res);
911 if (IS_ERR(host->data_va))
912 return PTR_ERR(host->data_va);
913
914 host->data_pa = (dma_addr_t)res->start;
915
916 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
917 host->addr_va = devm_ioremap_resource(&pdev->dev, res);
918 if (IS_ERR(host->addr_va))
919 return PTR_ERR(host->addr_va);
920
921 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
922 host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
923 if (IS_ERR(host->cmd_va))
924 return PTR_ERR(host->cmd_va);
925
926 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
927 host->regs_va = devm_ioremap_resource(&pdev->dev, res);
928 if (IS_ERR(host->regs_va))
929 return PTR_ERR(host->regs_va);
930
931 host->clk = devm_clk_get(&pdev->dev, NULL);
932 if (IS_ERR(host->clk)) {
933 dev_err(&pdev->dev, "failed to fetch block clock\n");
934 return PTR_ERR(host->clk);
935 }
936
937 ret = clk_prepare_enable(host->clk);
938 if (ret)
939 return ret;
940
941 /*
942 * This device ID is actually a common AMBA ID as used on the
943 * AMBA PrimeCell bus. However it is not a PrimeCell.
944 */
945 for (pid = 0, i = 0; i < 4; i++)
946 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
947 host->pid = pid;
948 dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
949 "revision %02x, config %02x\n",
950 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
951 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
952
953 host->dev = &pdev->dev;
954
955 if (host->mode == USE_DMA_ACCESS)
956 init_completion(&host->dma_access_complete);
957
958 /* Link all private pointers */
959 mtd = nand_to_mtd(&host->nand);
960 nand_set_controller_data(nand, host);
961 nand_set_flash_node(nand, pdev->dev.of_node);
962
963 mtd->dev.parent = &pdev->dev;
964 nand->IO_ADDR_R = host->data_va;
965 nand->IO_ADDR_W = host->data_va;
966 nand->cmd_ctrl = fsmc_cmd_ctrl;
967 nand->chip_delay = 30;
968
969 /*
970 * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
971 * can overwrite this value if the DT provides a different value.
972 */
973 nand->ecc.mode = NAND_ECC_HW;
974 nand->ecc.hwctl = fsmc_enable_hwecc;
975 nand->ecc.size = 512;
976 nand->badblockbits = 7;
977
978 switch (host->mode) {
979 case USE_DMA_ACCESS:
980 dma_cap_zero(mask);
981 dma_cap_set(DMA_MEMCPY, mask);
982 host->read_dma_chan = dma_request_channel(mask, filter, NULL);
983 if (!host->read_dma_chan) {
984 dev_err(&pdev->dev, "Unable to get read dma channel\n");
985 goto err_req_read_chnl;
986 }
987 host->write_dma_chan = dma_request_channel(mask, filter, NULL);
988 if (!host->write_dma_chan) {
989 dev_err(&pdev->dev, "Unable to get write dma channel\n");
990 goto err_req_write_chnl;
991 }
992 nand->read_buf = fsmc_read_buf_dma;
993 nand->write_buf = fsmc_write_buf_dma;
994 break;
995
996 default:
997 case USE_WORD_ACCESS:
998 nand->read_buf = fsmc_read_buf;
999 nand->write_buf = fsmc_write_buf;
1000 break;
1001 }
1002
1003 if (host->dev_timings)
1004 fsmc_nand_setup(host, host->dev_timings);
1005 else
1006 nand->setup_data_interface = fsmc_setup_data_interface;
1007
1008 if (AMBA_REV_BITS(host->pid) >= 8) {
1009 nand->ecc.read_page = fsmc_read_page_hwecc;
1010 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
1011 nand->ecc.correct = fsmc_bch8_correct_data;
1012 nand->ecc.bytes = 13;
1013 nand->ecc.strength = 8;
1014 }
1015
1016 /*
1017 * Scan to find existence of the device
1018 */
1019 ret = nand_scan_ident(mtd, 1, NULL);
1020 if (ret) {
1021 dev_err(&pdev->dev, "No NAND Device found!\n");
1022 goto err_scan_ident;
1023 }
1024
1025 if (AMBA_REV_BITS(host->pid) >= 8) {
1026 switch (mtd->oobsize) {
1027 case 16:
1028 case 64:
1029 case 128:
1030 case 224:
1031 case 256:
1032 break;
1033 default:
1034 dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
1035 mtd->oobsize);
1036 ret = -EINVAL;
1037 goto err_probe;
1038 }
1039
1040 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
1041 } else {
1042 switch (nand->ecc.mode) {
1043 case NAND_ECC_HW:
1044 dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
1045 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
1046 nand->ecc.correct = nand_correct_data;
1047 nand->ecc.bytes = 3;
1048 nand->ecc.strength = 1;
1049 break;
1050
1051 case NAND_ECC_SOFT:
1052 if (nand->ecc.algo == NAND_ECC_BCH) {
1053 dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
1054 break;
1055 }
1056
1057 case NAND_ECC_ON_DIE:
1058 break;
1059
1060 default:
1061 dev_err(&pdev->dev, "Unsupported ECC mode!\n");
1062 goto err_probe;
1063 }
1064
1065 /*
1066 * Don't set layout for BCH4 SW ECC. This will be
1067 * generated later in nand_bch_init() later.
1068 */
1069 if (nand->ecc.mode == NAND_ECC_HW) {
1070 switch (mtd->oobsize) {
1071 case 16:
1072 case 64:
1073 case 128:
1074 mtd_set_ooblayout(mtd,
1075 &fsmc_ecc1_ooblayout_ops);
1076 break;
1077 default:
1078 dev_warn(&pdev->dev,
1079 "No oob scheme defined for oobsize %d\n",
1080 mtd->oobsize);
1081 ret = -EINVAL;
1082 goto err_probe;
1083 }
1084 }
1085 }
1086
1087 /* Second stage of scan to fill MTD data-structures */
1088 ret = nand_scan_tail(mtd);
1089 if (ret)
1090 goto err_probe;
1091
1092 mtd->name = "nand";
1093 ret = mtd_device_register(mtd, NULL, 0);
1094 if (ret)
1095 goto err_probe;
1096
1097 platform_set_drvdata(pdev, host);
1098 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1099 return 0;
1100
1101 err_probe:
1102 err_scan_ident:
1103 if (host->mode == USE_DMA_ACCESS)
1104 dma_release_channel(host->write_dma_chan);
1105 err_req_write_chnl:
1106 if (host->mode == USE_DMA_ACCESS)
1107 dma_release_channel(host->read_dma_chan);
1108 err_req_read_chnl:
1109 clk_disable_unprepare(host->clk);
1110 return ret;
1111 }
1112
1113 /*
1114 * Clean up routine
1115 */
fsmc_nand_remove(struct platform_device * pdev)1116 static int fsmc_nand_remove(struct platform_device *pdev)
1117 {
1118 struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1119
1120 if (host) {
1121 nand_release(nand_to_mtd(&host->nand));
1122
1123 if (host->mode == USE_DMA_ACCESS) {
1124 dma_release_channel(host->write_dma_chan);
1125 dma_release_channel(host->read_dma_chan);
1126 }
1127 clk_disable_unprepare(host->clk);
1128 }
1129
1130 return 0;
1131 }
1132
1133 #ifdef CONFIG_PM_SLEEP
fsmc_nand_suspend(struct device * dev)1134 static int fsmc_nand_suspend(struct device *dev)
1135 {
1136 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1137 if (host)
1138 clk_disable_unprepare(host->clk);
1139 return 0;
1140 }
1141
fsmc_nand_resume(struct device * dev)1142 static int fsmc_nand_resume(struct device *dev)
1143 {
1144 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1145 if (host) {
1146 clk_prepare_enable(host->clk);
1147 if (host->dev_timings)
1148 fsmc_nand_setup(host, host->dev_timings);
1149 }
1150 return 0;
1151 }
1152 #endif
1153
1154 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1155
1156 static const struct of_device_id fsmc_nand_id_table[] = {
1157 { .compatible = "st,spear600-fsmc-nand" },
1158 { .compatible = "stericsson,fsmc-nand" },
1159 {}
1160 };
1161 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1162
1163 static struct platform_driver fsmc_nand_driver = {
1164 .remove = fsmc_nand_remove,
1165 .driver = {
1166 .name = "fsmc-nand",
1167 .of_match_table = fsmc_nand_id_table,
1168 .pm = &fsmc_nand_pm_ops,
1169 },
1170 };
1171
1172 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1173
1174 MODULE_LICENSE("GPL");
1175 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1176 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");
1177