1 /*
2 * CAN bus driver for Bosch M_CAN controller
3 *
4 * Copyright (C) 2014 Freescale Semiconductor, Inc.
5 * Dong Aisheng <b29396@freescale.com>
6 *
7 * Bosch M_CAN user manual can be obtained from:
8 * http://www.bosch-semiconductors.de/media/pdf_1/ipmodules_1/m_can/
9 * mcan_users_manual_v302.pdf
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/netdevice.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
26 #include <linux/iopoll.h>
27 #include <linux/can/dev.h>
28 #include <linux/pinctrl/consumer.h>
29
30 /* napi related */
31 #define M_CAN_NAPI_WEIGHT 64
32
33 /* message ram configuration data length */
34 #define MRAM_CFG_LEN 8
35
36 /* registers definition */
37 enum m_can_reg {
38 M_CAN_CREL = 0x0,
39 M_CAN_ENDN = 0x4,
40 M_CAN_CUST = 0x8,
41 M_CAN_DBTP = 0xc,
42 M_CAN_TEST = 0x10,
43 M_CAN_RWD = 0x14,
44 M_CAN_CCCR = 0x18,
45 M_CAN_NBTP = 0x1c,
46 M_CAN_TSCC = 0x20,
47 M_CAN_TSCV = 0x24,
48 M_CAN_TOCC = 0x28,
49 M_CAN_TOCV = 0x2c,
50 M_CAN_ECR = 0x40,
51 M_CAN_PSR = 0x44,
52 /* TDCR Register only available for version >=3.1.x */
53 M_CAN_TDCR = 0x48,
54 M_CAN_IR = 0x50,
55 M_CAN_IE = 0x54,
56 M_CAN_ILS = 0x58,
57 M_CAN_ILE = 0x5c,
58 M_CAN_GFC = 0x80,
59 M_CAN_SIDFC = 0x84,
60 M_CAN_XIDFC = 0x88,
61 M_CAN_XIDAM = 0x90,
62 M_CAN_HPMS = 0x94,
63 M_CAN_NDAT1 = 0x98,
64 M_CAN_NDAT2 = 0x9c,
65 M_CAN_RXF0C = 0xa0,
66 M_CAN_RXF0S = 0xa4,
67 M_CAN_RXF0A = 0xa8,
68 M_CAN_RXBC = 0xac,
69 M_CAN_RXF1C = 0xb0,
70 M_CAN_RXF1S = 0xb4,
71 M_CAN_RXF1A = 0xb8,
72 M_CAN_RXESC = 0xbc,
73 M_CAN_TXBC = 0xc0,
74 M_CAN_TXFQS = 0xc4,
75 M_CAN_TXESC = 0xc8,
76 M_CAN_TXBRP = 0xcc,
77 M_CAN_TXBAR = 0xd0,
78 M_CAN_TXBCR = 0xd4,
79 M_CAN_TXBTO = 0xd8,
80 M_CAN_TXBCF = 0xdc,
81 M_CAN_TXBTIE = 0xe0,
82 M_CAN_TXBCIE = 0xe4,
83 M_CAN_TXEFC = 0xf0,
84 M_CAN_TXEFS = 0xf4,
85 M_CAN_TXEFA = 0xf8,
86 };
87
88 /* m_can lec values */
89 enum m_can_lec_type {
90 LEC_NO_ERROR = 0,
91 LEC_STUFF_ERROR,
92 LEC_FORM_ERROR,
93 LEC_ACK_ERROR,
94 LEC_BIT1_ERROR,
95 LEC_BIT0_ERROR,
96 LEC_CRC_ERROR,
97 LEC_UNUSED,
98 };
99
100 enum m_can_mram_cfg {
101 MRAM_SIDF = 0,
102 MRAM_XIDF,
103 MRAM_RXF0,
104 MRAM_RXF1,
105 MRAM_RXB,
106 MRAM_TXE,
107 MRAM_TXB,
108 MRAM_CFG_NUM,
109 };
110
111 /* Core Release Register (CREL) */
112 #define CREL_REL_SHIFT 28
113 #define CREL_REL_MASK (0xF << CREL_REL_SHIFT)
114 #define CREL_STEP_SHIFT 24
115 #define CREL_STEP_MASK (0xF << CREL_STEP_SHIFT)
116 #define CREL_SUBSTEP_SHIFT 20
117 #define CREL_SUBSTEP_MASK (0xF << CREL_SUBSTEP_SHIFT)
118
119 /* Data Bit Timing & Prescaler Register (DBTP) */
120 #define DBTP_TDC BIT(23)
121 #define DBTP_DBRP_SHIFT 16
122 #define DBTP_DBRP_MASK (0x1f << DBTP_DBRP_SHIFT)
123 #define DBTP_DTSEG1_SHIFT 8
124 #define DBTP_DTSEG1_MASK (0x1f << DBTP_DTSEG1_SHIFT)
125 #define DBTP_DTSEG2_SHIFT 4
126 #define DBTP_DTSEG2_MASK (0xf << DBTP_DTSEG2_SHIFT)
127 #define DBTP_DSJW_SHIFT 0
128 #define DBTP_DSJW_MASK (0xf << DBTP_DSJW_SHIFT)
129
130 /* Test Register (TEST) */
131 #define TEST_LBCK BIT(4)
132
133 /* CC Control Register(CCCR) */
134 #define CCCR_CMR_MASK 0x3
135 #define CCCR_CMR_SHIFT 10
136 #define CCCR_CMR_CANFD 0x1
137 #define CCCR_CMR_CANFD_BRS 0x2
138 #define CCCR_CMR_CAN 0x3
139 #define CCCR_CME_MASK 0x3
140 #define CCCR_CME_SHIFT 8
141 #define CCCR_CME_CAN 0
142 #define CCCR_CME_CANFD 0x1
143 #define CCCR_CME_CANFD_BRS 0x2
144 #define CCCR_TXP BIT(14)
145 #define CCCR_TEST BIT(7)
146 #define CCCR_MON BIT(5)
147 #define CCCR_CSR BIT(4)
148 #define CCCR_CSA BIT(3)
149 #define CCCR_ASM BIT(2)
150 #define CCCR_CCE BIT(1)
151 #define CCCR_INIT BIT(0)
152 #define CCCR_CANFD 0x10
153 /* for version >=3.1.x */
154 #define CCCR_EFBI BIT(13)
155 #define CCCR_PXHD BIT(12)
156 #define CCCR_BRSE BIT(9)
157 #define CCCR_FDOE BIT(8)
158 /* only for version >=3.2.x */
159 #define CCCR_NISO BIT(15)
160
161 /* Nominal Bit Timing & Prescaler Register (NBTP) */
162 #define NBTP_NSJW_SHIFT 25
163 #define NBTP_NSJW_MASK (0x7f << NBTP_NSJW_SHIFT)
164 #define NBTP_NBRP_SHIFT 16
165 #define NBTP_NBRP_MASK (0x1ff << NBTP_NBRP_SHIFT)
166 #define NBTP_NTSEG1_SHIFT 8
167 #define NBTP_NTSEG1_MASK (0xff << NBTP_NTSEG1_SHIFT)
168 #define NBTP_NTSEG2_SHIFT 0
169 #define NBTP_NTSEG2_MASK (0x7f << NBTP_NTSEG2_SHIFT)
170
171 /* Error Counter Register(ECR) */
172 #define ECR_RP BIT(15)
173 #define ECR_REC_SHIFT 8
174 #define ECR_REC_MASK (0x7f << ECR_REC_SHIFT)
175 #define ECR_TEC_SHIFT 0
176 #define ECR_TEC_MASK 0xff
177
178 /* Protocol Status Register(PSR) */
179 #define PSR_BO BIT(7)
180 #define PSR_EW BIT(6)
181 #define PSR_EP BIT(5)
182 #define PSR_LEC_MASK 0x7
183
184 /* Interrupt Register(IR) */
185 #define IR_ALL_INT 0xffffffff
186
187 /* Renamed bits for versions > 3.1.x */
188 #define IR_ARA BIT(29)
189 #define IR_PED BIT(28)
190 #define IR_PEA BIT(27)
191
192 /* Bits for version 3.0.x */
193 #define IR_STE BIT(31)
194 #define IR_FOE BIT(30)
195 #define IR_ACKE BIT(29)
196 #define IR_BE BIT(28)
197 #define IR_CRCE BIT(27)
198 #define IR_WDI BIT(26)
199 #define IR_BO BIT(25)
200 #define IR_EW BIT(24)
201 #define IR_EP BIT(23)
202 #define IR_ELO BIT(22)
203 #define IR_BEU BIT(21)
204 #define IR_BEC BIT(20)
205 #define IR_DRX BIT(19)
206 #define IR_TOO BIT(18)
207 #define IR_MRAF BIT(17)
208 #define IR_TSW BIT(16)
209 #define IR_TEFL BIT(15)
210 #define IR_TEFF BIT(14)
211 #define IR_TEFW BIT(13)
212 #define IR_TEFN BIT(12)
213 #define IR_TFE BIT(11)
214 #define IR_TCF BIT(10)
215 #define IR_TC BIT(9)
216 #define IR_HPM BIT(8)
217 #define IR_RF1L BIT(7)
218 #define IR_RF1F BIT(6)
219 #define IR_RF1W BIT(5)
220 #define IR_RF1N BIT(4)
221 #define IR_RF0L BIT(3)
222 #define IR_RF0F BIT(2)
223 #define IR_RF0W BIT(1)
224 #define IR_RF0N BIT(0)
225 #define IR_ERR_STATE (IR_BO | IR_EW | IR_EP)
226
227 /* Interrupts for version 3.0.x */
228 #define IR_ERR_LEC_30X (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
229 #define IR_ERR_BUS_30X (IR_ERR_LEC_30X | IR_WDI | IR_ELO | IR_BEU | \
230 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
231 IR_RF1L | IR_RF0L)
232 #define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X)
233 /* Interrupts for version >= 3.1.x */
234 #define IR_ERR_LEC_31X (IR_PED | IR_PEA)
235 #define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_ELO | IR_BEU | \
236 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
237 IR_RF1L | IR_RF0L)
238 #define IR_ERR_ALL_31X (IR_ERR_STATE | IR_ERR_BUS_31X)
239
240 /* Interrupt Line Select (ILS) */
241 #define ILS_ALL_INT0 0x0
242 #define ILS_ALL_INT1 0xFFFFFFFF
243
244 /* Interrupt Line Enable (ILE) */
245 #define ILE_EINT1 BIT(1)
246 #define ILE_EINT0 BIT(0)
247
248 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
249 #define RXFC_FWM_SHIFT 24
250 #define RXFC_FWM_MASK (0x7f << RXFC_FWM_SHIFT)
251 #define RXFC_FS_SHIFT 16
252 #define RXFC_FS_MASK (0x7f << RXFC_FS_SHIFT)
253
254 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
255 #define RXFS_RFL BIT(25)
256 #define RXFS_FF BIT(24)
257 #define RXFS_FPI_SHIFT 16
258 #define RXFS_FPI_MASK 0x3f0000
259 #define RXFS_FGI_SHIFT 8
260 #define RXFS_FGI_MASK 0x3f00
261 #define RXFS_FFL_MASK 0x7f
262
263 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */
264 #define M_CAN_RXESC_8BYTES 0x0
265 #define M_CAN_RXESC_64BYTES 0x777
266
267 /* Tx Buffer Configuration(TXBC) */
268 #define TXBC_NDTB_SHIFT 16
269 #define TXBC_NDTB_MASK (0x3f << TXBC_NDTB_SHIFT)
270 #define TXBC_TFQS_SHIFT 24
271 #define TXBC_TFQS_MASK (0x3f << TXBC_TFQS_SHIFT)
272
273 /* Tx FIFO/Queue Status (TXFQS) */
274 #define TXFQS_TFQF BIT(21)
275 #define TXFQS_TFQPI_SHIFT 16
276 #define TXFQS_TFQPI_MASK (0x1f << TXFQS_TFQPI_SHIFT)
277 #define TXFQS_TFGI_SHIFT 8
278 #define TXFQS_TFGI_MASK (0x1f << TXFQS_TFGI_SHIFT)
279 #define TXFQS_TFFL_SHIFT 0
280 #define TXFQS_TFFL_MASK (0x3f << TXFQS_TFFL_SHIFT)
281
282 /* Tx Buffer Element Size Configuration(TXESC) */
283 #define TXESC_TBDS_8BYTES 0x0
284 #define TXESC_TBDS_64BYTES 0x7
285
286 /* Tx Event FIFO Configuration (TXEFC) */
287 #define TXEFC_EFS_SHIFT 16
288 #define TXEFC_EFS_MASK (0x3f << TXEFC_EFS_SHIFT)
289
290 /* Tx Event FIFO Status (TXEFS) */
291 #define TXEFS_TEFL BIT(25)
292 #define TXEFS_EFF BIT(24)
293 #define TXEFS_EFGI_SHIFT 8
294 #define TXEFS_EFGI_MASK (0x1f << TXEFS_EFGI_SHIFT)
295 #define TXEFS_EFFL_SHIFT 0
296 #define TXEFS_EFFL_MASK (0x3f << TXEFS_EFFL_SHIFT)
297
298 /* Tx Event FIFO Acknowledge (TXEFA) */
299 #define TXEFA_EFAI_SHIFT 0
300 #define TXEFA_EFAI_MASK (0x1f << TXEFA_EFAI_SHIFT)
301
302 /* Message RAM Configuration (in bytes) */
303 #define SIDF_ELEMENT_SIZE 4
304 #define XIDF_ELEMENT_SIZE 8
305 #define RXF0_ELEMENT_SIZE 72
306 #define RXF1_ELEMENT_SIZE 72
307 #define RXB_ELEMENT_SIZE 72
308 #define TXE_ELEMENT_SIZE 8
309 #define TXB_ELEMENT_SIZE 72
310
311 /* Message RAM Elements */
312 #define M_CAN_FIFO_ID 0x0
313 #define M_CAN_FIFO_DLC 0x4
314 #define M_CAN_FIFO_DATA(n) (0x8 + ((n) << 2))
315
316 /* Rx Buffer Element */
317 /* R0 */
318 #define RX_BUF_ESI BIT(31)
319 #define RX_BUF_XTD BIT(30)
320 #define RX_BUF_RTR BIT(29)
321 /* R1 */
322 #define RX_BUF_ANMF BIT(31)
323 #define RX_BUF_FDF BIT(21)
324 #define RX_BUF_BRS BIT(20)
325
326 /* Tx Buffer Element */
327 /* T0 */
328 #define TX_BUF_ESI BIT(31)
329 #define TX_BUF_XTD BIT(30)
330 #define TX_BUF_RTR BIT(29)
331 /* T1 */
332 #define TX_BUF_EFC BIT(23)
333 #define TX_BUF_FDF BIT(21)
334 #define TX_BUF_BRS BIT(20)
335 #define TX_BUF_MM_SHIFT 24
336 #define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT)
337
338 /* Tx event FIFO Element */
339 /* E1 */
340 #define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT
341 #define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT)
342
343 /* address offset and element number for each FIFO/Buffer in the Message RAM */
344 struct mram_cfg {
345 u16 off;
346 u8 num;
347 };
348
349 /* m_can private data structure */
350 struct m_can_priv {
351 struct can_priv can; /* must be the first member */
352 struct napi_struct napi;
353 struct net_device *dev;
354 struct device *device;
355 struct clk *hclk;
356 struct clk *cclk;
357 void __iomem *base;
358 u32 irqstatus;
359 int version;
360
361 /* message ram configuration */
362 void __iomem *mram_base;
363 struct mram_cfg mcfg[MRAM_CFG_NUM];
364 };
365
m_can_read(const struct m_can_priv * priv,enum m_can_reg reg)366 static inline u32 m_can_read(const struct m_can_priv *priv, enum m_can_reg reg)
367 {
368 return readl(priv->base + reg);
369 }
370
m_can_write(const struct m_can_priv * priv,enum m_can_reg reg,u32 val)371 static inline void m_can_write(const struct m_can_priv *priv,
372 enum m_can_reg reg, u32 val)
373 {
374 writel(val, priv->base + reg);
375 }
376
m_can_fifo_read(const struct m_can_priv * priv,u32 fgi,unsigned int offset)377 static inline u32 m_can_fifo_read(const struct m_can_priv *priv,
378 u32 fgi, unsigned int offset)
379 {
380 return readl(priv->mram_base + priv->mcfg[MRAM_RXF0].off +
381 fgi * RXF0_ELEMENT_SIZE + offset);
382 }
383
m_can_fifo_write(const struct m_can_priv * priv,u32 fpi,unsigned int offset,u32 val)384 static inline void m_can_fifo_write(const struct m_can_priv *priv,
385 u32 fpi, unsigned int offset, u32 val)
386 {
387 writel(val, priv->mram_base + priv->mcfg[MRAM_TXB].off +
388 fpi * TXB_ELEMENT_SIZE + offset);
389 }
390
m_can_txe_fifo_read(const struct m_can_priv * priv,u32 fgi,u32 offset)391 static inline u32 m_can_txe_fifo_read(const struct m_can_priv *priv,
392 u32 fgi,
393 u32 offset) {
394 return readl(priv->mram_base + priv->mcfg[MRAM_TXE].off +
395 fgi * TXE_ELEMENT_SIZE + offset);
396 }
397
m_can_tx_fifo_full(const struct m_can_priv * priv)398 static inline bool m_can_tx_fifo_full(const struct m_can_priv *priv)
399 {
400 return !!(m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQF);
401 }
402
m_can_config_endisable(const struct m_can_priv * priv,bool enable)403 static inline void m_can_config_endisable(const struct m_can_priv *priv,
404 bool enable)
405 {
406 u32 cccr = m_can_read(priv, M_CAN_CCCR);
407 u32 timeout = 10;
408 u32 val = 0;
409
410 if (enable) {
411 /* enable m_can configuration */
412 m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT);
413 udelay(5);
414 /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */
415 m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE);
416 } else {
417 m_can_write(priv, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE));
418 }
419
420 /* there's a delay for module initialization */
421 if (enable)
422 val = CCCR_INIT | CCCR_CCE;
423
424 while ((m_can_read(priv, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) {
425 if (timeout == 0) {
426 netdev_warn(priv->dev, "Failed to init module\n");
427 return;
428 }
429 timeout--;
430 udelay(1);
431 }
432 }
433
m_can_enable_all_interrupts(const struct m_can_priv * priv)434 static inline void m_can_enable_all_interrupts(const struct m_can_priv *priv)
435 {
436 /* Only interrupt line 0 is used in this driver */
437 m_can_write(priv, M_CAN_ILE, ILE_EINT0);
438 }
439
m_can_disable_all_interrupts(const struct m_can_priv * priv)440 static inline void m_can_disable_all_interrupts(const struct m_can_priv *priv)
441 {
442 m_can_write(priv, M_CAN_ILE, 0x0);
443 }
444
m_can_read_fifo(struct net_device * dev,u32 rxfs)445 static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
446 {
447 struct net_device_stats *stats = &dev->stats;
448 struct m_can_priv *priv = netdev_priv(dev);
449 struct canfd_frame *cf;
450 struct sk_buff *skb;
451 u32 id, fgi, dlc;
452 int i;
453
454 /* calculate the fifo get index for where to read data */
455 fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_SHIFT;
456 dlc = m_can_fifo_read(priv, fgi, M_CAN_FIFO_DLC);
457 if (dlc & RX_BUF_FDF)
458 skb = alloc_canfd_skb(dev, &cf);
459 else
460 skb = alloc_can_skb(dev, (struct can_frame **)&cf);
461 if (!skb) {
462 stats->rx_dropped++;
463 return;
464 }
465
466 if (dlc & RX_BUF_FDF)
467 cf->len = can_dlc2len((dlc >> 16) & 0x0F);
468 else
469 cf->len = get_can_dlc((dlc >> 16) & 0x0F);
470
471 id = m_can_fifo_read(priv, fgi, M_CAN_FIFO_ID);
472 if (id & RX_BUF_XTD)
473 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
474 else
475 cf->can_id = (id >> 18) & CAN_SFF_MASK;
476
477 if (id & RX_BUF_ESI) {
478 cf->flags |= CANFD_ESI;
479 netdev_dbg(dev, "ESI Error\n");
480 }
481
482 if (!(dlc & RX_BUF_FDF) && (id & RX_BUF_RTR)) {
483 cf->can_id |= CAN_RTR_FLAG;
484 } else {
485 if (dlc & RX_BUF_BRS)
486 cf->flags |= CANFD_BRS;
487
488 for (i = 0; i < cf->len; i += 4)
489 *(u32 *)(cf->data + i) =
490 m_can_fifo_read(priv, fgi,
491 M_CAN_FIFO_DATA(i / 4));
492 }
493
494 /* acknowledge rx fifo 0 */
495 m_can_write(priv, M_CAN_RXF0A, fgi);
496
497 stats->rx_packets++;
498 stats->rx_bytes += cf->len;
499
500 netif_receive_skb(skb);
501 }
502
m_can_do_rx_poll(struct net_device * dev,int quota)503 static int m_can_do_rx_poll(struct net_device *dev, int quota)
504 {
505 struct m_can_priv *priv = netdev_priv(dev);
506 u32 pkts = 0;
507 u32 rxfs;
508
509 rxfs = m_can_read(priv, M_CAN_RXF0S);
510 if (!(rxfs & RXFS_FFL_MASK)) {
511 netdev_dbg(dev, "no messages in fifo0\n");
512 return 0;
513 }
514
515 while ((rxfs & RXFS_FFL_MASK) && (quota > 0)) {
516 if (rxfs & RXFS_RFL)
517 netdev_warn(dev, "Rx FIFO 0 Message Lost\n");
518
519 m_can_read_fifo(dev, rxfs);
520
521 quota--;
522 pkts++;
523 rxfs = m_can_read(priv, M_CAN_RXF0S);
524 }
525
526 if (pkts)
527 can_led_event(dev, CAN_LED_EVENT_RX);
528
529 return pkts;
530 }
531
m_can_handle_lost_msg(struct net_device * dev)532 static int m_can_handle_lost_msg(struct net_device *dev)
533 {
534 struct net_device_stats *stats = &dev->stats;
535 struct sk_buff *skb;
536 struct can_frame *frame;
537
538 netdev_err(dev, "msg lost in rxf0\n");
539
540 stats->rx_errors++;
541 stats->rx_over_errors++;
542
543 skb = alloc_can_err_skb(dev, &frame);
544 if (unlikely(!skb))
545 return 0;
546
547 frame->can_id |= CAN_ERR_CRTL;
548 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
549
550 netif_receive_skb(skb);
551
552 return 1;
553 }
554
m_can_handle_lec_err(struct net_device * dev,enum m_can_lec_type lec_type)555 static int m_can_handle_lec_err(struct net_device *dev,
556 enum m_can_lec_type lec_type)
557 {
558 struct m_can_priv *priv = netdev_priv(dev);
559 struct net_device_stats *stats = &dev->stats;
560 struct can_frame *cf;
561 struct sk_buff *skb;
562
563 priv->can.can_stats.bus_error++;
564 stats->rx_errors++;
565
566 /* propagate the error condition to the CAN stack */
567 skb = alloc_can_err_skb(dev, &cf);
568 if (unlikely(!skb))
569 return 0;
570
571 /* check for 'last error code' which tells us the
572 * type of the last error to occur on the CAN bus
573 */
574 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
575
576 switch (lec_type) {
577 case LEC_STUFF_ERROR:
578 netdev_dbg(dev, "stuff error\n");
579 cf->data[2] |= CAN_ERR_PROT_STUFF;
580 break;
581 case LEC_FORM_ERROR:
582 netdev_dbg(dev, "form error\n");
583 cf->data[2] |= CAN_ERR_PROT_FORM;
584 break;
585 case LEC_ACK_ERROR:
586 netdev_dbg(dev, "ack error\n");
587 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
588 break;
589 case LEC_BIT1_ERROR:
590 netdev_dbg(dev, "bit1 error\n");
591 cf->data[2] |= CAN_ERR_PROT_BIT1;
592 break;
593 case LEC_BIT0_ERROR:
594 netdev_dbg(dev, "bit0 error\n");
595 cf->data[2] |= CAN_ERR_PROT_BIT0;
596 break;
597 case LEC_CRC_ERROR:
598 netdev_dbg(dev, "CRC error\n");
599 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
600 break;
601 default:
602 break;
603 }
604
605 stats->rx_packets++;
606 stats->rx_bytes += cf->can_dlc;
607 netif_receive_skb(skb);
608
609 return 1;
610 }
611
__m_can_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)612 static int __m_can_get_berr_counter(const struct net_device *dev,
613 struct can_berr_counter *bec)
614 {
615 struct m_can_priv *priv = netdev_priv(dev);
616 unsigned int ecr;
617
618 ecr = m_can_read(priv, M_CAN_ECR);
619 bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT;
620 bec->txerr = (ecr & ECR_TEC_MASK) >> ECR_TEC_SHIFT;
621
622 return 0;
623 }
624
m_can_clk_start(struct m_can_priv * priv)625 static int m_can_clk_start(struct m_can_priv *priv)
626 {
627 int err;
628
629 err = clk_prepare_enable(priv->hclk);
630 if (err)
631 return err;
632
633 err = clk_prepare_enable(priv->cclk);
634 if (err)
635 clk_disable_unprepare(priv->hclk);
636
637 return err;
638 }
639
m_can_clk_stop(struct m_can_priv * priv)640 static void m_can_clk_stop(struct m_can_priv *priv)
641 {
642 clk_disable_unprepare(priv->cclk);
643 clk_disable_unprepare(priv->hclk);
644 }
645
m_can_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)646 static int m_can_get_berr_counter(const struct net_device *dev,
647 struct can_berr_counter *bec)
648 {
649 struct m_can_priv *priv = netdev_priv(dev);
650 int err;
651
652 err = m_can_clk_start(priv);
653 if (err)
654 return err;
655
656 __m_can_get_berr_counter(dev, bec);
657
658 m_can_clk_stop(priv);
659
660 return 0;
661 }
662
m_can_handle_state_change(struct net_device * dev,enum can_state new_state)663 static int m_can_handle_state_change(struct net_device *dev,
664 enum can_state new_state)
665 {
666 struct m_can_priv *priv = netdev_priv(dev);
667 struct net_device_stats *stats = &dev->stats;
668 struct can_frame *cf;
669 struct sk_buff *skb;
670 struct can_berr_counter bec;
671 unsigned int ecr;
672
673 switch (new_state) {
674 case CAN_STATE_ERROR_ACTIVE:
675 /* error warning state */
676 priv->can.can_stats.error_warning++;
677 priv->can.state = CAN_STATE_ERROR_WARNING;
678 break;
679 case CAN_STATE_ERROR_PASSIVE:
680 /* error passive state */
681 priv->can.can_stats.error_passive++;
682 priv->can.state = CAN_STATE_ERROR_PASSIVE;
683 break;
684 case CAN_STATE_BUS_OFF:
685 /* bus-off state */
686 priv->can.state = CAN_STATE_BUS_OFF;
687 m_can_disable_all_interrupts(priv);
688 priv->can.can_stats.bus_off++;
689 can_bus_off(dev);
690 break;
691 default:
692 break;
693 }
694
695 /* propagate the error condition to the CAN stack */
696 skb = alloc_can_err_skb(dev, &cf);
697 if (unlikely(!skb))
698 return 0;
699
700 __m_can_get_berr_counter(dev, &bec);
701
702 switch (new_state) {
703 case CAN_STATE_ERROR_ACTIVE:
704 /* error warning state */
705 cf->can_id |= CAN_ERR_CRTL;
706 cf->data[1] = (bec.txerr > bec.rxerr) ?
707 CAN_ERR_CRTL_TX_WARNING :
708 CAN_ERR_CRTL_RX_WARNING;
709 cf->data[6] = bec.txerr;
710 cf->data[7] = bec.rxerr;
711 break;
712 case CAN_STATE_ERROR_PASSIVE:
713 /* error passive state */
714 cf->can_id |= CAN_ERR_CRTL;
715 ecr = m_can_read(priv, M_CAN_ECR);
716 if (ecr & ECR_RP)
717 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
718 if (bec.txerr > 127)
719 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
720 cf->data[6] = bec.txerr;
721 cf->data[7] = bec.rxerr;
722 break;
723 case CAN_STATE_BUS_OFF:
724 /* bus-off state */
725 cf->can_id |= CAN_ERR_BUSOFF;
726 break;
727 default:
728 break;
729 }
730
731 stats->rx_packets++;
732 stats->rx_bytes += cf->can_dlc;
733 netif_receive_skb(skb);
734
735 return 1;
736 }
737
m_can_handle_state_errors(struct net_device * dev,u32 psr)738 static int m_can_handle_state_errors(struct net_device *dev, u32 psr)
739 {
740 struct m_can_priv *priv = netdev_priv(dev);
741 int work_done = 0;
742
743 if ((psr & PSR_EW) &&
744 (priv->can.state != CAN_STATE_ERROR_WARNING)) {
745 netdev_dbg(dev, "entered error warning state\n");
746 work_done += m_can_handle_state_change(dev,
747 CAN_STATE_ERROR_WARNING);
748 }
749
750 if ((psr & PSR_EP) &&
751 (priv->can.state != CAN_STATE_ERROR_PASSIVE)) {
752 netdev_dbg(dev, "entered error passive state\n");
753 work_done += m_can_handle_state_change(dev,
754 CAN_STATE_ERROR_PASSIVE);
755 }
756
757 if ((psr & PSR_BO) &&
758 (priv->can.state != CAN_STATE_BUS_OFF)) {
759 netdev_dbg(dev, "entered error bus off state\n");
760 work_done += m_can_handle_state_change(dev,
761 CAN_STATE_BUS_OFF);
762 }
763
764 return work_done;
765 }
766
m_can_handle_other_err(struct net_device * dev,u32 irqstatus)767 static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus)
768 {
769 if (irqstatus & IR_WDI)
770 netdev_err(dev, "Message RAM Watchdog event due to missing READY\n");
771 if (irqstatus & IR_ELO)
772 netdev_err(dev, "Error Logging Overflow\n");
773 if (irqstatus & IR_BEU)
774 netdev_err(dev, "Bit Error Uncorrected\n");
775 if (irqstatus & IR_BEC)
776 netdev_err(dev, "Bit Error Corrected\n");
777 if (irqstatus & IR_TOO)
778 netdev_err(dev, "Timeout reached\n");
779 if (irqstatus & IR_MRAF)
780 netdev_err(dev, "Message RAM access failure occurred\n");
781 }
782
is_lec_err(u32 psr)783 static inline bool is_lec_err(u32 psr)
784 {
785 psr &= LEC_UNUSED;
786
787 return psr && (psr != LEC_UNUSED);
788 }
789
m_can_handle_bus_errors(struct net_device * dev,u32 irqstatus,u32 psr)790 static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus,
791 u32 psr)
792 {
793 struct m_can_priv *priv = netdev_priv(dev);
794 int work_done = 0;
795
796 if (irqstatus & IR_RF0L)
797 work_done += m_can_handle_lost_msg(dev);
798
799 /* handle lec errors on the bus */
800 if ((priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
801 is_lec_err(psr))
802 work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED);
803
804 /* other unproccessed error interrupts */
805 m_can_handle_other_err(dev, irqstatus);
806
807 return work_done;
808 }
809
m_can_poll(struct napi_struct * napi,int quota)810 static int m_can_poll(struct napi_struct *napi, int quota)
811 {
812 struct net_device *dev = napi->dev;
813 struct m_can_priv *priv = netdev_priv(dev);
814 int work_done = 0;
815 u32 irqstatus, psr;
816
817 irqstatus = priv->irqstatus | m_can_read(priv, M_CAN_IR);
818 if (!irqstatus)
819 goto end;
820
821 /* Errata workaround for issue "Needless activation of MRAF irq"
822 * During frame reception while the MCAN is in Error Passive state
823 * and the Receive Error Counter has the value MCAN_ECR.REC = 127,
824 * it may happen that MCAN_IR.MRAF is set although there was no
825 * Message RAM access failure.
826 * If MCAN_IR.MRAF is enabled, an interrupt to the Host CPU is generated
827 * The Message RAM Access Failure interrupt routine needs to check
828 * whether MCAN_ECR.RP = ’1’ and MCAN_ECR.REC = 127.
829 * In this case, reset MCAN_IR.MRAF. No further action is required.
830 */
831 if ((priv->version <= 31) && (irqstatus & IR_MRAF) &&
832 (m_can_read(priv, M_CAN_ECR) & ECR_RP)) {
833 struct can_berr_counter bec;
834
835 __m_can_get_berr_counter(dev, &bec);
836 if (bec.rxerr == 127) {
837 m_can_write(priv, M_CAN_IR, IR_MRAF);
838 irqstatus &= ~IR_MRAF;
839 }
840 }
841
842 psr = m_can_read(priv, M_CAN_PSR);
843 if (irqstatus & IR_ERR_STATE)
844 work_done += m_can_handle_state_errors(dev, psr);
845
846 if (irqstatus & IR_ERR_BUS_30X)
847 work_done += m_can_handle_bus_errors(dev, irqstatus, psr);
848
849 if (irqstatus & IR_RF0N)
850 work_done += m_can_do_rx_poll(dev, (quota - work_done));
851
852 if (work_done < quota) {
853 napi_complete_done(napi, work_done);
854 m_can_enable_all_interrupts(priv);
855 }
856
857 end:
858 return work_done;
859 }
860
m_can_echo_tx_event(struct net_device * dev)861 static void m_can_echo_tx_event(struct net_device *dev)
862 {
863 u32 txe_count = 0;
864 u32 m_can_txefs;
865 u32 fgi = 0;
866 int i = 0;
867 unsigned int msg_mark;
868
869 struct m_can_priv *priv = netdev_priv(dev);
870 struct net_device_stats *stats = &dev->stats;
871
872 /* read tx event fifo status */
873 m_can_txefs = m_can_read(priv, M_CAN_TXEFS);
874
875 /* Get Tx Event fifo element count */
876 txe_count = (m_can_txefs & TXEFS_EFFL_MASK)
877 >> TXEFS_EFFL_SHIFT;
878
879 /* Get and process all sent elements */
880 for (i = 0; i < txe_count; i++) {
881 /* retrieve get index */
882 fgi = (m_can_read(priv, M_CAN_TXEFS) & TXEFS_EFGI_MASK)
883 >> TXEFS_EFGI_SHIFT;
884
885 /* get message marker */
886 msg_mark = (m_can_txe_fifo_read(priv, fgi, 4) &
887 TX_EVENT_MM_MASK) >> TX_EVENT_MM_SHIFT;
888
889 /* ack txe element */
890 m_can_write(priv, M_CAN_TXEFA, (TXEFA_EFAI_MASK &
891 (fgi << TXEFA_EFAI_SHIFT)));
892
893 /* update stats */
894 stats->tx_bytes += can_get_echo_skb(dev, msg_mark);
895 stats->tx_packets++;
896 }
897 }
898
m_can_isr(int irq,void * dev_id)899 static irqreturn_t m_can_isr(int irq, void *dev_id)
900 {
901 struct net_device *dev = (struct net_device *)dev_id;
902 struct m_can_priv *priv = netdev_priv(dev);
903 struct net_device_stats *stats = &dev->stats;
904 u32 ir;
905
906 ir = m_can_read(priv, M_CAN_IR);
907 if (!ir)
908 return IRQ_NONE;
909
910 /* ACK all irqs */
911 if (ir & IR_ALL_INT)
912 m_can_write(priv, M_CAN_IR, ir);
913
914 /* schedule NAPI in case of
915 * - rx IRQ
916 * - state change IRQ
917 * - bus error IRQ and bus error reporting
918 */
919 if ((ir & IR_RF0N) || (ir & IR_ERR_ALL_30X)) {
920 priv->irqstatus = ir;
921 m_can_disable_all_interrupts(priv);
922 napi_schedule(&priv->napi);
923 }
924
925 if (priv->version == 30) {
926 if (ir & IR_TC) {
927 /* Transmission Complete Interrupt*/
928 stats->tx_bytes += can_get_echo_skb(dev, 0);
929 stats->tx_packets++;
930 can_led_event(dev, CAN_LED_EVENT_TX);
931 netif_wake_queue(dev);
932 }
933 } else {
934 if (ir & IR_TEFN) {
935 /* New TX FIFO Element arrived */
936 m_can_echo_tx_event(dev);
937 can_led_event(dev, CAN_LED_EVENT_TX);
938 if (netif_queue_stopped(dev) &&
939 !m_can_tx_fifo_full(priv))
940 netif_wake_queue(dev);
941 }
942 }
943
944 return IRQ_HANDLED;
945 }
946
947 static const struct can_bittiming_const m_can_bittiming_const_30X = {
948 .name = KBUILD_MODNAME,
949 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
950 .tseg1_max = 64,
951 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
952 .tseg2_max = 16,
953 .sjw_max = 16,
954 .brp_min = 1,
955 .brp_max = 1024,
956 .brp_inc = 1,
957 };
958
959 static const struct can_bittiming_const m_can_data_bittiming_const_30X = {
960 .name = KBUILD_MODNAME,
961 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
962 .tseg1_max = 16,
963 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
964 .tseg2_max = 8,
965 .sjw_max = 4,
966 .brp_min = 1,
967 .brp_max = 32,
968 .brp_inc = 1,
969 };
970
971 static const struct can_bittiming_const m_can_bittiming_const_31X = {
972 .name = KBUILD_MODNAME,
973 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
974 .tseg1_max = 256,
975 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
976 .tseg2_max = 128,
977 .sjw_max = 128,
978 .brp_min = 1,
979 .brp_max = 512,
980 .brp_inc = 1,
981 };
982
983 static const struct can_bittiming_const m_can_data_bittiming_const_31X = {
984 .name = KBUILD_MODNAME,
985 .tseg1_min = 1, /* Time segment 1 = prop_seg + phase_seg1 */
986 .tseg1_max = 32,
987 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
988 .tseg2_max = 16,
989 .sjw_max = 16,
990 .brp_min = 1,
991 .brp_max = 32,
992 .brp_inc = 1,
993 };
994
m_can_set_bittiming(struct net_device * dev)995 static int m_can_set_bittiming(struct net_device *dev)
996 {
997 struct m_can_priv *priv = netdev_priv(dev);
998 const struct can_bittiming *bt = &priv->can.bittiming;
999 const struct can_bittiming *dbt = &priv->can.data_bittiming;
1000 u16 brp, sjw, tseg1, tseg2;
1001 u32 reg_btp;
1002
1003 brp = bt->brp - 1;
1004 sjw = bt->sjw - 1;
1005 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1006 tseg2 = bt->phase_seg2 - 1;
1007 reg_btp = (brp << NBTP_NBRP_SHIFT) | (sjw << NBTP_NSJW_SHIFT) |
1008 (tseg1 << NBTP_NTSEG1_SHIFT) | (tseg2 << NBTP_NTSEG2_SHIFT);
1009 m_can_write(priv, M_CAN_NBTP, reg_btp);
1010
1011 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1012 brp = dbt->brp - 1;
1013 sjw = dbt->sjw - 1;
1014 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1015 tseg2 = dbt->phase_seg2 - 1;
1016 reg_btp = (brp << DBTP_DBRP_SHIFT) | (sjw << DBTP_DSJW_SHIFT) |
1017 (tseg1 << DBTP_DTSEG1_SHIFT) |
1018 (tseg2 << DBTP_DTSEG2_SHIFT);
1019 m_can_write(priv, M_CAN_DBTP, reg_btp);
1020 }
1021
1022 return 0;
1023 }
1024
1025 /* Configure M_CAN chip:
1026 * - set rx buffer/fifo element size
1027 * - configure rx fifo
1028 * - accept non-matching frame into fifo 0
1029 * - configure tx buffer
1030 * - >= v3.1.x: TX FIFO is used
1031 * - configure mode
1032 * - setup bittiming
1033 */
m_can_chip_config(struct net_device * dev)1034 static void m_can_chip_config(struct net_device *dev)
1035 {
1036 struct m_can_priv *priv = netdev_priv(dev);
1037 u32 cccr, test;
1038
1039 m_can_config_endisable(priv, true);
1040
1041 /* RX Buffer/FIFO Element Size 64 bytes data field */
1042 m_can_write(priv, M_CAN_RXESC, M_CAN_RXESC_64BYTES);
1043
1044 /* Accept Non-matching Frames Into FIFO 0 */
1045 m_can_write(priv, M_CAN_GFC, 0x0);
1046
1047 if (priv->version == 30) {
1048 /* only support one Tx Buffer currently */
1049 m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) |
1050 priv->mcfg[MRAM_TXB].off);
1051 } else {
1052 /* TX FIFO is used for newer IP Core versions */
1053 m_can_write(priv, M_CAN_TXBC,
1054 (priv->mcfg[MRAM_TXB].num << TXBC_TFQS_SHIFT) |
1055 (priv->mcfg[MRAM_TXB].off));
1056 }
1057
1058 /* support 64 bytes payload */
1059 m_can_write(priv, M_CAN_TXESC, TXESC_TBDS_64BYTES);
1060
1061 /* TX Event FIFO */
1062 if (priv->version == 30) {
1063 m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) |
1064 priv->mcfg[MRAM_TXE].off);
1065 } else {
1066 /* Full TX Event FIFO is used */
1067 m_can_write(priv, M_CAN_TXEFC,
1068 ((priv->mcfg[MRAM_TXE].num << TXEFC_EFS_SHIFT)
1069 & TXEFC_EFS_MASK) |
1070 priv->mcfg[MRAM_TXE].off);
1071 }
1072
1073 /* rx fifo configuration, blocking mode, fifo size 1 */
1074 m_can_write(priv, M_CAN_RXF0C,
1075 (priv->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) |
1076 priv->mcfg[MRAM_RXF0].off);
1077
1078 m_can_write(priv, M_CAN_RXF1C,
1079 (priv->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) |
1080 priv->mcfg[MRAM_RXF1].off);
1081
1082 cccr = m_can_read(priv, M_CAN_CCCR);
1083 test = m_can_read(priv, M_CAN_TEST);
1084 test &= ~TEST_LBCK;
1085 if (priv->version == 30) {
1086 /* Version 3.0.x */
1087
1088 cccr &= ~(CCCR_TEST | CCCR_MON |
1089 (CCCR_CMR_MASK << CCCR_CMR_SHIFT) |
1090 (CCCR_CME_MASK << CCCR_CME_SHIFT));
1091
1092 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1093 cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT;
1094
1095 } else {
1096 /* Version 3.1.x or 3.2.x */
1097 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE |
1098 CCCR_NISO);
1099
1100 /* Only 3.2.x has NISO Bit implemented */
1101 if (priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)
1102 cccr |= CCCR_NISO;
1103
1104 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1105 cccr |= (CCCR_BRSE | CCCR_FDOE);
1106 }
1107
1108 /* Loopback Mode */
1109 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1110 cccr |= CCCR_TEST | CCCR_MON;
1111 test |= TEST_LBCK;
1112 }
1113
1114 /* Enable Monitoring (all versions) */
1115 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1116 cccr |= CCCR_MON;
1117
1118 /* Write config */
1119 m_can_write(priv, M_CAN_CCCR, cccr);
1120 m_can_write(priv, M_CAN_TEST, test);
1121
1122 /* Enable interrupts */
1123 m_can_write(priv, M_CAN_IR, IR_ALL_INT);
1124 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1125 if (priv->version == 30)
1126 m_can_write(priv, M_CAN_IE, IR_ALL_INT &
1127 ~(IR_ERR_LEC_30X));
1128 else
1129 m_can_write(priv, M_CAN_IE, IR_ALL_INT &
1130 ~(IR_ERR_LEC_31X));
1131 else
1132 m_can_write(priv, M_CAN_IE, IR_ALL_INT);
1133
1134 /* route all interrupts to INT0 */
1135 m_can_write(priv, M_CAN_ILS, ILS_ALL_INT0);
1136
1137 /* set bittiming params */
1138 m_can_set_bittiming(dev);
1139
1140 m_can_config_endisable(priv, false);
1141 }
1142
m_can_start(struct net_device * dev)1143 static void m_can_start(struct net_device *dev)
1144 {
1145 struct m_can_priv *priv = netdev_priv(dev);
1146
1147 /* basic m_can configuration */
1148 m_can_chip_config(dev);
1149
1150 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1151
1152 m_can_enable_all_interrupts(priv);
1153 }
1154
m_can_set_mode(struct net_device * dev,enum can_mode mode)1155 static int m_can_set_mode(struct net_device *dev, enum can_mode mode)
1156 {
1157 switch (mode) {
1158 case CAN_MODE_START:
1159 m_can_start(dev);
1160 netif_wake_queue(dev);
1161 break;
1162 default:
1163 return -EOPNOTSUPP;
1164 }
1165
1166 return 0;
1167 }
1168
free_m_can_dev(struct net_device * dev)1169 static void free_m_can_dev(struct net_device *dev)
1170 {
1171 free_candev(dev);
1172 }
1173
1174 /* Checks core release number of M_CAN
1175 * returns 0 if an unsupported device is detected
1176 * else it returns the release and step coded as:
1177 * return value = 10 * <release> + 1 * <step>
1178 */
m_can_check_core_release(void __iomem * m_can_base)1179 static int m_can_check_core_release(void __iomem *m_can_base)
1180 {
1181 u32 crel_reg;
1182 u8 rel;
1183 u8 step;
1184 int res;
1185 struct m_can_priv temp_priv = {
1186 .base = m_can_base
1187 };
1188
1189 /* Read Core Release Version and split into version number
1190 * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1;
1191 */
1192 crel_reg = m_can_read(&temp_priv, M_CAN_CREL);
1193 rel = (u8)((crel_reg & CREL_REL_MASK) >> CREL_REL_SHIFT);
1194 step = (u8)((crel_reg & CREL_STEP_MASK) >> CREL_STEP_SHIFT);
1195
1196 if (rel == 3) {
1197 /* M_CAN v3.x.y: create return value */
1198 res = 30 + step;
1199 } else {
1200 /* Unsupported M_CAN version */
1201 res = 0;
1202 }
1203
1204 return res;
1205 }
1206
1207 /* Selectable Non ISO support only in version 3.2.x
1208 * This function checks if the bit is writable.
1209 */
m_can_niso_supported(const struct m_can_priv * priv)1210 static bool m_can_niso_supported(const struct m_can_priv *priv)
1211 {
1212 u32 cccr_reg, cccr_poll;
1213 int niso_timeout;
1214
1215 m_can_config_endisable(priv, true);
1216 cccr_reg = m_can_read(priv, M_CAN_CCCR);
1217 cccr_reg |= CCCR_NISO;
1218 m_can_write(priv, M_CAN_CCCR, cccr_reg);
1219
1220 niso_timeout = readl_poll_timeout((priv->base + M_CAN_CCCR), cccr_poll,
1221 (cccr_poll == cccr_reg), 0, 10);
1222
1223 /* Clear NISO */
1224 cccr_reg &= ~(CCCR_NISO);
1225 m_can_write(priv, M_CAN_CCCR, cccr_reg);
1226
1227 m_can_config_endisable(priv, false);
1228
1229 /* return false if time out (-ETIMEDOUT), else return true */
1230 return !niso_timeout;
1231 }
1232
alloc_m_can_dev(struct platform_device * pdev,void __iomem * addr,u32 tx_fifo_size)1233 static struct net_device *alloc_m_can_dev(struct platform_device *pdev,
1234 void __iomem *addr, u32 tx_fifo_size)
1235 {
1236 struct net_device *dev;
1237 struct m_can_priv *priv;
1238 int m_can_version;
1239 unsigned int echo_buffer_count;
1240
1241 m_can_version = m_can_check_core_release(addr);
1242 /* return if unsupported version */
1243 if (!m_can_version) {
1244 dev = NULL;
1245 goto return_dev;
1246 }
1247
1248 /* If version < 3.1.x, then only one echo buffer is used */
1249 echo_buffer_count = ((m_can_version == 30)
1250 ? 1U
1251 : (unsigned int)tx_fifo_size);
1252
1253 dev = alloc_candev(sizeof(*priv), echo_buffer_count);
1254 if (!dev) {
1255 dev = NULL;
1256 goto return_dev;
1257 }
1258 priv = netdev_priv(dev);
1259 netif_napi_add(dev, &priv->napi, m_can_poll, M_CAN_NAPI_WEIGHT);
1260
1261 /* Shared properties of all M_CAN versions */
1262 priv->version = m_can_version;
1263 priv->dev = dev;
1264 priv->base = addr;
1265 priv->can.do_set_mode = m_can_set_mode;
1266 priv->can.do_get_berr_counter = m_can_get_berr_counter;
1267
1268 /* Set M_CAN supported operations */
1269 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1270 CAN_CTRLMODE_LISTENONLY |
1271 CAN_CTRLMODE_BERR_REPORTING |
1272 CAN_CTRLMODE_FD;
1273
1274 /* Set properties depending on M_CAN version */
1275 switch (priv->version) {
1276 case 30:
1277 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */
1278 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1279 priv->can.bittiming_const = &m_can_bittiming_const_30X;
1280 priv->can.data_bittiming_const =
1281 &m_can_data_bittiming_const_30X;
1282 break;
1283 case 31:
1284 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */
1285 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1286 priv->can.bittiming_const = &m_can_bittiming_const_31X;
1287 priv->can.data_bittiming_const =
1288 &m_can_data_bittiming_const_31X;
1289 break;
1290 case 32:
1291 priv->can.bittiming_const = &m_can_bittiming_const_31X;
1292 priv->can.data_bittiming_const =
1293 &m_can_data_bittiming_const_31X;
1294 priv->can.ctrlmode_supported |= (m_can_niso_supported(priv)
1295 ? CAN_CTRLMODE_FD_NON_ISO
1296 : 0);
1297 break;
1298 default:
1299 /* Unsupported device: free candev */
1300 free_m_can_dev(dev);
1301 dev_err(&pdev->dev, "Unsupported version number: %2d",
1302 priv->version);
1303 dev = NULL;
1304 break;
1305 }
1306
1307 return_dev:
1308 return dev;
1309 }
1310
m_can_open(struct net_device * dev)1311 static int m_can_open(struct net_device *dev)
1312 {
1313 struct m_can_priv *priv = netdev_priv(dev);
1314 int err;
1315
1316 err = m_can_clk_start(priv);
1317 if (err)
1318 return err;
1319
1320 /* open the can device */
1321 err = open_candev(dev);
1322 if (err) {
1323 netdev_err(dev, "failed to open can device\n");
1324 goto exit_disable_clks;
1325 }
1326
1327 /* register interrupt handler */
1328 err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name,
1329 dev);
1330 if (err < 0) {
1331 netdev_err(dev, "failed to request interrupt\n");
1332 goto exit_irq_fail;
1333 }
1334
1335 /* start the m_can controller */
1336 m_can_start(dev);
1337
1338 can_led_event(dev, CAN_LED_EVENT_OPEN);
1339 napi_enable(&priv->napi);
1340 netif_start_queue(dev);
1341
1342 return 0;
1343
1344 exit_irq_fail:
1345 close_candev(dev);
1346 exit_disable_clks:
1347 m_can_clk_stop(priv);
1348 return err;
1349 }
1350
m_can_stop(struct net_device * dev)1351 static void m_can_stop(struct net_device *dev)
1352 {
1353 struct m_can_priv *priv = netdev_priv(dev);
1354
1355 /* disable all interrupts */
1356 m_can_disable_all_interrupts(priv);
1357
1358 /* set the state as STOPPED */
1359 priv->can.state = CAN_STATE_STOPPED;
1360 }
1361
m_can_close(struct net_device * dev)1362 static int m_can_close(struct net_device *dev)
1363 {
1364 struct m_can_priv *priv = netdev_priv(dev);
1365
1366 netif_stop_queue(dev);
1367 napi_disable(&priv->napi);
1368 m_can_stop(dev);
1369 m_can_clk_stop(priv);
1370 free_irq(dev->irq, dev);
1371 close_candev(dev);
1372 can_led_event(dev, CAN_LED_EVENT_STOP);
1373
1374 return 0;
1375 }
1376
m_can_next_echo_skb_occupied(struct net_device * dev,int putidx)1377 static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx)
1378 {
1379 struct m_can_priv *priv = netdev_priv(dev);
1380 /*get wrap around for loopback skb index */
1381 unsigned int wrap = priv->can.echo_skb_max;
1382 int next_idx;
1383
1384 /* calculate next index */
1385 next_idx = (++putidx >= wrap ? 0 : putidx);
1386
1387 /* check if occupied */
1388 return !!priv->can.echo_skb[next_idx];
1389 }
1390
m_can_start_xmit(struct sk_buff * skb,struct net_device * dev)1391 static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
1392 struct net_device *dev)
1393 {
1394 struct m_can_priv *priv = netdev_priv(dev);
1395 struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1396 u32 id, cccr, fdflags;
1397 int i;
1398 int putidx;
1399
1400 if (can_dropped_invalid_skb(dev, skb))
1401 return NETDEV_TX_OK;
1402
1403 /* Generate ID field for TX buffer Element */
1404 /* Common to all supported M_CAN versions */
1405 if (cf->can_id & CAN_EFF_FLAG) {
1406 id = cf->can_id & CAN_EFF_MASK;
1407 id |= TX_BUF_XTD;
1408 } else {
1409 id = ((cf->can_id & CAN_SFF_MASK) << 18);
1410 }
1411
1412 if (cf->can_id & CAN_RTR_FLAG)
1413 id |= TX_BUF_RTR;
1414
1415 if (priv->version == 30) {
1416 netif_stop_queue(dev);
1417
1418 /* message ram configuration */
1419 m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
1420 m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC,
1421 can_len2dlc(cf->len) << 16);
1422
1423 for (i = 0; i < cf->len; i += 4)
1424 m_can_fifo_write(priv, 0,
1425 M_CAN_FIFO_DATA(i / 4),
1426 *(u32 *)(cf->data + i));
1427
1428 can_put_echo_skb(skb, dev, 0);
1429
1430 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1431 cccr = m_can_read(priv, M_CAN_CCCR);
1432 cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
1433 if (can_is_canfd_skb(skb)) {
1434 if (cf->flags & CANFD_BRS)
1435 cccr |= CCCR_CMR_CANFD_BRS <<
1436 CCCR_CMR_SHIFT;
1437 else
1438 cccr |= CCCR_CMR_CANFD <<
1439 CCCR_CMR_SHIFT;
1440 } else {
1441 cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
1442 }
1443 m_can_write(priv, M_CAN_CCCR, cccr);
1444 }
1445 m_can_write(priv, M_CAN_TXBTIE, 0x1);
1446 m_can_write(priv, M_CAN_TXBAR, 0x1);
1447 /* End of xmit function for version 3.0.x */
1448 } else {
1449 /* Transmit routine for version >= v3.1.x */
1450
1451 /* Check if FIFO full */
1452 if (m_can_tx_fifo_full(priv)) {
1453 /* This shouldn't happen */
1454 netif_stop_queue(dev);
1455 netdev_warn(dev,
1456 "TX queue active although FIFO is full.");
1457 return NETDEV_TX_BUSY;
1458 }
1459
1460 /* get put index for frame */
1461 putidx = ((m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQPI_MASK)
1462 >> TXFQS_TFQPI_SHIFT);
1463 /* Write ID Field to FIFO Element */
1464 m_can_fifo_write(priv, putidx, M_CAN_FIFO_ID, id);
1465
1466 /* get CAN FD configuration of frame */
1467 fdflags = 0;
1468 if (can_is_canfd_skb(skb)) {
1469 fdflags |= TX_BUF_FDF;
1470 if (cf->flags & CANFD_BRS)
1471 fdflags |= TX_BUF_BRS;
1472 }
1473
1474 /* Construct DLC Field. Also contains CAN-FD configuration
1475 * use put index of fifo as message marker
1476 * it is used in TX interrupt for
1477 * sending the correct echo frame
1478 */
1479 m_can_fifo_write(priv, putidx, M_CAN_FIFO_DLC,
1480 ((putidx << TX_BUF_MM_SHIFT) &
1481 TX_BUF_MM_MASK) |
1482 (can_len2dlc(cf->len) << 16) |
1483 fdflags | TX_BUF_EFC);
1484
1485 for (i = 0; i < cf->len; i += 4)
1486 m_can_fifo_write(priv, putidx, M_CAN_FIFO_DATA(i / 4),
1487 *(u32 *)(cf->data + i));
1488
1489 /* Push loopback echo.
1490 * Will be looped back on TX interrupt based on message marker
1491 */
1492 can_put_echo_skb(skb, dev, putidx);
1493
1494 /* Enable TX FIFO element to start transfer */
1495 m_can_write(priv, M_CAN_TXBAR, (1 << putidx));
1496
1497 /* stop network queue if fifo full */
1498 if (m_can_tx_fifo_full(priv) ||
1499 m_can_next_echo_skb_occupied(dev, putidx))
1500 netif_stop_queue(dev);
1501 }
1502
1503 return NETDEV_TX_OK;
1504 }
1505
1506 static const struct net_device_ops m_can_netdev_ops = {
1507 .ndo_open = m_can_open,
1508 .ndo_stop = m_can_close,
1509 .ndo_start_xmit = m_can_start_xmit,
1510 .ndo_change_mtu = can_change_mtu,
1511 };
1512
register_m_can_dev(struct net_device * dev)1513 static int register_m_can_dev(struct net_device *dev)
1514 {
1515 dev->flags |= IFF_ECHO; /* we support local echo */
1516 dev->netdev_ops = &m_can_netdev_ops;
1517
1518 return register_candev(dev);
1519 }
1520
m_can_init_ram(struct m_can_priv * priv)1521 static void m_can_init_ram(struct m_can_priv *priv)
1522 {
1523 int end, i, start;
1524
1525 /* initialize the entire Message RAM in use to avoid possible
1526 * ECC/parity checksum errors when reading an uninitialized buffer
1527 */
1528 start = priv->mcfg[MRAM_SIDF].off;
1529 end = priv->mcfg[MRAM_TXB].off +
1530 priv->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
1531 for (i = start; i < end; i += 4)
1532 writel(0x0, priv->mram_base + i);
1533 }
1534
m_can_of_parse_mram(struct m_can_priv * priv,const u32 * mram_config_vals)1535 static void m_can_of_parse_mram(struct m_can_priv *priv,
1536 const u32 *mram_config_vals)
1537 {
1538 priv->mcfg[MRAM_SIDF].off = mram_config_vals[0];
1539 priv->mcfg[MRAM_SIDF].num = mram_config_vals[1];
1540 priv->mcfg[MRAM_XIDF].off = priv->mcfg[MRAM_SIDF].off +
1541 priv->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;
1542 priv->mcfg[MRAM_XIDF].num = mram_config_vals[2];
1543 priv->mcfg[MRAM_RXF0].off = priv->mcfg[MRAM_XIDF].off +
1544 priv->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
1545 priv->mcfg[MRAM_RXF0].num = mram_config_vals[3] &
1546 (RXFC_FS_MASK >> RXFC_FS_SHIFT);
1547 priv->mcfg[MRAM_RXF1].off = priv->mcfg[MRAM_RXF0].off +
1548 priv->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
1549 priv->mcfg[MRAM_RXF1].num = mram_config_vals[4] &
1550 (RXFC_FS_MASK >> RXFC_FS_SHIFT);
1551 priv->mcfg[MRAM_RXB].off = priv->mcfg[MRAM_RXF1].off +
1552 priv->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
1553 priv->mcfg[MRAM_RXB].num = mram_config_vals[5];
1554 priv->mcfg[MRAM_TXE].off = priv->mcfg[MRAM_RXB].off +
1555 priv->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;
1556 priv->mcfg[MRAM_TXE].num = mram_config_vals[6];
1557 priv->mcfg[MRAM_TXB].off = priv->mcfg[MRAM_TXE].off +
1558 priv->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
1559 priv->mcfg[MRAM_TXB].num = mram_config_vals[7] &
1560 (TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT);
1561
1562 dev_dbg(priv->device,
1563 "mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
1564 priv->mram_base,
1565 priv->mcfg[MRAM_SIDF].off, priv->mcfg[MRAM_SIDF].num,
1566 priv->mcfg[MRAM_XIDF].off, priv->mcfg[MRAM_XIDF].num,
1567 priv->mcfg[MRAM_RXF0].off, priv->mcfg[MRAM_RXF0].num,
1568 priv->mcfg[MRAM_RXF1].off, priv->mcfg[MRAM_RXF1].num,
1569 priv->mcfg[MRAM_RXB].off, priv->mcfg[MRAM_RXB].num,
1570 priv->mcfg[MRAM_TXE].off, priv->mcfg[MRAM_TXE].num,
1571 priv->mcfg[MRAM_TXB].off, priv->mcfg[MRAM_TXB].num);
1572
1573 m_can_init_ram(priv);
1574 }
1575
m_can_plat_probe(struct platform_device * pdev)1576 static int m_can_plat_probe(struct platform_device *pdev)
1577 {
1578 struct net_device *dev;
1579 struct m_can_priv *priv;
1580 struct resource *res;
1581 void __iomem *addr;
1582 void __iomem *mram_addr;
1583 struct clk *hclk, *cclk;
1584 int irq, ret;
1585 struct device_node *np;
1586 u32 mram_config_vals[MRAM_CFG_LEN];
1587 u32 tx_fifo_size;
1588
1589 np = pdev->dev.of_node;
1590
1591 hclk = devm_clk_get(&pdev->dev, "hclk");
1592 cclk = devm_clk_get(&pdev->dev, "cclk");
1593
1594 if (IS_ERR(hclk) || IS_ERR(cclk)) {
1595 dev_err(&pdev->dev, "no clock found\n");
1596 ret = -ENODEV;
1597 goto failed_ret;
1598 }
1599
1600 /* Enable clocks. Necessary to read Core Release in order to determine
1601 * M_CAN version
1602 */
1603 ret = clk_prepare_enable(hclk);
1604 if (ret)
1605 goto disable_hclk_ret;
1606
1607 ret = clk_prepare_enable(cclk);
1608 if (ret)
1609 goto disable_cclk_ret;
1610
1611 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "m_can");
1612 addr = devm_ioremap_resource(&pdev->dev, res);
1613 irq = platform_get_irq_byname(pdev, "int0");
1614
1615 if (IS_ERR(addr) || irq < 0) {
1616 ret = -EINVAL;
1617 goto disable_cclk_ret;
1618 }
1619
1620 /* message ram could be shared */
1621 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram");
1622 if (!res) {
1623 ret = -ENODEV;
1624 goto disable_cclk_ret;
1625 }
1626
1627 mram_addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1628 if (!mram_addr) {
1629 ret = -ENOMEM;
1630 goto disable_cclk_ret;
1631 }
1632
1633 /* get message ram configuration */
1634 ret = of_property_read_u32_array(np, "bosch,mram-cfg",
1635 mram_config_vals,
1636 sizeof(mram_config_vals) / 4);
1637 if (ret) {
1638 dev_err(&pdev->dev, "Could not get Message RAM configuration.");
1639 goto disable_cclk_ret;
1640 }
1641
1642 /* Get TX FIFO size
1643 * Defines the total amount of echo buffers for loopback
1644 */
1645 tx_fifo_size = mram_config_vals[7];
1646
1647 /* allocate the m_can device */
1648 dev = alloc_m_can_dev(pdev, addr, tx_fifo_size);
1649 if (!dev) {
1650 ret = -ENOMEM;
1651 goto disable_cclk_ret;
1652 }
1653 priv = netdev_priv(dev);
1654 dev->irq = irq;
1655 priv->device = &pdev->dev;
1656 priv->hclk = hclk;
1657 priv->cclk = cclk;
1658 priv->can.clock.freq = clk_get_rate(cclk);
1659 priv->mram_base = mram_addr;
1660
1661 platform_set_drvdata(pdev, dev);
1662 SET_NETDEV_DEV(dev, &pdev->dev);
1663
1664 ret = register_m_can_dev(dev);
1665 if (ret) {
1666 dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
1667 KBUILD_MODNAME, ret);
1668 goto failed_free_dev;
1669 }
1670
1671 m_can_of_parse_mram(priv, mram_config_vals);
1672
1673 devm_can_led_init(dev);
1674
1675 dev_info(&pdev->dev, "%s device registered (irq=%d, version=%d)\n",
1676 KBUILD_MODNAME, dev->irq, priv->version);
1677
1678 /* Probe finished
1679 * Stop clocks. They will be reactivated once the M_CAN device is opened
1680 */
1681
1682 goto disable_cclk_ret;
1683
1684 failed_free_dev:
1685 free_m_can_dev(dev);
1686 disable_cclk_ret:
1687 clk_disable_unprepare(cclk);
1688 disable_hclk_ret:
1689 clk_disable_unprepare(hclk);
1690 failed_ret:
1691 return ret;
1692 }
1693
1694 /* TODO: runtime PM with power down or sleep mode */
1695
m_can_suspend(struct device * dev)1696 static __maybe_unused int m_can_suspend(struct device *dev)
1697 {
1698 struct net_device *ndev = dev_get_drvdata(dev);
1699 struct m_can_priv *priv = netdev_priv(ndev);
1700
1701 if (netif_running(ndev)) {
1702 netif_stop_queue(ndev);
1703 netif_device_detach(ndev);
1704 m_can_stop(ndev);
1705 m_can_clk_stop(priv);
1706 }
1707
1708 pinctrl_pm_select_sleep_state(dev);
1709
1710 priv->can.state = CAN_STATE_SLEEPING;
1711
1712 return 0;
1713 }
1714
m_can_resume(struct device * dev)1715 static __maybe_unused int m_can_resume(struct device *dev)
1716 {
1717 struct net_device *ndev = dev_get_drvdata(dev);
1718 struct m_can_priv *priv = netdev_priv(ndev);
1719
1720 pinctrl_pm_select_default_state(dev);
1721
1722 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1723
1724 if (netif_running(ndev)) {
1725 int ret;
1726
1727 ret = m_can_clk_start(priv);
1728 if (ret)
1729 return ret;
1730
1731 m_can_init_ram(priv);
1732 m_can_start(ndev);
1733 netif_device_attach(ndev);
1734 netif_start_queue(ndev);
1735 }
1736
1737 return 0;
1738 }
1739
unregister_m_can_dev(struct net_device * dev)1740 static void unregister_m_can_dev(struct net_device *dev)
1741 {
1742 unregister_candev(dev);
1743 }
1744
m_can_plat_remove(struct platform_device * pdev)1745 static int m_can_plat_remove(struct platform_device *pdev)
1746 {
1747 struct net_device *dev = platform_get_drvdata(pdev);
1748
1749 unregister_m_can_dev(dev);
1750 platform_set_drvdata(pdev, NULL);
1751
1752 free_m_can_dev(dev);
1753
1754 return 0;
1755 }
1756
1757 static const struct dev_pm_ops m_can_pmops = {
1758 SET_SYSTEM_SLEEP_PM_OPS(m_can_suspend, m_can_resume)
1759 };
1760
1761 static const struct of_device_id m_can_of_table[] = {
1762 { .compatible = "bosch,m_can", .data = NULL },
1763 { /* sentinel */ },
1764 };
1765 MODULE_DEVICE_TABLE(of, m_can_of_table);
1766
1767 static struct platform_driver m_can_plat_driver = {
1768 .driver = {
1769 .name = KBUILD_MODNAME,
1770 .of_match_table = m_can_of_table,
1771 .pm = &m_can_pmops,
1772 },
1773 .probe = m_can_plat_probe,
1774 .remove = m_can_plat_remove,
1775 };
1776
1777 module_platform_driver(m_can_plat_driver);
1778
1779 MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>");
1780 MODULE_LICENSE("GPL v2");
1781 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller");
1782