1 /*
2 * Broadcom Starfighter 2 DSA switch driver
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12 #include <linux/list.h>
13 #include <linux/module.h>
14 #include <linux/netdevice.h>
15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h>
17 #include <linux/of.h>
18 #include <linux/phy.h>
19 #include <linux/phy_fixed.h>
20 #include <linux/mii.h>
21 #include <linux/of.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_address.h>
24 #include <linux/of_net.h>
25 #include <linux/of_mdio.h>
26 #include <net/dsa.h>
27 #include <linux/ethtool.h>
28 #include <linux/if_bridge.h>
29 #include <linux/brcmphy.h>
30 #include <linux/etherdevice.h>
31 #include <linux/platform_data/b53.h>
32
33 #include "bcm_sf2.h"
34 #include "bcm_sf2_regs.h"
35 #include "b53/b53_priv.h"
36 #include "b53/b53_regs.h"
37
bcm_sf2_sw_get_tag_protocol(struct dsa_switch * ds)38 static enum dsa_tag_protocol bcm_sf2_sw_get_tag_protocol(struct dsa_switch *ds)
39 {
40 return DSA_TAG_PROTO_BRCM;
41 }
42
bcm_sf2_imp_vlan_setup(struct dsa_switch * ds,int cpu_port)43 static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
44 {
45 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
46 unsigned int i;
47 u32 reg;
48
49 /* Enable the IMP Port to be in the same VLAN as the other ports
50 * on a per-port basis such that we only have Port i and IMP in
51 * the same VLAN.
52 */
53 for (i = 0; i < priv->hw_params.num_ports; i++) {
54 if (!((1 << i) & ds->enabled_port_mask))
55 continue;
56
57 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
58 reg |= (1 << cpu_port);
59 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
60 }
61 }
62
bcm_sf2_brcm_hdr_setup(struct bcm_sf2_priv * priv,int port)63 static void bcm_sf2_brcm_hdr_setup(struct bcm_sf2_priv *priv, int port)
64 {
65 u32 reg, val;
66
67 /* Resolve which bit controls the Broadcom tag */
68 switch (port) {
69 case 8:
70 val = BRCM_HDR_EN_P8;
71 break;
72 case 7:
73 val = BRCM_HDR_EN_P7;
74 break;
75 case 5:
76 val = BRCM_HDR_EN_P5;
77 break;
78 default:
79 val = 0;
80 break;
81 }
82
83 /* Enable Broadcom tags for IMP port */
84 reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
85 reg |= val;
86 core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
87
88 /* Enable reception Broadcom tag for CPU TX (switch RX) to
89 * allow us to tag outgoing frames
90 */
91 reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
92 reg &= ~(1 << port);
93 core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
94
95 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
96 * allow delivering frames to the per-port net_devices
97 */
98 reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
99 reg &= ~(1 << port);
100 core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
101 }
102
bcm_sf2_imp_setup(struct dsa_switch * ds,int port)103 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
104 {
105 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
106 unsigned int i;
107 u32 reg, offset;
108
109 /* Enable the port memories */
110 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
111 reg &= ~P_TXQ_PSM_VDD(port);
112 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
113
114 /* Enable forwarding */
115 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
116
117 /* Enable IMP port in dumb mode */
118 reg = core_readl(priv, CORE_SWITCH_CTRL);
119 reg |= MII_DUMB_FWDG_EN;
120 core_writel(priv, reg, CORE_SWITCH_CTRL);
121
122 /* Configure Traffic Class to QoS mapping, allow each priority to map
123 * to a different queue number
124 */
125 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
126 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
127 reg |= i << (PRT_TO_QID_SHIFT * i);
128 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
129
130 bcm_sf2_brcm_hdr_setup(priv, port);
131
132 if (port == 8) {
133 if (priv->type == BCM7445_DEVICE_ID)
134 offset = CORE_STS_OVERRIDE_IMP;
135 else
136 offset = CORE_STS_OVERRIDE_IMP2;
137
138 /* Force link status for IMP port */
139 reg = core_readl(priv, offset);
140 reg |= (MII_SW_OR | LINK_STS);
141 reg &= ~GMII_SPEED_UP_2G;
142 core_writel(priv, reg, offset);
143
144 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
145 reg = core_readl(priv, CORE_IMP_CTL);
146 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
147 reg &= ~(RX_DIS | TX_DIS);
148 core_writel(priv, reg, CORE_IMP_CTL);
149 } else {
150 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
151 reg &= ~(RX_DIS | TX_DIS);
152 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
153 }
154 }
155
bcm_sf2_eee_enable_set(struct dsa_switch * ds,int port,bool enable)156 static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
157 {
158 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
159 u32 reg;
160
161 reg = core_readl(priv, CORE_EEE_EN_CTRL);
162 if (enable)
163 reg |= 1 << port;
164 else
165 reg &= ~(1 << port);
166 core_writel(priv, reg, CORE_EEE_EN_CTRL);
167 }
168
bcm_sf2_gphy_enable_set(struct dsa_switch * ds,bool enable)169 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
170 {
171 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
172 u32 reg;
173
174 reg = reg_readl(priv, REG_SPHY_CNTRL);
175 if (enable) {
176 reg |= PHY_RESET;
177 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
178 reg_writel(priv, reg, REG_SPHY_CNTRL);
179 udelay(21);
180 reg = reg_readl(priv, REG_SPHY_CNTRL);
181 reg &= ~PHY_RESET;
182 } else {
183 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
184 reg_writel(priv, reg, REG_SPHY_CNTRL);
185 mdelay(1);
186 reg |= CK25_DIS;
187 }
188 reg_writel(priv, reg, REG_SPHY_CNTRL);
189
190 /* Use PHY-driven LED signaling */
191 if (!enable) {
192 reg = reg_readl(priv, REG_LED_CNTRL(0));
193 reg |= SPDLNK_SRC_SEL;
194 reg_writel(priv, reg, REG_LED_CNTRL(0));
195 }
196 }
197
bcm_sf2_port_intr_enable(struct bcm_sf2_priv * priv,int port)198 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
199 int port)
200 {
201 unsigned int off;
202
203 switch (port) {
204 case 7:
205 off = P7_IRQ_OFF;
206 break;
207 case 0:
208 /* Port 0 interrupts are located on the first bank */
209 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
210 return;
211 default:
212 off = P_IRQ_OFF(port);
213 break;
214 }
215
216 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
217 }
218
bcm_sf2_port_intr_disable(struct bcm_sf2_priv * priv,int port)219 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
220 int port)
221 {
222 unsigned int off;
223
224 switch (port) {
225 case 7:
226 off = P7_IRQ_OFF;
227 break;
228 case 0:
229 /* Port 0 interrupts are located on the first bank */
230 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
231 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
232 return;
233 default:
234 off = P_IRQ_OFF(port);
235 break;
236 }
237
238 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
239 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
240 }
241
bcm_sf2_port_setup(struct dsa_switch * ds,int port,struct phy_device * phy)242 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
243 struct phy_device *phy)
244 {
245 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
246 s8 cpu_port = ds->dst->cpu_dp->index;
247 unsigned int i;
248 u32 reg;
249
250 /* Clear the memory power down */
251 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
252 reg &= ~P_TXQ_PSM_VDD(port);
253 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
254
255 /* Enable Broadcom tags for that port if requested */
256 if (priv->brcm_tag_mask & BIT(port))
257 bcm_sf2_brcm_hdr_setup(priv, port);
258
259 /* Configure Traffic Class to QoS mapping, allow each priority to map
260 * to a different queue number
261 */
262 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
263 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
264 reg |= i << (PRT_TO_QID_SHIFT * i);
265 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
266
267 /* Clear the Rx and Tx disable bits and set to no spanning tree */
268 core_writel(priv, 0, CORE_G_PCTL_PORT(port));
269
270 /* Re-enable the GPHY and re-apply workarounds */
271 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
272 bcm_sf2_gphy_enable_set(ds, true);
273 if (phy) {
274 /* if phy_stop() has been called before, phy
275 * will be in halted state, and phy_start()
276 * will call resume.
277 *
278 * the resume path does not configure back
279 * autoneg settings, and since we hard reset
280 * the phy manually here, we need to reset the
281 * state machine also.
282 */
283 phy->state = PHY_READY;
284 phy_init_hw(phy);
285 }
286 }
287
288 /* Enable MoCA port interrupts to get notified */
289 if (port == priv->moca_port)
290 bcm_sf2_port_intr_enable(priv, port);
291
292 /* Set this port, and only this one to be in the default VLAN,
293 * if member of a bridge, restore its membership prior to
294 * bringing down this port.
295 */
296 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
297 reg &= ~PORT_VLAN_CTRL_MASK;
298 reg |= (1 << port);
299 reg |= priv->dev->ports[port].vlan_ctl_mask;
300 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
301
302 bcm_sf2_imp_vlan_setup(ds, cpu_port);
303
304 /* If EEE was enabled, restore it */
305 if (priv->port_sts[port].eee.eee_enabled)
306 bcm_sf2_eee_enable_set(ds, port, true);
307
308 return 0;
309 }
310
bcm_sf2_port_disable(struct dsa_switch * ds,int port,struct phy_device * phy)311 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
312 struct phy_device *phy)
313 {
314 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
315 u32 off, reg;
316
317 if (priv->wol_ports_mask & (1 << port))
318 return;
319
320 if (port == priv->moca_port)
321 bcm_sf2_port_intr_disable(priv, port);
322
323 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
324 bcm_sf2_gphy_enable_set(ds, false);
325
326 if (dsa_is_cpu_port(ds, port))
327 off = CORE_IMP_CTL;
328 else
329 off = CORE_G_PCTL_PORT(port);
330
331 reg = core_readl(priv, off);
332 reg |= RX_DIS | TX_DIS;
333 core_writel(priv, reg, off);
334
335 /* Power down the port memory */
336 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
337 reg |= P_TXQ_PSM_VDD(port);
338 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
339 }
340
341 /* Returns 0 if EEE was not enabled, or 1 otherwise
342 */
bcm_sf2_eee_init(struct dsa_switch * ds,int port,struct phy_device * phy)343 static int bcm_sf2_eee_init(struct dsa_switch *ds, int port,
344 struct phy_device *phy)
345 {
346 int ret;
347
348 ret = phy_init_eee(phy, 0);
349 if (ret)
350 return 0;
351
352 bcm_sf2_eee_enable_set(ds, port, true);
353
354 return 1;
355 }
356
bcm_sf2_sw_get_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)357 static int bcm_sf2_sw_get_mac_eee(struct dsa_switch *ds, int port,
358 struct ethtool_eee *e)
359 {
360 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
361 struct ethtool_eee *p = &priv->port_sts[port].eee;
362 u32 reg;
363
364 reg = core_readl(priv, CORE_EEE_LPI_INDICATE);
365 e->eee_enabled = p->eee_enabled;
366 e->eee_active = !!(reg & (1 << port));
367
368 return 0;
369 }
370
bcm_sf2_sw_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)371 static int bcm_sf2_sw_set_mac_eee(struct dsa_switch *ds, int port,
372 struct ethtool_eee *e)
373 {
374 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
375 struct ethtool_eee *p = &priv->port_sts[port].eee;
376
377 p->eee_enabled = e->eee_enabled;
378 bcm_sf2_eee_enable_set(ds, port, e->eee_enabled);
379
380 return 0;
381 }
382
bcm_sf2_sw_indir_rw(struct bcm_sf2_priv * priv,int op,int addr,int regnum,u16 val)383 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
384 int regnum, u16 val)
385 {
386 int ret = 0;
387 u32 reg;
388
389 reg = reg_readl(priv, REG_SWITCH_CNTRL);
390 reg |= MDIO_MASTER_SEL;
391 reg_writel(priv, reg, REG_SWITCH_CNTRL);
392
393 /* Page << 8 | offset */
394 reg = 0x70;
395 reg <<= 2;
396 core_writel(priv, addr, reg);
397
398 /* Page << 8 | offset */
399 reg = 0x80 << 8 | regnum << 1;
400 reg <<= 2;
401
402 if (op)
403 ret = core_readl(priv, reg);
404 else
405 core_writel(priv, val, reg);
406
407 reg = reg_readl(priv, REG_SWITCH_CNTRL);
408 reg &= ~MDIO_MASTER_SEL;
409 reg_writel(priv, reg, REG_SWITCH_CNTRL);
410
411 return ret & 0xffff;
412 }
413
bcm_sf2_sw_mdio_read(struct mii_bus * bus,int addr,int regnum)414 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
415 {
416 struct bcm_sf2_priv *priv = bus->priv;
417
418 /* Intercept reads from Broadcom pseudo-PHY address, else, send
419 * them to our master MDIO bus controller
420 */
421 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
422 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
423 else
424 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
425 }
426
bcm_sf2_sw_mdio_write(struct mii_bus * bus,int addr,int regnum,u16 val)427 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
428 u16 val)
429 {
430 struct bcm_sf2_priv *priv = bus->priv;
431
432 /* Intercept writes to the Broadcom pseudo-PHY address, else,
433 * send them to our master MDIO bus controller
434 */
435 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
436 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
437 else
438 return mdiobus_write_nested(priv->master_mii_bus, addr,
439 regnum, val);
440 }
441
bcm_sf2_switch_0_isr(int irq,void * dev_id)442 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
443 {
444 struct bcm_sf2_priv *priv = dev_id;
445
446 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
447 ~priv->irq0_mask;
448 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
449
450 return IRQ_HANDLED;
451 }
452
bcm_sf2_switch_1_isr(int irq,void * dev_id)453 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
454 {
455 struct bcm_sf2_priv *priv = dev_id;
456
457 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
458 ~priv->irq1_mask;
459 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
460
461 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
462 priv->port_sts[7].link = 1;
463 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
464 priv->port_sts[7].link = 0;
465
466 return IRQ_HANDLED;
467 }
468
bcm_sf2_sw_rst(struct bcm_sf2_priv * priv)469 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
470 {
471 unsigned int timeout = 1000;
472 u32 reg;
473
474 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
475 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
476 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
477
478 do {
479 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
480 if (!(reg & SOFTWARE_RESET))
481 break;
482
483 usleep_range(1000, 2000);
484 } while (timeout-- > 0);
485
486 if (timeout == 0)
487 return -ETIMEDOUT;
488
489 return 0;
490 }
491
bcm_sf2_intr_disable(struct bcm_sf2_priv * priv)492 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
493 {
494 intrl2_0_mask_set(priv, 0xffffffff);
495 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
496 intrl2_1_mask_set(priv, 0xffffffff);
497 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
498 }
499
bcm_sf2_identify_ports(struct bcm_sf2_priv * priv,struct device_node * dn)500 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
501 struct device_node *dn)
502 {
503 struct device_node *port;
504 int mode;
505 unsigned int port_num;
506
507 priv->moca_port = -1;
508
509 for_each_available_child_of_node(dn, port) {
510 if (of_property_read_u32(port, "reg", &port_num))
511 continue;
512
513 /* Internal PHYs get assigned a specific 'phy-mode' property
514 * value: "internal" to help flag them before MDIO probing
515 * has completed, since they might be turned off at that
516 * time
517 */
518 mode = of_get_phy_mode(port);
519 if (mode < 0)
520 continue;
521
522 if (mode == PHY_INTERFACE_MODE_INTERNAL)
523 priv->int_phy_mask |= 1 << port_num;
524
525 if (mode == PHY_INTERFACE_MODE_MOCA)
526 priv->moca_port = port_num;
527
528 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
529 priv->brcm_tag_mask |= 1 << port_num;
530 }
531 }
532
bcm_sf2_mdio_register(struct dsa_switch * ds)533 static int bcm_sf2_mdio_register(struct dsa_switch *ds)
534 {
535 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
536 struct device_node *dn;
537 static int index;
538 int err;
539
540 /* Find our integrated MDIO bus node */
541 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
542 priv->master_mii_bus = of_mdio_find_bus(dn);
543 if (!priv->master_mii_bus)
544 return -EPROBE_DEFER;
545
546 get_device(&priv->master_mii_bus->dev);
547 priv->master_mii_dn = dn;
548
549 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
550 if (!priv->slave_mii_bus)
551 return -ENOMEM;
552
553 priv->slave_mii_bus->priv = priv;
554 priv->slave_mii_bus->name = "sf2 slave mii";
555 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
556 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
557 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
558 index++);
559 priv->slave_mii_bus->dev.of_node = dn;
560
561 /* Include the pseudo-PHY address to divert reads towards our
562 * workaround. This is only required for 7445D0, since 7445E0
563 * disconnects the internal switch pseudo-PHY such that we can use the
564 * regular SWITCH_MDIO master controller instead.
565 *
566 * Here we flag the pseudo PHY as needing special treatment and would
567 * otherwise make all other PHY read/writes go to the master MDIO bus
568 * controller that comes with this switch backed by the "mdio-unimac"
569 * driver.
570 */
571 if (of_machine_is_compatible("brcm,bcm7445d0"))
572 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
573 else
574 priv->indir_phy_mask = 0;
575
576 ds->phys_mii_mask = priv->indir_phy_mask;
577 ds->slave_mii_bus = priv->slave_mii_bus;
578 priv->slave_mii_bus->parent = ds->dev->parent;
579 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
580
581 if (dn)
582 err = of_mdiobus_register(priv->slave_mii_bus, dn);
583 else
584 err = mdiobus_register(priv->slave_mii_bus);
585
586 if (err)
587 of_node_put(dn);
588
589 return err;
590 }
591
bcm_sf2_mdio_unregister(struct bcm_sf2_priv * priv)592 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
593 {
594 mdiobus_unregister(priv->slave_mii_bus);
595 if (priv->master_mii_dn)
596 of_node_put(priv->master_mii_dn);
597 }
598
bcm_sf2_sw_get_phy_flags(struct dsa_switch * ds,int port)599 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
600 {
601 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
602
603 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
604 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
605 * the REG_PHY_REVISION register layout is.
606 */
607
608 return priv->hw_params.gphy_rev;
609 }
610
bcm_sf2_sw_adjust_link(struct dsa_switch * ds,int port,struct phy_device * phydev)611 static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
612 struct phy_device *phydev)
613 {
614 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
615 struct ethtool_eee *p = &priv->port_sts[port].eee;
616 u32 id_mode_dis = 0, port_mode;
617 const char *str = NULL;
618 u32 reg, offset;
619
620 if (priv->type == BCM7445_DEVICE_ID)
621 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
622 else
623 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
624
625 switch (phydev->interface) {
626 case PHY_INTERFACE_MODE_RGMII:
627 str = "RGMII (no delay)";
628 id_mode_dis = 1;
629 case PHY_INTERFACE_MODE_RGMII_TXID:
630 if (!str)
631 str = "RGMII (TX delay)";
632 port_mode = EXT_GPHY;
633 break;
634 case PHY_INTERFACE_MODE_MII:
635 str = "MII";
636 port_mode = EXT_EPHY;
637 break;
638 case PHY_INTERFACE_MODE_REVMII:
639 str = "Reverse MII";
640 port_mode = EXT_REVMII;
641 break;
642 default:
643 /* All other PHYs: internal and MoCA */
644 goto force_link;
645 }
646
647 /* If the link is down, just disable the interface to conserve power */
648 if (!phydev->link) {
649 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
650 reg &= ~RGMII_MODE_EN;
651 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
652 goto force_link;
653 }
654
655 /* Clear id_mode_dis bit, and the existing port mode, but
656 * make sure we enable the RGMII block for data to pass
657 */
658 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
659 reg &= ~ID_MODE_DIS;
660 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
661 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
662
663 reg |= port_mode | RGMII_MODE_EN;
664 if (id_mode_dis)
665 reg |= ID_MODE_DIS;
666
667 if (phydev->pause) {
668 if (phydev->asym_pause)
669 reg |= TX_PAUSE_EN;
670 reg |= RX_PAUSE_EN;
671 }
672
673 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
674
675 pr_info("Port %d configured for %s\n", port, str);
676
677 force_link:
678 /* Force link settings detected from the PHY */
679 reg = SW_OVERRIDE;
680 switch (phydev->speed) {
681 case SPEED_1000:
682 reg |= SPDSTS_1000 << SPEED_SHIFT;
683 break;
684 case SPEED_100:
685 reg |= SPDSTS_100 << SPEED_SHIFT;
686 break;
687 }
688
689 if (phydev->link)
690 reg |= LINK_STS;
691 if (phydev->duplex == DUPLEX_FULL)
692 reg |= DUPLX_MODE;
693
694 core_writel(priv, reg, offset);
695
696 if (!phydev->is_pseudo_fixed_link)
697 p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
698 }
699
bcm_sf2_sw_fixed_link_update(struct dsa_switch * ds,int port,struct fixed_phy_status * status)700 static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
701 struct fixed_phy_status *status)
702 {
703 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
704 u32 duplex, pause, offset;
705 u32 reg;
706
707 if (priv->type == BCM7445_DEVICE_ID)
708 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
709 else
710 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
711
712 duplex = core_readl(priv, CORE_DUPSTS);
713 pause = core_readl(priv, CORE_PAUSESTS);
714
715 status->link = 0;
716
717 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
718 * which means that we need to force the link at the port override
719 * level to get the data to flow. We do use what the interrupt handler
720 * did determine before.
721 *
722 * For the other ports, we just force the link status, since this is
723 * a fixed PHY device.
724 */
725 if (port == priv->moca_port) {
726 status->link = priv->port_sts[port].link;
727 /* For MoCA interfaces, also force a link down notification
728 * since some version of the user-space daemon (mocad) use
729 * cmd->autoneg to force the link, which messes up the PHY
730 * state machine and make it go in PHY_FORCING state instead.
731 */
732 if (!status->link)
733 netif_carrier_off(ds->ports[port].netdev);
734 status->duplex = 1;
735 } else {
736 status->link = 1;
737 status->duplex = !!(duplex & (1 << port));
738 }
739
740 reg = core_readl(priv, offset);
741 reg |= SW_OVERRIDE;
742 if (status->link)
743 reg |= LINK_STS;
744 else
745 reg &= ~LINK_STS;
746 core_writel(priv, reg, offset);
747
748 if ((pause & (1 << port)) &&
749 (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
750 status->asym_pause = 1;
751 status->pause = 1;
752 }
753
754 if (pause & (1 << port))
755 status->pause = 1;
756 }
757
bcm_sf2_sw_suspend(struct dsa_switch * ds)758 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
759 {
760 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
761 unsigned int port;
762
763 bcm_sf2_intr_disable(priv);
764
765 /* Disable all ports physically present including the IMP
766 * port, the other ones have already been disabled during
767 * bcm_sf2_sw_setup
768 */
769 for (port = 0; port < DSA_MAX_PORTS; port++) {
770 if ((1 << port) & ds->enabled_port_mask ||
771 dsa_is_cpu_port(ds, port))
772 bcm_sf2_port_disable(ds, port, NULL);
773 }
774
775 return 0;
776 }
777
bcm_sf2_sw_resume(struct dsa_switch * ds)778 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
779 {
780 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
781 int ret;
782
783 ret = bcm_sf2_sw_rst(priv);
784 if (ret) {
785 pr_err("%s: failed to software reset switch\n", __func__);
786 return ret;
787 }
788
789 if (priv->hw_params.num_gphy == 1)
790 bcm_sf2_gphy_enable_set(ds, true);
791
792 ds->ops->setup(ds);
793
794 return 0;
795 }
796
bcm_sf2_sw_get_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)797 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
798 struct ethtool_wolinfo *wol)
799 {
800 struct net_device *p = ds->dst->cpu_dp->netdev;
801 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
802 struct ethtool_wolinfo pwol;
803
804 /* Get the parent device WoL settings */
805 p->ethtool_ops->get_wol(p, &pwol);
806
807 /* Advertise the parent device supported settings */
808 wol->supported = pwol.supported;
809 memset(&wol->sopass, 0, sizeof(wol->sopass));
810
811 if (pwol.wolopts & WAKE_MAGICSECURE)
812 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
813
814 if (priv->wol_ports_mask & (1 << port))
815 wol->wolopts = pwol.wolopts;
816 else
817 wol->wolopts = 0;
818 }
819
bcm_sf2_sw_set_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)820 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
821 struct ethtool_wolinfo *wol)
822 {
823 struct net_device *p = ds->dst->cpu_dp->netdev;
824 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
825 s8 cpu_port = ds->dst->cpu_dp->index;
826 struct ethtool_wolinfo pwol;
827
828 p->ethtool_ops->get_wol(p, &pwol);
829 if (wol->wolopts & ~pwol.supported)
830 return -EINVAL;
831
832 if (wol->wolopts)
833 priv->wol_ports_mask |= (1 << port);
834 else
835 priv->wol_ports_mask &= ~(1 << port);
836
837 /* If we have at least one port enabled, make sure the CPU port
838 * is also enabled. If the CPU port is the last one enabled, we disable
839 * it since this configuration does not make sense.
840 */
841 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
842 priv->wol_ports_mask |= (1 << cpu_port);
843 else
844 priv->wol_ports_mask &= ~(1 << cpu_port);
845
846 return p->ethtool_ops->set_wol(p, wol);
847 }
848
bcm_sf2_vlan_op_wait(struct bcm_sf2_priv * priv)849 static int bcm_sf2_vlan_op_wait(struct bcm_sf2_priv *priv)
850 {
851 unsigned int timeout = 10;
852 u32 reg;
853
854 do {
855 reg = core_readl(priv, CORE_ARLA_VTBL_RWCTRL);
856 if (!(reg & ARLA_VTBL_STDN))
857 return 0;
858
859 usleep_range(1000, 2000);
860 } while (timeout--);
861
862 return -ETIMEDOUT;
863 }
864
bcm_sf2_vlan_op(struct bcm_sf2_priv * priv,u8 op)865 static int bcm_sf2_vlan_op(struct bcm_sf2_priv *priv, u8 op)
866 {
867 core_writel(priv, ARLA_VTBL_STDN | op, CORE_ARLA_VTBL_RWCTRL);
868
869 return bcm_sf2_vlan_op_wait(priv);
870 }
871
bcm_sf2_sw_configure_vlan(struct dsa_switch * ds)872 static void bcm_sf2_sw_configure_vlan(struct dsa_switch *ds)
873 {
874 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
875 unsigned int port;
876
877 /* Clear all VLANs */
878 bcm_sf2_vlan_op(priv, ARLA_VTBL_CMD_CLEAR);
879
880 for (port = 0; port < priv->hw_params.num_ports; port++) {
881 if (!((1 << port) & ds->enabled_port_mask))
882 continue;
883
884 core_writel(priv, 1, CORE_DEFAULT_1Q_TAG_P(port));
885 }
886 }
887
bcm_sf2_sw_setup(struct dsa_switch * ds)888 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
889 {
890 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
891 unsigned int port;
892
893 /* Enable all valid ports and disable those unused */
894 for (port = 0; port < priv->hw_params.num_ports; port++) {
895 /* IMP port receives special treatment */
896 if ((1 << port) & ds->enabled_port_mask)
897 bcm_sf2_port_setup(ds, port, NULL);
898 else if (dsa_is_cpu_port(ds, port))
899 bcm_sf2_imp_setup(ds, port);
900 else
901 bcm_sf2_port_disable(ds, port, NULL);
902 }
903
904 bcm_sf2_sw_configure_vlan(ds);
905
906 return 0;
907 }
908
909 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
910 * register basis so we need to translate that into an address that the
911 * bus-glue understands.
912 */
913 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
914
bcm_sf2_core_read8(struct b53_device * dev,u8 page,u8 reg,u8 * val)915 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
916 u8 *val)
917 {
918 struct bcm_sf2_priv *priv = dev->priv;
919
920 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
921
922 return 0;
923 }
924
bcm_sf2_core_read16(struct b53_device * dev,u8 page,u8 reg,u16 * val)925 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
926 u16 *val)
927 {
928 struct bcm_sf2_priv *priv = dev->priv;
929
930 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
931
932 return 0;
933 }
934
bcm_sf2_core_read32(struct b53_device * dev,u8 page,u8 reg,u32 * val)935 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
936 u32 *val)
937 {
938 struct bcm_sf2_priv *priv = dev->priv;
939
940 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
941
942 return 0;
943 }
944
bcm_sf2_core_read64(struct b53_device * dev,u8 page,u8 reg,u64 * val)945 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
946 u64 *val)
947 {
948 struct bcm_sf2_priv *priv = dev->priv;
949
950 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
951
952 return 0;
953 }
954
bcm_sf2_core_write8(struct b53_device * dev,u8 page,u8 reg,u8 value)955 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
956 u8 value)
957 {
958 struct bcm_sf2_priv *priv = dev->priv;
959
960 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
961
962 return 0;
963 }
964
bcm_sf2_core_write16(struct b53_device * dev,u8 page,u8 reg,u16 value)965 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
966 u16 value)
967 {
968 struct bcm_sf2_priv *priv = dev->priv;
969
970 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
971
972 return 0;
973 }
974
bcm_sf2_core_write32(struct b53_device * dev,u8 page,u8 reg,u32 value)975 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
976 u32 value)
977 {
978 struct bcm_sf2_priv *priv = dev->priv;
979
980 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
981
982 return 0;
983 }
984
bcm_sf2_core_write64(struct b53_device * dev,u8 page,u8 reg,u64 value)985 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
986 u64 value)
987 {
988 struct bcm_sf2_priv *priv = dev->priv;
989
990 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
991
992 return 0;
993 }
994
995 static const struct b53_io_ops bcm_sf2_io_ops = {
996 .read8 = bcm_sf2_core_read8,
997 .read16 = bcm_sf2_core_read16,
998 .read32 = bcm_sf2_core_read32,
999 .read48 = bcm_sf2_core_read64,
1000 .read64 = bcm_sf2_core_read64,
1001 .write8 = bcm_sf2_core_write8,
1002 .write16 = bcm_sf2_core_write16,
1003 .write32 = bcm_sf2_core_write32,
1004 .write48 = bcm_sf2_core_write64,
1005 .write64 = bcm_sf2_core_write64,
1006 };
1007
1008 static const struct dsa_switch_ops bcm_sf2_ops = {
1009 .get_tag_protocol = bcm_sf2_sw_get_tag_protocol,
1010 .setup = bcm_sf2_sw_setup,
1011 .get_strings = b53_get_strings,
1012 .get_ethtool_stats = b53_get_ethtool_stats,
1013 .get_sset_count = b53_get_sset_count,
1014 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
1015 .adjust_link = bcm_sf2_sw_adjust_link,
1016 .fixed_link_update = bcm_sf2_sw_fixed_link_update,
1017 .suspend = bcm_sf2_sw_suspend,
1018 .resume = bcm_sf2_sw_resume,
1019 .get_wol = bcm_sf2_sw_get_wol,
1020 .set_wol = bcm_sf2_sw_set_wol,
1021 .port_enable = bcm_sf2_port_setup,
1022 .port_disable = bcm_sf2_port_disable,
1023 .get_mac_eee = bcm_sf2_sw_get_mac_eee,
1024 .set_mac_eee = bcm_sf2_sw_set_mac_eee,
1025 .port_bridge_join = b53_br_join,
1026 .port_bridge_leave = b53_br_leave,
1027 .port_stp_state_set = b53_br_set_stp_state,
1028 .port_fast_age = b53_br_fast_age,
1029 .port_vlan_filtering = b53_vlan_filtering,
1030 .port_vlan_prepare = b53_vlan_prepare,
1031 .port_vlan_add = b53_vlan_add,
1032 .port_vlan_del = b53_vlan_del,
1033 .port_fdb_dump = b53_fdb_dump,
1034 .port_fdb_add = b53_fdb_add,
1035 .port_fdb_del = b53_fdb_del,
1036 .get_rxnfc = bcm_sf2_get_rxnfc,
1037 .set_rxnfc = bcm_sf2_set_rxnfc,
1038 .port_mirror_add = b53_mirror_add,
1039 .port_mirror_del = b53_mirror_del,
1040 };
1041
1042 struct bcm_sf2_of_data {
1043 u32 type;
1044 const u16 *reg_offsets;
1045 unsigned int core_reg_align;
1046 unsigned int num_cfp_rules;
1047 };
1048
1049 /* Register offsets for the SWITCH_REG_* block */
1050 static const u16 bcm_sf2_7445_reg_offsets[] = {
1051 [REG_SWITCH_CNTRL] = 0x00,
1052 [REG_SWITCH_STATUS] = 0x04,
1053 [REG_DIR_DATA_WRITE] = 0x08,
1054 [REG_DIR_DATA_READ] = 0x0C,
1055 [REG_SWITCH_REVISION] = 0x18,
1056 [REG_PHY_REVISION] = 0x1C,
1057 [REG_SPHY_CNTRL] = 0x2C,
1058 [REG_RGMII_0_CNTRL] = 0x34,
1059 [REG_RGMII_1_CNTRL] = 0x40,
1060 [REG_RGMII_2_CNTRL] = 0x4c,
1061 [REG_LED_0_CNTRL] = 0x90,
1062 [REG_LED_1_CNTRL] = 0x94,
1063 [REG_LED_2_CNTRL] = 0x98,
1064 };
1065
1066 static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1067 .type = BCM7445_DEVICE_ID,
1068 .core_reg_align = 0,
1069 .reg_offsets = bcm_sf2_7445_reg_offsets,
1070 .num_cfp_rules = 256,
1071 };
1072
1073 static const u16 bcm_sf2_7278_reg_offsets[] = {
1074 [REG_SWITCH_CNTRL] = 0x00,
1075 [REG_SWITCH_STATUS] = 0x04,
1076 [REG_DIR_DATA_WRITE] = 0x08,
1077 [REG_DIR_DATA_READ] = 0x0c,
1078 [REG_SWITCH_REVISION] = 0x10,
1079 [REG_PHY_REVISION] = 0x14,
1080 [REG_SPHY_CNTRL] = 0x24,
1081 [REG_RGMII_0_CNTRL] = 0xe0,
1082 [REG_RGMII_1_CNTRL] = 0xec,
1083 [REG_RGMII_2_CNTRL] = 0xf8,
1084 [REG_LED_0_CNTRL] = 0x40,
1085 [REG_LED_1_CNTRL] = 0x4c,
1086 [REG_LED_2_CNTRL] = 0x58,
1087 };
1088
1089 static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1090 .type = BCM7278_DEVICE_ID,
1091 .core_reg_align = 1,
1092 .reg_offsets = bcm_sf2_7278_reg_offsets,
1093 .num_cfp_rules = 128,
1094 };
1095
1096 static const struct of_device_id bcm_sf2_of_match[] = {
1097 { .compatible = "brcm,bcm7445-switch-v4.0",
1098 .data = &bcm_sf2_7445_data
1099 },
1100 { .compatible = "brcm,bcm7278-switch-v4.0",
1101 .data = &bcm_sf2_7278_data
1102 },
1103 { /* sentinel */ },
1104 };
1105 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1106
bcm_sf2_sw_probe(struct platform_device * pdev)1107 static int bcm_sf2_sw_probe(struct platform_device *pdev)
1108 {
1109 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1110 struct device_node *dn = pdev->dev.of_node;
1111 const struct of_device_id *of_id = NULL;
1112 const struct bcm_sf2_of_data *data;
1113 struct b53_platform_data *pdata;
1114 struct dsa_switch_ops *ops;
1115 struct bcm_sf2_priv *priv;
1116 struct b53_device *dev;
1117 struct dsa_switch *ds;
1118 void __iomem **base;
1119 struct resource *r;
1120 unsigned int i;
1121 u32 reg, rev;
1122 int ret;
1123
1124 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1125 if (!priv)
1126 return -ENOMEM;
1127
1128 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1129 if (!ops)
1130 return -ENOMEM;
1131
1132 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1133 if (!dev)
1134 return -ENOMEM;
1135
1136 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1137 if (!pdata)
1138 return -ENOMEM;
1139
1140 of_id = of_match_node(bcm_sf2_of_match, dn);
1141 if (!of_id || !of_id->data)
1142 return -EINVAL;
1143
1144 data = of_id->data;
1145
1146 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1147 priv->type = data->type;
1148 priv->reg_offsets = data->reg_offsets;
1149 priv->core_reg_align = data->core_reg_align;
1150 priv->num_cfp_rules = data->num_cfp_rules;
1151
1152 /* Auto-detection using standard registers will not work, so
1153 * provide an indication of what kind of device we are for
1154 * b53_common to work with
1155 */
1156 pdata->chip_id = priv->type;
1157 dev->pdata = pdata;
1158
1159 priv->dev = dev;
1160 ds = dev->ds;
1161 ds->ops = &bcm_sf2_ops;
1162
1163 /* Advertise the 8 egress queues */
1164 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1165
1166 dev_set_drvdata(&pdev->dev, priv);
1167
1168 spin_lock_init(&priv->indir_lock);
1169 mutex_init(&priv->stats_mutex);
1170 mutex_init(&priv->cfp.lock);
1171
1172 /* CFP rule #0 cannot be used for specific classifications, flag it as
1173 * permanently used
1174 */
1175 set_bit(0, priv->cfp.used);
1176
1177 bcm_sf2_identify_ports(priv, dn->child);
1178
1179 priv->irq0 = irq_of_parse_and_map(dn, 0);
1180 priv->irq1 = irq_of_parse_and_map(dn, 1);
1181
1182 base = &priv->core;
1183 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1184 r = platform_get_resource(pdev, IORESOURCE_MEM, i);
1185 *base = devm_ioremap_resource(&pdev->dev, r);
1186 if (IS_ERR(*base)) {
1187 pr_err("unable to find register: %s\n", reg_names[i]);
1188 return PTR_ERR(*base);
1189 }
1190 base++;
1191 }
1192
1193 ret = bcm_sf2_sw_rst(priv);
1194 if (ret) {
1195 pr_err("unable to software reset switch: %d\n", ret);
1196 return ret;
1197 }
1198
1199 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1200
1201 ret = bcm_sf2_mdio_register(ds);
1202 if (ret) {
1203 pr_err("failed to register MDIO bus\n");
1204 return ret;
1205 }
1206
1207 bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1208
1209 ret = bcm_sf2_cfp_rst(priv);
1210 if (ret) {
1211 pr_err("failed to reset CFP\n");
1212 goto out_mdio;
1213 }
1214
1215 /* Disable all interrupts and request them */
1216 bcm_sf2_intr_disable(priv);
1217
1218 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1219 "switch_0", priv);
1220 if (ret < 0) {
1221 pr_err("failed to request switch_0 IRQ\n");
1222 goto out_mdio;
1223 }
1224
1225 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1226 "switch_1", priv);
1227 if (ret < 0) {
1228 pr_err("failed to request switch_1 IRQ\n");
1229 goto out_mdio;
1230 }
1231
1232 /* Reset the MIB counters */
1233 reg = core_readl(priv, CORE_GMNCFGCFG);
1234 reg |= RST_MIB_CNT;
1235 core_writel(priv, reg, CORE_GMNCFGCFG);
1236 reg &= ~RST_MIB_CNT;
1237 core_writel(priv, reg, CORE_GMNCFGCFG);
1238
1239 /* Get the maximum number of ports for this switch */
1240 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1241 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1242 priv->hw_params.num_ports = DSA_MAX_PORTS;
1243
1244 /* Assume a single GPHY setup if we can't read that property */
1245 if (of_property_read_u32(dn, "brcm,num-gphy",
1246 &priv->hw_params.num_gphy))
1247 priv->hw_params.num_gphy = 1;
1248
1249 rev = reg_readl(priv, REG_SWITCH_REVISION);
1250 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1251 SWITCH_TOP_REV_MASK;
1252 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1253
1254 rev = reg_readl(priv, REG_PHY_REVISION);
1255 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1256
1257 ret = b53_switch_register(dev);
1258 if (ret)
1259 goto out_mdio;
1260
1261 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
1262 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1263 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1264 priv->core, priv->irq0, priv->irq1);
1265
1266 return 0;
1267
1268 out_mdio:
1269 bcm_sf2_mdio_unregister(priv);
1270 return ret;
1271 }
1272
bcm_sf2_sw_remove(struct platform_device * pdev)1273 static int bcm_sf2_sw_remove(struct platform_device *pdev)
1274 {
1275 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1276
1277 priv->wol_ports_mask = 0;
1278 dsa_unregister_switch(priv->dev->ds);
1279 /* Disable all ports and interrupts */
1280 bcm_sf2_sw_suspend(priv->dev->ds);
1281 bcm_sf2_mdio_unregister(priv);
1282
1283 return 0;
1284 }
1285
bcm_sf2_sw_shutdown(struct platform_device * pdev)1286 static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1287 {
1288 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1289
1290 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1291 * successful MDIO bus scan to occur. If we did turn off the GPHY
1292 * before (e.g: port_disable), this will also power it back on.
1293 *
1294 * Do not rely on kexec_in_progress, just power the PHY on.
1295 */
1296 if (priv->hw_params.num_gphy == 1)
1297 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1298 }
1299
1300 #ifdef CONFIG_PM_SLEEP
bcm_sf2_suspend(struct device * dev)1301 static int bcm_sf2_suspend(struct device *dev)
1302 {
1303 struct platform_device *pdev = to_platform_device(dev);
1304 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1305
1306 return dsa_switch_suspend(priv->dev->ds);
1307 }
1308
bcm_sf2_resume(struct device * dev)1309 static int bcm_sf2_resume(struct device *dev)
1310 {
1311 struct platform_device *pdev = to_platform_device(dev);
1312 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1313
1314 return dsa_switch_resume(priv->dev->ds);
1315 }
1316 #endif /* CONFIG_PM_SLEEP */
1317
1318 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1319 bcm_sf2_suspend, bcm_sf2_resume);
1320
1321
1322 static struct platform_driver bcm_sf2_driver = {
1323 .probe = bcm_sf2_sw_probe,
1324 .remove = bcm_sf2_sw_remove,
1325 .shutdown = bcm_sf2_sw_shutdown,
1326 .driver = {
1327 .name = "brcm-sf2",
1328 .of_match_table = bcm_sf2_of_match,
1329 .pm = &bcm_sf2_pm_ops,
1330 },
1331 };
1332 module_platform_driver(bcm_sf2_driver);
1333
1334 MODULE_AUTHOR("Broadcom Corporation");
1335 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1336 MODULE_LICENSE("GPL");
1337 MODULE_ALIAS("platform:brcm-sf2");
1338