1 /*
2 * Copyright 2015 Amazon.com, Inc. or its affiliates.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef ENA_COM
34 #define ENA_COM
35
36 #include <linux/compiler.h>
37 #include <linux/delay.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/gfp.h>
40 #include <linux/sched.h>
41 #include <linux/sizes.h>
42 #include <linux/spinlock.h>
43 #include <linux/types.h>
44 #include <linux/wait.h>
45 #include <linux/netdevice.h>
46
47 #include "ena_common_defs.h"
48 #include "ena_admin_defs.h"
49 #include "ena_eth_io_defs.h"
50 #include "ena_regs_defs.h"
51
52 #undef pr_fmt
53 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
54
55 #define ENA_MAX_NUM_IO_QUEUES 128U
56 /* We need to queues for each IO (on for Tx and one for Rx) */
57 #define ENA_TOTAL_NUM_QUEUES (2 * (ENA_MAX_NUM_IO_QUEUES))
58
59 #define ENA_MAX_HANDLERS 256
60
61 #define ENA_MAX_PHYS_ADDR_SIZE_BITS 48
62
63 /* Unit in usec */
64 #define ENA_REG_READ_TIMEOUT 200000
65
66 #define ADMIN_SQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aq_entry))
67 #define ADMIN_CQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_acq_entry))
68 #define ADMIN_AENQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aenq_entry))
69
70 /*****************************************************************************/
71 /*****************************************************************************/
72 /* ENA adaptive interrupt moderation settings */
73
74 #define ENA_INTR_LOWEST_USECS (0)
75 #define ENA_INTR_LOWEST_PKTS (3)
76 #define ENA_INTR_LOWEST_BYTES (2 * 1524)
77
78 #define ENA_INTR_LOW_USECS (32)
79 #define ENA_INTR_LOW_PKTS (12)
80 #define ENA_INTR_LOW_BYTES (16 * 1024)
81
82 #define ENA_INTR_MID_USECS (80)
83 #define ENA_INTR_MID_PKTS (48)
84 #define ENA_INTR_MID_BYTES (64 * 1024)
85
86 #define ENA_INTR_HIGH_USECS (128)
87 #define ENA_INTR_HIGH_PKTS (96)
88 #define ENA_INTR_HIGH_BYTES (128 * 1024)
89
90 #define ENA_INTR_HIGHEST_USECS (192)
91 #define ENA_INTR_HIGHEST_PKTS (128)
92 #define ENA_INTR_HIGHEST_BYTES (192 * 1024)
93
94 #define ENA_INTR_INITIAL_TX_INTERVAL_USECS 196
95 #define ENA_INTR_INITIAL_RX_INTERVAL_USECS 4
96 #define ENA_INTR_DELAY_OLD_VALUE_WEIGHT 6
97 #define ENA_INTR_DELAY_NEW_VALUE_WEIGHT 4
98 #define ENA_INTR_MODER_LEVEL_STRIDE 2
99 #define ENA_INTR_BYTE_COUNT_NOT_SUPPORTED 0xFFFFFF
100
101 #define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF
102
103 enum ena_intr_moder_level {
104 ENA_INTR_MODER_LOWEST = 0,
105 ENA_INTR_MODER_LOW,
106 ENA_INTR_MODER_MID,
107 ENA_INTR_MODER_HIGH,
108 ENA_INTR_MODER_HIGHEST,
109 ENA_INTR_MAX_NUM_OF_LEVELS,
110 };
111
112 struct ena_intr_moder_entry {
113 unsigned int intr_moder_interval;
114 unsigned int pkts_per_interval;
115 unsigned int bytes_per_interval;
116 };
117
118 enum queue_direction {
119 ENA_COM_IO_QUEUE_DIRECTION_TX,
120 ENA_COM_IO_QUEUE_DIRECTION_RX
121 };
122
123 struct ena_com_buf {
124 dma_addr_t paddr; /**< Buffer physical address */
125 u16 len; /**< Buffer length in bytes */
126 };
127
128 struct ena_com_rx_buf_info {
129 u16 len;
130 u16 req_id;
131 };
132
133 struct ena_com_io_desc_addr {
134 u8 __iomem *pbuf_dev_addr; /* LLQ address */
135 u8 *virt_addr;
136 dma_addr_t phys_addr;
137 };
138
139 struct ena_com_tx_meta {
140 u16 mss;
141 u16 l3_hdr_len;
142 u16 l3_hdr_offset;
143 u16 l4_hdr_len; /* In words */
144 };
145
146 struct ena_com_io_cq {
147 struct ena_com_io_desc_addr cdesc_addr;
148
149 /* Interrupt unmask register */
150 u32 __iomem *unmask_reg;
151
152 /* The completion queue head doorbell register */
153 u32 __iomem *cq_head_db_reg;
154
155 /* numa configuration register (for TPH) */
156 u32 __iomem *numa_node_cfg_reg;
157
158 /* The value to write to the above register to unmask
159 * the interrupt of this queue
160 */
161 u32 msix_vector;
162
163 enum queue_direction direction;
164
165 /* holds the number of cdesc of the current packet */
166 u16 cur_rx_pkt_cdesc_count;
167 /* save the firt cdesc idx of the current packet */
168 u16 cur_rx_pkt_cdesc_start_idx;
169
170 u16 q_depth;
171 /* Caller qid */
172 u16 qid;
173
174 /* Device queue index */
175 u16 idx;
176 u16 head;
177 u16 last_head_update;
178 u8 phase;
179 u8 cdesc_entry_size_in_bytes;
180
181 } ____cacheline_aligned;
182
183 struct ena_com_io_sq {
184 struct ena_com_io_desc_addr desc_addr;
185
186 u32 __iomem *db_addr;
187 u8 __iomem *header_addr;
188
189 enum queue_direction direction;
190 enum ena_admin_placement_policy_type mem_queue_type;
191
192 u32 msix_vector;
193 struct ena_com_tx_meta cached_tx_meta;
194
195 u16 q_depth;
196 u16 qid;
197
198 u16 idx;
199 u16 tail;
200 u16 next_to_comp;
201 u32 tx_max_header_size;
202 u8 phase;
203 u8 desc_entry_size;
204 u8 dma_addr_bits;
205 } ____cacheline_aligned;
206
207 struct ena_com_admin_cq {
208 struct ena_admin_acq_entry *entries;
209 dma_addr_t dma_addr;
210
211 u16 head;
212 u8 phase;
213 };
214
215 struct ena_com_admin_sq {
216 struct ena_admin_aq_entry *entries;
217 dma_addr_t dma_addr;
218
219 u32 __iomem *db_addr;
220
221 u16 head;
222 u16 tail;
223 u8 phase;
224
225 };
226
227 struct ena_com_stats_admin {
228 u32 aborted_cmd;
229 u32 submitted_cmd;
230 u32 completed_cmd;
231 u32 out_of_space;
232 u32 no_completion;
233 };
234
235 struct ena_com_admin_queue {
236 void *q_dmadev;
237 spinlock_t q_lock; /* spinlock for the admin queue */
238
239 struct ena_comp_ctx *comp_ctx;
240 u32 completion_timeout;
241 u16 q_depth;
242 struct ena_com_admin_cq cq;
243 struct ena_com_admin_sq sq;
244
245 /* Indicate if the admin queue should poll for completion */
246 bool polling;
247
248 u16 curr_cmd_id;
249
250 /* Indicate that the ena was initialized and can
251 * process new admin commands
252 */
253 bool running_state;
254
255 /* Count the number of outstanding admin commands */
256 atomic_t outstanding_cmds;
257
258 struct ena_com_stats_admin stats;
259 };
260
261 struct ena_aenq_handlers;
262
263 struct ena_com_aenq {
264 u16 head;
265 u8 phase;
266 struct ena_admin_aenq_entry *entries;
267 dma_addr_t dma_addr;
268 u16 q_depth;
269 struct ena_aenq_handlers *aenq_handlers;
270 };
271
272 struct ena_com_mmio_read {
273 struct ena_admin_ena_mmio_req_read_less_resp *read_resp;
274 dma_addr_t read_resp_dma_addr;
275 u32 reg_read_to; /* in us */
276 u16 seq_num;
277 bool readless_supported;
278 /* spin lock to ensure a single outstanding read */
279 spinlock_t lock;
280 };
281
282 struct ena_rss {
283 /* Indirect table */
284 u16 *host_rss_ind_tbl;
285 struct ena_admin_rss_ind_table_entry *rss_ind_tbl;
286 dma_addr_t rss_ind_tbl_dma_addr;
287 u16 tbl_log_size;
288
289 /* Hash key */
290 enum ena_admin_hash_functions hash_func;
291 struct ena_admin_feature_rss_flow_hash_control *hash_key;
292 dma_addr_t hash_key_dma_addr;
293 u32 hash_init_val;
294
295 /* Flow Control */
296 struct ena_admin_feature_rss_hash_control *hash_ctrl;
297 dma_addr_t hash_ctrl_dma_addr;
298
299 };
300
301 struct ena_host_attribute {
302 /* Debug area */
303 u8 *debug_area_virt_addr;
304 dma_addr_t debug_area_dma_addr;
305 u32 debug_area_size;
306
307 /* Host information */
308 struct ena_admin_host_info *host_info;
309 dma_addr_t host_info_dma_addr;
310 };
311
312 /* Each ena_dev is a PCI function. */
313 struct ena_com_dev {
314 struct ena_com_admin_queue admin_queue;
315 struct ena_com_aenq aenq;
316 struct ena_com_io_cq io_cq_queues[ENA_TOTAL_NUM_QUEUES];
317 struct ena_com_io_sq io_sq_queues[ENA_TOTAL_NUM_QUEUES];
318 u8 __iomem *reg_bar;
319 void __iomem *mem_bar;
320 void *dmadev;
321
322 enum ena_admin_placement_policy_type tx_mem_queue_type;
323 u32 tx_max_header_size;
324 u16 stats_func; /* Selected function for extended statistic dump */
325 u16 stats_queue; /* Selected queue for extended statistic dump */
326
327 struct ena_com_mmio_read mmio_read;
328
329 struct ena_rss rss;
330 u32 supported_features;
331 u32 dma_addr_bits;
332
333 struct ena_host_attribute host_attr;
334 bool adaptive_coalescing;
335 u16 intr_delay_resolution;
336 u32 intr_moder_tx_interval;
337 struct ena_intr_moder_entry *intr_moder_tbl;
338 };
339
340 struct ena_com_dev_get_features_ctx {
341 struct ena_admin_queue_feature_desc max_queues;
342 struct ena_admin_device_attr_feature_desc dev_attr;
343 struct ena_admin_feature_aenq_desc aenq;
344 struct ena_admin_feature_offload_desc offload;
345 struct ena_admin_ena_hw_hints hw_hints;
346 };
347
348 struct ena_com_create_io_ctx {
349 enum ena_admin_placement_policy_type mem_queue_type;
350 enum queue_direction direction;
351 int numa_node;
352 u32 msix_vector;
353 u16 queue_size;
354 u16 qid;
355 };
356
357 typedef void (*ena_aenq_handler)(void *data,
358 struct ena_admin_aenq_entry *aenq_e);
359
360 /* Holds aenq handlers. Indexed by AENQ event group */
361 struct ena_aenq_handlers {
362 ena_aenq_handler handlers[ENA_MAX_HANDLERS];
363 ena_aenq_handler unimplemented_handler;
364 };
365
366 /*****************************************************************************/
367 /*****************************************************************************/
368
369 /* ena_com_mmio_reg_read_request_init - Init the mmio reg read mechanism
370 * @ena_dev: ENA communication layer struct
371 *
372 * Initialize the register read mechanism.
373 *
374 * @note: This method must be the first stage in the initialization sequence.
375 *
376 * @return - 0 on success, negative value on failure.
377 */
378 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev);
379
380 /* ena_com_set_mmio_read_mode - Enable/disable the mmio reg read mechanism
381 * @ena_dev: ENA communication layer struct
382 * @readless_supported: readless mode (enable/disable)
383 */
384 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev,
385 bool readless_supported);
386
387 /* ena_com_mmio_reg_read_request_write_dev_addr - Write the mmio reg read return
388 * value physical address.
389 * @ena_dev: ENA communication layer struct
390 */
391 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev);
392
393 /* ena_com_mmio_reg_read_request_destroy - Destroy the mmio reg read mechanism
394 * @ena_dev: ENA communication layer struct
395 */
396 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev);
397
398 /* ena_com_admin_init - Init the admin and the async queues
399 * @ena_dev: ENA communication layer struct
400 * @aenq_handlers: Those handlers to be called upon event.
401 * @init_spinlock: Indicate if this method should init the admin spinlock or
402 * the spinlock was init before (for example, in a case of FLR).
403 *
404 * Initialize the admin submission and completion queues.
405 * Initialize the asynchronous events notification queues.
406 *
407 * @return - 0 on success, negative value on failure.
408 */
409 int ena_com_admin_init(struct ena_com_dev *ena_dev,
410 struct ena_aenq_handlers *aenq_handlers,
411 bool init_spinlock);
412
413 /* ena_com_admin_destroy - Destroy the admin and the async events queues.
414 * @ena_dev: ENA communication layer struct
415 *
416 * @note: Before calling this method, the caller must validate that the device
417 * won't send any additional admin completions/aenq.
418 * To achieve that, a FLR is recommended.
419 */
420 void ena_com_admin_destroy(struct ena_com_dev *ena_dev);
421
422 /* ena_com_dev_reset - Perform device FLR to the device.
423 * @ena_dev: ENA communication layer struct
424 * @reset_reason: Specify what is the trigger for the reset in case of an error.
425 *
426 * @return - 0 on success, negative value on failure.
427 */
428 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
429 enum ena_regs_reset_reason_types reset_reason);
430
431 /* ena_com_create_io_queue - Create io queue.
432 * @ena_dev: ENA communication layer struct
433 * @ctx - create context structure
434 *
435 * Create the submission and the completion queues.
436 *
437 * @return - 0 on success, negative value on failure.
438 */
439 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
440 struct ena_com_create_io_ctx *ctx);
441
442 /* ena_com_destroy_io_queue - Destroy IO queue with the queue id - qid.
443 * @ena_dev: ENA communication layer struct
444 * @qid - the caller virtual queue id.
445 */
446 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid);
447
448 /* ena_com_get_io_handlers - Return the io queue handlers
449 * @ena_dev: ENA communication layer struct
450 * @qid - the caller virtual queue id.
451 * @io_sq - IO submission queue handler
452 * @io_cq - IO completion queue handler.
453 *
454 * @return - 0 on success, negative value on failure.
455 */
456 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
457 struct ena_com_io_sq **io_sq,
458 struct ena_com_io_cq **io_cq);
459
460 /* ena_com_admin_aenq_enable - ENAble asynchronous event notifications
461 * @ena_dev: ENA communication layer struct
462 *
463 * After this method, aenq event can be received via AENQ.
464 */
465 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev);
466
467 /* ena_com_set_admin_running_state - Set the state of the admin queue
468 * @ena_dev: ENA communication layer struct
469 *
470 * Change the state of the admin queue (enable/disable)
471 */
472 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state);
473
474 /* ena_com_get_admin_running_state - Get the admin queue state
475 * @ena_dev: ENA communication layer struct
476 *
477 * Retrieve the state of the admin queue (enable/disable)
478 *
479 * @return - current polling mode (enable/disable)
480 */
481 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev);
482
483 /* ena_com_set_admin_polling_mode - Set the admin completion queue polling mode
484 * @ena_dev: ENA communication layer struct
485 * @polling: ENAble/Disable polling mode
486 *
487 * Set the admin completion mode.
488 */
489 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling);
490
491 /* ena_com_set_admin_polling_mode - Get the admin completion queue polling mode
492 * @ena_dev: ENA communication layer struct
493 *
494 * Get the admin completion mode.
495 * If polling mode is on, ena_com_execute_admin_command will perform a
496 * polling on the admin completion queue for the commands completion,
497 * otherwise it will wait on wait event.
498 *
499 * @return state
500 */
501 bool ena_com_get_ena_admin_polling_mode(struct ena_com_dev *ena_dev);
502
503 /* ena_com_admin_q_comp_intr_handler - admin queue interrupt handler
504 * @ena_dev: ENA communication layer struct
505 *
506 * This method go over the admin completion queue and wake up all the pending
507 * threads that wait on the commands wait event.
508 *
509 * @note: Should be called after MSI-X interrupt.
510 */
511 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev);
512
513 /* ena_com_aenq_intr_handler - AENQ interrupt handler
514 * @ena_dev: ENA communication layer struct
515 *
516 * This method go over the async event notification queue and call the proper
517 * aenq handler.
518 */
519 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data);
520
521 /* ena_com_abort_admin_commands - Abort all the outstanding admin commands.
522 * @ena_dev: ENA communication layer struct
523 *
524 * This method aborts all the outstanding admin commands.
525 * The caller should then call ena_com_wait_for_abort_completion to make sure
526 * all the commands were completed.
527 */
528 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev);
529
530 /* ena_com_wait_for_abort_completion - Wait for admin commands abort.
531 * @ena_dev: ENA communication layer struct
532 *
533 * This method wait until all the outstanding admin commands will be completed.
534 */
535 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev);
536
537 /* ena_com_validate_version - Validate the device parameters
538 * @ena_dev: ENA communication layer struct
539 *
540 * This method validate the device parameters are the same as the saved
541 * parameters in ena_dev.
542 * This method is useful after device reset, to validate the device mac address
543 * and the device offloads are the same as before the reset.
544 *
545 * @return - 0 on success negative value otherwise.
546 */
547 int ena_com_validate_version(struct ena_com_dev *ena_dev);
548
549 /* ena_com_get_link_params - Retrieve physical link parameters.
550 * @ena_dev: ENA communication layer struct
551 * @resp: Link parameters
552 *
553 * Retrieve the physical link parameters,
554 * like speed, auto-negotiation and full duplex support.
555 *
556 * @return - 0 on Success negative value otherwise.
557 */
558 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
559 struct ena_admin_get_feat_resp *resp);
560
561 /* ena_com_get_dma_width - Retrieve physical dma address width the device
562 * supports.
563 * @ena_dev: ENA communication layer struct
564 *
565 * Retrieve the maximum physical address bits the device can handle.
566 *
567 * @return: > 0 on Success and negative value otherwise.
568 */
569 int ena_com_get_dma_width(struct ena_com_dev *ena_dev);
570
571 /* ena_com_set_aenq_config - Set aenq groups configurations
572 * @ena_dev: ENA communication layer struct
573 * @groups flag: bit fields flags of enum ena_admin_aenq_group.
574 *
575 * Configure which aenq event group the driver would like to receive.
576 *
577 * @return: 0 on Success and negative value otherwise.
578 */
579 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag);
580
581 /* ena_com_get_dev_attr_feat - Get device features
582 * @ena_dev: ENA communication layer struct
583 * @get_feat_ctx: returned context that contain the get features.
584 *
585 * @return: 0 on Success and negative value otherwise.
586 */
587 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
588 struct ena_com_dev_get_features_ctx *get_feat_ctx);
589
590 /* ena_com_get_dev_basic_stats - Get device basic statistics
591 * @ena_dev: ENA communication layer struct
592 * @stats: stats return value
593 *
594 * @return: 0 on Success and negative value otherwise.
595 */
596 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
597 struct ena_admin_basic_stats *stats);
598
599 /* ena_com_set_dev_mtu - Configure the device mtu.
600 * @ena_dev: ENA communication layer struct
601 * @mtu: mtu value
602 *
603 * @return: 0 on Success and negative value otherwise.
604 */
605 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu);
606
607 /* ena_com_get_offload_settings - Retrieve the device offloads capabilities
608 * @ena_dev: ENA communication layer struct
609 * @offlad: offload return value
610 *
611 * @return: 0 on Success and negative value otherwise.
612 */
613 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
614 struct ena_admin_feature_offload_desc *offload);
615
616 /* ena_com_rss_init - Init RSS
617 * @ena_dev: ENA communication layer struct
618 * @log_size: indirection log size
619 *
620 * Allocate RSS/RFS resources.
621 * The caller then can configure rss using ena_com_set_hash_function,
622 * ena_com_set_hash_ctrl and ena_com_indirect_table_set.
623 *
624 * @return: 0 on Success and negative value otherwise.
625 */
626 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 log_size);
627
628 /* ena_com_rss_destroy - Destroy rss
629 * @ena_dev: ENA communication layer struct
630 *
631 * Free all the RSS/RFS resources.
632 */
633 void ena_com_rss_destroy(struct ena_com_dev *ena_dev);
634
635 /* ena_com_get_current_hash_function - Get RSS hash function
636 * @ena_dev: ENA communication layer struct
637 *
638 * Return the current hash function.
639 * @return: 0 or one of the ena_admin_hash_functions values.
640 */
641 int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev);
642
643 /* ena_com_fill_hash_function - Fill RSS hash function
644 * @ena_dev: ENA communication layer struct
645 * @func: The hash function (Toeplitz or crc)
646 * @key: Hash key (for toeplitz hash)
647 * @key_len: key length (max length 10 DW)
648 * @init_val: initial value for the hash function
649 *
650 * Fill the ena_dev resources with the desire hash function, hash key, key_len
651 * and key initial value (if needed by the hash function).
652 * To flush the key into the device the caller should call
653 * ena_com_set_hash_function.
654 *
655 * @return: 0 on Success and negative value otherwise.
656 */
657 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
658 enum ena_admin_hash_functions func,
659 const u8 *key, u16 key_len, u32 init_val);
660
661 /* ena_com_set_hash_function - Flush the hash function and it dependencies to
662 * the device.
663 * @ena_dev: ENA communication layer struct
664 *
665 * Flush the hash function and it dependencies (key, key length and
666 * initial value) if needed.
667 *
668 * @note: Prior to this method the caller should call ena_com_fill_hash_function
669 *
670 * @return: 0 on Success and negative value otherwise.
671 */
672 int ena_com_set_hash_function(struct ena_com_dev *ena_dev);
673
674 /* ena_com_get_hash_function - Retrieve the hash function and the hash key
675 * from the device.
676 * @ena_dev: ENA communication layer struct
677 * @func: hash function
678 * @key: hash key
679 *
680 * Retrieve the hash function and the hash key from the device.
681 *
682 * @note: If the caller called ena_com_fill_hash_function but didn't flash
683 * it to the device, the new configuration will be lost.
684 *
685 * @return: 0 on Success and negative value otherwise.
686 */
687 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
688 enum ena_admin_hash_functions *func,
689 u8 *key);
690
691 /* ena_com_fill_hash_ctrl - Fill RSS hash control
692 * @ena_dev: ENA communication layer struct.
693 * @proto: The protocol to configure.
694 * @hash_fields: bit mask of ena_admin_flow_hash_fields
695 *
696 * Fill the ena_dev resources with the desire hash control (the ethernet
697 * fields that take part of the hash) for a specific protocol.
698 * To flush the hash control to the device, the caller should call
699 * ena_com_set_hash_ctrl.
700 *
701 * @return: 0 on Success and negative value otherwise.
702 */
703 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
704 enum ena_admin_flow_hash_proto proto,
705 u16 hash_fields);
706
707 /* ena_com_set_hash_ctrl - Flush the hash control resources to the device.
708 * @ena_dev: ENA communication layer struct
709 *
710 * Flush the hash control (the ethernet fields that take part of the hash)
711 *
712 * @note: Prior to this method the caller should call ena_com_fill_hash_ctrl.
713 *
714 * @return: 0 on Success and negative value otherwise.
715 */
716 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev);
717
718 /* ena_com_get_hash_ctrl - Retrieve the hash control from the device.
719 * @ena_dev: ENA communication layer struct
720 * @proto: The protocol to retrieve.
721 * @fields: bit mask of ena_admin_flow_hash_fields.
722 *
723 * Retrieve the hash control from the device.
724 *
725 * @note, If the caller called ena_com_fill_hash_ctrl but didn't flash
726 * it to the device, the new configuration will be lost.
727 *
728 * @return: 0 on Success and negative value otherwise.
729 */
730 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
731 enum ena_admin_flow_hash_proto proto,
732 u16 *fields);
733
734 /* ena_com_set_default_hash_ctrl - Set the hash control to a default
735 * configuration.
736 * @ena_dev: ENA communication layer struct
737 *
738 * Fill the ena_dev resources with the default hash control configuration.
739 * To flush the hash control to the device, the caller should call
740 * ena_com_set_hash_ctrl.
741 *
742 * @return: 0 on Success and negative value otherwise.
743 */
744 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev);
745
746 /* ena_com_indirect_table_fill_entry - Fill a single entry in the RSS
747 * indirection table
748 * @ena_dev: ENA communication layer struct.
749 * @entry_idx - indirection table entry.
750 * @entry_value - redirection value
751 *
752 * Fill a single entry of the RSS indirection table in the ena_dev resources.
753 * To flush the indirection table to the device, the called should call
754 * ena_com_indirect_table_set.
755 *
756 * @return: 0 on Success and negative value otherwise.
757 */
758 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
759 u16 entry_idx, u16 entry_value);
760
761 /* ena_com_indirect_table_set - Flush the indirection table to the device.
762 * @ena_dev: ENA communication layer struct
763 *
764 * Flush the indirection hash control to the device.
765 * Prior to this method the caller should call ena_com_indirect_table_fill_entry
766 *
767 * @return: 0 on Success and negative value otherwise.
768 */
769 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev);
770
771 /* ena_com_indirect_table_get - Retrieve the indirection table from the device.
772 * @ena_dev: ENA communication layer struct
773 * @ind_tbl: indirection table
774 *
775 * Retrieve the RSS indirection table from the device.
776 *
777 * @note: If the caller called ena_com_indirect_table_fill_entry but didn't flash
778 * it to the device, the new configuration will be lost.
779 *
780 * @return: 0 on Success and negative value otherwise.
781 */
782 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl);
783
784 /* ena_com_allocate_host_info - Allocate host info resources.
785 * @ena_dev: ENA communication layer struct
786 *
787 * @return: 0 on Success and negative value otherwise.
788 */
789 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev);
790
791 /* ena_com_allocate_debug_area - Allocate debug area.
792 * @ena_dev: ENA communication layer struct
793 * @debug_area_size - debug area size.
794 *
795 * @return: 0 on Success and negative value otherwise.
796 */
797 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
798 u32 debug_area_size);
799
800 /* ena_com_delete_debug_area - Free the debug area resources.
801 * @ena_dev: ENA communication layer struct
802 *
803 * Free the allocate debug area.
804 */
805 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev);
806
807 /* ena_com_delete_host_info - Free the host info resources.
808 * @ena_dev: ENA communication layer struct
809 *
810 * Free the allocate host info.
811 */
812 void ena_com_delete_host_info(struct ena_com_dev *ena_dev);
813
814 /* ena_com_set_host_attributes - Update the device with the host
815 * attributes (debug area and host info) base address.
816 * @ena_dev: ENA communication layer struct
817 *
818 * @return: 0 on Success and negative value otherwise.
819 */
820 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev);
821
822 /* ena_com_create_io_cq - Create io completion queue.
823 * @ena_dev: ENA communication layer struct
824 * @io_cq - io completion queue handler
825
826 * Create IO completion queue.
827 *
828 * @return - 0 on success, negative value on failure.
829 */
830 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
831 struct ena_com_io_cq *io_cq);
832
833 /* ena_com_destroy_io_cq - Destroy io completion queue.
834 * @ena_dev: ENA communication layer struct
835 * @io_cq - io completion queue handler
836
837 * Destroy IO completion queue.
838 *
839 * @return - 0 on success, negative value on failure.
840 */
841 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
842 struct ena_com_io_cq *io_cq);
843
844 /* ena_com_execute_admin_command - Execute admin command
845 * @admin_queue: admin queue.
846 * @cmd: the admin command to execute.
847 * @cmd_size: the command size.
848 * @cmd_completion: command completion return value.
849 * @cmd_comp_size: command completion size.
850
851 * Submit an admin command and then wait until the device will return a
852 * completion.
853 * The completion will be copyed into cmd_comp.
854 *
855 * @return - 0 on success, negative value on failure.
856 */
857 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
858 struct ena_admin_aq_entry *cmd,
859 size_t cmd_size,
860 struct ena_admin_acq_entry *cmd_comp,
861 size_t cmd_comp_size);
862
863 /* ena_com_init_interrupt_moderation - Init interrupt moderation
864 * @ena_dev: ENA communication layer struct
865 *
866 * @return - 0 on success, negative value on failure.
867 */
868 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev);
869
870 /* ena_com_destroy_interrupt_moderation - Destroy interrupt moderation resources
871 * @ena_dev: ENA communication layer struct
872 */
873 void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev);
874
875 /* ena_com_interrupt_moderation_supported - Return if interrupt moderation
876 * capability is supported by the device.
877 *
878 * @return - supported or not.
879 */
880 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev);
881
882 /* ena_com_config_default_interrupt_moderation_table - Restore the interrupt
883 * moderation table back to the default parameters.
884 * @ena_dev: ENA communication layer struct
885 */
886 void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev);
887
888 /* ena_com_update_nonadaptive_moderation_interval_tx - Update the
889 * non-adaptive interval in Tx direction.
890 * @ena_dev: ENA communication layer struct
891 * @tx_coalesce_usecs: Interval in usec.
892 *
893 * @return - 0 on success, negative value on failure.
894 */
895 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
896 u32 tx_coalesce_usecs);
897
898 /* ena_com_update_nonadaptive_moderation_interval_rx - Update the
899 * non-adaptive interval in Rx direction.
900 * @ena_dev: ENA communication layer struct
901 * @rx_coalesce_usecs: Interval in usec.
902 *
903 * @return - 0 on success, negative value on failure.
904 */
905 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
906 u32 rx_coalesce_usecs);
907
908 /* ena_com_get_nonadaptive_moderation_interval_tx - Retrieve the
909 * non-adaptive interval in Tx direction.
910 * @ena_dev: ENA communication layer struct
911 *
912 * @return - interval in usec
913 */
914 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev);
915
916 /* ena_com_get_nonadaptive_moderation_interval_rx - Retrieve the
917 * non-adaptive interval in Rx direction.
918 * @ena_dev: ENA communication layer struct
919 *
920 * @return - interval in usec
921 */
922 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev);
923
924 /* ena_com_init_intr_moderation_entry - Update a single entry in the interrupt
925 * moderation table.
926 * @ena_dev: ENA communication layer struct
927 * @level: Interrupt moderation table level
928 * @entry: Entry value
929 *
930 * Update a single entry in the interrupt moderation table.
931 */
932 void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev,
933 enum ena_intr_moder_level level,
934 struct ena_intr_moder_entry *entry);
935
936 /* ena_com_get_intr_moderation_entry - Init ena_intr_moder_entry.
937 * @ena_dev: ENA communication layer struct
938 * @level: Interrupt moderation table level
939 * @entry: Entry to fill.
940 *
941 * Initialize the entry according to the adaptive interrupt moderation table.
942 */
943 void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev,
944 enum ena_intr_moder_level level,
945 struct ena_intr_moder_entry *entry);
946
ena_com_get_adaptive_moderation_enabled(struct ena_com_dev * ena_dev)947 static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev)
948 {
949 return ena_dev->adaptive_coalescing;
950 }
951
ena_com_enable_adaptive_moderation(struct ena_com_dev * ena_dev)952 static inline void ena_com_enable_adaptive_moderation(struct ena_com_dev *ena_dev)
953 {
954 ena_dev->adaptive_coalescing = true;
955 }
956
ena_com_disable_adaptive_moderation(struct ena_com_dev * ena_dev)957 static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_dev)
958 {
959 ena_dev->adaptive_coalescing = false;
960 }
961
962 /* ena_com_calculate_interrupt_delay - Calculate new interrupt delay
963 * @ena_dev: ENA communication layer struct
964 * @pkts: Number of packets since the last update
965 * @bytes: Number of bytes received since the last update.
966 * @smoothed_interval: Returned interval
967 * @moder_tbl_idx: Current table level as input update new level as return
968 * value.
969 */
ena_com_calculate_interrupt_delay(struct ena_com_dev * ena_dev,unsigned int pkts,unsigned int bytes,unsigned int * smoothed_interval,unsigned int * moder_tbl_idx)970 static inline void ena_com_calculate_interrupt_delay(struct ena_com_dev *ena_dev,
971 unsigned int pkts,
972 unsigned int bytes,
973 unsigned int *smoothed_interval,
974 unsigned int *moder_tbl_idx)
975 {
976 enum ena_intr_moder_level curr_moder_idx, new_moder_idx;
977 struct ena_intr_moder_entry *curr_moder_entry;
978 struct ena_intr_moder_entry *pred_moder_entry;
979 struct ena_intr_moder_entry *new_moder_entry;
980 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
981 unsigned int interval;
982
983 /* We apply adaptive moderation on Rx path only.
984 * Tx uses static interrupt moderation.
985 */
986 if (!pkts || !bytes)
987 /* Tx interrupt, or spurious interrupt,
988 * in both cases we just use same delay values
989 */
990 return;
991
992 curr_moder_idx = (enum ena_intr_moder_level)(*moder_tbl_idx);
993 if (unlikely(curr_moder_idx >= ENA_INTR_MAX_NUM_OF_LEVELS)) {
994 pr_err("Wrong moderation index %u\n", curr_moder_idx);
995 return;
996 }
997
998 curr_moder_entry = &intr_moder_tbl[curr_moder_idx];
999 new_moder_idx = curr_moder_idx;
1000
1001 if (curr_moder_idx == ENA_INTR_MODER_LOWEST) {
1002 if ((pkts > curr_moder_entry->pkts_per_interval) ||
1003 (bytes > curr_moder_entry->bytes_per_interval))
1004 new_moder_idx =
1005 (enum ena_intr_moder_level)(curr_moder_idx + ENA_INTR_MODER_LEVEL_STRIDE);
1006 } else {
1007 pred_moder_entry = &intr_moder_tbl[curr_moder_idx - ENA_INTR_MODER_LEVEL_STRIDE];
1008
1009 if ((pkts <= pred_moder_entry->pkts_per_interval) ||
1010 (bytes <= pred_moder_entry->bytes_per_interval))
1011 new_moder_idx =
1012 (enum ena_intr_moder_level)(curr_moder_idx - ENA_INTR_MODER_LEVEL_STRIDE);
1013 else if ((pkts > curr_moder_entry->pkts_per_interval) ||
1014 (bytes > curr_moder_entry->bytes_per_interval)) {
1015 if (curr_moder_idx != ENA_INTR_MODER_HIGHEST)
1016 new_moder_idx =
1017 (enum ena_intr_moder_level)(curr_moder_idx + ENA_INTR_MODER_LEVEL_STRIDE);
1018 }
1019 }
1020 new_moder_entry = &intr_moder_tbl[new_moder_idx];
1021
1022 interval = new_moder_entry->intr_moder_interval;
1023 *smoothed_interval = (
1024 (interval * ENA_INTR_DELAY_NEW_VALUE_WEIGHT +
1025 ENA_INTR_DELAY_OLD_VALUE_WEIGHT * (*smoothed_interval)) + 5) /
1026 10;
1027
1028 *moder_tbl_idx = new_moder_idx;
1029 }
1030
1031 /* ena_com_update_intr_reg - Prepare interrupt register
1032 * @intr_reg: interrupt register to update.
1033 * @rx_delay_interval: Rx interval in usecs
1034 * @tx_delay_interval: Tx interval in usecs
1035 * @unmask: unask enable/disable
1036 *
1037 * Prepare interrupt update register with the supplied parameters.
1038 */
ena_com_update_intr_reg(struct ena_eth_io_intr_reg * intr_reg,u32 rx_delay_interval,u32 tx_delay_interval,bool unmask)1039 static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg,
1040 u32 rx_delay_interval,
1041 u32 tx_delay_interval,
1042 bool unmask)
1043 {
1044 intr_reg->intr_control = 0;
1045 intr_reg->intr_control |= rx_delay_interval &
1046 ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
1047
1048 intr_reg->intr_control |=
1049 (tx_delay_interval << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT)
1050 & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK;
1051
1052 if (unmask)
1053 intr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;
1054 }
1055
1056 #endif /* !(ENA_COM) */
1057