1 /*
2 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
3 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
4 *
5 * Derived from Intel e1000 driver
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23 #include <linux/atomic.h>
24 #include <linux/crc32.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/etherdevice.h>
27 #include <linux/ethtool.h>
28 #include <linux/hardirq.h>
29 #include <linux/if_vlan.h>
30 #include <linux/in.h>
31 #include <linux/interrupt.h>
32 #include <linux/ip.h>
33 #include <linux/irqflags.h>
34 #include <linux/irqreturn.h>
35 #include <linux/mii.h>
36 #include <linux/net.h>
37 #include <linux/netdevice.h>
38 #include <linux/pci.h>
39 #include <linux/pci_ids.h>
40 #include <linux/pm.h>
41 #include <linux/skbuff.h>
42 #include <linux/slab.h>
43 #include <linux/spinlock.h>
44 #include <linux/string.h>
45 #include <linux/tcp.h>
46 #include <linux/timer.h>
47 #include <linux/types.h>
48 #include <linux/workqueue.h>
49
50 #include "atl2.h"
51
52 #define ATL2_DRV_VERSION "2.2.3"
53
54 static const char atl2_driver_name[] = "atl2";
55 static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver";
56 static const char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation.";
57 static const char atl2_driver_version[] = ATL2_DRV_VERSION;
58 static const struct ethtool_ops atl2_ethtool_ops;
59
60 MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>");
61 MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver");
62 MODULE_LICENSE("GPL");
63 MODULE_VERSION(ATL2_DRV_VERSION);
64
65 /*
66 * atl2_pci_tbl - PCI Device ID Table
67 */
68 static const struct pci_device_id atl2_pci_tbl[] = {
69 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)},
70 /* required last entry */
71 {0,}
72 };
73 MODULE_DEVICE_TABLE(pci, atl2_pci_tbl);
74
75 static void atl2_check_options(struct atl2_adapter *adapter);
76
77 /**
78 * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
79 * @adapter: board private structure to initialize
80 *
81 * atl2_sw_init initializes the Adapter private data structure.
82 * Fields are initialized based on PCI device information and
83 * OS network device settings (MTU size).
84 */
atl2_sw_init(struct atl2_adapter * adapter)85 static int atl2_sw_init(struct atl2_adapter *adapter)
86 {
87 struct atl2_hw *hw = &adapter->hw;
88 struct pci_dev *pdev = adapter->pdev;
89
90 /* PCI config space info */
91 hw->vendor_id = pdev->vendor;
92 hw->device_id = pdev->device;
93 hw->subsystem_vendor_id = pdev->subsystem_vendor;
94 hw->subsystem_id = pdev->subsystem_device;
95 hw->revision_id = pdev->revision;
96
97 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
98
99 adapter->wol = 0;
100 adapter->ict = 50000; /* ~100ms */
101 adapter->link_speed = SPEED_0; /* hardware init */
102 adapter->link_duplex = FULL_DUPLEX;
103
104 hw->phy_configured = false;
105 hw->preamble_len = 7;
106 hw->ipgt = 0x60;
107 hw->min_ifg = 0x50;
108 hw->ipgr1 = 0x40;
109 hw->ipgr2 = 0x60;
110 hw->retry_buf = 2;
111 hw->max_retry = 0xf;
112 hw->lcol = 0x37;
113 hw->jam_ipg = 7;
114 hw->fc_rxd_hi = 0;
115 hw->fc_rxd_lo = 0;
116 hw->max_frame_size = adapter->netdev->mtu;
117
118 spin_lock_init(&adapter->stats_lock);
119
120 set_bit(__ATL2_DOWN, &adapter->flags);
121
122 return 0;
123 }
124
125 /**
126 * atl2_set_multi - Multicast and Promiscuous mode set
127 * @netdev: network interface device structure
128 *
129 * The set_multi entry point is called whenever the multicast address
130 * list or the network interface flags are updated. This routine is
131 * responsible for configuring the hardware for proper multicast,
132 * promiscuous mode, and all-multi behavior.
133 */
atl2_set_multi(struct net_device * netdev)134 static void atl2_set_multi(struct net_device *netdev)
135 {
136 struct atl2_adapter *adapter = netdev_priv(netdev);
137 struct atl2_hw *hw = &adapter->hw;
138 struct netdev_hw_addr *ha;
139 u32 rctl;
140 u32 hash_value;
141
142 /* Check for Promiscuous and All Multicast modes */
143 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL);
144
145 if (netdev->flags & IFF_PROMISC) {
146 rctl |= MAC_CTRL_PROMIS_EN;
147 } else if (netdev->flags & IFF_ALLMULTI) {
148 rctl |= MAC_CTRL_MC_ALL_EN;
149 rctl &= ~MAC_CTRL_PROMIS_EN;
150 } else
151 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
152
153 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);
154
155 /* clear the old settings from the multicast hash table */
156 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
157 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
158
159 /* comoute mc addresses' hash value ,and put it into hash table */
160 netdev_for_each_mc_addr(ha, netdev) {
161 hash_value = atl2_hash_mc_addr(hw, ha->addr);
162 atl2_hash_set(hw, hash_value);
163 }
164 }
165
init_ring_ptrs(struct atl2_adapter * adapter)166 static void init_ring_ptrs(struct atl2_adapter *adapter)
167 {
168 /* Read / Write Ptr Initialize: */
169 adapter->txd_write_ptr = 0;
170 atomic_set(&adapter->txd_read_ptr, 0);
171
172 adapter->rxd_read_ptr = 0;
173 adapter->rxd_write_ptr = 0;
174
175 atomic_set(&adapter->txs_write_ptr, 0);
176 adapter->txs_next_clear = 0;
177 }
178
179 /**
180 * atl2_configure - Configure Transmit&Receive Unit after Reset
181 * @adapter: board private structure
182 *
183 * Configure the Tx /Rx unit of the MAC after a reset.
184 */
atl2_configure(struct atl2_adapter * adapter)185 static int atl2_configure(struct atl2_adapter *adapter)
186 {
187 struct atl2_hw *hw = &adapter->hw;
188 u32 value;
189
190 /* clear interrupt status */
191 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);
192
193 /* set MAC Address */
194 value = (((u32)hw->mac_addr[2]) << 24) |
195 (((u32)hw->mac_addr[3]) << 16) |
196 (((u32)hw->mac_addr[4]) << 8) |
197 (((u32)hw->mac_addr[5]));
198 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);
199 value = (((u32)hw->mac_addr[0]) << 8) |
200 (((u32)hw->mac_addr[1]));
201 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);
202
203 /* HI base address */
204 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
205 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32));
206
207 /* LO base address */
208 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,
209 (u32)(adapter->txd_dma & 0x00000000ffffffffULL));
210 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,
211 (u32)(adapter->txs_dma & 0x00000000ffffffffULL));
212 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,
213 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL));
214
215 /* element count */
216 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));
217 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);
218 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size);
219
220 /* config Internal SRAM */
221 /*
222 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);
223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);
224 */
225
226 /* config IPG/IFG */
227 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) <<
228 MAC_IPG_IFG_IPGT_SHIFT) |
229 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) <<
230 MAC_IPG_IFG_MIFG_SHIFT) |
231 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) <<
232 MAC_IPG_IFG_IPGR1_SHIFT)|
233 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) <<
234 MAC_IPG_IFG_IPGR2_SHIFT);
235 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);
236
237 /* config Half-Duplex Control */
238 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
239 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) <<
240 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
241 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
242 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
243 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) <<
244 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
245 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);
246
247 /* set Interrupt Moderator Timer */
248 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);
249 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);
250
251 /* set Interrupt Clear Timer */
252 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);
253
254 /* set MTU */
255 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +
256 ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
257
258 /* 1590 */
259 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);
260
261 /* flow control */
262 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);
263 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);
264
265 /* Init mailbox */
266 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);
267 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);
268
269 /* enable DMA read/write */
270 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN);
271 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN);
272
273 value = ATL2_READ_REG(&adapter->hw, REG_ISR);
274 if ((value & ISR_PHY_LINKDOWN) != 0)
275 value = 1; /* config failed */
276 else
277 value = 0;
278
279 /* clear all interrupt status */
280 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);
281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
282 return value;
283 }
284
285 /**
286 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources
287 * @adapter: board private structure
288 *
289 * Return 0 on success, negative on failure
290 */
atl2_setup_ring_resources(struct atl2_adapter * adapter)291 static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter)
292 {
293 struct pci_dev *pdev = adapter->pdev;
294 int size;
295 u8 offset = 0;
296
297 /* real ring DMA buffer */
298 adapter->ring_size = size =
299 adapter->txd_ring_size * 1 + 7 + /* dword align */
300 adapter->txs_ring_size * 4 + 7 + /* dword align */
301 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */
302
303 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size,
304 &adapter->ring_dma);
305 if (!adapter->ring_vir_addr)
306 return -ENOMEM;
307 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
308
309 /* Init TXD Ring */
310 adapter->txd_dma = adapter->ring_dma ;
311 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;
312 adapter->txd_dma += offset;
313 adapter->txd_ring = adapter->ring_vir_addr + offset;
314
315 /* Init TXS Ring */
316 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;
317 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0;
318 adapter->txs_dma += offset;
319 adapter->txs_ring = (struct tx_pkt_status *)
320 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset));
321
322 /* Init RXD Ring */
323 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4;
324 offset = (adapter->rxd_dma & 127) ?
325 (128 - (adapter->rxd_dma & 127)) : 0;
326 if (offset > 7)
327 offset -= 8;
328 else
329 offset += (128 - 8);
330
331 adapter->rxd_dma += offset;
332 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) +
333 (adapter->txs_ring_size * 4 + offset));
334
335 /*
336 * Read / Write Ptr Initialize:
337 * init_ring_ptrs(adapter);
338 */
339 return 0;
340 }
341
342 /**
343 * atl2_irq_enable - Enable default interrupt generation settings
344 * @adapter: board private structure
345 */
atl2_irq_enable(struct atl2_adapter * adapter)346 static inline void atl2_irq_enable(struct atl2_adapter *adapter)
347 {
348 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
349 ATL2_WRITE_FLUSH(&adapter->hw);
350 }
351
352 /**
353 * atl2_irq_disable - Mask off interrupt generation on the NIC
354 * @adapter: board private structure
355 */
atl2_irq_disable(struct atl2_adapter * adapter)356 static inline void atl2_irq_disable(struct atl2_adapter *adapter)
357 {
358 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);
359 ATL2_WRITE_FLUSH(&adapter->hw);
360 synchronize_irq(adapter->pdev->irq);
361 }
362
__atl2_vlan_mode(netdev_features_t features,u32 * ctrl)363 static void __atl2_vlan_mode(netdev_features_t features, u32 *ctrl)
364 {
365 if (features & NETIF_F_HW_VLAN_CTAG_RX) {
366 /* enable VLAN tag insert/strip */
367 *ctrl |= MAC_CTRL_RMV_VLAN;
368 } else {
369 /* disable VLAN tag insert/strip */
370 *ctrl &= ~MAC_CTRL_RMV_VLAN;
371 }
372 }
373
atl2_vlan_mode(struct net_device * netdev,netdev_features_t features)374 static void atl2_vlan_mode(struct net_device *netdev,
375 netdev_features_t features)
376 {
377 struct atl2_adapter *adapter = netdev_priv(netdev);
378 u32 ctrl;
379
380 atl2_irq_disable(adapter);
381
382 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
383 __atl2_vlan_mode(features, &ctrl);
384 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
385
386 atl2_irq_enable(adapter);
387 }
388
atl2_restore_vlan(struct atl2_adapter * adapter)389 static void atl2_restore_vlan(struct atl2_adapter *adapter)
390 {
391 atl2_vlan_mode(adapter->netdev, adapter->netdev->features);
392 }
393
atl2_fix_features(struct net_device * netdev,netdev_features_t features)394 static netdev_features_t atl2_fix_features(struct net_device *netdev,
395 netdev_features_t features)
396 {
397 /*
398 * Since there is no support for separate rx/tx vlan accel
399 * enable/disable make sure tx flag is always in same state as rx.
400 */
401 if (features & NETIF_F_HW_VLAN_CTAG_RX)
402 features |= NETIF_F_HW_VLAN_CTAG_TX;
403 else
404 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
405
406 return features;
407 }
408
atl2_set_features(struct net_device * netdev,netdev_features_t features)409 static int atl2_set_features(struct net_device *netdev,
410 netdev_features_t features)
411 {
412 netdev_features_t changed = netdev->features ^ features;
413
414 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
415 atl2_vlan_mode(netdev, features);
416
417 return 0;
418 }
419
atl2_intr_rx(struct atl2_adapter * adapter)420 static void atl2_intr_rx(struct atl2_adapter *adapter)
421 {
422 struct net_device *netdev = adapter->netdev;
423 struct rx_desc *rxd;
424 struct sk_buff *skb;
425
426 do {
427 rxd = adapter->rxd_ring+adapter->rxd_write_ptr;
428 if (!rxd->status.update)
429 break; /* end of tx */
430
431 /* clear this flag at once */
432 rxd->status.update = 0;
433
434 if (rxd->status.ok && rxd->status.pkt_size >= 60) {
435 int rx_size = (int)(rxd->status.pkt_size - 4);
436 /* alloc new buffer */
437 skb = netdev_alloc_skb_ip_align(netdev, rx_size);
438 if (NULL == skb) {
439 /*
440 * Check that some rx space is free. If not,
441 * free one and mark stats->rx_dropped++.
442 */
443 netdev->stats.rx_dropped++;
444 break;
445 }
446 memcpy(skb->data, rxd->packet, rx_size);
447 skb_put(skb, rx_size);
448 skb->protocol = eth_type_trans(skb, netdev);
449 if (rxd->status.vlan) {
450 u16 vlan_tag = (rxd->status.vtag>>4) |
451 ((rxd->status.vtag&7) << 13) |
452 ((rxd->status.vtag&8) << 9);
453
454 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
455 }
456 netif_rx(skb);
457 netdev->stats.rx_bytes += rx_size;
458 netdev->stats.rx_packets++;
459 } else {
460 netdev->stats.rx_errors++;
461
462 if (rxd->status.ok && rxd->status.pkt_size <= 60)
463 netdev->stats.rx_length_errors++;
464 if (rxd->status.mcast)
465 netdev->stats.multicast++;
466 if (rxd->status.crc)
467 netdev->stats.rx_crc_errors++;
468 if (rxd->status.align)
469 netdev->stats.rx_frame_errors++;
470 }
471
472 /* advance write ptr */
473 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size)
474 adapter->rxd_write_ptr = 0;
475 } while (1);
476
477 /* update mailbox? */
478 adapter->rxd_read_ptr = adapter->rxd_write_ptr;
479 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr);
480 }
481
atl2_intr_tx(struct atl2_adapter * adapter)482 static void atl2_intr_tx(struct atl2_adapter *adapter)
483 {
484 struct net_device *netdev = adapter->netdev;
485 u32 txd_read_ptr;
486 u32 txs_write_ptr;
487 struct tx_pkt_status *txs;
488 struct tx_pkt_header *txph;
489 int free_hole = 0;
490
491 do {
492 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
493 txs = adapter->txs_ring + txs_write_ptr;
494 if (!txs->update)
495 break; /* tx stop here */
496
497 free_hole = 1;
498 txs->update = 0;
499
500 if (++txs_write_ptr == adapter->txs_ring_size)
501 txs_write_ptr = 0;
502 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr);
503
504 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr);
505 txph = (struct tx_pkt_header *)
506 (((u8 *)adapter->txd_ring) + txd_read_ptr);
507
508 if (txph->pkt_size != txs->pkt_size) {
509 struct tx_pkt_status *old_txs = txs;
510 printk(KERN_WARNING
511 "%s: txs packet size not consistent with txd"
512 " txd_:0x%08x, txs_:0x%08x!\n",
513 adapter->netdev->name,
514 *(u32 *)txph, *(u32 *)txs);
515 printk(KERN_WARNING
516 "txd read ptr: 0x%x\n",
517 txd_read_ptr);
518 txs = adapter->txs_ring + txs_write_ptr;
519 printk(KERN_WARNING
520 "txs-behind:0x%08x\n",
521 *(u32 *)txs);
522 if (txs_write_ptr < 2) {
523 txs = adapter->txs_ring +
524 (adapter->txs_ring_size +
525 txs_write_ptr - 2);
526 } else {
527 txs = adapter->txs_ring + (txs_write_ptr - 2);
528 }
529 printk(KERN_WARNING
530 "txs-before:0x%08x\n",
531 *(u32 *)txs);
532 txs = old_txs;
533 }
534
535 /* 4for TPH */
536 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3);
537 if (txd_read_ptr >= adapter->txd_ring_size)
538 txd_read_ptr -= adapter->txd_ring_size;
539
540 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr);
541
542 /* tx statistics: */
543 if (txs->ok) {
544 netdev->stats.tx_bytes += txs->pkt_size;
545 netdev->stats.tx_packets++;
546 }
547 else
548 netdev->stats.tx_errors++;
549
550 if (txs->defer)
551 netdev->stats.collisions++;
552 if (txs->abort_col)
553 netdev->stats.tx_aborted_errors++;
554 if (txs->late_col)
555 netdev->stats.tx_window_errors++;
556 if (txs->underun)
557 netdev->stats.tx_fifo_errors++;
558 } while (1);
559
560 if (free_hole) {
561 if (netif_queue_stopped(adapter->netdev) &&
562 netif_carrier_ok(adapter->netdev))
563 netif_wake_queue(adapter->netdev);
564 }
565 }
566
atl2_check_for_link(struct atl2_adapter * adapter)567 static void atl2_check_for_link(struct atl2_adapter *adapter)
568 {
569 struct net_device *netdev = adapter->netdev;
570 u16 phy_data = 0;
571
572 spin_lock(&adapter->stats_lock);
573 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
574 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
575 spin_unlock(&adapter->stats_lock);
576
577 /* notify upper layer link down ASAP */
578 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
579 if (netif_carrier_ok(netdev)) { /* old link state: Up */
580 printk(KERN_INFO "%s: %s NIC Link is Down\n",
581 atl2_driver_name, netdev->name);
582 adapter->link_speed = SPEED_0;
583 netif_carrier_off(netdev);
584 netif_stop_queue(netdev);
585 }
586 }
587 schedule_work(&adapter->link_chg_task);
588 }
589
atl2_clear_phy_int(struct atl2_adapter * adapter)590 static inline void atl2_clear_phy_int(struct atl2_adapter *adapter)
591 {
592 u16 phy_data;
593 spin_lock(&adapter->stats_lock);
594 atl2_read_phy_reg(&adapter->hw, 19, &phy_data);
595 spin_unlock(&adapter->stats_lock);
596 }
597
598 /**
599 * atl2_intr - Interrupt Handler
600 * @irq: interrupt number
601 * @data: pointer to a network interface device structure
602 */
atl2_intr(int irq,void * data)603 static irqreturn_t atl2_intr(int irq, void *data)
604 {
605 struct atl2_adapter *adapter = netdev_priv(data);
606 struct atl2_hw *hw = &adapter->hw;
607 u32 status;
608
609 status = ATL2_READ_REG(hw, REG_ISR);
610 if (0 == status)
611 return IRQ_NONE;
612
613 /* link event */
614 if (status & ISR_PHY)
615 atl2_clear_phy_int(adapter);
616
617 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
618 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
619
620 /* check if PCIE PHY Link down */
621 if (status & ISR_PHY_LINKDOWN) {
622 if (netif_running(adapter->netdev)) { /* reset MAC */
623 ATL2_WRITE_REG(hw, REG_ISR, 0);
624 ATL2_WRITE_REG(hw, REG_IMR, 0);
625 ATL2_WRITE_FLUSH(hw);
626 schedule_work(&adapter->reset_task);
627 return IRQ_HANDLED;
628 }
629 }
630
631 /* check if DMA read/write error? */
632 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
633 ATL2_WRITE_REG(hw, REG_ISR, 0);
634 ATL2_WRITE_REG(hw, REG_IMR, 0);
635 ATL2_WRITE_FLUSH(hw);
636 schedule_work(&adapter->reset_task);
637 return IRQ_HANDLED;
638 }
639
640 /* link event */
641 if (status & (ISR_PHY | ISR_MANUAL)) {
642 adapter->netdev->stats.tx_carrier_errors++;
643 atl2_check_for_link(adapter);
644 }
645
646 /* transmit event */
647 if (status & ISR_TX_EVENT)
648 atl2_intr_tx(adapter);
649
650 /* rx exception */
651 if (status & ISR_RX_EVENT)
652 atl2_intr_rx(adapter);
653
654 /* re-enable Interrupt */
655 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
656 return IRQ_HANDLED;
657 }
658
atl2_request_irq(struct atl2_adapter * adapter)659 static int atl2_request_irq(struct atl2_adapter *adapter)
660 {
661 struct net_device *netdev = adapter->netdev;
662 int flags, err = 0;
663
664 flags = IRQF_SHARED;
665 adapter->have_msi = true;
666 err = pci_enable_msi(adapter->pdev);
667 if (err)
668 adapter->have_msi = false;
669
670 if (adapter->have_msi)
671 flags &= ~IRQF_SHARED;
672
673 return request_irq(adapter->pdev->irq, atl2_intr, flags, netdev->name,
674 netdev);
675 }
676
677 /**
678 * atl2_free_ring_resources - Free Tx / RX descriptor Resources
679 * @adapter: board private structure
680 *
681 * Free all transmit software resources
682 */
atl2_free_ring_resources(struct atl2_adapter * adapter)683 static void atl2_free_ring_resources(struct atl2_adapter *adapter)
684 {
685 struct pci_dev *pdev = adapter->pdev;
686 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr,
687 adapter->ring_dma);
688 }
689
690 /**
691 * atl2_open - Called when a network interface is made active
692 * @netdev: network interface device structure
693 *
694 * Returns 0 on success, negative value on failure
695 *
696 * The open entry point is called when a network interface is made
697 * active by the system (IFF_UP). At this point all resources needed
698 * for transmit and receive operations are allocated, the interrupt
699 * handler is registered with the OS, the watchdog timer is started,
700 * and the stack is notified that the interface is ready.
701 */
atl2_open(struct net_device * netdev)702 static int atl2_open(struct net_device *netdev)
703 {
704 struct atl2_adapter *adapter = netdev_priv(netdev);
705 int err;
706 u32 val;
707
708 /* disallow open during test */
709 if (test_bit(__ATL2_TESTING, &adapter->flags))
710 return -EBUSY;
711
712 /* allocate transmit descriptors */
713 err = atl2_setup_ring_resources(adapter);
714 if (err)
715 return err;
716
717 err = atl2_init_hw(&adapter->hw);
718 if (err) {
719 err = -EIO;
720 goto err_init_hw;
721 }
722
723 /* hardware has been reset, we need to reload some things */
724 atl2_set_multi(netdev);
725 init_ring_ptrs(adapter);
726
727 atl2_restore_vlan(adapter);
728
729 if (atl2_configure(adapter)) {
730 err = -EIO;
731 goto err_config;
732 }
733
734 err = atl2_request_irq(adapter);
735 if (err)
736 goto err_req_irq;
737
738 clear_bit(__ATL2_DOWN, &adapter->flags);
739
740 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ));
741
742 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
743 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
744 val | MASTER_CTRL_MANUAL_INT);
745
746 atl2_irq_enable(adapter);
747
748 return 0;
749
750 err_init_hw:
751 err_req_irq:
752 err_config:
753 atl2_free_ring_resources(adapter);
754 atl2_reset_hw(&adapter->hw);
755
756 return err;
757 }
758
atl2_down(struct atl2_adapter * adapter)759 static void atl2_down(struct atl2_adapter *adapter)
760 {
761 struct net_device *netdev = adapter->netdev;
762
763 /* signal that we're down so the interrupt handler does not
764 * reschedule our watchdog timer */
765 set_bit(__ATL2_DOWN, &adapter->flags);
766
767 netif_tx_disable(netdev);
768
769 /* reset MAC to disable all RX/TX */
770 atl2_reset_hw(&adapter->hw);
771 msleep(1);
772
773 atl2_irq_disable(adapter);
774
775 del_timer_sync(&adapter->watchdog_timer);
776 del_timer_sync(&adapter->phy_config_timer);
777 clear_bit(0, &adapter->cfg_phy);
778
779 netif_carrier_off(netdev);
780 adapter->link_speed = SPEED_0;
781 adapter->link_duplex = -1;
782 }
783
atl2_free_irq(struct atl2_adapter * adapter)784 static void atl2_free_irq(struct atl2_adapter *adapter)
785 {
786 struct net_device *netdev = adapter->netdev;
787
788 free_irq(adapter->pdev->irq, netdev);
789
790 #ifdef CONFIG_PCI_MSI
791 if (adapter->have_msi)
792 pci_disable_msi(adapter->pdev);
793 #endif
794 }
795
796 /**
797 * atl2_close - Disables a network interface
798 * @netdev: network interface device structure
799 *
800 * Returns 0, this is not allowed to fail
801 *
802 * The close entry point is called when an interface is de-activated
803 * by the OS. The hardware is still under the drivers control, but
804 * needs to be disabled. A global MAC reset is issued to stop the
805 * hardware, and all transmit and receive resources are freed.
806 */
atl2_close(struct net_device * netdev)807 static int atl2_close(struct net_device *netdev)
808 {
809 struct atl2_adapter *adapter = netdev_priv(netdev);
810
811 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
812
813 atl2_down(adapter);
814 atl2_free_irq(adapter);
815 atl2_free_ring_resources(adapter);
816
817 return 0;
818 }
819
TxsFreeUnit(struct atl2_adapter * adapter)820 static inline int TxsFreeUnit(struct atl2_adapter *adapter)
821 {
822 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
823
824 return (adapter->txs_next_clear >= txs_write_ptr) ?
825 (int) (adapter->txs_ring_size - adapter->txs_next_clear +
826 txs_write_ptr - 1) :
827 (int) (txs_write_ptr - adapter->txs_next_clear - 1);
828 }
829
TxdFreeBytes(struct atl2_adapter * adapter)830 static inline int TxdFreeBytes(struct atl2_adapter *adapter)
831 {
832 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr);
833
834 return (adapter->txd_write_ptr >= txd_read_ptr) ?
835 (int) (adapter->txd_ring_size - adapter->txd_write_ptr +
836 txd_read_ptr - 1) :
837 (int) (txd_read_ptr - adapter->txd_write_ptr - 1);
838 }
839
atl2_xmit_frame(struct sk_buff * skb,struct net_device * netdev)840 static netdev_tx_t atl2_xmit_frame(struct sk_buff *skb,
841 struct net_device *netdev)
842 {
843 struct atl2_adapter *adapter = netdev_priv(netdev);
844 struct tx_pkt_header *txph;
845 u32 offset, copy_len;
846 int txs_unused;
847 int txbuf_unused;
848
849 if (test_bit(__ATL2_DOWN, &adapter->flags)) {
850 dev_kfree_skb_any(skb);
851 return NETDEV_TX_OK;
852 }
853
854 if (unlikely(skb->len <= 0)) {
855 dev_kfree_skb_any(skb);
856 return NETDEV_TX_OK;
857 }
858
859 txs_unused = TxsFreeUnit(adapter);
860 txbuf_unused = TxdFreeBytes(adapter);
861
862 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused ||
863 txs_unused < 1) {
864 /* not enough resources */
865 netif_stop_queue(netdev);
866 return NETDEV_TX_BUSY;
867 }
868
869 offset = adapter->txd_write_ptr;
870
871 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset);
872
873 *(u32 *)txph = 0;
874 txph->pkt_size = skb->len;
875
876 offset += 4;
877 if (offset >= adapter->txd_ring_size)
878 offset -= adapter->txd_ring_size;
879 copy_len = adapter->txd_ring_size - offset;
880 if (copy_len >= skb->len) {
881 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len);
882 offset += ((u32)(skb->len + 3) & ~3);
883 } else {
884 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len);
885 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len,
886 skb->len-copy_len);
887 offset = ((u32)(skb->len-copy_len + 3) & ~3);
888 }
889 #ifdef NETIF_F_HW_VLAN_CTAG_TX
890 if (skb_vlan_tag_present(skb)) {
891 u16 vlan_tag = skb_vlan_tag_get(skb);
892 vlan_tag = (vlan_tag << 4) |
893 (vlan_tag >> 13) |
894 ((vlan_tag >> 9) & 0x8);
895 txph->ins_vlan = 1;
896 txph->vlan = vlan_tag;
897 }
898 #endif
899 if (offset >= adapter->txd_ring_size)
900 offset -= adapter->txd_ring_size;
901 adapter->txd_write_ptr = offset;
902
903 /* clear txs before send */
904 adapter->txs_ring[adapter->txs_next_clear].update = 0;
905 if (++adapter->txs_next_clear == adapter->txs_ring_size)
906 adapter->txs_next_clear = 0;
907
908 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX,
909 (adapter->txd_write_ptr >> 2));
910
911 mmiowb();
912 dev_kfree_skb_any(skb);
913 return NETDEV_TX_OK;
914 }
915
916 /**
917 * atl2_change_mtu - Change the Maximum Transfer Unit
918 * @netdev: network interface device structure
919 * @new_mtu: new value for maximum frame size
920 *
921 * Returns 0 on success, negative on failure
922 */
atl2_change_mtu(struct net_device * netdev,int new_mtu)923 static int atl2_change_mtu(struct net_device *netdev, int new_mtu)
924 {
925 struct atl2_adapter *adapter = netdev_priv(netdev);
926 struct atl2_hw *hw = &adapter->hw;
927
928 /* set MTU */
929 netdev->mtu = new_mtu;
930 hw->max_frame_size = new_mtu;
931 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ETH_HLEN +
932 VLAN_HLEN + ETH_FCS_LEN);
933
934 return 0;
935 }
936
937 /**
938 * atl2_set_mac - Change the Ethernet Address of the NIC
939 * @netdev: network interface device structure
940 * @p: pointer to an address structure
941 *
942 * Returns 0 on success, negative on failure
943 */
atl2_set_mac(struct net_device * netdev,void * p)944 static int atl2_set_mac(struct net_device *netdev, void *p)
945 {
946 struct atl2_adapter *adapter = netdev_priv(netdev);
947 struct sockaddr *addr = p;
948
949 if (!is_valid_ether_addr(addr->sa_data))
950 return -EADDRNOTAVAIL;
951
952 if (netif_running(netdev))
953 return -EBUSY;
954
955 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
956 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
957
958 atl2_set_mac_addr(&adapter->hw);
959
960 return 0;
961 }
962
atl2_mii_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)963 static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
964 {
965 struct atl2_adapter *adapter = netdev_priv(netdev);
966 struct mii_ioctl_data *data = if_mii(ifr);
967 unsigned long flags;
968
969 switch (cmd) {
970 case SIOCGMIIPHY:
971 data->phy_id = 0;
972 break;
973 case SIOCGMIIREG:
974 spin_lock_irqsave(&adapter->stats_lock, flags);
975 if (atl2_read_phy_reg(&adapter->hw,
976 data->reg_num & 0x1F, &data->val_out)) {
977 spin_unlock_irqrestore(&adapter->stats_lock, flags);
978 return -EIO;
979 }
980 spin_unlock_irqrestore(&adapter->stats_lock, flags);
981 break;
982 case SIOCSMIIREG:
983 if (data->reg_num & ~(0x1F))
984 return -EFAULT;
985 spin_lock_irqsave(&adapter->stats_lock, flags);
986 if (atl2_write_phy_reg(&adapter->hw, data->reg_num,
987 data->val_in)) {
988 spin_unlock_irqrestore(&adapter->stats_lock, flags);
989 return -EIO;
990 }
991 spin_unlock_irqrestore(&adapter->stats_lock, flags);
992 break;
993 default:
994 return -EOPNOTSUPP;
995 }
996 return 0;
997 }
998
atl2_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)999 static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1000 {
1001 switch (cmd) {
1002 case SIOCGMIIPHY:
1003 case SIOCGMIIREG:
1004 case SIOCSMIIREG:
1005 return atl2_mii_ioctl(netdev, ifr, cmd);
1006 #ifdef ETHTOOL_OPS_COMPAT
1007 case SIOCETHTOOL:
1008 return ethtool_ioctl(ifr);
1009 #endif
1010 default:
1011 return -EOPNOTSUPP;
1012 }
1013 }
1014
1015 /**
1016 * atl2_tx_timeout - Respond to a Tx Hang
1017 * @netdev: network interface device structure
1018 */
atl2_tx_timeout(struct net_device * netdev)1019 static void atl2_tx_timeout(struct net_device *netdev)
1020 {
1021 struct atl2_adapter *adapter = netdev_priv(netdev);
1022
1023 /* Do the reset outside of interrupt context */
1024 schedule_work(&adapter->reset_task);
1025 }
1026
1027 /**
1028 * atl2_watchdog - Timer Call-back
1029 * @data: pointer to netdev cast into an unsigned long
1030 */
atl2_watchdog(unsigned long data)1031 static void atl2_watchdog(unsigned long data)
1032 {
1033 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1034
1035 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1036 u32 drop_rxd, drop_rxs;
1037 unsigned long flags;
1038
1039 spin_lock_irqsave(&adapter->stats_lock, flags);
1040 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV);
1041 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV);
1042 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1043
1044 adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs;
1045
1046 /* Reset the timer */
1047 mod_timer(&adapter->watchdog_timer,
1048 round_jiffies(jiffies + 4 * HZ));
1049 }
1050 }
1051
1052 /**
1053 * atl2_phy_config - Timer Call-back
1054 * @data: pointer to netdev cast into an unsigned long
1055 */
atl2_phy_config(unsigned long data)1056 static void atl2_phy_config(unsigned long data)
1057 {
1058 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1059 struct atl2_hw *hw = &adapter->hw;
1060 unsigned long flags;
1061
1062 spin_lock_irqsave(&adapter->stats_lock, flags);
1063 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1064 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN |
1065 MII_CR_RESTART_AUTO_NEG);
1066 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1067 clear_bit(0, &adapter->cfg_phy);
1068 }
1069
atl2_up(struct atl2_adapter * adapter)1070 static int atl2_up(struct atl2_adapter *adapter)
1071 {
1072 struct net_device *netdev = adapter->netdev;
1073 int err = 0;
1074 u32 val;
1075
1076 /* hardware has been reset, we need to reload some things */
1077
1078 err = atl2_init_hw(&adapter->hw);
1079 if (err) {
1080 err = -EIO;
1081 return err;
1082 }
1083
1084 atl2_set_multi(netdev);
1085 init_ring_ptrs(adapter);
1086
1087 atl2_restore_vlan(adapter);
1088
1089 if (atl2_configure(adapter)) {
1090 err = -EIO;
1091 goto err_up;
1092 }
1093
1094 clear_bit(__ATL2_DOWN, &adapter->flags);
1095
1096 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1097 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |
1098 MASTER_CTRL_MANUAL_INT);
1099
1100 atl2_irq_enable(adapter);
1101
1102 err_up:
1103 return err;
1104 }
1105
atl2_reinit_locked(struct atl2_adapter * adapter)1106 static void atl2_reinit_locked(struct atl2_adapter *adapter)
1107 {
1108 WARN_ON(in_interrupt());
1109 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1110 msleep(1);
1111 atl2_down(adapter);
1112 atl2_up(adapter);
1113 clear_bit(__ATL2_RESETTING, &adapter->flags);
1114 }
1115
atl2_reset_task(struct work_struct * work)1116 static void atl2_reset_task(struct work_struct *work)
1117 {
1118 struct atl2_adapter *adapter;
1119 adapter = container_of(work, struct atl2_adapter, reset_task);
1120
1121 atl2_reinit_locked(adapter);
1122 }
1123
atl2_setup_mac_ctrl(struct atl2_adapter * adapter)1124 static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter)
1125 {
1126 u32 value;
1127 struct atl2_hw *hw = &adapter->hw;
1128 struct net_device *netdev = adapter->netdev;
1129
1130 /* Config MAC CTRL Register */
1131 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1132
1133 /* duplex */
1134 if (FULL_DUPLEX == adapter->link_duplex)
1135 value |= MAC_CTRL_DUPLX;
1136
1137 /* flow control */
1138 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1139
1140 /* PAD & CRC */
1141 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1142
1143 /* preamble length */
1144 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1145 MAC_CTRL_PRMLEN_SHIFT);
1146
1147 /* vlan */
1148 __atl2_vlan_mode(netdev->features, &value);
1149
1150 /* filter mode */
1151 value |= MAC_CTRL_BC_EN;
1152 if (netdev->flags & IFF_PROMISC)
1153 value |= MAC_CTRL_PROMIS_EN;
1154 else if (netdev->flags & IFF_ALLMULTI)
1155 value |= MAC_CTRL_MC_ALL_EN;
1156
1157 /* half retry buffer */
1158 value |= (((u32)(adapter->hw.retry_buf &
1159 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1160
1161 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1162 }
1163
atl2_check_link(struct atl2_adapter * adapter)1164 static int atl2_check_link(struct atl2_adapter *adapter)
1165 {
1166 struct atl2_hw *hw = &adapter->hw;
1167 struct net_device *netdev = adapter->netdev;
1168 int ret_val;
1169 u16 speed, duplex, phy_data;
1170 int reconfig = 0;
1171
1172 /* MII_BMSR must read twise */
1173 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1174 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1175 if (!(phy_data&BMSR_LSTATUS)) { /* link down */
1176 if (netif_carrier_ok(netdev)) { /* old link state: Up */
1177 u32 value;
1178 /* disable rx */
1179 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1180 value &= ~MAC_CTRL_RX_EN;
1181 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1182 adapter->link_speed = SPEED_0;
1183 netif_carrier_off(netdev);
1184 netif_stop_queue(netdev);
1185 }
1186 return 0;
1187 }
1188
1189 /* Link Up */
1190 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1191 if (ret_val)
1192 return ret_val;
1193 switch (hw->MediaType) {
1194 case MEDIA_TYPE_100M_FULL:
1195 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1196 reconfig = 1;
1197 break;
1198 case MEDIA_TYPE_100M_HALF:
1199 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1200 reconfig = 1;
1201 break;
1202 case MEDIA_TYPE_10M_FULL:
1203 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1204 reconfig = 1;
1205 break;
1206 case MEDIA_TYPE_10M_HALF:
1207 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1208 reconfig = 1;
1209 break;
1210 }
1211 /* link result is our setting */
1212 if (reconfig == 0) {
1213 if (adapter->link_speed != speed ||
1214 adapter->link_duplex != duplex) {
1215 adapter->link_speed = speed;
1216 adapter->link_duplex = duplex;
1217 atl2_setup_mac_ctrl(adapter);
1218 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n",
1219 atl2_driver_name, netdev->name,
1220 adapter->link_speed,
1221 adapter->link_duplex == FULL_DUPLEX ?
1222 "Full Duplex" : "Half Duplex");
1223 }
1224
1225 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
1226 netif_carrier_on(netdev);
1227 netif_wake_queue(netdev);
1228 }
1229 return 0;
1230 }
1231
1232 /* change original link status */
1233 if (netif_carrier_ok(netdev)) {
1234 u32 value;
1235 /* disable rx */
1236 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1237 value &= ~MAC_CTRL_RX_EN;
1238 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1239
1240 adapter->link_speed = SPEED_0;
1241 netif_carrier_off(netdev);
1242 netif_stop_queue(netdev);
1243 }
1244
1245 /* auto-neg, insert timer to re-config phy
1246 * (if interval smaller than 5 seconds, something strange) */
1247 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1248 if (!test_and_set_bit(0, &adapter->cfg_phy))
1249 mod_timer(&adapter->phy_config_timer,
1250 round_jiffies(jiffies + 5 * HZ));
1251 }
1252
1253 return 0;
1254 }
1255
1256 /**
1257 * atl2_link_chg_task - deal with link change event Out of interrupt context
1258 */
atl2_link_chg_task(struct work_struct * work)1259 static void atl2_link_chg_task(struct work_struct *work)
1260 {
1261 struct atl2_adapter *adapter;
1262 unsigned long flags;
1263
1264 adapter = container_of(work, struct atl2_adapter, link_chg_task);
1265
1266 spin_lock_irqsave(&adapter->stats_lock, flags);
1267 atl2_check_link(adapter);
1268 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1269 }
1270
atl2_setup_pcicmd(struct pci_dev * pdev)1271 static void atl2_setup_pcicmd(struct pci_dev *pdev)
1272 {
1273 u16 cmd;
1274
1275 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1276
1277 if (cmd & PCI_COMMAND_INTX_DISABLE)
1278 cmd &= ~PCI_COMMAND_INTX_DISABLE;
1279 if (cmd & PCI_COMMAND_IO)
1280 cmd &= ~PCI_COMMAND_IO;
1281 if (0 == (cmd & PCI_COMMAND_MEMORY))
1282 cmd |= PCI_COMMAND_MEMORY;
1283 if (0 == (cmd & PCI_COMMAND_MASTER))
1284 cmd |= PCI_COMMAND_MASTER;
1285 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1286
1287 /*
1288 * some motherboards BIOS(PXE/EFI) driver may set PME
1289 * while they transfer control to OS (Windows/Linux)
1290 * so we should clear this bit before NIC work normally
1291 */
1292 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
1293 }
1294
1295 #ifdef CONFIG_NET_POLL_CONTROLLER
atl2_poll_controller(struct net_device * netdev)1296 static void atl2_poll_controller(struct net_device *netdev)
1297 {
1298 disable_irq(netdev->irq);
1299 atl2_intr(netdev->irq, netdev);
1300 enable_irq(netdev->irq);
1301 }
1302 #endif
1303
1304
1305 static const struct net_device_ops atl2_netdev_ops = {
1306 .ndo_open = atl2_open,
1307 .ndo_stop = atl2_close,
1308 .ndo_start_xmit = atl2_xmit_frame,
1309 .ndo_set_rx_mode = atl2_set_multi,
1310 .ndo_validate_addr = eth_validate_addr,
1311 .ndo_set_mac_address = atl2_set_mac,
1312 .ndo_change_mtu = atl2_change_mtu,
1313 .ndo_fix_features = atl2_fix_features,
1314 .ndo_set_features = atl2_set_features,
1315 .ndo_do_ioctl = atl2_ioctl,
1316 .ndo_tx_timeout = atl2_tx_timeout,
1317 #ifdef CONFIG_NET_POLL_CONTROLLER
1318 .ndo_poll_controller = atl2_poll_controller,
1319 #endif
1320 };
1321
1322 /**
1323 * atl2_probe - Device Initialization Routine
1324 * @pdev: PCI device information struct
1325 * @ent: entry in atl2_pci_tbl
1326 *
1327 * Returns 0 on success, negative on failure
1328 *
1329 * atl2_probe initializes an adapter identified by a pci_dev structure.
1330 * The OS initialization, configuring of the adapter private structure,
1331 * and a hardware reset occur.
1332 */
atl2_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1333 static int atl2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1334 {
1335 struct net_device *netdev;
1336 struct atl2_adapter *adapter;
1337 static int cards_found = 0;
1338 unsigned long mmio_start;
1339 int mmio_len;
1340 int err;
1341
1342 err = pci_enable_device(pdev);
1343 if (err)
1344 return err;
1345
1346 /*
1347 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA
1348 * until the kernel has the proper infrastructure to support 64-bit DMA
1349 * on these devices.
1350 */
1351 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) &&
1352 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1353 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n");
1354 err = -EIO;
1355 goto err_dma;
1356 }
1357
1358 /* Mark all PCI regions associated with PCI device
1359 * pdev as being reserved by owner atl2_driver_name */
1360 err = pci_request_regions(pdev, atl2_driver_name);
1361 if (err)
1362 goto err_pci_reg;
1363
1364 /* Enables bus-mastering on the device and calls
1365 * pcibios_set_master to do the needed arch specific settings */
1366 pci_set_master(pdev);
1367
1368 netdev = alloc_etherdev(sizeof(struct atl2_adapter));
1369 if (!netdev) {
1370 err = -ENOMEM;
1371 goto err_alloc_etherdev;
1372 }
1373
1374 SET_NETDEV_DEV(netdev, &pdev->dev);
1375
1376 pci_set_drvdata(pdev, netdev);
1377 adapter = netdev_priv(netdev);
1378 adapter->netdev = netdev;
1379 adapter->pdev = pdev;
1380 adapter->hw.back = adapter;
1381
1382 mmio_start = pci_resource_start(pdev, 0x0);
1383 mmio_len = pci_resource_len(pdev, 0x0);
1384
1385 adapter->hw.mem_rang = (u32)mmio_len;
1386 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1387 if (!adapter->hw.hw_addr) {
1388 err = -EIO;
1389 goto err_ioremap;
1390 }
1391
1392 atl2_setup_pcicmd(pdev);
1393
1394 netdev->netdev_ops = &atl2_netdev_ops;
1395 netdev->ethtool_ops = &atl2_ethtool_ops;
1396 netdev->watchdog_timeo = 5 * HZ;
1397 netdev->min_mtu = 40;
1398 netdev->max_mtu = ETH_DATA_LEN + VLAN_HLEN;
1399 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1400
1401 netdev->mem_start = mmio_start;
1402 netdev->mem_end = mmio_start + mmio_len;
1403 adapter->bd_number = cards_found;
1404 adapter->pci_using_64 = false;
1405
1406 /* setup the private structure */
1407 err = atl2_sw_init(adapter);
1408 if (err)
1409 goto err_sw_init;
1410
1411 netdev->hw_features = NETIF_F_HW_VLAN_CTAG_RX;
1412 netdev->features |= (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1413
1414 /* Init PHY as early as possible due to power saving issue */
1415 atl2_phy_init(&adapter->hw);
1416
1417 /* reset the controller to
1418 * put the device in a known good starting state */
1419
1420 if (atl2_reset_hw(&adapter->hw)) {
1421 err = -EIO;
1422 goto err_reset;
1423 }
1424
1425 /* copy the MAC address out of the EEPROM */
1426 atl2_read_mac_addr(&adapter->hw);
1427 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
1428 if (!is_valid_ether_addr(netdev->dev_addr)) {
1429 err = -EIO;
1430 goto err_eeprom;
1431 }
1432
1433 atl2_check_options(adapter);
1434
1435 setup_timer(&adapter->watchdog_timer, atl2_watchdog,
1436 (unsigned long)adapter);
1437
1438 setup_timer(&adapter->phy_config_timer, atl2_phy_config,
1439 (unsigned long)adapter);
1440
1441 INIT_WORK(&adapter->reset_task, atl2_reset_task);
1442 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task);
1443
1444 strcpy(netdev->name, "eth%d"); /* ?? */
1445 err = register_netdev(netdev);
1446 if (err)
1447 goto err_register;
1448
1449 /* assume we have no link for now */
1450 netif_carrier_off(netdev);
1451 netif_stop_queue(netdev);
1452
1453 cards_found++;
1454
1455 return 0;
1456
1457 err_reset:
1458 err_register:
1459 err_sw_init:
1460 err_eeprom:
1461 iounmap(adapter->hw.hw_addr);
1462 err_ioremap:
1463 free_netdev(netdev);
1464 err_alloc_etherdev:
1465 pci_release_regions(pdev);
1466 err_pci_reg:
1467 err_dma:
1468 pci_disable_device(pdev);
1469 return err;
1470 }
1471
1472 /**
1473 * atl2_remove - Device Removal Routine
1474 * @pdev: PCI device information struct
1475 *
1476 * atl2_remove is called by the PCI subsystem to alert the driver
1477 * that it should release a PCI device. The could be caused by a
1478 * Hot-Plug event, or because the driver is going to be removed from
1479 * memory.
1480 */
1481 /* FIXME: write the original MAC address back in case it was changed from a
1482 * BIOS-set value, as in atl1 -- CHS */
atl2_remove(struct pci_dev * pdev)1483 static void atl2_remove(struct pci_dev *pdev)
1484 {
1485 struct net_device *netdev = pci_get_drvdata(pdev);
1486 struct atl2_adapter *adapter = netdev_priv(netdev);
1487
1488 /* flush_scheduled work may reschedule our watchdog task, so
1489 * explicitly disable watchdog tasks from being rescheduled */
1490 set_bit(__ATL2_DOWN, &adapter->flags);
1491
1492 del_timer_sync(&adapter->watchdog_timer);
1493 del_timer_sync(&adapter->phy_config_timer);
1494 cancel_work_sync(&adapter->reset_task);
1495 cancel_work_sync(&adapter->link_chg_task);
1496
1497 unregister_netdev(netdev);
1498
1499 atl2_force_ps(&adapter->hw);
1500
1501 iounmap(adapter->hw.hw_addr);
1502 pci_release_regions(pdev);
1503
1504 free_netdev(netdev);
1505
1506 pci_disable_device(pdev);
1507 }
1508
atl2_suspend(struct pci_dev * pdev,pm_message_t state)1509 static int atl2_suspend(struct pci_dev *pdev, pm_message_t state)
1510 {
1511 struct net_device *netdev = pci_get_drvdata(pdev);
1512 struct atl2_adapter *adapter = netdev_priv(netdev);
1513 struct atl2_hw *hw = &adapter->hw;
1514 u16 speed, duplex;
1515 u32 ctrl = 0;
1516 u32 wufc = adapter->wol;
1517
1518 #ifdef CONFIG_PM
1519 int retval = 0;
1520 #endif
1521
1522 netif_device_detach(netdev);
1523
1524 if (netif_running(netdev)) {
1525 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
1526 atl2_down(adapter);
1527 }
1528
1529 #ifdef CONFIG_PM
1530 retval = pci_save_state(pdev);
1531 if (retval)
1532 return retval;
1533 #endif
1534
1535 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1536 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1537 if (ctrl & BMSR_LSTATUS)
1538 wufc &= ~ATLX_WUFC_LNKC;
1539
1540 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {
1541 u32 ret_val;
1542 /* get current link speed & duplex */
1543 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1544 if (ret_val) {
1545 printk(KERN_DEBUG
1546 "%s: get speed&duplex error while suspend\n",
1547 atl2_driver_name);
1548 goto wol_dis;
1549 }
1550
1551 ctrl = 0;
1552
1553 /* turn on magic packet wol */
1554 if (wufc & ATLX_WUFC_MAG)
1555 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
1556
1557 /* ignore Link Chg event when Link is up */
1558 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1559
1560 /* Config MAC CTRL Register */
1561 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1562 if (FULL_DUPLEX == adapter->link_duplex)
1563 ctrl |= MAC_CTRL_DUPLX;
1564 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1565 ctrl |= (((u32)adapter->hw.preamble_len &
1566 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1567 ctrl |= (((u32)(adapter->hw.retry_buf &
1568 MAC_CTRL_HALF_LEFT_BUF_MASK)) <<
1569 MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1570 if (wufc & ATLX_WUFC_MAG) {
1571 /* magic packet maybe Broadcast&multicast&Unicast */
1572 ctrl |= MAC_CTRL_BC_EN;
1573 }
1574
1575 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);
1576
1577 /* pcie patch */
1578 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1579 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1580 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1581 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1582 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1583 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1584
1585 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1586 goto suspend_exit;
1587 }
1588
1589 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) {
1590 /* link is down, so only LINK CHG WOL event enable */
1591 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
1592 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1593 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);
1594
1595 /* pcie patch */
1596 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1597 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1598 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1599 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1600 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1601 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1602
1603 hw->phy_configured = false; /* re-init PHY when resume */
1604
1605 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1606
1607 goto suspend_exit;
1608 }
1609
1610 wol_dis:
1611 /* WOL disabled */
1612 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);
1613
1614 /* pcie patch */
1615 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1616 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1617 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1618 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1619 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1620 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1621
1622 atl2_force_ps(hw);
1623 hw->phy_configured = false; /* re-init PHY when resume */
1624
1625 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1626
1627 suspend_exit:
1628 if (netif_running(netdev))
1629 atl2_free_irq(adapter);
1630
1631 pci_disable_device(pdev);
1632
1633 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1634
1635 return 0;
1636 }
1637
1638 #ifdef CONFIG_PM
atl2_resume(struct pci_dev * pdev)1639 static int atl2_resume(struct pci_dev *pdev)
1640 {
1641 struct net_device *netdev = pci_get_drvdata(pdev);
1642 struct atl2_adapter *adapter = netdev_priv(netdev);
1643 u32 err;
1644
1645 pci_set_power_state(pdev, PCI_D0);
1646 pci_restore_state(pdev);
1647
1648 err = pci_enable_device(pdev);
1649 if (err) {
1650 printk(KERN_ERR
1651 "atl2: Cannot enable PCI device from suspend\n");
1652 return err;
1653 }
1654
1655 pci_set_master(pdev);
1656
1657 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
1658
1659 pci_enable_wake(pdev, PCI_D3hot, 0);
1660 pci_enable_wake(pdev, PCI_D3cold, 0);
1661
1662 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
1663
1664 if (netif_running(netdev)) {
1665 err = atl2_request_irq(adapter);
1666 if (err)
1667 return err;
1668 }
1669
1670 atl2_reset_hw(&adapter->hw);
1671
1672 if (netif_running(netdev))
1673 atl2_up(adapter);
1674
1675 netif_device_attach(netdev);
1676
1677 return 0;
1678 }
1679 #endif
1680
atl2_shutdown(struct pci_dev * pdev)1681 static void atl2_shutdown(struct pci_dev *pdev)
1682 {
1683 atl2_suspend(pdev, PMSG_SUSPEND);
1684 }
1685
1686 static struct pci_driver atl2_driver = {
1687 .name = atl2_driver_name,
1688 .id_table = atl2_pci_tbl,
1689 .probe = atl2_probe,
1690 .remove = atl2_remove,
1691 /* Power Management Hooks */
1692 .suspend = atl2_suspend,
1693 #ifdef CONFIG_PM
1694 .resume = atl2_resume,
1695 #endif
1696 .shutdown = atl2_shutdown,
1697 };
1698
1699 /**
1700 * atl2_init_module - Driver Registration Routine
1701 *
1702 * atl2_init_module is the first routine called when the driver is
1703 * loaded. All it does is register with the PCI subsystem.
1704 */
atl2_init_module(void)1705 static int __init atl2_init_module(void)
1706 {
1707 printk(KERN_INFO "%s - version %s\n", atl2_driver_string,
1708 atl2_driver_version);
1709 printk(KERN_INFO "%s\n", atl2_copyright);
1710 return pci_register_driver(&atl2_driver);
1711 }
1712 module_init(atl2_init_module);
1713
1714 /**
1715 * atl2_exit_module - Driver Exit Cleanup Routine
1716 *
1717 * atl2_exit_module is called just before the driver is removed
1718 * from memory.
1719 */
atl2_exit_module(void)1720 static void __exit atl2_exit_module(void)
1721 {
1722 pci_unregister_driver(&atl2_driver);
1723 }
1724 module_exit(atl2_exit_module);
1725
atl2_read_pci_cfg(struct atl2_hw * hw,u32 reg,u16 * value)1726 static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1727 {
1728 struct atl2_adapter *adapter = hw->back;
1729 pci_read_config_word(adapter->pdev, reg, value);
1730 }
1731
atl2_write_pci_cfg(struct atl2_hw * hw,u32 reg,u16 * value)1732 static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1733 {
1734 struct atl2_adapter *adapter = hw->back;
1735 pci_write_config_word(adapter->pdev, reg, *value);
1736 }
1737
atl2_get_link_ksettings(struct net_device * netdev,struct ethtool_link_ksettings * cmd)1738 static int atl2_get_link_ksettings(struct net_device *netdev,
1739 struct ethtool_link_ksettings *cmd)
1740 {
1741 struct atl2_adapter *adapter = netdev_priv(netdev);
1742 struct atl2_hw *hw = &adapter->hw;
1743 u32 supported, advertising;
1744
1745 supported = (SUPPORTED_10baseT_Half |
1746 SUPPORTED_10baseT_Full |
1747 SUPPORTED_100baseT_Half |
1748 SUPPORTED_100baseT_Full |
1749 SUPPORTED_Autoneg |
1750 SUPPORTED_TP);
1751 advertising = ADVERTISED_TP;
1752
1753 advertising |= ADVERTISED_Autoneg;
1754 advertising |= hw->autoneg_advertised;
1755
1756 cmd->base.port = PORT_TP;
1757 cmd->base.phy_address = 0;
1758
1759 if (adapter->link_speed != SPEED_0) {
1760 cmd->base.speed = adapter->link_speed;
1761 if (adapter->link_duplex == FULL_DUPLEX)
1762 cmd->base.duplex = DUPLEX_FULL;
1763 else
1764 cmd->base.duplex = DUPLEX_HALF;
1765 } else {
1766 cmd->base.speed = SPEED_UNKNOWN;
1767 cmd->base.duplex = DUPLEX_UNKNOWN;
1768 }
1769
1770 cmd->base.autoneg = AUTONEG_ENABLE;
1771
1772 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1773 supported);
1774 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1775 advertising);
1776
1777 return 0;
1778 }
1779
atl2_set_link_ksettings(struct net_device * netdev,const struct ethtool_link_ksettings * cmd)1780 static int atl2_set_link_ksettings(struct net_device *netdev,
1781 const struct ethtool_link_ksettings *cmd)
1782 {
1783 struct atl2_adapter *adapter = netdev_priv(netdev);
1784 struct atl2_hw *hw = &adapter->hw;
1785 u32 advertising;
1786
1787 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1788 cmd->link_modes.advertising);
1789
1790 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1791 msleep(1);
1792
1793 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1794 #define MY_ADV_MASK (ADVERTISE_10_HALF | \
1795 ADVERTISE_10_FULL | \
1796 ADVERTISE_100_HALF| \
1797 ADVERTISE_100_FULL)
1798
1799 if ((advertising & MY_ADV_MASK) == MY_ADV_MASK) {
1800 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR;
1801 hw->autoneg_advertised = MY_ADV_MASK;
1802 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_100_FULL) {
1803 hw->MediaType = MEDIA_TYPE_100M_FULL;
1804 hw->autoneg_advertised = ADVERTISE_100_FULL;
1805 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_100_HALF) {
1806 hw->MediaType = MEDIA_TYPE_100M_HALF;
1807 hw->autoneg_advertised = ADVERTISE_100_HALF;
1808 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_10_FULL) {
1809 hw->MediaType = MEDIA_TYPE_10M_FULL;
1810 hw->autoneg_advertised = ADVERTISE_10_FULL;
1811 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_10_HALF) {
1812 hw->MediaType = MEDIA_TYPE_10M_HALF;
1813 hw->autoneg_advertised = ADVERTISE_10_HALF;
1814 } else {
1815 clear_bit(__ATL2_RESETTING, &adapter->flags);
1816 return -EINVAL;
1817 }
1818 advertising = hw->autoneg_advertised |
1819 ADVERTISED_TP | ADVERTISED_Autoneg;
1820 } else {
1821 clear_bit(__ATL2_RESETTING, &adapter->flags);
1822 return -EINVAL;
1823 }
1824
1825 /* reset the link */
1826 if (netif_running(adapter->netdev)) {
1827 atl2_down(adapter);
1828 atl2_up(adapter);
1829 } else
1830 atl2_reset_hw(&adapter->hw);
1831
1832 clear_bit(__ATL2_RESETTING, &adapter->flags);
1833 return 0;
1834 }
1835
atl2_get_msglevel(struct net_device * netdev)1836 static u32 atl2_get_msglevel(struct net_device *netdev)
1837 {
1838 return 0;
1839 }
1840
1841 /*
1842 * It's sane for this to be empty, but we might want to take advantage of this.
1843 */
atl2_set_msglevel(struct net_device * netdev,u32 data)1844 static void atl2_set_msglevel(struct net_device *netdev, u32 data)
1845 {
1846 }
1847
atl2_get_regs_len(struct net_device * netdev)1848 static int atl2_get_regs_len(struct net_device *netdev)
1849 {
1850 #define ATL2_REGS_LEN 42
1851 return sizeof(u32) * ATL2_REGS_LEN;
1852 }
1853
atl2_get_regs(struct net_device * netdev,struct ethtool_regs * regs,void * p)1854 static void atl2_get_regs(struct net_device *netdev,
1855 struct ethtool_regs *regs, void *p)
1856 {
1857 struct atl2_adapter *adapter = netdev_priv(netdev);
1858 struct atl2_hw *hw = &adapter->hw;
1859 u32 *regs_buff = p;
1860 u16 phy_data;
1861
1862 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN);
1863
1864 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
1865
1866 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP);
1867 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
1868 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG);
1869 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL);
1870 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
1871 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL);
1872 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT);
1873 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
1874 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE);
1875 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER);
1876 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS);
1877 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL);
1878 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK);
1879 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL);
1880 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG);
1881 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
1882 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4);
1883 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE);
1884 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4);
1885 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
1886 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU);
1887 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);
1888 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END);
1889 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI);
1890 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO);
1891 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE);
1892 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO);
1893 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE);
1894 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO);
1895 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM);
1896 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR);
1897 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH);
1898 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW);
1899 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH);
1900 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH);
1901 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX);
1902 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX);
1903 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR);
1904 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR);
1905
1906 atl2_read_phy_reg(hw, MII_BMCR, &phy_data);
1907 regs_buff[40] = (u32)phy_data;
1908 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1909 regs_buff[41] = (u32)phy_data;
1910 }
1911
atl2_get_eeprom_len(struct net_device * netdev)1912 static int atl2_get_eeprom_len(struct net_device *netdev)
1913 {
1914 struct atl2_adapter *adapter = netdev_priv(netdev);
1915
1916 if (!atl2_check_eeprom_exist(&adapter->hw))
1917 return 512;
1918 else
1919 return 0;
1920 }
1921
atl2_get_eeprom(struct net_device * netdev,struct ethtool_eeprom * eeprom,u8 * bytes)1922 static int atl2_get_eeprom(struct net_device *netdev,
1923 struct ethtool_eeprom *eeprom, u8 *bytes)
1924 {
1925 struct atl2_adapter *adapter = netdev_priv(netdev);
1926 struct atl2_hw *hw = &adapter->hw;
1927 u32 *eeprom_buff;
1928 int first_dword, last_dword;
1929 int ret_val = 0;
1930 int i;
1931
1932 if (eeprom->len == 0)
1933 return -EINVAL;
1934
1935 if (atl2_check_eeprom_exist(hw))
1936 return -EINVAL;
1937
1938 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1939
1940 first_dword = eeprom->offset >> 2;
1941 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1942
1943 eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1),
1944 GFP_KERNEL);
1945 if (!eeprom_buff)
1946 return -ENOMEM;
1947
1948 for (i = first_dword; i < last_dword; i++) {
1949 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) {
1950 ret_val = -EIO;
1951 goto free;
1952 }
1953 }
1954
1955 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
1956 eeprom->len);
1957 free:
1958 kfree(eeprom_buff);
1959
1960 return ret_val;
1961 }
1962
atl2_set_eeprom(struct net_device * netdev,struct ethtool_eeprom * eeprom,u8 * bytes)1963 static int atl2_set_eeprom(struct net_device *netdev,
1964 struct ethtool_eeprom *eeprom, u8 *bytes)
1965 {
1966 struct atl2_adapter *adapter = netdev_priv(netdev);
1967 struct atl2_hw *hw = &adapter->hw;
1968 u32 *eeprom_buff;
1969 u32 *ptr;
1970 int max_len, first_dword, last_dword, ret_val = 0;
1971 int i;
1972
1973 if (eeprom->len == 0)
1974 return -EOPNOTSUPP;
1975
1976 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
1977 return -EFAULT;
1978
1979 max_len = 512;
1980
1981 first_dword = eeprom->offset >> 2;
1982 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1983 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
1984 if (!eeprom_buff)
1985 return -ENOMEM;
1986
1987 ptr = eeprom_buff;
1988
1989 if (eeprom->offset & 3) {
1990 /* need read/modify/write of first changed EEPROM word */
1991 /* only the second byte of the word is being modified */
1992 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0]))) {
1993 ret_val = -EIO;
1994 goto out;
1995 }
1996 ptr++;
1997 }
1998 if (((eeprom->offset + eeprom->len) & 3)) {
1999 /*
2000 * need read/modify/write of last changed EEPROM word
2001 * only the first byte of the word is being modified
2002 */
2003 if (!atl2_read_eeprom(hw, last_dword * 4,
2004 &(eeprom_buff[last_dword - first_dword]))) {
2005 ret_val = -EIO;
2006 goto out;
2007 }
2008 }
2009
2010 /* Device's eeprom is always little-endian, word addressable */
2011 memcpy(ptr, bytes, eeprom->len);
2012
2013 for (i = 0; i < last_dword - first_dword + 1; i++) {
2014 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i])) {
2015 ret_val = -EIO;
2016 goto out;
2017 }
2018 }
2019 out:
2020 kfree(eeprom_buff);
2021 return ret_val;
2022 }
2023
atl2_get_drvinfo(struct net_device * netdev,struct ethtool_drvinfo * drvinfo)2024 static void atl2_get_drvinfo(struct net_device *netdev,
2025 struct ethtool_drvinfo *drvinfo)
2026 {
2027 struct atl2_adapter *adapter = netdev_priv(netdev);
2028
2029 strlcpy(drvinfo->driver, atl2_driver_name, sizeof(drvinfo->driver));
2030 strlcpy(drvinfo->version, atl2_driver_version,
2031 sizeof(drvinfo->version));
2032 strlcpy(drvinfo->fw_version, "L2", sizeof(drvinfo->fw_version));
2033 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
2034 sizeof(drvinfo->bus_info));
2035 }
2036
atl2_get_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)2037 static void atl2_get_wol(struct net_device *netdev,
2038 struct ethtool_wolinfo *wol)
2039 {
2040 struct atl2_adapter *adapter = netdev_priv(netdev);
2041
2042 wol->supported = WAKE_MAGIC;
2043 wol->wolopts = 0;
2044
2045 if (adapter->wol & ATLX_WUFC_EX)
2046 wol->wolopts |= WAKE_UCAST;
2047 if (adapter->wol & ATLX_WUFC_MC)
2048 wol->wolopts |= WAKE_MCAST;
2049 if (adapter->wol & ATLX_WUFC_BC)
2050 wol->wolopts |= WAKE_BCAST;
2051 if (adapter->wol & ATLX_WUFC_MAG)
2052 wol->wolopts |= WAKE_MAGIC;
2053 if (adapter->wol & ATLX_WUFC_LNKC)
2054 wol->wolopts |= WAKE_PHY;
2055 }
2056
atl2_set_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)2057 static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2058 {
2059 struct atl2_adapter *adapter = netdev_priv(netdev);
2060
2061 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2062 return -EOPNOTSUPP;
2063
2064 if (wol->wolopts & (WAKE_UCAST | WAKE_BCAST | WAKE_MCAST))
2065 return -EOPNOTSUPP;
2066
2067 /* these settings will always override what we currently have */
2068 adapter->wol = 0;
2069
2070 if (wol->wolopts & WAKE_MAGIC)
2071 adapter->wol |= ATLX_WUFC_MAG;
2072 if (wol->wolopts & WAKE_PHY)
2073 adapter->wol |= ATLX_WUFC_LNKC;
2074
2075 return 0;
2076 }
2077
atl2_nway_reset(struct net_device * netdev)2078 static int atl2_nway_reset(struct net_device *netdev)
2079 {
2080 struct atl2_adapter *adapter = netdev_priv(netdev);
2081 if (netif_running(netdev))
2082 atl2_reinit_locked(adapter);
2083 return 0;
2084 }
2085
2086 static const struct ethtool_ops atl2_ethtool_ops = {
2087 .get_drvinfo = atl2_get_drvinfo,
2088 .get_regs_len = atl2_get_regs_len,
2089 .get_regs = atl2_get_regs,
2090 .get_wol = atl2_get_wol,
2091 .set_wol = atl2_set_wol,
2092 .get_msglevel = atl2_get_msglevel,
2093 .set_msglevel = atl2_set_msglevel,
2094 .nway_reset = atl2_nway_reset,
2095 .get_link = ethtool_op_get_link,
2096 .get_eeprom_len = atl2_get_eeprom_len,
2097 .get_eeprom = atl2_get_eeprom,
2098 .set_eeprom = atl2_set_eeprom,
2099 .get_link_ksettings = atl2_get_link_ksettings,
2100 .set_link_ksettings = atl2_set_link_ksettings,
2101 };
2102
2103 #define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
2104 (((a) & 0xff00ff00) >> 8))
2105 #define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
2106 #define SHORTSWAP(a) (((a) << 8) | ((a) >> 8))
2107
2108 /*
2109 * Reset the transmit and receive units; mask and clear all interrupts.
2110 *
2111 * hw - Struct containing variables accessed by shared code
2112 * return : 0 or idle status (if error)
2113 */
atl2_reset_hw(struct atl2_hw * hw)2114 static s32 atl2_reset_hw(struct atl2_hw *hw)
2115 {
2116 u32 icr;
2117 u16 pci_cfg_cmd_word;
2118 int i;
2119
2120 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
2121 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2122 if ((pci_cfg_cmd_word &
2123 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) !=
2124 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {
2125 pci_cfg_cmd_word |=
2126 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);
2127 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2128 }
2129
2130 /* Clear Interrupt mask to stop board from generating
2131 * interrupts & Clear any pending interrupt events
2132 */
2133 /* FIXME */
2134 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */
2135 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */
2136
2137 /* Issue Soft Reset to the MAC. This will reset the chip's
2138 * transmit, receive, DMA. It will not effect
2139 * the current PCI configuration. The global reset bit is self-
2140 * clearing, and should clear within a microsecond.
2141 */
2142 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
2143 wmb();
2144 msleep(1); /* delay about 1ms */
2145
2146 /* Wait at least 10ms for All module to be Idle */
2147 for (i = 0; i < 10; i++) {
2148 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS);
2149 if (!icr)
2150 break;
2151 msleep(1); /* delay 1 ms */
2152 cpu_relax();
2153 }
2154
2155 if (icr)
2156 return icr;
2157
2158 return 0;
2159 }
2160
2161 #define CUSTOM_SPI_CS_SETUP 2
2162 #define CUSTOM_SPI_CLK_HI 2
2163 #define CUSTOM_SPI_CLK_LO 2
2164 #define CUSTOM_SPI_CS_HOLD 2
2165 #define CUSTOM_SPI_CS_HI 3
2166
2167 static struct atl2_spi_flash_dev flash_table[] =
2168 {
2169 /* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
2170 {"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 },
2171 {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 },
2172 {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 },
2173 };
2174
atl2_spi_read(struct atl2_hw * hw,u32 addr,u32 * buf)2175 static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf)
2176 {
2177 int i;
2178 u32 value;
2179
2180 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);
2181 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);
2182
2183 value = SPI_FLASH_CTRL_WAIT_READY |
2184 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
2185 SPI_FLASH_CTRL_CS_SETUP_SHIFT |
2186 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) <<
2187 SPI_FLASH_CTRL_CLK_HI_SHIFT |
2188 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) <<
2189 SPI_FLASH_CTRL_CLK_LO_SHIFT |
2190 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) <<
2191 SPI_FLASH_CTRL_CS_HOLD_SHIFT |
2192 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) <<
2193 SPI_FLASH_CTRL_CS_HI_SHIFT |
2194 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT;
2195
2196 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2197
2198 value |= SPI_FLASH_CTRL_START;
2199
2200 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2201
2202 for (i = 0; i < 10; i++) {
2203 msleep(1);
2204 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2205 if (!(value & SPI_FLASH_CTRL_START))
2206 break;
2207 }
2208
2209 if (value & SPI_FLASH_CTRL_START)
2210 return false;
2211
2212 *buf = ATL2_READ_REG(hw, REG_SPI_DATA);
2213
2214 return true;
2215 }
2216
2217 /*
2218 * get_permanent_address
2219 * return 0 if get valid mac address,
2220 */
get_permanent_address(struct atl2_hw * hw)2221 static int get_permanent_address(struct atl2_hw *hw)
2222 {
2223 u32 Addr[2];
2224 u32 i, Control;
2225 u16 Register;
2226 u8 EthAddr[ETH_ALEN];
2227 bool KeyValid;
2228
2229 if (is_valid_ether_addr(hw->perm_mac_addr))
2230 return 0;
2231
2232 Addr[0] = 0;
2233 Addr[1] = 0;
2234
2235 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */
2236 Register = 0;
2237 KeyValid = false;
2238
2239 /* Read out all EEPROM content */
2240 i = 0;
2241 while (1) {
2242 if (atl2_read_eeprom(hw, i + 0x100, &Control)) {
2243 if (KeyValid) {
2244 if (Register == REG_MAC_STA_ADDR)
2245 Addr[0] = Control;
2246 else if (Register ==
2247 (REG_MAC_STA_ADDR + 4))
2248 Addr[1] = Control;
2249 KeyValid = false;
2250 } else if ((Control & 0xff) == 0x5A) {
2251 KeyValid = true;
2252 Register = (u16) (Control >> 16);
2253 } else {
2254 /* assume data end while encount an invalid KEYWORD */
2255 break;
2256 }
2257 } else {
2258 break; /* read error */
2259 }
2260 i += 4;
2261 }
2262
2263 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2264 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2265
2266 if (is_valid_ether_addr(EthAddr)) {
2267 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN);
2268 return 0;
2269 }
2270 return 1;
2271 }
2272
2273 /* see if SPI flash exists? */
2274 Addr[0] = 0;
2275 Addr[1] = 0;
2276 Register = 0;
2277 KeyValid = false;
2278 i = 0;
2279 while (1) {
2280 if (atl2_spi_read(hw, i + 0x1f000, &Control)) {
2281 if (KeyValid) {
2282 if (Register == REG_MAC_STA_ADDR)
2283 Addr[0] = Control;
2284 else if (Register == (REG_MAC_STA_ADDR + 4))
2285 Addr[1] = Control;
2286 KeyValid = false;
2287 } else if ((Control & 0xff) == 0x5A) {
2288 KeyValid = true;
2289 Register = (u16) (Control >> 16);
2290 } else {
2291 break; /* data end */
2292 }
2293 } else {
2294 break; /* read error */
2295 }
2296 i += 4;
2297 }
2298
2299 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2300 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]);
2301 if (is_valid_ether_addr(EthAddr)) {
2302 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN);
2303 return 0;
2304 }
2305 /* maybe MAC-address is from BIOS */
2306 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
2307 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4);
2308 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2309 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2310
2311 if (is_valid_ether_addr(EthAddr)) {
2312 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN);
2313 return 0;
2314 }
2315
2316 return 1;
2317 }
2318
2319 /*
2320 * Reads the adapter's MAC address from the EEPROM
2321 *
2322 * hw - Struct containing variables accessed by shared code
2323 */
atl2_read_mac_addr(struct atl2_hw * hw)2324 static s32 atl2_read_mac_addr(struct atl2_hw *hw)
2325 {
2326 if (get_permanent_address(hw)) {
2327 /* for test */
2328 /* FIXME: shouldn't we use eth_random_addr() here? */
2329 hw->perm_mac_addr[0] = 0x00;
2330 hw->perm_mac_addr[1] = 0x13;
2331 hw->perm_mac_addr[2] = 0x74;
2332 hw->perm_mac_addr[3] = 0x00;
2333 hw->perm_mac_addr[4] = 0x5c;
2334 hw->perm_mac_addr[5] = 0x38;
2335 }
2336
2337 memcpy(hw->mac_addr, hw->perm_mac_addr, ETH_ALEN);
2338
2339 return 0;
2340 }
2341
2342 /*
2343 * Hashes an address to determine its location in the multicast table
2344 *
2345 * hw - Struct containing variables accessed by shared code
2346 * mc_addr - the multicast address to hash
2347 *
2348 * atl2_hash_mc_addr
2349 * purpose
2350 * set hash value for a multicast address
2351 * hash calcu processing :
2352 * 1. calcu 32bit CRC for multicast address
2353 * 2. reverse crc with MSB to LSB
2354 */
atl2_hash_mc_addr(struct atl2_hw * hw,u8 * mc_addr)2355 static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr)
2356 {
2357 u32 crc32, value;
2358 int i;
2359
2360 value = 0;
2361 crc32 = ether_crc_le(6, mc_addr);
2362
2363 for (i = 0; i < 32; i++)
2364 value |= (((crc32 >> i) & 1) << (31 - i));
2365
2366 return value;
2367 }
2368
2369 /*
2370 * Sets the bit in the multicast table corresponding to the hash value.
2371 *
2372 * hw - Struct containing variables accessed by shared code
2373 * hash_value - Multicast address hash value
2374 */
atl2_hash_set(struct atl2_hw * hw,u32 hash_value)2375 static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value)
2376 {
2377 u32 hash_bit, hash_reg;
2378 u32 mta;
2379
2380 /* The HASH Table is a register array of 2 32-bit registers.
2381 * It is treated like an array of 64 bits. We want to set
2382 * bit BitArray[hash_value]. So we figure out what register
2383 * the bit is in, read it, OR in the new bit, then write
2384 * back the new value. The register is determined by the
2385 * upper 7 bits of the hash value and the bit within that
2386 * register are determined by the lower 5 bits of the value.
2387 */
2388 hash_reg = (hash_value >> 31) & 0x1;
2389 hash_bit = (hash_value >> 26) & 0x1F;
2390
2391 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
2392
2393 mta |= (1 << hash_bit);
2394
2395 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
2396 }
2397
2398 /*
2399 * atl2_init_pcie - init PCIE module
2400 */
atl2_init_pcie(struct atl2_hw * hw)2401 static void atl2_init_pcie(struct atl2_hw *hw)
2402 {
2403 u32 value;
2404 value = LTSSM_TEST_MODE_DEF;
2405 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
2406
2407 value = PCIE_DLL_TX_CTRL1_DEF;
2408 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);
2409 }
2410
atl2_init_flash_opcode(struct atl2_hw * hw)2411 static void atl2_init_flash_opcode(struct atl2_hw *hw)
2412 {
2413 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
2414 hw->flash_vendor = 0; /* ATMEL */
2415
2416 /* Init OP table */
2417 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM,
2418 flash_table[hw->flash_vendor].cmdPROGRAM);
2419 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE,
2420 flash_table[hw->flash_vendor].cmdSECTOR_ERASE);
2421 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE,
2422 flash_table[hw->flash_vendor].cmdCHIP_ERASE);
2423 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID,
2424 flash_table[hw->flash_vendor].cmdRDID);
2425 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN,
2426 flash_table[hw->flash_vendor].cmdWREN);
2427 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR,
2428 flash_table[hw->flash_vendor].cmdRDSR);
2429 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR,
2430 flash_table[hw->flash_vendor].cmdWRSR);
2431 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ,
2432 flash_table[hw->flash_vendor].cmdREAD);
2433 }
2434
2435 /********************************************************************
2436 * Performs basic configuration of the adapter.
2437 *
2438 * hw - Struct containing variables accessed by shared code
2439 * Assumes that the controller has previously been reset and is in a
2440 * post-reset uninitialized state. Initializes multicast table,
2441 * and Calls routines to setup link
2442 * Leaves the transmit and receive units disabled and uninitialized.
2443 ********************************************************************/
atl2_init_hw(struct atl2_hw * hw)2444 static s32 atl2_init_hw(struct atl2_hw *hw)
2445 {
2446 u32 ret_val = 0;
2447
2448 atl2_init_pcie(hw);
2449
2450 /* Zero out the Multicast HASH table */
2451 /* clear the old settings from the multicast hash table */
2452 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
2453 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
2454
2455 atl2_init_flash_opcode(hw);
2456
2457 ret_val = atl2_phy_init(hw);
2458
2459 return ret_val;
2460 }
2461
2462 /*
2463 * Detects the current speed and duplex settings of the hardware.
2464 *
2465 * hw - Struct containing variables accessed by shared code
2466 * speed - Speed of the connection
2467 * duplex - Duplex setting of the connection
2468 */
atl2_get_speed_and_duplex(struct atl2_hw * hw,u16 * speed,u16 * duplex)2469 static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
2470 u16 *duplex)
2471 {
2472 s32 ret_val;
2473 u16 phy_data;
2474
2475 /* Read PHY Specific Status Register (17) */
2476 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
2477 if (ret_val)
2478 return ret_val;
2479
2480 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
2481 return ATLX_ERR_PHY_RES;
2482
2483 switch (phy_data & MII_ATLX_PSSR_SPEED) {
2484 case MII_ATLX_PSSR_100MBS:
2485 *speed = SPEED_100;
2486 break;
2487 case MII_ATLX_PSSR_10MBS:
2488 *speed = SPEED_10;
2489 break;
2490 default:
2491 return ATLX_ERR_PHY_SPEED;
2492 }
2493
2494 if (phy_data & MII_ATLX_PSSR_DPLX)
2495 *duplex = FULL_DUPLEX;
2496 else
2497 *duplex = HALF_DUPLEX;
2498
2499 return 0;
2500 }
2501
2502 /*
2503 * Reads the value from a PHY register
2504 * hw - Struct containing variables accessed by shared code
2505 * reg_addr - address of the PHY register to read
2506 */
atl2_read_phy_reg(struct atl2_hw * hw,u16 reg_addr,u16 * phy_data)2507 static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data)
2508 {
2509 u32 val;
2510 int i;
2511
2512 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
2513 MDIO_START |
2514 MDIO_SUP_PREAMBLE |
2515 MDIO_RW |
2516 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2517 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2518
2519 wmb();
2520
2521 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2522 udelay(2);
2523 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2524 if (!(val & (MDIO_START | MDIO_BUSY)))
2525 break;
2526 wmb();
2527 }
2528 if (!(val & (MDIO_START | MDIO_BUSY))) {
2529 *phy_data = (u16)val;
2530 return 0;
2531 }
2532
2533 return ATLX_ERR_PHY;
2534 }
2535
2536 /*
2537 * Writes a value to a PHY register
2538 * hw - Struct containing variables accessed by shared code
2539 * reg_addr - address of the PHY register to write
2540 * data - data to write to the PHY
2541 */
atl2_write_phy_reg(struct atl2_hw * hw,u32 reg_addr,u16 phy_data)2542 static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data)
2543 {
2544 int i;
2545 u32 val;
2546
2547 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
2548 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
2549 MDIO_SUP_PREAMBLE |
2550 MDIO_START |
2551 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2552 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2553
2554 wmb();
2555
2556 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2557 udelay(2);
2558 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2559 if (!(val & (MDIO_START | MDIO_BUSY)))
2560 break;
2561
2562 wmb();
2563 }
2564
2565 if (!(val & (MDIO_START | MDIO_BUSY)))
2566 return 0;
2567
2568 return ATLX_ERR_PHY;
2569 }
2570
2571 /*
2572 * Configures PHY autoneg and flow control advertisement settings
2573 *
2574 * hw - Struct containing variables accessed by shared code
2575 */
atl2_phy_setup_autoneg_adv(struct atl2_hw * hw)2576 static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)
2577 {
2578 s32 ret_val;
2579 s16 mii_autoneg_adv_reg;
2580
2581 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2582 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
2583
2584 /* Need to parse autoneg_advertised and set up
2585 * the appropriate PHY registers. First we will parse for
2586 * autoneg_advertised software override. Since we can advertise
2587 * a plethora of combinations, we need to check each bit
2588 * individually.
2589 */
2590
2591 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2592 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2593 * the 1000Base-T Control Register (Address 9). */
2594 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
2595
2596 /* Need to parse MediaType and setup the
2597 * appropriate PHY registers. */
2598 switch (hw->MediaType) {
2599 case MEDIA_TYPE_AUTO_SENSOR:
2600 mii_autoneg_adv_reg |=
2601 (MII_AR_10T_HD_CAPS |
2602 MII_AR_10T_FD_CAPS |
2603 MII_AR_100TX_HD_CAPS|
2604 MII_AR_100TX_FD_CAPS);
2605 hw->autoneg_advertised =
2606 ADVERTISE_10_HALF |
2607 ADVERTISE_10_FULL |
2608 ADVERTISE_100_HALF|
2609 ADVERTISE_100_FULL;
2610 break;
2611 case MEDIA_TYPE_100M_FULL:
2612 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
2613 hw->autoneg_advertised = ADVERTISE_100_FULL;
2614 break;
2615 case MEDIA_TYPE_100M_HALF:
2616 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
2617 hw->autoneg_advertised = ADVERTISE_100_HALF;
2618 break;
2619 case MEDIA_TYPE_10M_FULL:
2620 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
2621 hw->autoneg_advertised = ADVERTISE_10_FULL;
2622 break;
2623 default:
2624 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
2625 hw->autoneg_advertised = ADVERTISE_10_HALF;
2626 break;
2627 }
2628
2629 /* flow control fixed to enable all */
2630 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
2631
2632 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
2633
2634 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
2635
2636 if (ret_val)
2637 return ret_val;
2638
2639 return 0;
2640 }
2641
2642 /*
2643 * Resets the PHY and make all config validate
2644 *
2645 * hw - Struct containing variables accessed by shared code
2646 *
2647 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
2648 */
atl2_phy_commit(struct atl2_hw * hw)2649 static s32 atl2_phy_commit(struct atl2_hw *hw)
2650 {
2651 s32 ret_val;
2652 u16 phy_data;
2653
2654 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2655 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data);
2656 if (ret_val) {
2657 u32 val;
2658 int i;
2659 /* pcie serdes link may be down ! */
2660 for (i = 0; i < 25; i++) {
2661 msleep(1);
2662 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2663 if (!(val & (MDIO_START | MDIO_BUSY)))
2664 break;
2665 }
2666
2667 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
2668 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n");
2669 return ret_val;
2670 }
2671 }
2672 return 0;
2673 }
2674
atl2_phy_init(struct atl2_hw * hw)2675 static s32 atl2_phy_init(struct atl2_hw *hw)
2676 {
2677 s32 ret_val;
2678 u16 phy_val;
2679
2680 if (hw->phy_configured)
2681 return 0;
2682
2683 /* Enable PHY */
2684 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1);
2685 ATL2_WRITE_FLUSH(hw);
2686 msleep(1);
2687
2688 /* check if the PHY is in powersaving mode */
2689 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2690 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2691
2692 /* 024E / 124E 0r 0274 / 1274 ? */
2693 if (phy_val & 0x1000) {
2694 phy_val &= ~0x1000;
2695 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val);
2696 }
2697
2698 msleep(1);
2699
2700 /*Enable PHY LinkChange Interrupt */
2701 ret_val = atl2_write_phy_reg(hw, 18, 0xC00);
2702 if (ret_val)
2703 return ret_val;
2704
2705 /* setup AutoNeg parameters */
2706 ret_val = atl2_phy_setup_autoneg_adv(hw);
2707 if (ret_val)
2708 return ret_val;
2709
2710 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */
2711 ret_val = atl2_phy_commit(hw);
2712 if (ret_val)
2713 return ret_val;
2714
2715 hw->phy_configured = true;
2716
2717 return ret_val;
2718 }
2719
atl2_set_mac_addr(struct atl2_hw * hw)2720 static void atl2_set_mac_addr(struct atl2_hw *hw)
2721 {
2722 u32 value;
2723 /* 00-0B-6A-F6-00-DC
2724 * 0: 6AF600DC 1: 000B
2725 * low dword */
2726 value = (((u32)hw->mac_addr[2]) << 24) |
2727 (((u32)hw->mac_addr[3]) << 16) |
2728 (((u32)hw->mac_addr[4]) << 8) |
2729 (((u32)hw->mac_addr[5]));
2730 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
2731 /* hight dword */
2732 value = (((u32)hw->mac_addr[0]) << 8) |
2733 (((u32)hw->mac_addr[1]));
2734 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
2735 }
2736
2737 /*
2738 * check_eeprom_exist
2739 * return 0 if eeprom exist
2740 */
atl2_check_eeprom_exist(struct atl2_hw * hw)2741 static int atl2_check_eeprom_exist(struct atl2_hw *hw)
2742 {
2743 u32 value;
2744
2745 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2746 if (value & SPI_FLASH_CTRL_EN_VPD) {
2747 value &= ~SPI_FLASH_CTRL_EN_VPD;
2748 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2749 }
2750 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST);
2751 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
2752 }
2753
2754 /* FIXME: This doesn't look right. -- CHS */
atl2_write_eeprom(struct atl2_hw * hw,u32 offset,u32 value)2755 static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value)
2756 {
2757 return true;
2758 }
2759
atl2_read_eeprom(struct atl2_hw * hw,u32 Offset,u32 * pValue)2760 static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue)
2761 {
2762 int i;
2763 u32 Control;
2764
2765 if (Offset & 0x3)
2766 return false; /* address do not align */
2767
2768 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);
2769 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
2770 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);
2771
2772 for (i = 0; i < 10; i++) {
2773 msleep(2);
2774 Control = ATL2_READ_REG(hw, REG_VPD_CAP);
2775 if (Control & VPD_CAP_VPD_FLAG)
2776 break;
2777 }
2778
2779 if (Control & VPD_CAP_VPD_FLAG) {
2780 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA);
2781 return true;
2782 }
2783 return false; /* timeout */
2784 }
2785
atl2_force_ps(struct atl2_hw * hw)2786 static void atl2_force_ps(struct atl2_hw *hw)
2787 {
2788 u16 phy_val;
2789
2790 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2791 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2792 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000);
2793
2794 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2);
2795 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
2796 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3);
2797 atl2_write_phy_reg(hw, MII_DBG_DATA, 0);
2798 }
2799
2800 /* This is the only thing that needs to be changed to adjust the
2801 * maximum number of ports that the driver can manage.
2802 */
2803 #define ATL2_MAX_NIC 4
2804
2805 #define OPTION_UNSET -1
2806 #define OPTION_DISABLED 0
2807 #define OPTION_ENABLED 1
2808
2809 /* All parameters are treated the same, as an integer array of values.
2810 * This macro just reduces the need to repeat the same declaration code
2811 * over and over (plus this helps to avoid typo bugs).
2812 */
2813 #define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET}
2814 #ifndef module_param_array
2815 /* Module Parameters are always initialized to -1, so that the driver
2816 * can tell the difference between no user specified value or the
2817 * user asking for the default value.
2818 * The true default values are loaded in when atl2_check_options is called.
2819 *
2820 * This is a GCC extension to ANSI C.
2821 * See the item "Labeled Elements in Initializers" in the section
2822 * "Extensions to the C Language Family" of the GCC documentation.
2823 */
2824
2825 #define ATL2_PARAM(X, desc) \
2826 static const int X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \
2827 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \
2828 MODULE_PARM_DESC(X, desc);
2829 #else
2830 #define ATL2_PARAM(X, desc) \
2831 static int X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \
2832 static unsigned int num_##X; \
2833 module_param_array_named(X, X, int, &num_##X, 0); \
2834 MODULE_PARM_DESC(X, desc);
2835 #endif
2836
2837 /*
2838 * Transmit Memory Size
2839 * Valid Range: 64-2048
2840 * Default Value: 128
2841 */
2842 #define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */
2843 #define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */
2844 #define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */
2845 ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory");
2846
2847 /*
2848 * Receive Memory Block Count
2849 * Valid Range: 16-512
2850 * Default Value: 128
2851 */
2852 #define ATL2_MIN_RXD_COUNT 16
2853 #define ATL2_MAX_RXD_COUNT 512
2854 #define ATL2_DEFAULT_RXD_COUNT 64
2855 ATL2_PARAM(RxMemBlock, "Number of receive memory block");
2856
2857 /*
2858 * User Specified MediaType Override
2859 *
2860 * Valid Range: 0-5
2861 * - 0 - auto-negotiate at all supported speeds
2862 * - 1 - only link at 1000Mbps Full Duplex
2863 * - 2 - only link at 100Mbps Full Duplex
2864 * - 3 - only link at 100Mbps Half Duplex
2865 * - 4 - only link at 10Mbps Full Duplex
2866 * - 5 - only link at 10Mbps Half Duplex
2867 * Default Value: 0
2868 */
2869 ATL2_PARAM(MediaType, "MediaType Select");
2870
2871 /*
2872 * Interrupt Moderate Timer in units of 2048 ns (~2 us)
2873 * Valid Range: 10-65535
2874 * Default Value: 45000(90ms)
2875 */
2876 #define INT_MOD_DEFAULT_CNT 100 /* 200us */
2877 #define INT_MOD_MAX_CNT 65000
2878 #define INT_MOD_MIN_CNT 50
2879 ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer");
2880
2881 /*
2882 * FlashVendor
2883 * Valid Range: 0-2
2884 * 0 - Atmel
2885 * 1 - SST
2886 * 2 - ST
2887 */
2888 ATL2_PARAM(FlashVendor, "SPI Flash Vendor");
2889
2890 #define AUTONEG_ADV_DEFAULT 0x2F
2891 #define AUTONEG_ADV_MASK 0x2F
2892 #define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
2893
2894 #define FLASH_VENDOR_DEFAULT 0
2895 #define FLASH_VENDOR_MIN 0
2896 #define FLASH_VENDOR_MAX 2
2897
2898 struct atl2_option {
2899 enum { enable_option, range_option, list_option } type;
2900 char *name;
2901 char *err;
2902 int def;
2903 union {
2904 struct { /* range_option info */
2905 int min;
2906 int max;
2907 } r;
2908 struct { /* list_option info */
2909 int nr;
2910 struct atl2_opt_list { int i; char *str; } *p;
2911 } l;
2912 } arg;
2913 };
2914
atl2_validate_option(int * value,struct atl2_option * opt)2915 static int atl2_validate_option(int *value, struct atl2_option *opt)
2916 {
2917 int i;
2918 struct atl2_opt_list *ent;
2919
2920 if (*value == OPTION_UNSET) {
2921 *value = opt->def;
2922 return 0;
2923 }
2924
2925 switch (opt->type) {
2926 case enable_option:
2927 switch (*value) {
2928 case OPTION_ENABLED:
2929 printk(KERN_INFO "%s Enabled\n", opt->name);
2930 return 0;
2931 case OPTION_DISABLED:
2932 printk(KERN_INFO "%s Disabled\n", opt->name);
2933 return 0;
2934 }
2935 break;
2936 case range_option:
2937 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
2938 printk(KERN_INFO "%s set to %i\n", opt->name, *value);
2939 return 0;
2940 }
2941 break;
2942 case list_option:
2943 for (i = 0; i < opt->arg.l.nr; i++) {
2944 ent = &opt->arg.l.p[i];
2945 if (*value == ent->i) {
2946 if (ent->str[0] != '\0')
2947 printk(KERN_INFO "%s\n", ent->str);
2948 return 0;
2949 }
2950 }
2951 break;
2952 default:
2953 BUG();
2954 }
2955
2956 printk(KERN_INFO "Invalid %s specified (%i) %s\n",
2957 opt->name, *value, opt->err);
2958 *value = opt->def;
2959 return -1;
2960 }
2961
2962 /**
2963 * atl2_check_options - Range Checking for Command Line Parameters
2964 * @adapter: board private structure
2965 *
2966 * This routine checks all command line parameters for valid user
2967 * input. If an invalid value is given, or if no user specified
2968 * value exists, a default value is used. The final value is stored
2969 * in a variable in the adapter structure.
2970 */
atl2_check_options(struct atl2_adapter * adapter)2971 static void atl2_check_options(struct atl2_adapter *adapter)
2972 {
2973 int val;
2974 struct atl2_option opt;
2975 int bd = adapter->bd_number;
2976 if (bd >= ATL2_MAX_NIC) {
2977 printk(KERN_NOTICE "Warning: no configuration for board #%i\n",
2978 bd);
2979 printk(KERN_NOTICE "Using defaults for all values\n");
2980 #ifndef module_param_array
2981 bd = ATL2_MAX_NIC;
2982 #endif
2983 }
2984
2985 /* Bytes of Transmit Memory */
2986 opt.type = range_option;
2987 opt.name = "Bytes of Transmit Memory";
2988 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE);
2989 opt.def = ATL2_DEFAULT_TX_MEMSIZE;
2990 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE;
2991 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE;
2992 #ifdef module_param_array
2993 if (num_TxMemSize > bd) {
2994 #endif
2995 val = TxMemSize[bd];
2996 atl2_validate_option(&val, &opt);
2997 adapter->txd_ring_size = ((u32) val) * 1024;
2998 #ifdef module_param_array
2999 } else
3000 adapter->txd_ring_size = ((u32)opt.def) * 1024;
3001 #endif
3002 /* txs ring size: */
3003 adapter->txs_ring_size = adapter->txd_ring_size / 128;
3004 if (adapter->txs_ring_size > 160)
3005 adapter->txs_ring_size = 160;
3006
3007 /* Receive Memory Block Count */
3008 opt.type = range_option;
3009 opt.name = "Number of receive memory block";
3010 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT);
3011 opt.def = ATL2_DEFAULT_RXD_COUNT;
3012 opt.arg.r.min = ATL2_MIN_RXD_COUNT;
3013 opt.arg.r.max = ATL2_MAX_RXD_COUNT;
3014 #ifdef module_param_array
3015 if (num_RxMemBlock > bd) {
3016 #endif
3017 val = RxMemBlock[bd];
3018 atl2_validate_option(&val, &opt);
3019 adapter->rxd_ring_size = (u32)val;
3020 /* FIXME */
3021 /* ((u16)val)&~1; */ /* even number */
3022 #ifdef module_param_array
3023 } else
3024 adapter->rxd_ring_size = (u32)opt.def;
3025 #endif
3026 /* init RXD Flow control value */
3027 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7;
3028 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) >
3029 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) :
3030 (adapter->rxd_ring_size / 12);
3031
3032 /* Interrupt Moderate Timer */
3033 opt.type = range_option;
3034 opt.name = "Interrupt Moderate Timer";
3035 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT);
3036 opt.def = INT_MOD_DEFAULT_CNT;
3037 opt.arg.r.min = INT_MOD_MIN_CNT;
3038 opt.arg.r.max = INT_MOD_MAX_CNT;
3039 #ifdef module_param_array
3040 if (num_IntModTimer > bd) {
3041 #endif
3042 val = IntModTimer[bd];
3043 atl2_validate_option(&val, &opt);
3044 adapter->imt = (u16) val;
3045 #ifdef module_param_array
3046 } else
3047 adapter->imt = (u16)(opt.def);
3048 #endif
3049 /* Flash Vendor */
3050 opt.type = range_option;
3051 opt.name = "SPI Flash Vendor";
3052 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT);
3053 opt.def = FLASH_VENDOR_DEFAULT;
3054 opt.arg.r.min = FLASH_VENDOR_MIN;
3055 opt.arg.r.max = FLASH_VENDOR_MAX;
3056 #ifdef module_param_array
3057 if (num_FlashVendor > bd) {
3058 #endif
3059 val = FlashVendor[bd];
3060 atl2_validate_option(&val, &opt);
3061 adapter->hw.flash_vendor = (u8) val;
3062 #ifdef module_param_array
3063 } else
3064 adapter->hw.flash_vendor = (u8)(opt.def);
3065 #endif
3066 /* MediaType */
3067 opt.type = range_option;
3068 opt.name = "Speed/Duplex Selection";
3069 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR);
3070 opt.def = MEDIA_TYPE_AUTO_SENSOR;
3071 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR;
3072 opt.arg.r.max = MEDIA_TYPE_10M_HALF;
3073 #ifdef module_param_array
3074 if (num_MediaType > bd) {
3075 #endif
3076 val = MediaType[bd];
3077 atl2_validate_option(&val, &opt);
3078 adapter->hw.MediaType = (u16) val;
3079 #ifdef module_param_array
3080 } else
3081 adapter->hw.MediaType = (u16)(opt.def);
3082 #endif
3083 }
3084