1 /*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014-2017 Broadcom
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #define pr_fmt(fmt) "bcmgenet: " fmt
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/sched.h>
16 #include <linux/types.h>
17 #include <linux/fcntl.h>
18 #include <linux/interrupt.h>
19 #include <linux/string.h>
20 #include <linux/if_ether.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <linux/platform_device.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm.h>
27 #include <linux/clk.h>
28 #include <linux/of.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_net.h>
32 #include <linux/of_platform.h>
33 #include <net/arp.h>
34
35 #include <linux/mii.h>
36 #include <linux/ethtool.h>
37 #include <linux/netdevice.h>
38 #include <linux/inetdevice.h>
39 #include <linux/etherdevice.h>
40 #include <linux/skbuff.h>
41 #include <linux/in.h>
42 #include <linux/ip.h>
43 #include <linux/ipv6.h>
44 #include <linux/phy.h>
45 #include <linux/platform_data/bcmgenet.h>
46
47 #include <asm/unaligned.h>
48
49 #include "bcmgenet.h"
50
51 /* Maximum number of hardware queues, downsized if needed */
52 #define GENET_MAX_MQ_CNT 4
53
54 /* Default highest priority queue for multi queue support */
55 #define GENET_Q0_PRIORITY 0
56
57 #define GENET_Q16_RX_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
59 #define GENET_Q16_TX_BD_CNT \
60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
61
62 #define RX_BUF_LENGTH 2048
63 #define SKB_ALIGNMENT 32
64
65 /* Tx/Rx DMA register offset, skip 256 descriptors */
66 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
67 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
68
69 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
73 TOTAL_DESC * DMA_DESC_SIZE)
74
bcmgenet_writel(u32 value,void __iomem * offset)75 static inline void bcmgenet_writel(u32 value, void __iomem *offset)
76 {
77 /* MIPS chips strapped for BE will automagically configure the
78 * peripheral registers for CPU-native byte order.
79 */
80 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
81 __raw_writel(value, offset);
82 else
83 writel_relaxed(value, offset);
84 }
85
bcmgenet_readl(void __iomem * offset)86 static inline u32 bcmgenet_readl(void __iomem *offset)
87 {
88 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
89 return __raw_readl(offset);
90 else
91 return readl_relaxed(offset);
92 }
93
dmadesc_set_length_status(struct bcmgenet_priv * priv,void __iomem * d,u32 value)94 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
95 void __iomem *d, u32 value)
96 {
97 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
98 }
99
dmadesc_get_length_status(struct bcmgenet_priv * priv,void __iomem * d)100 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
101 void __iomem *d)
102 {
103 return bcmgenet_readl(d + DMA_DESC_LENGTH_STATUS);
104 }
105
dmadesc_set_addr(struct bcmgenet_priv * priv,void __iomem * d,dma_addr_t addr)106 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
107 void __iomem *d,
108 dma_addr_t addr)
109 {
110 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
111
112 /* Register writes to GISB bus can take couple hundred nanoseconds
113 * and are done for each packet, save these expensive writes unless
114 * the platform is explicitly configured for 64-bits/LPAE.
115 */
116 #ifdef CONFIG_PHYS_ADDR_T_64BIT
117 if (priv->hw_params->flags & GENET_HAS_40BITS)
118 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
119 #endif
120 }
121
122 /* Combined address + length/status setter */
dmadesc_set(struct bcmgenet_priv * priv,void __iomem * d,dma_addr_t addr,u32 val)123 static inline void dmadesc_set(struct bcmgenet_priv *priv,
124 void __iomem *d, dma_addr_t addr, u32 val)
125 {
126 dmadesc_set_addr(priv, d, addr);
127 dmadesc_set_length_status(priv, d, val);
128 }
129
dmadesc_get_addr(struct bcmgenet_priv * priv,void __iomem * d)130 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
131 void __iomem *d)
132 {
133 dma_addr_t addr;
134
135 addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO);
136
137 /* Register writes to GISB bus can take couple hundred nanoseconds
138 * and are done for each packet, save these expensive writes unless
139 * the platform is explicitly configured for 64-bits/LPAE.
140 */
141 #ifdef CONFIG_PHYS_ADDR_T_64BIT
142 if (priv->hw_params->flags & GENET_HAS_40BITS)
143 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32;
144 #endif
145 return addr;
146 }
147
148 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
149
150 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
151 NETIF_MSG_LINK)
152
bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv * priv)153 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
154 {
155 if (GENET_IS_V1(priv))
156 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
157 else
158 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
159 }
160
bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv * priv,u32 val)161 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
162 {
163 if (GENET_IS_V1(priv))
164 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
165 else
166 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
167 }
168
169 /* These macros are defined to deal with register map change
170 * between GENET1.1 and GENET2. Only those currently being used
171 * by driver are defined.
172 */
bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv * priv)173 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
174 {
175 if (GENET_IS_V1(priv))
176 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
177 else
178 return bcmgenet_readl(priv->base +
179 priv->hw_params->tbuf_offset + TBUF_CTRL);
180 }
181
bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv * priv,u32 val)182 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
183 {
184 if (GENET_IS_V1(priv))
185 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
186 else
187 bcmgenet_writel(val, priv->base +
188 priv->hw_params->tbuf_offset + TBUF_CTRL);
189 }
190
bcmgenet_bp_mc_get(struct bcmgenet_priv * priv)191 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
192 {
193 if (GENET_IS_V1(priv))
194 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
195 else
196 return bcmgenet_readl(priv->base +
197 priv->hw_params->tbuf_offset + TBUF_BP_MC);
198 }
199
bcmgenet_bp_mc_set(struct bcmgenet_priv * priv,u32 val)200 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
201 {
202 if (GENET_IS_V1(priv))
203 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
204 else
205 bcmgenet_writel(val, priv->base +
206 priv->hw_params->tbuf_offset + TBUF_BP_MC);
207 }
208
209 /* RX/TX DMA register accessors */
210 enum dma_reg {
211 DMA_RING_CFG = 0,
212 DMA_CTRL,
213 DMA_STATUS,
214 DMA_SCB_BURST_SIZE,
215 DMA_ARB_CTRL,
216 DMA_PRIORITY_0,
217 DMA_PRIORITY_1,
218 DMA_PRIORITY_2,
219 DMA_INDEX2RING_0,
220 DMA_INDEX2RING_1,
221 DMA_INDEX2RING_2,
222 DMA_INDEX2RING_3,
223 DMA_INDEX2RING_4,
224 DMA_INDEX2RING_5,
225 DMA_INDEX2RING_6,
226 DMA_INDEX2RING_7,
227 DMA_RING0_TIMEOUT,
228 DMA_RING1_TIMEOUT,
229 DMA_RING2_TIMEOUT,
230 DMA_RING3_TIMEOUT,
231 DMA_RING4_TIMEOUT,
232 DMA_RING5_TIMEOUT,
233 DMA_RING6_TIMEOUT,
234 DMA_RING7_TIMEOUT,
235 DMA_RING8_TIMEOUT,
236 DMA_RING9_TIMEOUT,
237 DMA_RING10_TIMEOUT,
238 DMA_RING11_TIMEOUT,
239 DMA_RING12_TIMEOUT,
240 DMA_RING13_TIMEOUT,
241 DMA_RING14_TIMEOUT,
242 DMA_RING15_TIMEOUT,
243 DMA_RING16_TIMEOUT,
244 };
245
246 static const u8 bcmgenet_dma_regs_v3plus[] = {
247 [DMA_RING_CFG] = 0x00,
248 [DMA_CTRL] = 0x04,
249 [DMA_STATUS] = 0x08,
250 [DMA_SCB_BURST_SIZE] = 0x0C,
251 [DMA_ARB_CTRL] = 0x2C,
252 [DMA_PRIORITY_0] = 0x30,
253 [DMA_PRIORITY_1] = 0x34,
254 [DMA_PRIORITY_2] = 0x38,
255 [DMA_RING0_TIMEOUT] = 0x2C,
256 [DMA_RING1_TIMEOUT] = 0x30,
257 [DMA_RING2_TIMEOUT] = 0x34,
258 [DMA_RING3_TIMEOUT] = 0x38,
259 [DMA_RING4_TIMEOUT] = 0x3c,
260 [DMA_RING5_TIMEOUT] = 0x40,
261 [DMA_RING6_TIMEOUT] = 0x44,
262 [DMA_RING7_TIMEOUT] = 0x48,
263 [DMA_RING8_TIMEOUT] = 0x4c,
264 [DMA_RING9_TIMEOUT] = 0x50,
265 [DMA_RING10_TIMEOUT] = 0x54,
266 [DMA_RING11_TIMEOUT] = 0x58,
267 [DMA_RING12_TIMEOUT] = 0x5c,
268 [DMA_RING13_TIMEOUT] = 0x60,
269 [DMA_RING14_TIMEOUT] = 0x64,
270 [DMA_RING15_TIMEOUT] = 0x68,
271 [DMA_RING16_TIMEOUT] = 0x6C,
272 [DMA_INDEX2RING_0] = 0x70,
273 [DMA_INDEX2RING_1] = 0x74,
274 [DMA_INDEX2RING_2] = 0x78,
275 [DMA_INDEX2RING_3] = 0x7C,
276 [DMA_INDEX2RING_4] = 0x80,
277 [DMA_INDEX2RING_5] = 0x84,
278 [DMA_INDEX2RING_6] = 0x88,
279 [DMA_INDEX2RING_7] = 0x8C,
280 };
281
282 static const u8 bcmgenet_dma_regs_v2[] = {
283 [DMA_RING_CFG] = 0x00,
284 [DMA_CTRL] = 0x04,
285 [DMA_STATUS] = 0x08,
286 [DMA_SCB_BURST_SIZE] = 0x0C,
287 [DMA_ARB_CTRL] = 0x30,
288 [DMA_PRIORITY_0] = 0x34,
289 [DMA_PRIORITY_1] = 0x38,
290 [DMA_PRIORITY_2] = 0x3C,
291 [DMA_RING0_TIMEOUT] = 0x2C,
292 [DMA_RING1_TIMEOUT] = 0x30,
293 [DMA_RING2_TIMEOUT] = 0x34,
294 [DMA_RING3_TIMEOUT] = 0x38,
295 [DMA_RING4_TIMEOUT] = 0x3c,
296 [DMA_RING5_TIMEOUT] = 0x40,
297 [DMA_RING6_TIMEOUT] = 0x44,
298 [DMA_RING7_TIMEOUT] = 0x48,
299 [DMA_RING8_TIMEOUT] = 0x4c,
300 [DMA_RING9_TIMEOUT] = 0x50,
301 [DMA_RING10_TIMEOUT] = 0x54,
302 [DMA_RING11_TIMEOUT] = 0x58,
303 [DMA_RING12_TIMEOUT] = 0x5c,
304 [DMA_RING13_TIMEOUT] = 0x60,
305 [DMA_RING14_TIMEOUT] = 0x64,
306 [DMA_RING15_TIMEOUT] = 0x68,
307 [DMA_RING16_TIMEOUT] = 0x6C,
308 };
309
310 static const u8 bcmgenet_dma_regs_v1[] = {
311 [DMA_CTRL] = 0x00,
312 [DMA_STATUS] = 0x04,
313 [DMA_SCB_BURST_SIZE] = 0x0C,
314 [DMA_ARB_CTRL] = 0x30,
315 [DMA_PRIORITY_0] = 0x34,
316 [DMA_PRIORITY_1] = 0x38,
317 [DMA_PRIORITY_2] = 0x3C,
318 [DMA_RING0_TIMEOUT] = 0x2C,
319 [DMA_RING1_TIMEOUT] = 0x30,
320 [DMA_RING2_TIMEOUT] = 0x34,
321 [DMA_RING3_TIMEOUT] = 0x38,
322 [DMA_RING4_TIMEOUT] = 0x3c,
323 [DMA_RING5_TIMEOUT] = 0x40,
324 [DMA_RING6_TIMEOUT] = 0x44,
325 [DMA_RING7_TIMEOUT] = 0x48,
326 [DMA_RING8_TIMEOUT] = 0x4c,
327 [DMA_RING9_TIMEOUT] = 0x50,
328 [DMA_RING10_TIMEOUT] = 0x54,
329 [DMA_RING11_TIMEOUT] = 0x58,
330 [DMA_RING12_TIMEOUT] = 0x5c,
331 [DMA_RING13_TIMEOUT] = 0x60,
332 [DMA_RING14_TIMEOUT] = 0x64,
333 [DMA_RING15_TIMEOUT] = 0x68,
334 [DMA_RING16_TIMEOUT] = 0x6C,
335 };
336
337 /* Set at runtime once bcmgenet version is known */
338 static const u8 *bcmgenet_dma_regs;
339
dev_to_priv(struct device * dev)340 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
341 {
342 return netdev_priv(dev_get_drvdata(dev));
343 }
344
bcmgenet_tdma_readl(struct bcmgenet_priv * priv,enum dma_reg r)345 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
346 enum dma_reg r)
347 {
348 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
349 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
350 }
351
bcmgenet_tdma_writel(struct bcmgenet_priv * priv,u32 val,enum dma_reg r)352 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
353 u32 val, enum dma_reg r)
354 {
355 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
356 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
357 }
358
bcmgenet_rdma_readl(struct bcmgenet_priv * priv,enum dma_reg r)359 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
360 enum dma_reg r)
361 {
362 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
363 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
364 }
365
bcmgenet_rdma_writel(struct bcmgenet_priv * priv,u32 val,enum dma_reg r)366 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
367 u32 val, enum dma_reg r)
368 {
369 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
370 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
371 }
372
373 /* RDMA/TDMA ring registers and accessors
374 * we merge the common fields and just prefix with T/D the registers
375 * having different meaning depending on the direction
376 */
377 enum dma_ring_reg {
378 TDMA_READ_PTR = 0,
379 RDMA_WRITE_PTR = TDMA_READ_PTR,
380 TDMA_READ_PTR_HI,
381 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
382 TDMA_CONS_INDEX,
383 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
384 TDMA_PROD_INDEX,
385 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
386 DMA_RING_BUF_SIZE,
387 DMA_START_ADDR,
388 DMA_START_ADDR_HI,
389 DMA_END_ADDR,
390 DMA_END_ADDR_HI,
391 DMA_MBUF_DONE_THRESH,
392 TDMA_FLOW_PERIOD,
393 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
394 TDMA_WRITE_PTR,
395 RDMA_READ_PTR = TDMA_WRITE_PTR,
396 TDMA_WRITE_PTR_HI,
397 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
398 };
399
400 /* GENET v4 supports 40-bits pointer addressing
401 * for obvious reasons the LO and HI word parts
402 * are contiguous, but this offsets the other
403 * registers.
404 */
405 static const u8 genet_dma_ring_regs_v4[] = {
406 [TDMA_READ_PTR] = 0x00,
407 [TDMA_READ_PTR_HI] = 0x04,
408 [TDMA_CONS_INDEX] = 0x08,
409 [TDMA_PROD_INDEX] = 0x0C,
410 [DMA_RING_BUF_SIZE] = 0x10,
411 [DMA_START_ADDR] = 0x14,
412 [DMA_START_ADDR_HI] = 0x18,
413 [DMA_END_ADDR] = 0x1C,
414 [DMA_END_ADDR_HI] = 0x20,
415 [DMA_MBUF_DONE_THRESH] = 0x24,
416 [TDMA_FLOW_PERIOD] = 0x28,
417 [TDMA_WRITE_PTR] = 0x2C,
418 [TDMA_WRITE_PTR_HI] = 0x30,
419 };
420
421 static const u8 genet_dma_ring_regs_v123[] = {
422 [TDMA_READ_PTR] = 0x00,
423 [TDMA_CONS_INDEX] = 0x04,
424 [TDMA_PROD_INDEX] = 0x08,
425 [DMA_RING_BUF_SIZE] = 0x0C,
426 [DMA_START_ADDR] = 0x10,
427 [DMA_END_ADDR] = 0x14,
428 [DMA_MBUF_DONE_THRESH] = 0x18,
429 [TDMA_FLOW_PERIOD] = 0x1C,
430 [TDMA_WRITE_PTR] = 0x20,
431 };
432
433 /* Set at runtime once GENET version is known */
434 static const u8 *genet_dma_ring_regs;
435
bcmgenet_tdma_ring_readl(struct bcmgenet_priv * priv,unsigned int ring,enum dma_ring_reg r)436 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
437 unsigned int ring,
438 enum dma_ring_reg r)
439 {
440 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
441 (DMA_RING_SIZE * ring) +
442 genet_dma_ring_regs[r]);
443 }
444
bcmgenet_tdma_ring_writel(struct bcmgenet_priv * priv,unsigned int ring,u32 val,enum dma_ring_reg r)445 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
446 unsigned int ring, u32 val,
447 enum dma_ring_reg r)
448 {
449 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
450 (DMA_RING_SIZE * ring) +
451 genet_dma_ring_regs[r]);
452 }
453
bcmgenet_rdma_ring_readl(struct bcmgenet_priv * priv,unsigned int ring,enum dma_ring_reg r)454 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
455 unsigned int ring,
456 enum dma_ring_reg r)
457 {
458 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
459 (DMA_RING_SIZE * ring) +
460 genet_dma_ring_regs[r]);
461 }
462
bcmgenet_rdma_ring_writel(struct bcmgenet_priv * priv,unsigned int ring,u32 val,enum dma_ring_reg r)463 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
464 unsigned int ring, u32 val,
465 enum dma_ring_reg r)
466 {
467 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
468 (DMA_RING_SIZE * ring) +
469 genet_dma_ring_regs[r]);
470 }
471
bcmgenet_begin(struct net_device * dev)472 static int bcmgenet_begin(struct net_device *dev)
473 {
474 struct bcmgenet_priv *priv = netdev_priv(dev);
475
476 /* Turn on the clock */
477 return clk_prepare_enable(priv->clk);
478 }
479
bcmgenet_complete(struct net_device * dev)480 static void bcmgenet_complete(struct net_device *dev)
481 {
482 struct bcmgenet_priv *priv = netdev_priv(dev);
483
484 /* Turn off the clock */
485 clk_disable_unprepare(priv->clk);
486 }
487
bcmgenet_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)488 static int bcmgenet_get_link_ksettings(struct net_device *dev,
489 struct ethtool_link_ksettings *cmd)
490 {
491 struct bcmgenet_priv *priv = netdev_priv(dev);
492
493 if (!netif_running(dev))
494 return -EINVAL;
495
496 if (!priv->phydev)
497 return -ENODEV;
498
499 phy_ethtool_ksettings_get(priv->phydev, cmd);
500
501 return 0;
502 }
503
bcmgenet_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)504 static int bcmgenet_set_link_ksettings(struct net_device *dev,
505 const struct ethtool_link_ksettings *cmd)
506 {
507 struct bcmgenet_priv *priv = netdev_priv(dev);
508
509 if (!netif_running(dev))
510 return -EINVAL;
511
512 if (!priv->phydev)
513 return -ENODEV;
514
515 return phy_ethtool_ksettings_set(priv->phydev, cmd);
516 }
517
bcmgenet_set_rx_csum(struct net_device * dev,netdev_features_t wanted)518 static int bcmgenet_set_rx_csum(struct net_device *dev,
519 netdev_features_t wanted)
520 {
521 struct bcmgenet_priv *priv = netdev_priv(dev);
522 u32 rbuf_chk_ctrl;
523 bool rx_csum_en;
524
525 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
526
527 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
528
529 /* enable rx checksumming */
530 if (rx_csum_en)
531 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
532 else
533 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
534 priv->desc_rxchk_en = rx_csum_en;
535
536 /* If UniMAC forwards CRC, we need to skip over it to get
537 * a valid CHK bit to be set in the per-packet status word
538 */
539 if (rx_csum_en && priv->crc_fwd_en)
540 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
541 else
542 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
543
544 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
545
546 return 0;
547 }
548
bcmgenet_set_tx_csum(struct net_device * dev,netdev_features_t wanted)549 static int bcmgenet_set_tx_csum(struct net_device *dev,
550 netdev_features_t wanted)
551 {
552 struct bcmgenet_priv *priv = netdev_priv(dev);
553 bool desc_64b_en;
554 u32 tbuf_ctrl, rbuf_ctrl;
555
556 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
557 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
558
559 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
560
561 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
562 if (desc_64b_en) {
563 tbuf_ctrl |= RBUF_64B_EN;
564 rbuf_ctrl |= RBUF_64B_EN;
565 } else {
566 tbuf_ctrl &= ~RBUF_64B_EN;
567 rbuf_ctrl &= ~RBUF_64B_EN;
568 }
569 priv->desc_64b_en = desc_64b_en;
570
571 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
572 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
573
574 return 0;
575 }
576
bcmgenet_set_features(struct net_device * dev,netdev_features_t features)577 static int bcmgenet_set_features(struct net_device *dev,
578 netdev_features_t features)
579 {
580 netdev_features_t changed = features ^ dev->features;
581 netdev_features_t wanted = dev->wanted_features;
582 int ret = 0;
583
584 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
585 ret = bcmgenet_set_tx_csum(dev, wanted);
586 if (changed & (NETIF_F_RXCSUM))
587 ret = bcmgenet_set_rx_csum(dev, wanted);
588
589 return ret;
590 }
591
bcmgenet_get_msglevel(struct net_device * dev)592 static u32 bcmgenet_get_msglevel(struct net_device *dev)
593 {
594 struct bcmgenet_priv *priv = netdev_priv(dev);
595
596 return priv->msg_enable;
597 }
598
bcmgenet_set_msglevel(struct net_device * dev,u32 level)599 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
600 {
601 struct bcmgenet_priv *priv = netdev_priv(dev);
602
603 priv->msg_enable = level;
604 }
605
bcmgenet_get_coalesce(struct net_device * dev,struct ethtool_coalesce * ec)606 static int bcmgenet_get_coalesce(struct net_device *dev,
607 struct ethtool_coalesce *ec)
608 {
609 struct bcmgenet_priv *priv = netdev_priv(dev);
610
611 ec->tx_max_coalesced_frames =
612 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
613 DMA_MBUF_DONE_THRESH);
614 ec->rx_max_coalesced_frames =
615 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
616 DMA_MBUF_DONE_THRESH);
617 ec->rx_coalesce_usecs =
618 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
619
620 return 0;
621 }
622
bcmgenet_set_coalesce(struct net_device * dev,struct ethtool_coalesce * ec)623 static int bcmgenet_set_coalesce(struct net_device *dev,
624 struct ethtool_coalesce *ec)
625 {
626 struct bcmgenet_priv *priv = netdev_priv(dev);
627 unsigned int i;
628 u32 reg;
629
630 /* Base system clock is 125Mhz, DMA timeout is this reference clock
631 * divided by 1024, which yields roughly 8.192us, our maximum value
632 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
633 */
634 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
635 ec->tx_max_coalesced_frames == 0 ||
636 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
637 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
638 return -EINVAL;
639
640 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
641 return -EINVAL;
642
643 /* GENET TDMA hardware does not support a configurable timeout, but will
644 * always generate an interrupt either after MBDONE packets have been
645 * transmitted, or when the ring is empty.
646 */
647 if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
648 ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low)
649 return -EOPNOTSUPP;
650
651 /* Program all TX queues with the same values, as there is no
652 * ethtool knob to do coalescing on a per-queue basis
653 */
654 for (i = 0; i < priv->hw_params->tx_queues; i++)
655 bcmgenet_tdma_ring_writel(priv, i,
656 ec->tx_max_coalesced_frames,
657 DMA_MBUF_DONE_THRESH);
658 bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
659 ec->tx_max_coalesced_frames,
660 DMA_MBUF_DONE_THRESH);
661
662 for (i = 0; i < priv->hw_params->rx_queues; i++) {
663 bcmgenet_rdma_ring_writel(priv, i,
664 ec->rx_max_coalesced_frames,
665 DMA_MBUF_DONE_THRESH);
666
667 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
668 reg &= ~DMA_TIMEOUT_MASK;
669 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
670 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
671 }
672
673 bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
674 ec->rx_max_coalesced_frames,
675 DMA_MBUF_DONE_THRESH);
676
677 reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT);
678 reg &= ~DMA_TIMEOUT_MASK;
679 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
680 bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT);
681
682 return 0;
683 }
684
685 /* standard ethtool support functions. */
686 enum bcmgenet_stat_type {
687 BCMGENET_STAT_NETDEV = -1,
688 BCMGENET_STAT_MIB_RX,
689 BCMGENET_STAT_MIB_TX,
690 BCMGENET_STAT_RUNT,
691 BCMGENET_STAT_MISC,
692 BCMGENET_STAT_SOFT,
693 };
694
695 struct bcmgenet_stats {
696 char stat_string[ETH_GSTRING_LEN];
697 int stat_sizeof;
698 int stat_offset;
699 enum bcmgenet_stat_type type;
700 /* reg offset from UMAC base for misc counters */
701 u16 reg_offset;
702 };
703
704 #define STAT_NETDEV(m) { \
705 .stat_string = __stringify(m), \
706 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
707 .stat_offset = offsetof(struct net_device_stats, m), \
708 .type = BCMGENET_STAT_NETDEV, \
709 }
710
711 #define STAT_GENET_MIB(str, m, _type) { \
712 .stat_string = str, \
713 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
714 .stat_offset = offsetof(struct bcmgenet_priv, m), \
715 .type = _type, \
716 }
717
718 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
719 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
720 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
721 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
722
723 #define STAT_GENET_MISC(str, m, offset) { \
724 .stat_string = str, \
725 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
726 .stat_offset = offsetof(struct bcmgenet_priv, m), \
727 .type = BCMGENET_STAT_MISC, \
728 .reg_offset = offset, \
729 }
730
731 #define STAT_GENET_Q(num) \
732 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
733 tx_rings[num].packets), \
734 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
735 tx_rings[num].bytes), \
736 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
737 rx_rings[num].bytes), \
738 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
739 rx_rings[num].packets), \
740 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
741 rx_rings[num].errors), \
742 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
743 rx_rings[num].dropped)
744
745 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
746 * between the end of TX stats and the beginning of the RX RUNT
747 */
748 #define BCMGENET_STAT_OFFSET 0xc
749
750 /* Hardware counters must be kept in sync because the order/offset
751 * is important here (order in structure declaration = order in hardware)
752 */
753 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
754 /* general stats */
755 STAT_NETDEV(rx_packets),
756 STAT_NETDEV(tx_packets),
757 STAT_NETDEV(rx_bytes),
758 STAT_NETDEV(tx_bytes),
759 STAT_NETDEV(rx_errors),
760 STAT_NETDEV(tx_errors),
761 STAT_NETDEV(rx_dropped),
762 STAT_NETDEV(tx_dropped),
763 STAT_NETDEV(multicast),
764 /* UniMAC RSV counters */
765 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
766 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
767 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
768 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
769 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
770 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
771 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
772 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
773 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
774 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
775 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
776 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
777 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
778 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
779 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
780 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
781 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
782 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
783 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
784 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
785 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
786 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
787 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
788 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
789 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
790 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
791 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
792 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
793 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
794 /* UniMAC TSV counters */
795 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
796 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
797 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
798 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
799 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
800 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
801 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
802 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
803 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
804 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
805 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
806 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
807 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
808 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
809 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
810 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
811 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
812 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
813 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
814 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
815 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
816 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
817 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
818 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
819 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
820 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
821 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
822 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
823 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
824 /* UniMAC RUNT counters */
825 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
826 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
827 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
828 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
829 /* Misc UniMAC counters */
830 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
831 UMAC_RBUF_OVFL_CNT_V1),
832 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
833 UMAC_RBUF_ERR_CNT_V1),
834 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
835 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
836 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
837 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
838 /* Per TX queues */
839 STAT_GENET_Q(0),
840 STAT_GENET_Q(1),
841 STAT_GENET_Q(2),
842 STAT_GENET_Q(3),
843 STAT_GENET_Q(16),
844 };
845
846 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
847
bcmgenet_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)848 static void bcmgenet_get_drvinfo(struct net_device *dev,
849 struct ethtool_drvinfo *info)
850 {
851 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
852 strlcpy(info->version, "v2.0", sizeof(info->version));
853 }
854
bcmgenet_get_sset_count(struct net_device * dev,int string_set)855 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
856 {
857 switch (string_set) {
858 case ETH_SS_STATS:
859 return BCMGENET_STATS_LEN;
860 default:
861 return -EOPNOTSUPP;
862 }
863 }
864
bcmgenet_get_strings(struct net_device * dev,u32 stringset,u8 * data)865 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
866 u8 *data)
867 {
868 int i;
869
870 switch (stringset) {
871 case ETH_SS_STATS:
872 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
873 memcpy(data + i * ETH_GSTRING_LEN,
874 bcmgenet_gstrings_stats[i].stat_string,
875 ETH_GSTRING_LEN);
876 }
877 break;
878 }
879 }
880
bcmgenet_update_stat_misc(struct bcmgenet_priv * priv,u16 offset)881 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
882 {
883 u16 new_offset;
884 u32 val;
885
886 switch (offset) {
887 case UMAC_RBUF_OVFL_CNT_V1:
888 if (GENET_IS_V2(priv))
889 new_offset = RBUF_OVFL_CNT_V2;
890 else
891 new_offset = RBUF_OVFL_CNT_V3PLUS;
892
893 val = bcmgenet_rbuf_readl(priv, new_offset);
894 /* clear if overflowed */
895 if (val == ~0)
896 bcmgenet_rbuf_writel(priv, 0, new_offset);
897 break;
898 case UMAC_RBUF_ERR_CNT_V1:
899 if (GENET_IS_V2(priv))
900 new_offset = RBUF_ERR_CNT_V2;
901 else
902 new_offset = RBUF_ERR_CNT_V3PLUS;
903
904 val = bcmgenet_rbuf_readl(priv, new_offset);
905 /* clear if overflowed */
906 if (val == ~0)
907 bcmgenet_rbuf_writel(priv, 0, new_offset);
908 break;
909 default:
910 val = bcmgenet_umac_readl(priv, offset);
911 /* clear if overflowed */
912 if (val == ~0)
913 bcmgenet_umac_writel(priv, 0, offset);
914 break;
915 }
916
917 return val;
918 }
919
bcmgenet_update_mib_counters(struct bcmgenet_priv * priv)920 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
921 {
922 int i, j = 0;
923
924 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
925 const struct bcmgenet_stats *s;
926 u8 offset = 0;
927 u32 val = 0;
928 char *p;
929
930 s = &bcmgenet_gstrings_stats[i];
931 switch (s->type) {
932 case BCMGENET_STAT_NETDEV:
933 case BCMGENET_STAT_SOFT:
934 continue;
935 case BCMGENET_STAT_RUNT:
936 offset += BCMGENET_STAT_OFFSET;
937 /* fall through */
938 case BCMGENET_STAT_MIB_TX:
939 offset += BCMGENET_STAT_OFFSET;
940 /* fall through */
941 case BCMGENET_STAT_MIB_RX:
942 val = bcmgenet_umac_readl(priv,
943 UMAC_MIB_START + j + offset);
944 offset = 0; /* Reset Offset */
945 break;
946 case BCMGENET_STAT_MISC:
947 if (GENET_IS_V1(priv)) {
948 val = bcmgenet_umac_readl(priv, s->reg_offset);
949 /* clear if overflowed */
950 if (val == ~0)
951 bcmgenet_umac_writel(priv, 0,
952 s->reg_offset);
953 } else {
954 val = bcmgenet_update_stat_misc(priv,
955 s->reg_offset);
956 }
957 break;
958 }
959
960 j += s->stat_sizeof;
961 p = (char *)priv + s->stat_offset;
962 *(u32 *)p = val;
963 }
964 }
965
bcmgenet_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)966 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
967 struct ethtool_stats *stats,
968 u64 *data)
969 {
970 struct bcmgenet_priv *priv = netdev_priv(dev);
971 int i;
972
973 if (netif_running(dev))
974 bcmgenet_update_mib_counters(priv);
975
976 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
977 const struct bcmgenet_stats *s;
978 char *p;
979
980 s = &bcmgenet_gstrings_stats[i];
981 if (s->type == BCMGENET_STAT_NETDEV)
982 p = (char *)&dev->stats;
983 else
984 p = (char *)priv;
985 p += s->stat_offset;
986 if (sizeof(unsigned long) != sizeof(u32) &&
987 s->stat_sizeof == sizeof(unsigned long))
988 data[i] = *(unsigned long *)p;
989 else
990 data[i] = *(u32 *)p;
991 }
992 }
993
bcmgenet_eee_enable_set(struct net_device * dev,bool enable)994 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
995 {
996 struct bcmgenet_priv *priv = netdev_priv(dev);
997 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
998 u32 reg;
999
1000 if (enable && !priv->clk_eee_enabled) {
1001 clk_prepare_enable(priv->clk_eee);
1002 priv->clk_eee_enabled = true;
1003 }
1004
1005 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
1006 if (enable)
1007 reg |= EEE_EN;
1008 else
1009 reg &= ~EEE_EN;
1010 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
1011
1012 /* Enable EEE and switch to a 27Mhz clock automatically */
1013 reg = bcmgenet_readl(priv->base + off);
1014 if (enable)
1015 reg |= TBUF_EEE_EN | TBUF_PM_EN;
1016 else
1017 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
1018 bcmgenet_writel(reg, priv->base + off);
1019
1020 /* Do the same for thing for RBUF */
1021 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
1022 if (enable)
1023 reg |= RBUF_EEE_EN | RBUF_PM_EN;
1024 else
1025 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
1026 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
1027
1028 if (!enable && priv->clk_eee_enabled) {
1029 clk_disable_unprepare(priv->clk_eee);
1030 priv->clk_eee_enabled = false;
1031 }
1032
1033 priv->eee.eee_enabled = enable;
1034 priv->eee.eee_active = enable;
1035 }
1036
bcmgenet_get_eee(struct net_device * dev,struct ethtool_eee * e)1037 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
1038 {
1039 struct bcmgenet_priv *priv = netdev_priv(dev);
1040 struct ethtool_eee *p = &priv->eee;
1041
1042 if (GENET_IS_V1(priv))
1043 return -EOPNOTSUPP;
1044
1045 e->eee_enabled = p->eee_enabled;
1046 e->eee_active = p->eee_active;
1047 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1048
1049 return phy_ethtool_get_eee(priv->phydev, e);
1050 }
1051
bcmgenet_set_eee(struct net_device * dev,struct ethtool_eee * e)1052 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
1053 {
1054 struct bcmgenet_priv *priv = netdev_priv(dev);
1055 struct ethtool_eee *p = &priv->eee;
1056 int ret = 0;
1057
1058 if (GENET_IS_V1(priv))
1059 return -EOPNOTSUPP;
1060
1061 p->eee_enabled = e->eee_enabled;
1062
1063 if (!p->eee_enabled) {
1064 bcmgenet_eee_enable_set(dev, false);
1065 } else {
1066 ret = phy_init_eee(priv->phydev, 0);
1067 if (ret) {
1068 netif_err(priv, hw, dev, "EEE initialization failed\n");
1069 return ret;
1070 }
1071
1072 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1073 bcmgenet_eee_enable_set(dev, true);
1074 }
1075
1076 return phy_ethtool_set_eee(priv->phydev, e);
1077 }
1078
1079 /* standard ethtool support functions. */
1080 static const struct ethtool_ops bcmgenet_ethtool_ops = {
1081 .begin = bcmgenet_begin,
1082 .complete = bcmgenet_complete,
1083 .get_strings = bcmgenet_get_strings,
1084 .get_sset_count = bcmgenet_get_sset_count,
1085 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
1086 .get_drvinfo = bcmgenet_get_drvinfo,
1087 .get_link = ethtool_op_get_link,
1088 .get_msglevel = bcmgenet_get_msglevel,
1089 .set_msglevel = bcmgenet_set_msglevel,
1090 .get_wol = bcmgenet_get_wol,
1091 .set_wol = bcmgenet_set_wol,
1092 .get_eee = bcmgenet_get_eee,
1093 .set_eee = bcmgenet_set_eee,
1094 .nway_reset = phy_ethtool_nway_reset,
1095 .get_coalesce = bcmgenet_get_coalesce,
1096 .set_coalesce = bcmgenet_set_coalesce,
1097 .get_link_ksettings = bcmgenet_get_link_ksettings,
1098 .set_link_ksettings = bcmgenet_set_link_ksettings,
1099 };
1100
1101 /* Power down the unimac, based on mode. */
bcmgenet_power_down(struct bcmgenet_priv * priv,enum bcmgenet_power_mode mode)1102 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1103 enum bcmgenet_power_mode mode)
1104 {
1105 int ret = 0;
1106 u32 reg;
1107
1108 switch (mode) {
1109 case GENET_POWER_CABLE_SENSE:
1110 phy_detach(priv->phydev);
1111 break;
1112
1113 case GENET_POWER_WOL_MAGIC:
1114 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1115 break;
1116
1117 case GENET_POWER_PASSIVE:
1118 /* Power down LED */
1119 if (priv->hw_params->flags & GENET_HAS_EXT) {
1120 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1121 if (GENET_IS_V5(priv))
1122 reg |= EXT_PWR_DOWN_PHY_EN |
1123 EXT_PWR_DOWN_PHY_RD |
1124 EXT_PWR_DOWN_PHY_SD |
1125 EXT_PWR_DOWN_PHY_RX |
1126 EXT_PWR_DOWN_PHY_TX |
1127 EXT_IDDQ_GLBL_PWR;
1128 else
1129 reg |= EXT_PWR_DOWN_PHY;
1130
1131 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1132 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1133
1134 bcmgenet_phy_power_set(priv->dev, false);
1135 }
1136 break;
1137 default:
1138 break;
1139 }
1140
1141 return ret;
1142 }
1143
bcmgenet_power_up(struct bcmgenet_priv * priv,enum bcmgenet_power_mode mode)1144 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1145 enum bcmgenet_power_mode mode)
1146 {
1147 u32 reg;
1148
1149 if (!(priv->hw_params->flags & GENET_HAS_EXT))
1150 return;
1151
1152 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1153
1154 switch (mode) {
1155 case GENET_POWER_PASSIVE:
1156 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1157 if (GENET_IS_V5(priv)) {
1158 reg &= ~(EXT_PWR_DOWN_PHY_EN |
1159 EXT_PWR_DOWN_PHY_RD |
1160 EXT_PWR_DOWN_PHY_SD |
1161 EXT_PWR_DOWN_PHY_RX |
1162 EXT_PWR_DOWN_PHY_TX |
1163 EXT_IDDQ_GLBL_PWR);
1164 reg |= EXT_PHY_RESET;
1165 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1166 mdelay(1);
1167
1168 reg &= ~EXT_PHY_RESET;
1169 } else {
1170 reg &= ~EXT_PWR_DOWN_PHY;
1171 reg |= EXT_PWR_DN_EN_LD;
1172 }
1173 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1174 bcmgenet_phy_power_set(priv->dev, true);
1175 bcmgenet_mii_reset(priv->dev);
1176 break;
1177
1178 case GENET_POWER_CABLE_SENSE:
1179 /* enable APD */
1180 if (!GENET_IS_V5(priv)) {
1181 reg |= EXT_PWR_DN_EN_LD;
1182 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1183 }
1184 break;
1185 case GENET_POWER_WOL_MAGIC:
1186 bcmgenet_wol_power_up_cfg(priv, mode);
1187 return;
1188 default:
1189 break;
1190 }
1191 }
1192
1193 /* ioctl handle special commands that are not present in ethtool. */
bcmgenet_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)1194 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1195 {
1196 struct bcmgenet_priv *priv = netdev_priv(dev);
1197
1198 if (!netif_running(dev))
1199 return -EINVAL;
1200
1201 if (!priv->phydev)
1202 return -ENODEV;
1203
1204 return phy_mii_ioctl(priv->phydev, rq, cmd);
1205 }
1206
bcmgenet_get_txcb(struct bcmgenet_priv * priv,struct bcmgenet_tx_ring * ring)1207 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1208 struct bcmgenet_tx_ring *ring)
1209 {
1210 struct enet_cb *tx_cb_ptr;
1211
1212 tx_cb_ptr = ring->cbs;
1213 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1214
1215 /* Advancing local write pointer */
1216 if (ring->write_ptr == ring->end_ptr)
1217 ring->write_ptr = ring->cb_ptr;
1218 else
1219 ring->write_ptr++;
1220
1221 return tx_cb_ptr;
1222 }
1223
bcmgenet_put_txcb(struct bcmgenet_priv * priv,struct bcmgenet_tx_ring * ring)1224 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1225 struct bcmgenet_tx_ring *ring)
1226 {
1227 struct enet_cb *tx_cb_ptr;
1228
1229 tx_cb_ptr = ring->cbs;
1230 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1231
1232 /* Rewinding local write pointer */
1233 if (ring->write_ptr == ring->cb_ptr)
1234 ring->write_ptr = ring->end_ptr;
1235 else
1236 ring->write_ptr--;
1237
1238 return tx_cb_ptr;
1239 }
1240
bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring * ring)1241 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1242 {
1243 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1244 INTRL2_CPU_MASK_SET);
1245 }
1246
bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring * ring)1247 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1248 {
1249 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1250 INTRL2_CPU_MASK_CLEAR);
1251 }
1252
bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring * ring)1253 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1254 {
1255 bcmgenet_intrl2_1_writel(ring->priv,
1256 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1257 INTRL2_CPU_MASK_SET);
1258 }
1259
bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring * ring)1260 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1261 {
1262 bcmgenet_intrl2_1_writel(ring->priv,
1263 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1264 INTRL2_CPU_MASK_CLEAR);
1265 }
1266
bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring * ring)1267 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1268 {
1269 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1270 INTRL2_CPU_MASK_SET);
1271 }
1272
bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring * ring)1273 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1274 {
1275 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1276 INTRL2_CPU_MASK_CLEAR);
1277 }
1278
bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring * ring)1279 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1280 {
1281 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1282 INTRL2_CPU_MASK_CLEAR);
1283 }
1284
bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring * ring)1285 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1286 {
1287 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1288 INTRL2_CPU_MASK_SET);
1289 }
1290
1291 /* Simple helper to free a transmit control block's resources
1292 * Returns an skb when the last transmit control block associated with the
1293 * skb is freed. The skb should be freed by the caller if necessary.
1294 */
bcmgenet_free_tx_cb(struct device * dev,struct enet_cb * cb)1295 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1296 struct enet_cb *cb)
1297 {
1298 struct sk_buff *skb;
1299
1300 skb = cb->skb;
1301
1302 if (skb) {
1303 cb->skb = NULL;
1304 if (cb == GENET_CB(skb)->first_cb)
1305 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1306 dma_unmap_len(cb, dma_len),
1307 DMA_TO_DEVICE);
1308 else
1309 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1310 dma_unmap_len(cb, dma_len),
1311 DMA_TO_DEVICE);
1312 dma_unmap_addr_set(cb, dma_addr, 0);
1313
1314 if (cb == GENET_CB(skb)->last_cb)
1315 return skb;
1316
1317 } else if (dma_unmap_addr(cb, dma_addr)) {
1318 dma_unmap_page(dev,
1319 dma_unmap_addr(cb, dma_addr),
1320 dma_unmap_len(cb, dma_len),
1321 DMA_TO_DEVICE);
1322 dma_unmap_addr_set(cb, dma_addr, 0);
1323 }
1324
1325 return 0;
1326 }
1327
1328 /* Simple helper to free a receive control block's resources */
bcmgenet_free_rx_cb(struct device * dev,struct enet_cb * cb)1329 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1330 struct enet_cb *cb)
1331 {
1332 struct sk_buff *skb;
1333
1334 skb = cb->skb;
1335 cb->skb = NULL;
1336
1337 if (dma_unmap_addr(cb, dma_addr)) {
1338 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1339 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1340 dma_unmap_addr_set(cb, dma_addr, 0);
1341 }
1342
1343 return skb;
1344 }
1345
1346 /* Unlocked version of the reclaim routine */
__bcmgenet_tx_reclaim(struct net_device * dev,struct bcmgenet_tx_ring * ring)1347 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1348 struct bcmgenet_tx_ring *ring)
1349 {
1350 struct bcmgenet_priv *priv = netdev_priv(dev);
1351 unsigned int txbds_processed = 0;
1352 unsigned int bytes_compl = 0;
1353 unsigned int pkts_compl = 0;
1354 unsigned int txbds_ready;
1355 unsigned int c_index;
1356 struct sk_buff *skb;
1357
1358 /* Clear status before servicing to reduce spurious interrupts */
1359 if (ring->index == DESC_INDEX)
1360 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1361 INTRL2_CPU_CLEAR);
1362 else
1363 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1364 INTRL2_CPU_CLEAR);
1365
1366 /* Compute how many buffers are transmitted since last xmit call */
1367 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1368 & DMA_C_INDEX_MASK;
1369 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1370
1371 netif_dbg(priv, tx_done, dev,
1372 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1373 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1374
1375 /* Reclaim transmitted buffers */
1376 while (txbds_processed < txbds_ready) {
1377 skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1378 &priv->tx_cbs[ring->clean_ptr]);
1379 if (skb) {
1380 pkts_compl++;
1381 bytes_compl += GENET_CB(skb)->bytes_sent;
1382 dev_consume_skb_any(skb);
1383 }
1384
1385 txbds_processed++;
1386 if (likely(ring->clean_ptr < ring->end_ptr))
1387 ring->clean_ptr++;
1388 else
1389 ring->clean_ptr = ring->cb_ptr;
1390 }
1391
1392 ring->free_bds += txbds_processed;
1393 ring->c_index = c_index;
1394
1395 ring->packets += pkts_compl;
1396 ring->bytes += bytes_compl;
1397
1398 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
1399 pkts_compl, bytes_compl);
1400
1401 return txbds_processed;
1402 }
1403
bcmgenet_tx_reclaim(struct net_device * dev,struct bcmgenet_tx_ring * ring)1404 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1405 struct bcmgenet_tx_ring *ring)
1406 {
1407 unsigned int released;
1408 unsigned long flags;
1409
1410 spin_lock_irqsave(&ring->lock, flags);
1411 released = __bcmgenet_tx_reclaim(dev, ring);
1412 spin_unlock_irqrestore(&ring->lock, flags);
1413
1414 return released;
1415 }
1416
bcmgenet_tx_poll(struct napi_struct * napi,int budget)1417 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1418 {
1419 struct bcmgenet_tx_ring *ring =
1420 container_of(napi, struct bcmgenet_tx_ring, napi);
1421 unsigned int work_done = 0;
1422 struct netdev_queue *txq;
1423 unsigned long flags;
1424
1425 spin_lock_irqsave(&ring->lock, flags);
1426 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1427 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1428 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
1429 netif_tx_wake_queue(txq);
1430 }
1431 spin_unlock_irqrestore(&ring->lock, flags);
1432
1433 if (work_done == 0) {
1434 napi_complete(napi);
1435 ring->int_enable(ring);
1436
1437 return 0;
1438 }
1439
1440 return budget;
1441 }
1442
bcmgenet_tx_reclaim_all(struct net_device * dev)1443 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1444 {
1445 struct bcmgenet_priv *priv = netdev_priv(dev);
1446 int i;
1447
1448 if (netif_is_multiqueue(dev)) {
1449 for (i = 0; i < priv->hw_params->tx_queues; i++)
1450 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1451 }
1452
1453 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1454 }
1455
1456 /* Reallocate the SKB to put enough headroom in front of it and insert
1457 * the transmit checksum offsets in the descriptors
1458 */
bcmgenet_put_tx_csum(struct net_device * dev,struct sk_buff * skb)1459 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1460 struct sk_buff *skb)
1461 {
1462 struct status_64 *status = NULL;
1463 struct sk_buff *new_skb;
1464 u16 offset;
1465 u8 ip_proto;
1466 u16 ip_ver;
1467 u32 tx_csum_info;
1468
1469 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1470 /* If 64 byte status block enabled, must make sure skb has
1471 * enough headroom for us to insert 64B status block.
1472 */
1473 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1474 dev_kfree_skb(skb);
1475 if (!new_skb) {
1476 dev->stats.tx_dropped++;
1477 return NULL;
1478 }
1479 skb = new_skb;
1480 }
1481
1482 skb_push(skb, sizeof(*status));
1483 status = (struct status_64 *)skb->data;
1484
1485 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1486 ip_ver = htons(skb->protocol);
1487 switch (ip_ver) {
1488 case ETH_P_IP:
1489 ip_proto = ip_hdr(skb)->protocol;
1490 break;
1491 case ETH_P_IPV6:
1492 ip_proto = ipv6_hdr(skb)->nexthdr;
1493 break;
1494 default:
1495 return skb;
1496 }
1497
1498 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1499 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1500 (offset + skb->csum_offset);
1501
1502 /* Set the length valid bit for TCP and UDP and just set
1503 * the special UDP flag for IPv4, else just set to 0.
1504 */
1505 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1506 tx_csum_info |= STATUS_TX_CSUM_LV;
1507 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1508 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1509 } else {
1510 tx_csum_info = 0;
1511 }
1512
1513 status->tx_csum_info = tx_csum_info;
1514 }
1515
1516 return skb;
1517 }
1518
bcmgenet_xmit(struct sk_buff * skb,struct net_device * dev)1519 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1520 {
1521 struct bcmgenet_priv *priv = netdev_priv(dev);
1522 struct device *kdev = &priv->pdev->dev;
1523 struct bcmgenet_tx_ring *ring = NULL;
1524 struct enet_cb *tx_cb_ptr;
1525 struct netdev_queue *txq;
1526 unsigned long flags = 0;
1527 int nr_frags, index;
1528 dma_addr_t mapping;
1529 unsigned int size;
1530 skb_frag_t *frag;
1531 u32 len_stat;
1532 int ret;
1533 int i;
1534
1535 index = skb_get_queue_mapping(skb);
1536 /* Mapping strategy:
1537 * queue_mapping = 0, unclassified, packet xmited through ring16
1538 * queue_mapping = 1, goes to ring 0. (highest priority queue
1539 * queue_mapping = 2, goes to ring 1.
1540 * queue_mapping = 3, goes to ring 2.
1541 * queue_mapping = 4, goes to ring 3.
1542 */
1543 if (index == 0)
1544 index = DESC_INDEX;
1545 else
1546 index -= 1;
1547
1548 ring = &priv->tx_rings[index];
1549 txq = netdev_get_tx_queue(dev, ring->queue);
1550
1551 nr_frags = skb_shinfo(skb)->nr_frags;
1552
1553 spin_lock_irqsave(&ring->lock, flags);
1554 if (ring->free_bds <= (nr_frags + 1)) {
1555 if (!netif_tx_queue_stopped(txq)) {
1556 netif_tx_stop_queue(txq);
1557 netdev_err(dev,
1558 "%s: tx ring %d full when queue %d awake\n",
1559 __func__, index, ring->queue);
1560 }
1561 ret = NETDEV_TX_BUSY;
1562 goto out;
1563 }
1564
1565 if (skb_padto(skb, ETH_ZLEN)) {
1566 ret = NETDEV_TX_OK;
1567 goto out;
1568 }
1569
1570 /* Retain how many bytes will be sent on the wire, without TSB inserted
1571 * by transmit checksum offload
1572 */
1573 GENET_CB(skb)->bytes_sent = skb->len;
1574
1575 /* set the SKB transmit checksum */
1576 if (priv->desc_64b_en) {
1577 skb = bcmgenet_put_tx_csum(dev, skb);
1578 if (!skb) {
1579 ret = NETDEV_TX_OK;
1580 goto out;
1581 }
1582 }
1583
1584 for (i = 0; i <= nr_frags; i++) {
1585 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1586
1587 if (unlikely(!tx_cb_ptr))
1588 BUG();
1589
1590 if (!i) {
1591 /* Transmit single SKB or head of fragment list */
1592 GENET_CB(skb)->first_cb = tx_cb_ptr;
1593 size = skb_headlen(skb);
1594 mapping = dma_map_single(kdev, skb->data, size,
1595 DMA_TO_DEVICE);
1596 } else {
1597 /* xmit fragment */
1598 frag = &skb_shinfo(skb)->frags[i - 1];
1599 size = skb_frag_size(frag);
1600 mapping = skb_frag_dma_map(kdev, frag, 0, size,
1601 DMA_TO_DEVICE);
1602 }
1603
1604 ret = dma_mapping_error(kdev, mapping);
1605 if (ret) {
1606 priv->mib.tx_dma_failed++;
1607 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1608 ret = NETDEV_TX_OK;
1609 goto out_unmap_frags;
1610 }
1611 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1612 dma_unmap_len_set(tx_cb_ptr, dma_len, size);
1613
1614 tx_cb_ptr->skb = skb;
1615
1616 len_stat = (size << DMA_BUFLENGTH_SHIFT) |
1617 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
1618
1619 if (!i) {
1620 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP;
1621 if (skb->ip_summed == CHECKSUM_PARTIAL)
1622 len_stat |= DMA_TX_DO_CSUM;
1623 }
1624 if (i == nr_frags)
1625 len_stat |= DMA_EOP;
1626
1627 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
1628 }
1629
1630 GENET_CB(skb)->last_cb = tx_cb_ptr;
1631 skb_tx_timestamp(skb);
1632
1633 /* Decrement total BD count and advance our write pointer */
1634 ring->free_bds -= nr_frags + 1;
1635 ring->prod_index += nr_frags + 1;
1636 ring->prod_index &= DMA_P_INDEX_MASK;
1637
1638 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
1639
1640 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1641 netif_tx_stop_queue(txq);
1642
1643 if (!skb->xmit_more || netif_xmit_stopped(txq))
1644 /* Packets are ready, update producer index */
1645 bcmgenet_tdma_ring_writel(priv, ring->index,
1646 ring->prod_index, TDMA_PROD_INDEX);
1647 out:
1648 spin_unlock_irqrestore(&ring->lock, flags);
1649
1650 return ret;
1651
1652 out_unmap_frags:
1653 /* Back up for failed control block mapping */
1654 bcmgenet_put_txcb(priv, ring);
1655
1656 /* Unmap successfully mapped control blocks */
1657 while (i-- > 0) {
1658 tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
1659 bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
1660 }
1661
1662 dev_kfree_skb(skb);
1663 goto out;
1664 }
1665
bcmgenet_rx_refill(struct bcmgenet_priv * priv,struct enet_cb * cb)1666 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1667 struct enet_cb *cb)
1668 {
1669 struct device *kdev = &priv->pdev->dev;
1670 struct sk_buff *skb;
1671 struct sk_buff *rx_skb;
1672 dma_addr_t mapping;
1673
1674 /* Allocate a new Rx skb */
1675 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1676 if (!skb) {
1677 priv->mib.alloc_rx_buff_failed++;
1678 netif_err(priv, rx_err, priv->dev,
1679 "%s: Rx skb allocation failed\n", __func__);
1680 return NULL;
1681 }
1682
1683 /* DMA-map the new Rx skb */
1684 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1685 DMA_FROM_DEVICE);
1686 if (dma_mapping_error(kdev, mapping)) {
1687 priv->mib.rx_dma_failed++;
1688 dev_kfree_skb_any(skb);
1689 netif_err(priv, rx_err, priv->dev,
1690 "%s: Rx skb DMA mapping failed\n", __func__);
1691 return NULL;
1692 }
1693
1694 /* Grab the current Rx skb from the ring and DMA-unmap it */
1695 rx_skb = bcmgenet_free_rx_cb(kdev, cb);
1696
1697 /* Put the new Rx skb on the ring */
1698 cb->skb = skb;
1699 dma_unmap_addr_set(cb, dma_addr, mapping);
1700 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
1701 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1702
1703 /* Return the current Rx skb to caller */
1704 return rx_skb;
1705 }
1706
1707 /* bcmgenet_desc_rx - descriptor based rx process.
1708 * this could be called from bottom half, or from NAPI polling method.
1709 */
bcmgenet_desc_rx(struct bcmgenet_rx_ring * ring,unsigned int budget)1710 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1711 unsigned int budget)
1712 {
1713 struct bcmgenet_priv *priv = ring->priv;
1714 struct net_device *dev = priv->dev;
1715 struct enet_cb *cb;
1716 struct sk_buff *skb;
1717 u32 dma_length_status;
1718 unsigned long dma_flag;
1719 int len;
1720 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1721 unsigned int p_index, mask;
1722 unsigned int discards;
1723 unsigned int chksum_ok = 0;
1724
1725 /* Clear status before servicing to reduce spurious interrupts */
1726 if (ring->index == DESC_INDEX) {
1727 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
1728 INTRL2_CPU_CLEAR);
1729 } else {
1730 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
1731 bcmgenet_intrl2_1_writel(priv,
1732 mask,
1733 INTRL2_CPU_CLEAR);
1734 }
1735
1736 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1737
1738 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1739 DMA_P_INDEX_DISCARD_CNT_MASK;
1740 if (discards > ring->old_discards) {
1741 discards = discards - ring->old_discards;
1742 ring->errors += discards;
1743 ring->old_discards += discards;
1744
1745 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1746 if (ring->old_discards >= 0xC000) {
1747 ring->old_discards = 0;
1748 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1749 RDMA_PROD_INDEX);
1750 }
1751 }
1752
1753 p_index &= DMA_P_INDEX_MASK;
1754 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
1755
1756 netif_dbg(priv, rx_status, dev,
1757 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1758
1759 while ((rxpktprocessed < rxpkttoprocess) &&
1760 (rxpktprocessed < budget)) {
1761 cb = &priv->rx_cbs[ring->read_ptr];
1762 skb = bcmgenet_rx_refill(priv, cb);
1763
1764 if (unlikely(!skb)) {
1765 ring->dropped++;
1766 goto next;
1767 }
1768
1769 if (!priv->desc_64b_en) {
1770 dma_length_status =
1771 dmadesc_get_length_status(priv, cb->bd_addr);
1772 } else {
1773 struct status_64 *status;
1774
1775 status = (struct status_64 *)skb->data;
1776 dma_length_status = status->length_status;
1777 }
1778
1779 /* DMA flags and length are still valid no matter how
1780 * we got the Receive Status Vector (64B RSB or register)
1781 */
1782 dma_flag = dma_length_status & 0xffff;
1783 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1784
1785 netif_dbg(priv, rx_status, dev,
1786 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1787 __func__, p_index, ring->c_index,
1788 ring->read_ptr, dma_length_status);
1789
1790 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1791 netif_err(priv, rx_status, dev,
1792 "dropping fragmented packet!\n");
1793 ring->errors++;
1794 dev_kfree_skb_any(skb);
1795 goto next;
1796 }
1797
1798 /* report errors */
1799 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1800 DMA_RX_OV |
1801 DMA_RX_NO |
1802 DMA_RX_LG |
1803 DMA_RX_RXER))) {
1804 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1805 (unsigned int)dma_flag);
1806 if (dma_flag & DMA_RX_CRC_ERROR)
1807 dev->stats.rx_crc_errors++;
1808 if (dma_flag & DMA_RX_OV)
1809 dev->stats.rx_over_errors++;
1810 if (dma_flag & DMA_RX_NO)
1811 dev->stats.rx_frame_errors++;
1812 if (dma_flag & DMA_RX_LG)
1813 dev->stats.rx_length_errors++;
1814 dev->stats.rx_errors++;
1815 dev_kfree_skb_any(skb);
1816 goto next;
1817 } /* error packet */
1818
1819 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1820 priv->desc_rxchk_en;
1821
1822 skb_put(skb, len);
1823 if (priv->desc_64b_en) {
1824 skb_pull(skb, 64);
1825 len -= 64;
1826 }
1827
1828 if (likely(chksum_ok))
1829 skb->ip_summed = CHECKSUM_UNNECESSARY;
1830
1831 /* remove hardware 2bytes added for IP alignment */
1832 skb_pull(skb, 2);
1833 len -= 2;
1834
1835 if (priv->crc_fwd_en) {
1836 skb_trim(skb, len - ETH_FCS_LEN);
1837 len -= ETH_FCS_LEN;
1838 }
1839
1840 /*Finish setting up the received SKB and send it to the kernel*/
1841 skb->protocol = eth_type_trans(skb, priv->dev);
1842 ring->packets++;
1843 ring->bytes += len;
1844 if (dma_flag & DMA_RX_MULT)
1845 dev->stats.multicast++;
1846
1847 /* Notify kernel */
1848 napi_gro_receive(&ring->napi, skb);
1849 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1850
1851 next:
1852 rxpktprocessed++;
1853 if (likely(ring->read_ptr < ring->end_ptr))
1854 ring->read_ptr++;
1855 else
1856 ring->read_ptr = ring->cb_ptr;
1857
1858 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1859 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1860 }
1861
1862 return rxpktprocessed;
1863 }
1864
1865 /* Rx NAPI polling method */
bcmgenet_rx_poll(struct napi_struct * napi,int budget)1866 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1867 {
1868 struct bcmgenet_rx_ring *ring = container_of(napi,
1869 struct bcmgenet_rx_ring, napi);
1870 unsigned int work_done;
1871
1872 work_done = bcmgenet_desc_rx(ring, budget);
1873
1874 if (work_done < budget) {
1875 napi_complete_done(napi, work_done);
1876 ring->int_enable(ring);
1877 }
1878
1879 return work_done;
1880 }
1881
1882 /* Assign skb to RX DMA descriptor. */
bcmgenet_alloc_rx_buffers(struct bcmgenet_priv * priv,struct bcmgenet_rx_ring * ring)1883 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1884 struct bcmgenet_rx_ring *ring)
1885 {
1886 struct enet_cb *cb;
1887 struct sk_buff *skb;
1888 int i;
1889
1890 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1891
1892 /* loop here for each buffer needing assign */
1893 for (i = 0; i < ring->size; i++) {
1894 cb = ring->cbs + i;
1895 skb = bcmgenet_rx_refill(priv, cb);
1896 if (skb)
1897 dev_consume_skb_any(skb);
1898 if (!cb->skb)
1899 return -ENOMEM;
1900 }
1901
1902 return 0;
1903 }
1904
bcmgenet_free_rx_buffers(struct bcmgenet_priv * priv)1905 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1906 {
1907 struct sk_buff *skb;
1908 struct enet_cb *cb;
1909 int i;
1910
1911 for (i = 0; i < priv->num_rx_bds; i++) {
1912 cb = &priv->rx_cbs[i];
1913
1914 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
1915 if (skb)
1916 dev_consume_skb_any(skb);
1917 }
1918 }
1919
umac_enable_set(struct bcmgenet_priv * priv,u32 mask,bool enable)1920 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1921 {
1922 u32 reg;
1923
1924 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1925 if (enable)
1926 reg |= mask;
1927 else
1928 reg &= ~mask;
1929 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1930
1931 /* UniMAC stops on a packet boundary, wait for a full-size packet
1932 * to be processed
1933 */
1934 if (enable == 0)
1935 usleep_range(1000, 2000);
1936 }
1937
reset_umac(struct bcmgenet_priv * priv)1938 static int reset_umac(struct bcmgenet_priv *priv)
1939 {
1940 struct device *kdev = &priv->pdev->dev;
1941 unsigned int timeout = 0;
1942 u32 reg;
1943
1944 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1945 bcmgenet_rbuf_ctrl_set(priv, 0);
1946 udelay(10);
1947
1948 /* disable MAC while updating its registers */
1949 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1950
1951 /* issue soft reset, wait for it to complete */
1952 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1953 while (timeout++ < 1000) {
1954 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1955 if (!(reg & CMD_SW_RESET))
1956 return 0;
1957
1958 udelay(1);
1959 }
1960
1961 if (timeout == 1000) {
1962 dev_err(kdev,
1963 "timeout waiting for MAC to come out of reset\n");
1964 return -ETIMEDOUT;
1965 }
1966
1967 return 0;
1968 }
1969
bcmgenet_intr_disable(struct bcmgenet_priv * priv)1970 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1971 {
1972 /* Mask all interrupts.*/
1973 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1974 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1975 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1976 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1977 }
1978
bcmgenet_link_intr_enable(struct bcmgenet_priv * priv)1979 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
1980 {
1981 u32 int0_enable = 0;
1982
1983 /* Monitor cable plug/unplugged event for internal PHY, external PHY
1984 * and MoCA PHY
1985 */
1986 if (priv->internal_phy) {
1987 int0_enable |= UMAC_IRQ_LINK_EVENT;
1988 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
1989 int0_enable |= UMAC_IRQ_PHY_DET_R;
1990 } else if (priv->ext_phy) {
1991 int0_enable |= UMAC_IRQ_LINK_EVENT;
1992 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1993 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
1994 int0_enable |= UMAC_IRQ_LINK_EVENT;
1995 }
1996 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1997 }
1998
init_umac(struct bcmgenet_priv * priv)1999 static int init_umac(struct bcmgenet_priv *priv)
2000 {
2001 struct device *kdev = &priv->pdev->dev;
2002 int ret;
2003 u32 reg;
2004 u32 int0_enable = 0;
2005
2006 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
2007
2008 ret = reset_umac(priv);
2009 if (ret)
2010 return ret;
2011
2012 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
2013 /* clear tx/rx counter */
2014 bcmgenet_umac_writel(priv,
2015 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
2016 UMAC_MIB_CTRL);
2017 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
2018
2019 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2020
2021 /* init rx registers, enable ip header optimization */
2022 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
2023 reg |= RBUF_ALIGN_2B;
2024 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
2025
2026 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
2027 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
2028
2029 bcmgenet_intr_disable(priv);
2030
2031 /* Configure backpressure vectors for MoCA */
2032 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2033 reg = bcmgenet_bp_mc_get(priv);
2034 reg |= BIT(priv->hw_params->bp_in_en_shift);
2035
2036 /* bp_mask: back pressure mask */
2037 if (netif_is_multiqueue(priv->dev))
2038 reg |= priv->hw_params->bp_in_mask;
2039 else
2040 reg &= ~priv->hw_params->bp_in_mask;
2041 bcmgenet_bp_mc_set(priv, reg);
2042 }
2043
2044 /* Enable MDIO interrupts on GENET v3+ */
2045 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
2046 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2047
2048 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2049
2050 dev_dbg(kdev, "done init umac\n");
2051
2052 return 0;
2053 }
2054
2055 /* Initialize a Tx ring along with corresponding hardware registers */
bcmgenet_init_tx_ring(struct bcmgenet_priv * priv,unsigned int index,unsigned int size,unsigned int start_ptr,unsigned int end_ptr)2056 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2057 unsigned int index, unsigned int size,
2058 unsigned int start_ptr, unsigned int end_ptr)
2059 {
2060 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2061 u32 words_per_bd = WORDS_PER_BD(priv);
2062 u32 flow_period_val = 0;
2063
2064 spin_lock_init(&ring->lock);
2065 ring->priv = priv;
2066 ring->index = index;
2067 if (index == DESC_INDEX) {
2068 ring->queue = 0;
2069 ring->int_enable = bcmgenet_tx_ring16_int_enable;
2070 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2071 } else {
2072 ring->queue = index + 1;
2073 ring->int_enable = bcmgenet_tx_ring_int_enable;
2074 ring->int_disable = bcmgenet_tx_ring_int_disable;
2075 }
2076 ring->cbs = priv->tx_cbs + start_ptr;
2077 ring->size = size;
2078 ring->clean_ptr = start_ptr;
2079 ring->c_index = 0;
2080 ring->free_bds = size;
2081 ring->write_ptr = start_ptr;
2082 ring->cb_ptr = start_ptr;
2083 ring->end_ptr = end_ptr - 1;
2084 ring->prod_index = 0;
2085
2086 /* Set flow period for ring != 16 */
2087 if (index != DESC_INDEX)
2088 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2089
2090 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2091 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2092 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2093 /* Disable rate control for now */
2094 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
2095 TDMA_FLOW_PERIOD);
2096 bcmgenet_tdma_ring_writel(priv, index,
2097 ((size << DMA_RING_SIZE_SHIFT) |
2098 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2099
2100 /* Set start and end address, read and write pointers */
2101 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2102 DMA_START_ADDR);
2103 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2104 TDMA_READ_PTR);
2105 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2106 TDMA_WRITE_PTR);
2107 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2108 DMA_END_ADDR);
2109 }
2110
2111 /* Initialize a RDMA ring */
bcmgenet_init_rx_ring(struct bcmgenet_priv * priv,unsigned int index,unsigned int size,unsigned int start_ptr,unsigned int end_ptr)2112 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2113 unsigned int index, unsigned int size,
2114 unsigned int start_ptr, unsigned int end_ptr)
2115 {
2116 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2117 u32 words_per_bd = WORDS_PER_BD(priv);
2118 int ret;
2119
2120 ring->priv = priv;
2121 ring->index = index;
2122 if (index == DESC_INDEX) {
2123 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2124 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2125 } else {
2126 ring->int_enable = bcmgenet_rx_ring_int_enable;
2127 ring->int_disable = bcmgenet_rx_ring_int_disable;
2128 }
2129 ring->cbs = priv->rx_cbs + start_ptr;
2130 ring->size = size;
2131 ring->c_index = 0;
2132 ring->read_ptr = start_ptr;
2133 ring->cb_ptr = start_ptr;
2134 ring->end_ptr = end_ptr - 1;
2135
2136 ret = bcmgenet_alloc_rx_buffers(priv, ring);
2137 if (ret)
2138 return ret;
2139
2140 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2141 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2142 bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2143 bcmgenet_rdma_ring_writel(priv, index,
2144 ((size << DMA_RING_SIZE_SHIFT) |
2145 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2146 bcmgenet_rdma_ring_writel(priv, index,
2147 (DMA_FC_THRESH_LO <<
2148 DMA_XOFF_THRESHOLD_SHIFT) |
2149 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2150
2151 /* Set start and end address, read and write pointers */
2152 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2153 DMA_START_ADDR);
2154 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2155 RDMA_READ_PTR);
2156 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2157 RDMA_WRITE_PTR);
2158 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2159 DMA_END_ADDR);
2160
2161 return ret;
2162 }
2163
bcmgenet_init_tx_napi(struct bcmgenet_priv * priv)2164 static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv)
2165 {
2166 unsigned int i;
2167 struct bcmgenet_tx_ring *ring;
2168
2169 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2170 ring = &priv->tx_rings[i];
2171 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2172 }
2173
2174 ring = &priv->tx_rings[DESC_INDEX];
2175 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2176 }
2177
bcmgenet_enable_tx_napi(struct bcmgenet_priv * priv)2178 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2179 {
2180 unsigned int i;
2181 u32 int0_enable = UMAC_IRQ_TXDMA_DONE;
2182 u32 int1_enable = 0;
2183 struct bcmgenet_tx_ring *ring;
2184
2185 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2186 ring = &priv->tx_rings[i];
2187 napi_enable(&ring->napi);
2188 int1_enable |= (1 << i);
2189 }
2190
2191 ring = &priv->tx_rings[DESC_INDEX];
2192 napi_enable(&ring->napi);
2193
2194 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2195 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
2196 }
2197
bcmgenet_disable_tx_napi(struct bcmgenet_priv * priv)2198 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2199 {
2200 unsigned int i;
2201 u32 int0_disable = UMAC_IRQ_TXDMA_DONE;
2202 u32 int1_disable = 0xffff;
2203 struct bcmgenet_tx_ring *ring;
2204
2205 bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET);
2206 bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET);
2207
2208 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2209 ring = &priv->tx_rings[i];
2210 napi_disable(&ring->napi);
2211 }
2212
2213 ring = &priv->tx_rings[DESC_INDEX];
2214 napi_disable(&ring->napi);
2215 }
2216
bcmgenet_fini_tx_napi(struct bcmgenet_priv * priv)2217 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2218 {
2219 unsigned int i;
2220 struct bcmgenet_tx_ring *ring;
2221
2222 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2223 ring = &priv->tx_rings[i];
2224 netif_napi_del(&ring->napi);
2225 }
2226
2227 ring = &priv->tx_rings[DESC_INDEX];
2228 netif_napi_del(&ring->napi);
2229 }
2230
2231 /* Initialize Tx queues
2232 *
2233 * Queues 0-3 are priority-based, each one has 32 descriptors,
2234 * with queue 0 being the highest priority queue.
2235 *
2236 * Queue 16 is the default Tx queue with
2237 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2238 *
2239 * The transmit control block pool is then partitioned as follows:
2240 * - Tx queue 0 uses tx_cbs[0..31]
2241 * - Tx queue 1 uses tx_cbs[32..63]
2242 * - Tx queue 2 uses tx_cbs[64..95]
2243 * - Tx queue 3 uses tx_cbs[96..127]
2244 * - Tx queue 16 uses tx_cbs[128..255]
2245 */
bcmgenet_init_tx_queues(struct net_device * dev)2246 static void bcmgenet_init_tx_queues(struct net_device *dev)
2247 {
2248 struct bcmgenet_priv *priv = netdev_priv(dev);
2249 u32 i, dma_enable;
2250 u32 dma_ctrl, ring_cfg;
2251 u32 dma_priority[3] = {0, 0, 0};
2252
2253 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2254 dma_enable = dma_ctrl & DMA_EN;
2255 dma_ctrl &= ~DMA_EN;
2256 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2257
2258 dma_ctrl = 0;
2259 ring_cfg = 0;
2260
2261 /* Enable strict priority arbiter mode */
2262 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2263
2264 /* Initialize Tx priority queues */
2265 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2266 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2267 i * priv->hw_params->tx_bds_per_q,
2268 (i + 1) * priv->hw_params->tx_bds_per_q);
2269 ring_cfg |= (1 << i);
2270 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2271 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2272 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2273 }
2274
2275 /* Initialize Tx default queue 16 */
2276 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2277 priv->hw_params->tx_queues *
2278 priv->hw_params->tx_bds_per_q,
2279 TOTAL_DESC);
2280 ring_cfg |= (1 << DESC_INDEX);
2281 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2282 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2283 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2284 DMA_PRIO_REG_SHIFT(DESC_INDEX));
2285
2286 /* Set Tx queue priorities */
2287 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2288 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2289 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2290
2291 /* Initialize Tx NAPI */
2292 bcmgenet_init_tx_napi(priv);
2293
2294 /* Enable Tx queues */
2295 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2296
2297 /* Enable Tx DMA */
2298 if (dma_enable)
2299 dma_ctrl |= DMA_EN;
2300 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2301 }
2302
bcmgenet_init_rx_napi(struct bcmgenet_priv * priv)2303 static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv)
2304 {
2305 unsigned int i;
2306 struct bcmgenet_rx_ring *ring;
2307
2308 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2309 ring = &priv->rx_rings[i];
2310 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2311 }
2312
2313 ring = &priv->rx_rings[DESC_INDEX];
2314 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2315 }
2316
bcmgenet_enable_rx_napi(struct bcmgenet_priv * priv)2317 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2318 {
2319 unsigned int i;
2320 u32 int0_enable = UMAC_IRQ_RXDMA_DONE;
2321 u32 int1_enable = 0;
2322 struct bcmgenet_rx_ring *ring;
2323
2324 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2325 ring = &priv->rx_rings[i];
2326 napi_enable(&ring->napi);
2327 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i));
2328 }
2329
2330 ring = &priv->rx_rings[DESC_INDEX];
2331 napi_enable(&ring->napi);
2332
2333 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2334 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
2335 }
2336
bcmgenet_disable_rx_napi(struct bcmgenet_priv * priv)2337 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2338 {
2339 unsigned int i;
2340 u32 int0_disable = UMAC_IRQ_RXDMA_DONE;
2341 u32 int1_disable = 0xffff << UMAC_IRQ1_RX_INTR_SHIFT;
2342 struct bcmgenet_rx_ring *ring;
2343
2344 bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET);
2345 bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET);
2346
2347 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2348 ring = &priv->rx_rings[i];
2349 napi_disable(&ring->napi);
2350 }
2351
2352 ring = &priv->rx_rings[DESC_INDEX];
2353 napi_disable(&ring->napi);
2354 }
2355
bcmgenet_fini_rx_napi(struct bcmgenet_priv * priv)2356 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2357 {
2358 unsigned int i;
2359 struct bcmgenet_rx_ring *ring;
2360
2361 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2362 ring = &priv->rx_rings[i];
2363 netif_napi_del(&ring->napi);
2364 }
2365
2366 ring = &priv->rx_rings[DESC_INDEX];
2367 netif_napi_del(&ring->napi);
2368 }
2369
2370 /* Initialize Rx queues
2371 *
2372 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2373 * used to direct traffic to these queues.
2374 *
2375 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2376 */
bcmgenet_init_rx_queues(struct net_device * dev)2377 static int bcmgenet_init_rx_queues(struct net_device *dev)
2378 {
2379 struct bcmgenet_priv *priv = netdev_priv(dev);
2380 u32 i;
2381 u32 dma_enable;
2382 u32 dma_ctrl;
2383 u32 ring_cfg;
2384 int ret;
2385
2386 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2387 dma_enable = dma_ctrl & DMA_EN;
2388 dma_ctrl &= ~DMA_EN;
2389 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2390
2391 dma_ctrl = 0;
2392 ring_cfg = 0;
2393
2394 /* Initialize Rx priority queues */
2395 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2396 ret = bcmgenet_init_rx_ring(priv, i,
2397 priv->hw_params->rx_bds_per_q,
2398 i * priv->hw_params->rx_bds_per_q,
2399 (i + 1) *
2400 priv->hw_params->rx_bds_per_q);
2401 if (ret)
2402 return ret;
2403
2404 ring_cfg |= (1 << i);
2405 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2406 }
2407
2408 /* Initialize Rx default queue 16 */
2409 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2410 priv->hw_params->rx_queues *
2411 priv->hw_params->rx_bds_per_q,
2412 TOTAL_DESC);
2413 if (ret)
2414 return ret;
2415
2416 ring_cfg |= (1 << DESC_INDEX);
2417 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2418
2419 /* Initialize Rx NAPI */
2420 bcmgenet_init_rx_napi(priv);
2421
2422 /* Enable rings */
2423 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2424
2425 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2426 if (dma_enable)
2427 dma_ctrl |= DMA_EN;
2428 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2429
2430 return 0;
2431 }
2432
bcmgenet_dma_teardown(struct bcmgenet_priv * priv)2433 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2434 {
2435 int ret = 0;
2436 int timeout = 0;
2437 u32 reg;
2438 u32 dma_ctrl;
2439 int i;
2440
2441 /* Disable TDMA to stop add more frames in TX DMA */
2442 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2443 reg &= ~DMA_EN;
2444 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2445
2446 /* Check TDMA status register to confirm TDMA is disabled */
2447 while (timeout++ < DMA_TIMEOUT_VAL) {
2448 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2449 if (reg & DMA_DISABLED)
2450 break;
2451
2452 udelay(1);
2453 }
2454
2455 if (timeout == DMA_TIMEOUT_VAL) {
2456 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2457 ret = -ETIMEDOUT;
2458 }
2459
2460 /* Wait 10ms for packet drain in both tx and rx dma */
2461 usleep_range(10000, 20000);
2462
2463 /* Disable RDMA */
2464 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2465 reg &= ~DMA_EN;
2466 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2467
2468 timeout = 0;
2469 /* Check RDMA status register to confirm RDMA is disabled */
2470 while (timeout++ < DMA_TIMEOUT_VAL) {
2471 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2472 if (reg & DMA_DISABLED)
2473 break;
2474
2475 udelay(1);
2476 }
2477
2478 if (timeout == DMA_TIMEOUT_VAL) {
2479 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2480 ret = -ETIMEDOUT;
2481 }
2482
2483 dma_ctrl = 0;
2484 for (i = 0; i < priv->hw_params->rx_queues; i++)
2485 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2486 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2487 reg &= ~dma_ctrl;
2488 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2489
2490 dma_ctrl = 0;
2491 for (i = 0; i < priv->hw_params->tx_queues; i++)
2492 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2493 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2494 reg &= ~dma_ctrl;
2495 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2496
2497 return ret;
2498 }
2499
bcmgenet_fini_dma(struct bcmgenet_priv * priv)2500 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2501 {
2502 struct netdev_queue *txq;
2503 struct sk_buff *skb;
2504 struct enet_cb *cb;
2505 int i;
2506
2507 bcmgenet_fini_rx_napi(priv);
2508 bcmgenet_fini_tx_napi(priv);
2509
2510 /* disable DMA */
2511 bcmgenet_dma_teardown(priv);
2512
2513 for (i = 0; i < priv->num_tx_bds; i++) {
2514 cb = priv->tx_cbs + i;
2515 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, cb);
2516 if (skb)
2517 dev_kfree_skb(skb);
2518 }
2519
2520 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2521 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
2522 netdev_tx_reset_queue(txq);
2523 }
2524
2525 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
2526 netdev_tx_reset_queue(txq);
2527
2528 bcmgenet_free_rx_buffers(priv);
2529 kfree(priv->rx_cbs);
2530 kfree(priv->tx_cbs);
2531 }
2532
2533 /* init_edma: Initialize DMA control register */
bcmgenet_init_dma(struct bcmgenet_priv * priv)2534 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2535 {
2536 int ret;
2537 unsigned int i;
2538 struct enet_cb *cb;
2539
2540 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2541
2542 /* Initialize common Rx ring structures */
2543 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2544 priv->num_rx_bds = TOTAL_DESC;
2545 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2546 GFP_KERNEL);
2547 if (!priv->rx_cbs)
2548 return -ENOMEM;
2549
2550 for (i = 0; i < priv->num_rx_bds; i++) {
2551 cb = priv->rx_cbs + i;
2552 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2553 }
2554
2555 /* Initialize common TX ring structures */
2556 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2557 priv->num_tx_bds = TOTAL_DESC;
2558 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2559 GFP_KERNEL);
2560 if (!priv->tx_cbs) {
2561 kfree(priv->rx_cbs);
2562 return -ENOMEM;
2563 }
2564
2565 for (i = 0; i < priv->num_tx_bds; i++) {
2566 cb = priv->tx_cbs + i;
2567 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2568 }
2569
2570 /* Init rDma */
2571 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2572
2573 /* Initialize Rx queues */
2574 ret = bcmgenet_init_rx_queues(priv->dev);
2575 if (ret) {
2576 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2577 bcmgenet_free_rx_buffers(priv);
2578 kfree(priv->rx_cbs);
2579 kfree(priv->tx_cbs);
2580 return ret;
2581 }
2582
2583 /* Init tDma */
2584 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2585
2586 /* Initialize Tx queues */
2587 bcmgenet_init_tx_queues(priv->dev);
2588
2589 return 0;
2590 }
2591
2592 /* Interrupt bottom half */
bcmgenet_irq_task(struct work_struct * work)2593 static void bcmgenet_irq_task(struct work_struct *work)
2594 {
2595 unsigned long flags;
2596 unsigned int status;
2597 struct bcmgenet_priv *priv = container_of(
2598 work, struct bcmgenet_priv, bcmgenet_irq_work);
2599
2600 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2601
2602 spin_lock_irqsave(&priv->lock, flags);
2603 status = priv->irq0_stat;
2604 priv->irq0_stat = 0;
2605 spin_unlock_irqrestore(&priv->lock, flags);
2606
2607 if (status & UMAC_IRQ_MPD_R) {
2608 netif_dbg(priv, wol, priv->dev,
2609 "magic packet detected, waking up\n");
2610 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2611 }
2612
2613 if (status & UMAC_IRQ_PHY_DET_R &&
2614 priv->dev->phydev->autoneg != AUTONEG_ENABLE) {
2615 phy_init_hw(priv->dev->phydev);
2616 genphy_config_aneg(priv->dev->phydev);
2617 }
2618
2619 /* Link UP/DOWN event */
2620 if (status & UMAC_IRQ_LINK_EVENT)
2621 phy_mac_interrupt(priv->phydev,
2622 !!(status & UMAC_IRQ_LINK_UP));
2623 }
2624
2625 /* bcmgenet_isr1: handle Rx and Tx priority queues */
bcmgenet_isr1(int irq,void * dev_id)2626 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2627 {
2628 struct bcmgenet_priv *priv = dev_id;
2629 struct bcmgenet_rx_ring *rx_ring;
2630 struct bcmgenet_tx_ring *tx_ring;
2631 unsigned int index, status;
2632
2633 /* Read irq status */
2634 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2635 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2636
2637 /* clear interrupts */
2638 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
2639
2640 netif_dbg(priv, intr, priv->dev,
2641 "%s: IRQ=0x%x\n", __func__, status);
2642
2643 /* Check Rx priority queue interrupts */
2644 for (index = 0; index < priv->hw_params->rx_queues; index++) {
2645 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2646 continue;
2647
2648 rx_ring = &priv->rx_rings[index];
2649
2650 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2651 rx_ring->int_disable(rx_ring);
2652 __napi_schedule_irqoff(&rx_ring->napi);
2653 }
2654 }
2655
2656 /* Check Tx priority queue interrupts */
2657 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2658 if (!(status & BIT(index)))
2659 continue;
2660
2661 tx_ring = &priv->tx_rings[index];
2662
2663 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2664 tx_ring->int_disable(tx_ring);
2665 __napi_schedule_irqoff(&tx_ring->napi);
2666 }
2667 }
2668
2669 return IRQ_HANDLED;
2670 }
2671
2672 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
bcmgenet_isr0(int irq,void * dev_id)2673 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2674 {
2675 struct bcmgenet_priv *priv = dev_id;
2676 struct bcmgenet_rx_ring *rx_ring;
2677 struct bcmgenet_tx_ring *tx_ring;
2678 unsigned int status;
2679 unsigned long flags;
2680
2681 /* Read irq status */
2682 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2683 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2684
2685 /* clear interrupts */
2686 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
2687
2688 netif_dbg(priv, intr, priv->dev,
2689 "IRQ=0x%x\n", status);
2690
2691 if (status & UMAC_IRQ_RXDMA_DONE) {
2692 rx_ring = &priv->rx_rings[DESC_INDEX];
2693
2694 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2695 rx_ring->int_disable(rx_ring);
2696 __napi_schedule_irqoff(&rx_ring->napi);
2697 }
2698 }
2699
2700 if (status & UMAC_IRQ_TXDMA_DONE) {
2701 tx_ring = &priv->tx_rings[DESC_INDEX];
2702
2703 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2704 tx_ring->int_disable(tx_ring);
2705 __napi_schedule_irqoff(&tx_ring->napi);
2706 }
2707 }
2708
2709 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2710 UMAC_IRQ_PHY_DET_F |
2711 UMAC_IRQ_LINK_EVENT |
2712 UMAC_IRQ_HFB_SM |
2713 UMAC_IRQ_HFB_MM)) {
2714 /* all other interested interrupts handled in bottom half */
2715 schedule_work(&priv->bcmgenet_irq_work);
2716 }
2717
2718 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2719 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2720 wake_up(&priv->wq);
2721 }
2722
2723 /* all other interested interrupts handled in bottom half */
2724 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_MPD_R | UMAC_IRQ_PHY_DET_R);
2725 if (status) {
2726 /* Save irq status for bottom-half processing. */
2727 spin_lock_irqsave(&priv->lock, flags);
2728 priv->irq0_stat |= status;
2729 spin_unlock_irqrestore(&priv->lock, flags);
2730
2731 schedule_work(&priv->bcmgenet_irq_work);
2732 }
2733
2734 return IRQ_HANDLED;
2735 }
2736
bcmgenet_wol_isr(int irq,void * dev_id)2737 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2738 {
2739 struct bcmgenet_priv *priv = dev_id;
2740
2741 pm_wakeup_event(&priv->pdev->dev, 0);
2742
2743 return IRQ_HANDLED;
2744 }
2745
2746 #ifdef CONFIG_NET_POLL_CONTROLLER
bcmgenet_poll_controller(struct net_device * dev)2747 static void bcmgenet_poll_controller(struct net_device *dev)
2748 {
2749 struct bcmgenet_priv *priv = netdev_priv(dev);
2750
2751 /* Invoke the main RX/TX interrupt handler */
2752 disable_irq(priv->irq0);
2753 bcmgenet_isr0(priv->irq0, priv);
2754 enable_irq(priv->irq0);
2755
2756 /* And the interrupt handler for RX/TX priority queues */
2757 disable_irq(priv->irq1);
2758 bcmgenet_isr1(priv->irq1, priv);
2759 enable_irq(priv->irq1);
2760 }
2761 #endif
2762
bcmgenet_umac_reset(struct bcmgenet_priv * priv)2763 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2764 {
2765 u32 reg;
2766
2767 reg = bcmgenet_rbuf_ctrl_get(priv);
2768 reg |= BIT(1);
2769 bcmgenet_rbuf_ctrl_set(priv, reg);
2770 udelay(10);
2771
2772 reg &= ~BIT(1);
2773 bcmgenet_rbuf_ctrl_set(priv, reg);
2774 udelay(10);
2775 }
2776
bcmgenet_set_hw_addr(struct bcmgenet_priv * priv,unsigned char * addr)2777 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2778 unsigned char *addr)
2779 {
2780 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2781 (addr[2] << 8) | addr[3], UMAC_MAC0);
2782 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2783 }
2784
2785 /* Returns a reusable dma control register value */
bcmgenet_dma_disable(struct bcmgenet_priv * priv)2786 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2787 {
2788 u32 reg;
2789 u32 dma_ctrl;
2790
2791 /* disable DMA */
2792 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2793 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2794 reg &= ~dma_ctrl;
2795 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2796
2797 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2798 reg &= ~dma_ctrl;
2799 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2800
2801 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2802 udelay(10);
2803 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2804
2805 return dma_ctrl;
2806 }
2807
bcmgenet_enable_dma(struct bcmgenet_priv * priv,u32 dma_ctrl)2808 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2809 {
2810 u32 reg;
2811
2812 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2813 reg |= dma_ctrl;
2814 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2815
2816 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2817 reg |= dma_ctrl;
2818 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2819 }
2820
2821 /* bcmgenet_hfb_clear
2822 *
2823 * Clear Hardware Filter Block and disable all filtering.
2824 */
bcmgenet_hfb_clear(struct bcmgenet_priv * priv)2825 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2826 {
2827 u32 i;
2828
2829 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2830 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2831 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2832
2833 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2834 bcmgenet_rdma_writel(priv, 0x0, i);
2835
2836 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2837 bcmgenet_hfb_reg_writel(priv, 0x0,
2838 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2839
2840 for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2841 priv->hw_params->hfb_filter_size; i++)
2842 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2843 }
2844
bcmgenet_hfb_init(struct bcmgenet_priv * priv)2845 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2846 {
2847 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2848 return;
2849
2850 bcmgenet_hfb_clear(priv);
2851 }
2852
bcmgenet_netif_start(struct net_device * dev)2853 static void bcmgenet_netif_start(struct net_device *dev)
2854 {
2855 struct bcmgenet_priv *priv = netdev_priv(dev);
2856
2857 /* Start the network engine */
2858 bcmgenet_enable_rx_napi(priv);
2859 bcmgenet_enable_tx_napi(priv);
2860
2861 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2862
2863 netif_tx_start_all_queues(dev);
2864
2865 /* Monitor link interrupts now */
2866 bcmgenet_link_intr_enable(priv);
2867
2868 phy_start(priv->phydev);
2869 }
2870
bcmgenet_open(struct net_device * dev)2871 static int bcmgenet_open(struct net_device *dev)
2872 {
2873 struct bcmgenet_priv *priv = netdev_priv(dev);
2874 unsigned long dma_ctrl;
2875 u32 reg;
2876 int ret;
2877
2878 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2879
2880 /* Turn on the clock */
2881 clk_prepare_enable(priv->clk);
2882
2883 /* If this is an internal GPHY, power it back on now, before UniMAC is
2884 * brought out of reset as absolutely no UniMAC activity is allowed
2885 */
2886 if (priv->internal_phy)
2887 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2888
2889 /* take MAC out of reset */
2890 bcmgenet_umac_reset(priv);
2891
2892 ret = init_umac(priv);
2893 if (ret)
2894 goto err_clk_disable;
2895
2896 /* disable ethernet MAC while updating its registers */
2897 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2898
2899 /* Make sure we reflect the value of CRC_CMD_FWD */
2900 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2901 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2902
2903 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2904
2905 if (priv->internal_phy) {
2906 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2907 reg |= EXT_ENERGY_DET_MASK;
2908 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2909 }
2910
2911 /* Disable RX/TX DMA and flush TX queues */
2912 dma_ctrl = bcmgenet_dma_disable(priv);
2913
2914 /* Reinitialize TDMA and RDMA and SW housekeeping */
2915 ret = bcmgenet_init_dma(priv);
2916 if (ret) {
2917 netdev_err(dev, "failed to initialize DMA\n");
2918 goto err_clk_disable;
2919 }
2920
2921 /* Always enable ring 16 - descriptor ring */
2922 bcmgenet_enable_dma(priv, dma_ctrl);
2923
2924 /* HFB init */
2925 bcmgenet_hfb_init(priv);
2926
2927 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2928 dev->name, priv);
2929 if (ret < 0) {
2930 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2931 goto err_fini_dma;
2932 }
2933
2934 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2935 dev->name, priv);
2936 if (ret < 0) {
2937 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2938 goto err_irq0;
2939 }
2940
2941 ret = bcmgenet_mii_probe(dev);
2942 if (ret) {
2943 netdev_err(dev, "failed to connect to PHY\n");
2944 goto err_irq1;
2945 }
2946
2947 bcmgenet_netif_start(dev);
2948
2949 return 0;
2950
2951 err_irq1:
2952 free_irq(priv->irq1, priv);
2953 err_irq0:
2954 free_irq(priv->irq0, priv);
2955 err_fini_dma:
2956 bcmgenet_fini_dma(priv);
2957 err_clk_disable:
2958 if (priv->internal_phy)
2959 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2960 clk_disable_unprepare(priv->clk);
2961 return ret;
2962 }
2963
bcmgenet_netif_stop(struct net_device * dev)2964 static void bcmgenet_netif_stop(struct net_device *dev)
2965 {
2966 struct bcmgenet_priv *priv = netdev_priv(dev);
2967
2968 netif_tx_stop_all_queues(dev);
2969 phy_stop(priv->phydev);
2970 bcmgenet_intr_disable(priv);
2971 bcmgenet_disable_rx_napi(priv);
2972 bcmgenet_disable_tx_napi(priv);
2973
2974 /* Wait for pending work items to complete. Since interrupts are
2975 * disabled no new work will be scheduled.
2976 */
2977 cancel_work_sync(&priv->bcmgenet_irq_work);
2978
2979 priv->old_link = -1;
2980 priv->old_speed = -1;
2981 priv->old_duplex = -1;
2982 priv->old_pause = -1;
2983 }
2984
bcmgenet_close(struct net_device * dev)2985 static int bcmgenet_close(struct net_device *dev)
2986 {
2987 struct bcmgenet_priv *priv = netdev_priv(dev);
2988 int ret;
2989
2990 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2991
2992 bcmgenet_netif_stop(dev);
2993
2994 /* Really kill the PHY state machine and disconnect from it */
2995 phy_disconnect(priv->phydev);
2996
2997 /* Disable MAC receive */
2998 umac_enable_set(priv, CMD_RX_EN, false);
2999
3000 ret = bcmgenet_dma_teardown(priv);
3001 if (ret)
3002 return ret;
3003
3004 /* Disable MAC transmit. TX DMA disabled must be done before this */
3005 umac_enable_set(priv, CMD_TX_EN, false);
3006
3007 /* tx reclaim */
3008 bcmgenet_tx_reclaim_all(dev);
3009 bcmgenet_fini_dma(priv);
3010
3011 free_irq(priv->irq0, priv);
3012 free_irq(priv->irq1, priv);
3013
3014 if (priv->internal_phy)
3015 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3016
3017 clk_disable_unprepare(priv->clk);
3018
3019 return ret;
3020 }
3021
bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring * ring)3022 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
3023 {
3024 struct bcmgenet_priv *priv = ring->priv;
3025 u32 p_index, c_index, intsts, intmsk;
3026 struct netdev_queue *txq;
3027 unsigned int free_bds;
3028 unsigned long flags;
3029 bool txq_stopped;
3030
3031 if (!netif_msg_tx_err(priv))
3032 return;
3033
3034 txq = netdev_get_tx_queue(priv->dev, ring->queue);
3035
3036 spin_lock_irqsave(&ring->lock, flags);
3037 if (ring->index == DESC_INDEX) {
3038 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3039 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
3040 } else {
3041 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3042 intmsk = 1 << ring->index;
3043 }
3044 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3045 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3046 txq_stopped = netif_tx_queue_stopped(txq);
3047 free_bds = ring->free_bds;
3048 spin_unlock_irqrestore(&ring->lock, flags);
3049
3050 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3051 "TX queue status: %s, interrupts: %s\n"
3052 "(sw)free_bds: %d (sw)size: %d\n"
3053 "(sw)p_index: %d (hw)p_index: %d\n"
3054 "(sw)c_index: %d (hw)c_index: %d\n"
3055 "(sw)clean_p: %d (sw)write_p: %d\n"
3056 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3057 ring->index, ring->queue,
3058 txq_stopped ? "stopped" : "active",
3059 intsts & intmsk ? "enabled" : "disabled",
3060 free_bds, ring->size,
3061 ring->prod_index, p_index & DMA_P_INDEX_MASK,
3062 ring->c_index, c_index & DMA_C_INDEX_MASK,
3063 ring->clean_ptr, ring->write_ptr,
3064 ring->cb_ptr, ring->end_ptr);
3065 }
3066
bcmgenet_timeout(struct net_device * dev)3067 static void bcmgenet_timeout(struct net_device *dev)
3068 {
3069 struct bcmgenet_priv *priv = netdev_priv(dev);
3070 u32 int0_enable = 0;
3071 u32 int1_enable = 0;
3072 unsigned int q;
3073
3074 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3075
3076 for (q = 0; q < priv->hw_params->tx_queues; q++)
3077 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3078 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3079
3080 bcmgenet_tx_reclaim_all(dev);
3081
3082 for (q = 0; q < priv->hw_params->tx_queues; q++)
3083 int1_enable |= (1 << q);
3084
3085 int0_enable = UMAC_IRQ_TXDMA_DONE;
3086
3087 /* Re-enable TX interrupts if disabled */
3088 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3089 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3090
3091 netif_trans_update(dev);
3092
3093 dev->stats.tx_errors++;
3094
3095 netif_tx_wake_all_queues(dev);
3096 }
3097
3098 #define MAX_MDF_FILTER 17
3099
bcmgenet_set_mdf_addr(struct bcmgenet_priv * priv,unsigned char * addr,int * i)3100 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3101 unsigned char *addr,
3102 int *i)
3103 {
3104 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3105 UMAC_MDF_ADDR + (*i * 4));
3106 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3107 addr[4] << 8 | addr[5],
3108 UMAC_MDF_ADDR + ((*i + 1) * 4));
3109 *i += 2;
3110 }
3111
bcmgenet_set_rx_mode(struct net_device * dev)3112 static void bcmgenet_set_rx_mode(struct net_device *dev)
3113 {
3114 struct bcmgenet_priv *priv = netdev_priv(dev);
3115 struct netdev_hw_addr *ha;
3116 int i, nfilter;
3117 u32 reg;
3118
3119 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3120
3121 /* Number of filters needed */
3122 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2;
3123
3124 /*
3125 * Turn on promicuous mode for three scenarios
3126 * 1. IFF_PROMISC flag is set
3127 * 2. IFF_ALLMULTI flag is set
3128 * 3. The number of filters needed exceeds the number filters
3129 * supported by the hardware.
3130 */
3131 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3132 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
3133 (nfilter > MAX_MDF_FILTER)) {
3134 reg |= CMD_PROMISC;
3135 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3136 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3137 return;
3138 } else {
3139 reg &= ~CMD_PROMISC;
3140 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3141 }
3142
3143 /* update MDF filter */
3144 i = 0;
3145 /* Broadcast */
3146 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i);
3147 /* my own address.*/
3148 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i);
3149
3150 /* Unicast */
3151 netdev_for_each_uc_addr(ha, dev)
3152 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3153
3154 /* Multicast */
3155 netdev_for_each_mc_addr(ha, dev)
3156 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3157
3158 /* Enable filters */
3159 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);
3160 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3161 }
3162
3163 /* Set the hardware MAC address. */
bcmgenet_set_mac_addr(struct net_device * dev,void * p)3164 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3165 {
3166 struct sockaddr *addr = p;
3167
3168 /* Setting the MAC address at the hardware level is not possible
3169 * without disabling the UniMAC RX/TX enable bits.
3170 */
3171 if (netif_running(dev))
3172 return -EBUSY;
3173
3174 ether_addr_copy(dev->dev_addr, addr->sa_data);
3175
3176 return 0;
3177 }
3178
bcmgenet_get_stats(struct net_device * dev)3179 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3180 {
3181 struct bcmgenet_priv *priv = netdev_priv(dev);
3182 unsigned long tx_bytes = 0, tx_packets = 0;
3183 unsigned long rx_bytes = 0, rx_packets = 0;
3184 unsigned long rx_errors = 0, rx_dropped = 0;
3185 struct bcmgenet_tx_ring *tx_ring;
3186 struct bcmgenet_rx_ring *rx_ring;
3187 unsigned int q;
3188
3189 for (q = 0; q < priv->hw_params->tx_queues; q++) {
3190 tx_ring = &priv->tx_rings[q];
3191 tx_bytes += tx_ring->bytes;
3192 tx_packets += tx_ring->packets;
3193 }
3194 tx_ring = &priv->tx_rings[DESC_INDEX];
3195 tx_bytes += tx_ring->bytes;
3196 tx_packets += tx_ring->packets;
3197
3198 for (q = 0; q < priv->hw_params->rx_queues; q++) {
3199 rx_ring = &priv->rx_rings[q];
3200
3201 rx_bytes += rx_ring->bytes;
3202 rx_packets += rx_ring->packets;
3203 rx_errors += rx_ring->errors;
3204 rx_dropped += rx_ring->dropped;
3205 }
3206 rx_ring = &priv->rx_rings[DESC_INDEX];
3207 rx_bytes += rx_ring->bytes;
3208 rx_packets += rx_ring->packets;
3209 rx_errors += rx_ring->errors;
3210 rx_dropped += rx_ring->dropped;
3211
3212 dev->stats.tx_bytes = tx_bytes;
3213 dev->stats.tx_packets = tx_packets;
3214 dev->stats.rx_bytes = rx_bytes;
3215 dev->stats.rx_packets = rx_packets;
3216 dev->stats.rx_errors = rx_errors;
3217 dev->stats.rx_missed_errors = rx_errors;
3218 return &dev->stats;
3219 }
3220
3221 static const struct net_device_ops bcmgenet_netdev_ops = {
3222 .ndo_open = bcmgenet_open,
3223 .ndo_stop = bcmgenet_close,
3224 .ndo_start_xmit = bcmgenet_xmit,
3225 .ndo_tx_timeout = bcmgenet_timeout,
3226 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
3227 .ndo_set_mac_address = bcmgenet_set_mac_addr,
3228 .ndo_do_ioctl = bcmgenet_ioctl,
3229 .ndo_set_features = bcmgenet_set_features,
3230 #ifdef CONFIG_NET_POLL_CONTROLLER
3231 .ndo_poll_controller = bcmgenet_poll_controller,
3232 #endif
3233 .ndo_get_stats = bcmgenet_get_stats,
3234 };
3235
3236 /* Array of GENET hardware parameters/characteristics */
3237 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3238 [GENET_V1] = {
3239 .tx_queues = 0,
3240 .tx_bds_per_q = 0,
3241 .rx_queues = 0,
3242 .rx_bds_per_q = 0,
3243 .bp_in_en_shift = 16,
3244 .bp_in_mask = 0xffff,
3245 .hfb_filter_cnt = 16,
3246 .qtag_mask = 0x1F,
3247 .hfb_offset = 0x1000,
3248 .rdma_offset = 0x2000,
3249 .tdma_offset = 0x3000,
3250 .words_per_bd = 2,
3251 },
3252 [GENET_V2] = {
3253 .tx_queues = 4,
3254 .tx_bds_per_q = 32,
3255 .rx_queues = 0,
3256 .rx_bds_per_q = 0,
3257 .bp_in_en_shift = 16,
3258 .bp_in_mask = 0xffff,
3259 .hfb_filter_cnt = 16,
3260 .qtag_mask = 0x1F,
3261 .tbuf_offset = 0x0600,
3262 .hfb_offset = 0x1000,
3263 .hfb_reg_offset = 0x2000,
3264 .rdma_offset = 0x3000,
3265 .tdma_offset = 0x4000,
3266 .words_per_bd = 2,
3267 .flags = GENET_HAS_EXT,
3268 },
3269 [GENET_V3] = {
3270 .tx_queues = 4,
3271 .tx_bds_per_q = 32,
3272 .rx_queues = 0,
3273 .rx_bds_per_q = 0,
3274 .bp_in_en_shift = 17,
3275 .bp_in_mask = 0x1ffff,
3276 .hfb_filter_cnt = 48,
3277 .hfb_filter_size = 128,
3278 .qtag_mask = 0x3F,
3279 .tbuf_offset = 0x0600,
3280 .hfb_offset = 0x8000,
3281 .hfb_reg_offset = 0xfc00,
3282 .rdma_offset = 0x10000,
3283 .tdma_offset = 0x11000,
3284 .words_per_bd = 2,
3285 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3286 GENET_HAS_MOCA_LINK_DET,
3287 },
3288 [GENET_V4] = {
3289 .tx_queues = 4,
3290 .tx_bds_per_q = 32,
3291 .rx_queues = 0,
3292 .rx_bds_per_q = 0,
3293 .bp_in_en_shift = 17,
3294 .bp_in_mask = 0x1ffff,
3295 .hfb_filter_cnt = 48,
3296 .hfb_filter_size = 128,
3297 .qtag_mask = 0x3F,
3298 .tbuf_offset = 0x0600,
3299 .hfb_offset = 0x8000,
3300 .hfb_reg_offset = 0xfc00,
3301 .rdma_offset = 0x2000,
3302 .tdma_offset = 0x4000,
3303 .words_per_bd = 3,
3304 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3305 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3306 },
3307 [GENET_V5] = {
3308 .tx_queues = 4,
3309 .tx_bds_per_q = 32,
3310 .rx_queues = 0,
3311 .rx_bds_per_q = 0,
3312 .bp_in_en_shift = 17,
3313 .bp_in_mask = 0x1ffff,
3314 .hfb_filter_cnt = 48,
3315 .hfb_filter_size = 128,
3316 .qtag_mask = 0x3F,
3317 .tbuf_offset = 0x0600,
3318 .hfb_offset = 0x8000,
3319 .hfb_reg_offset = 0xfc00,
3320 .rdma_offset = 0x2000,
3321 .tdma_offset = 0x4000,
3322 .words_per_bd = 3,
3323 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3324 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3325 },
3326 };
3327
3328 /* Infer hardware parameters from the detected GENET version */
bcmgenet_set_hw_params(struct bcmgenet_priv * priv)3329 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3330 {
3331 struct bcmgenet_hw_params *params;
3332 u32 reg;
3333 u8 major;
3334 u16 gphy_rev;
3335
3336 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
3337 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3338 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3339 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3340 } else if (GENET_IS_V3(priv)) {
3341 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3342 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3343 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3344 } else if (GENET_IS_V2(priv)) {
3345 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3346 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3347 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3348 } else if (GENET_IS_V1(priv)) {
3349 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3350 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3351 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3352 }
3353
3354 /* enum genet_version starts at 1 */
3355 priv->hw_params = &bcmgenet_hw_params[priv->version];
3356 params = priv->hw_params;
3357
3358 /* Read GENET HW version */
3359 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3360 major = (reg >> 24 & 0x0f);
3361 if (major == 6)
3362 major = 5;
3363 else if (major == 5)
3364 major = 4;
3365 else if (major == 0)
3366 major = 1;
3367 if (major != priv->version) {
3368 dev_err(&priv->pdev->dev,
3369 "GENET version mismatch, got: %d, configured for: %d\n",
3370 major, priv->version);
3371 }
3372
3373 /* Print the GENET core version */
3374 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3375 major, (reg >> 16) & 0x0f, reg & 0xffff);
3376
3377 /* Store the integrated PHY revision for the MDIO probing function
3378 * to pass this information to the PHY driver. The PHY driver expects
3379 * to find the PHY major revision in bits 15:8 while the GENET register
3380 * stores that information in bits 7:0, account for that.
3381 *
3382 * On newer chips, starting with PHY revision G0, a new scheme is
3383 * deployed similar to the Starfighter 2 switch with GPHY major
3384 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3385 * is reserved as well as special value 0x01ff, we have a small
3386 * heuristic to check for the new GPHY revision and re-arrange things
3387 * so the GPHY driver is happy.
3388 */
3389 gphy_rev = reg & 0xffff;
3390
3391 if (GENET_IS_V5(priv)) {
3392 /* The EPHY revision should come from the MDIO registers of
3393 * the PHY not from GENET.
3394 */
3395 if (gphy_rev != 0) {
3396 pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3397 gphy_rev);
3398 }
3399 /* This is reserved so should require special treatment */
3400 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3401 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3402 return;
3403 /* This is the good old scheme, just GPHY major, no minor nor patch */
3404 } else if ((gphy_rev & 0xf0) != 0) {
3405 priv->gphy_rev = gphy_rev << 8;
3406 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3407 } else if ((gphy_rev & 0xff00) != 0) {
3408 priv->gphy_rev = gphy_rev;
3409 }
3410
3411 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3412 if (!(params->flags & GENET_HAS_40BITS))
3413 pr_warn("GENET does not support 40-bits PA\n");
3414 #endif
3415
3416 pr_debug("Configuration for version: %d\n"
3417 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3418 "BP << en: %2d, BP msk: 0x%05x\n"
3419 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3420 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3421 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3422 "Words/BD: %d\n",
3423 priv->version,
3424 params->tx_queues, params->tx_bds_per_q,
3425 params->rx_queues, params->rx_bds_per_q,
3426 params->bp_in_en_shift, params->bp_in_mask,
3427 params->hfb_filter_cnt, params->qtag_mask,
3428 params->tbuf_offset, params->hfb_offset,
3429 params->hfb_reg_offset,
3430 params->rdma_offset, params->tdma_offset,
3431 params->words_per_bd);
3432 }
3433
3434 static const struct of_device_id bcmgenet_match[] = {
3435 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3436 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3437 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3438 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3439 { .compatible = "brcm,genet-v5", .data = (void *)GENET_V5 },
3440 { },
3441 };
3442 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3443
bcmgenet_probe(struct platform_device * pdev)3444 static int bcmgenet_probe(struct platform_device *pdev)
3445 {
3446 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3447 struct device_node *dn = pdev->dev.of_node;
3448 const struct of_device_id *of_id = NULL;
3449 struct bcmgenet_priv *priv;
3450 struct net_device *dev;
3451 const void *macaddr;
3452 struct resource *r;
3453 int err = -EIO;
3454 const char *phy_mode_str;
3455
3456 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3457 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3458 GENET_MAX_MQ_CNT + 1);
3459 if (!dev) {
3460 dev_err(&pdev->dev, "can't allocate net device\n");
3461 return -ENOMEM;
3462 }
3463
3464 if (dn) {
3465 of_id = of_match_node(bcmgenet_match, dn);
3466 if (!of_id)
3467 return -EINVAL;
3468 }
3469
3470 priv = netdev_priv(dev);
3471 priv->irq0 = platform_get_irq(pdev, 0);
3472 priv->irq1 = platform_get_irq(pdev, 1);
3473 priv->wol_irq = platform_get_irq(pdev, 2);
3474 if (!priv->irq0 || !priv->irq1) {
3475 dev_err(&pdev->dev, "can't find IRQs\n");
3476 err = -EINVAL;
3477 goto err;
3478 }
3479
3480 if (dn) {
3481 macaddr = of_get_mac_address(dn);
3482 if (!macaddr) {
3483 dev_err(&pdev->dev, "can't find MAC address\n");
3484 err = -EINVAL;
3485 goto err;
3486 }
3487 } else {
3488 macaddr = pd->mac_address;
3489 }
3490
3491 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3492 priv->base = devm_ioremap_resource(&pdev->dev, r);
3493 if (IS_ERR(priv->base)) {
3494 err = PTR_ERR(priv->base);
3495 goto err;
3496 }
3497
3498 spin_lock_init(&priv->lock);
3499
3500 SET_NETDEV_DEV(dev, &pdev->dev);
3501 dev_set_drvdata(&pdev->dev, dev);
3502 ether_addr_copy(dev->dev_addr, macaddr);
3503 dev->watchdog_timeo = 2 * HZ;
3504 dev->ethtool_ops = &bcmgenet_ethtool_ops;
3505 dev->netdev_ops = &bcmgenet_netdev_ops;
3506
3507 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3508
3509 /* Set hardware features */
3510 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3511 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3512
3513 /* Request the WOL interrupt and advertise suspend if available */
3514 priv->wol_irq_disabled = true;
3515 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3516 dev->name, priv);
3517 if (!err)
3518 device_set_wakeup_capable(&pdev->dev, 1);
3519
3520 /* Set the needed headroom to account for any possible
3521 * features enabling/disabling at runtime
3522 */
3523 dev->needed_headroom += 64;
3524
3525 netdev_boot_setup_check(dev);
3526
3527 priv->dev = dev;
3528 priv->pdev = pdev;
3529 if (of_id)
3530 priv->version = (enum bcmgenet_version)of_id->data;
3531 else
3532 priv->version = pd->genet_version;
3533
3534 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3535 if (IS_ERR(priv->clk)) {
3536 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3537 priv->clk = NULL;
3538 }
3539
3540 clk_prepare_enable(priv->clk);
3541
3542 bcmgenet_set_hw_params(priv);
3543
3544 /* Mii wait queue */
3545 init_waitqueue_head(&priv->wq);
3546 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3547 priv->rx_buf_len = RX_BUF_LENGTH;
3548 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3549
3550 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3551 if (IS_ERR(priv->clk_wol)) {
3552 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3553 priv->clk_wol = NULL;
3554 }
3555
3556 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3557 if (IS_ERR(priv->clk_eee)) {
3558 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3559 priv->clk_eee = NULL;
3560 }
3561
3562 /* If this is an internal GPHY, power it on now, before UniMAC is
3563 * brought out of reset as absolutely no UniMAC activity is allowed
3564 */
3565 if (dn && !of_property_read_string(dn, "phy-mode", &phy_mode_str) &&
3566 !strcasecmp(phy_mode_str, "internal"))
3567 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3568
3569 err = reset_umac(priv);
3570 if (err)
3571 goto err_clk_disable;
3572
3573 err = bcmgenet_mii_init(dev);
3574 if (err)
3575 goto err_clk_disable;
3576
3577 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
3578 * just the ring 16 descriptor based TX
3579 */
3580 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3581 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3582
3583 /* libphy will determine the link state */
3584 netif_carrier_off(dev);
3585
3586 /* Turn off the main clock, WOL clock is handled separately */
3587 clk_disable_unprepare(priv->clk);
3588
3589 err = register_netdev(dev);
3590 if (err)
3591 goto err;
3592
3593 return err;
3594
3595 err_clk_disable:
3596 clk_disable_unprepare(priv->clk);
3597 err:
3598 free_netdev(dev);
3599 return err;
3600 }
3601
bcmgenet_remove(struct platform_device * pdev)3602 static int bcmgenet_remove(struct platform_device *pdev)
3603 {
3604 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3605
3606 dev_set_drvdata(&pdev->dev, NULL);
3607 unregister_netdev(priv->dev);
3608 bcmgenet_mii_exit(priv->dev);
3609 free_netdev(priv->dev);
3610
3611 return 0;
3612 }
3613
3614 #ifdef CONFIG_PM_SLEEP
bcmgenet_suspend(struct device * d)3615 static int bcmgenet_suspend(struct device *d)
3616 {
3617 struct net_device *dev = dev_get_drvdata(d);
3618 struct bcmgenet_priv *priv = netdev_priv(dev);
3619 int ret;
3620
3621 if (!netif_running(dev))
3622 return 0;
3623
3624 bcmgenet_netif_stop(dev);
3625
3626 if (!device_may_wakeup(d))
3627 phy_suspend(priv->phydev);
3628
3629 netif_device_detach(dev);
3630
3631 /* Disable MAC receive */
3632 umac_enable_set(priv, CMD_RX_EN, false);
3633
3634 ret = bcmgenet_dma_teardown(priv);
3635 if (ret)
3636 return ret;
3637
3638 /* Disable MAC transmit. TX DMA disabled must be done before this */
3639 umac_enable_set(priv, CMD_TX_EN, false);
3640
3641 /* tx reclaim */
3642 bcmgenet_tx_reclaim_all(dev);
3643 bcmgenet_fini_dma(priv);
3644
3645 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3646 if (device_may_wakeup(d) && priv->wolopts) {
3647 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3648 clk_prepare_enable(priv->clk_wol);
3649 } else if (priv->internal_phy) {
3650 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3651 }
3652
3653 /* Turn off the clocks */
3654 clk_disable_unprepare(priv->clk);
3655
3656 return ret;
3657 }
3658
bcmgenet_resume(struct device * d)3659 static int bcmgenet_resume(struct device *d)
3660 {
3661 struct net_device *dev = dev_get_drvdata(d);
3662 struct bcmgenet_priv *priv = netdev_priv(dev);
3663 unsigned long dma_ctrl;
3664 int ret;
3665 u32 reg;
3666
3667 if (!netif_running(dev))
3668 return 0;
3669
3670 /* Turn on the clock */
3671 ret = clk_prepare_enable(priv->clk);
3672 if (ret)
3673 return ret;
3674
3675 /* If this is an internal GPHY, power it back on now, before UniMAC is
3676 * brought out of reset as absolutely no UniMAC activity is allowed
3677 */
3678 if (priv->internal_phy)
3679 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3680
3681 bcmgenet_umac_reset(priv);
3682
3683 ret = init_umac(priv);
3684 if (ret)
3685 goto out_clk_disable;
3686
3687 /* From WOL-enabled suspend, switch to regular clock */
3688 if (priv->wolopts)
3689 clk_disable_unprepare(priv->clk_wol);
3690
3691 phy_init_hw(priv->phydev);
3692 /* Speed settings must be restored */
3693 genphy_config_aneg(dev->phydev);
3694 bcmgenet_mii_config(priv->dev, false);
3695
3696 /* disable ethernet MAC while updating its registers */
3697 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3698
3699 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3700
3701 if (priv->internal_phy) {
3702 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3703 reg |= EXT_ENERGY_DET_MASK;
3704 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3705 }
3706
3707 if (priv->wolopts)
3708 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3709
3710 /* Disable RX/TX DMA and flush TX queues */
3711 dma_ctrl = bcmgenet_dma_disable(priv);
3712
3713 /* Reinitialize TDMA and RDMA and SW housekeeping */
3714 ret = bcmgenet_init_dma(priv);
3715 if (ret) {
3716 netdev_err(dev, "failed to initialize DMA\n");
3717 goto out_clk_disable;
3718 }
3719
3720 /* Always enable ring 16 - descriptor ring */
3721 bcmgenet_enable_dma(priv, dma_ctrl);
3722
3723 netif_device_attach(dev);
3724
3725 if (!device_may_wakeup(d))
3726 phy_resume(priv->phydev);
3727
3728 if (priv->eee.eee_enabled)
3729 bcmgenet_eee_enable_set(dev, true);
3730
3731 bcmgenet_netif_start(dev);
3732
3733 return 0;
3734
3735 out_clk_disable:
3736 if (priv->internal_phy)
3737 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3738 clk_disable_unprepare(priv->clk);
3739 return ret;
3740 }
3741 #endif /* CONFIG_PM_SLEEP */
3742
3743 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3744
3745 static struct platform_driver bcmgenet_driver = {
3746 .probe = bcmgenet_probe,
3747 .remove = bcmgenet_remove,
3748 .driver = {
3749 .name = "bcmgenet",
3750 .of_match_table = bcmgenet_match,
3751 .pm = &bcmgenet_pm_ops,
3752 },
3753 };
3754 module_platform_driver(bcmgenet_driver);
3755
3756 MODULE_AUTHOR("Broadcom Corporation");
3757 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3758 MODULE_ALIAS("platform:bcmgenet");
3759 MODULE_LICENSE("GPL");
3760