1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 /*! \file octeon_iq.h 19 * \brief Host Driver: Implementation of Octeon input queues. "Input" is 20 * with respect to the Octeon device on the NIC. From this driver's 21 * point of view they are egress queues. 22 */ 23 24 #ifndef __OCTEON_IQ_H__ 25 #define __OCTEON_IQ_H__ 26 27 #define IQ_STATUS_RUNNING 1 28 29 #define IQ_SEND_OK 0 30 #define IQ_SEND_STOP 1 31 #define IQ_SEND_FAILED -1 32 33 /*------------------------- INSTRUCTION QUEUE --------------------------*/ 34 35 /* \cond */ 36 37 #define REQTYPE_NONE 0 38 #define REQTYPE_NORESP_NET 1 39 #define REQTYPE_NORESP_NET_SG 2 40 #define REQTYPE_RESP_NET 3 41 #define REQTYPE_RESP_NET_SG 4 42 #define REQTYPE_SOFT_COMMAND 5 43 #define REQTYPE_LAST 5 44 45 struct octeon_request_list { 46 u32 reqtype; 47 void *buf; 48 }; 49 50 /* \endcond */ 51 52 /** Input Queue statistics. Each input queue has four stats fields. */ 53 struct oct_iq_stats { 54 u64 instr_posted; /**< Instructions posted to this queue. */ 55 u64 instr_processed; /**< Instructions processed in this queue. */ 56 u64 instr_dropped; /**< Instructions that could not be processed */ 57 u64 bytes_sent; /**< Bytes sent through this queue. */ 58 u64 sgentry_sent;/**< Gather entries sent through this queue. */ 59 u64 tx_done;/**< Num of packets sent to network. */ 60 u64 tx_iq_busy;/**< Numof times this iq was found to be full. */ 61 u64 tx_dropped;/**< Numof pkts dropped dueto xmitpath errors. */ 62 u64 tx_tot_bytes;/**< Total count of bytes sento to network. */ 63 u64 tx_gso; /* count of tso */ 64 u64 tx_vxlan; /* tunnel */ 65 u64 tx_dmamap_fail; 66 u64 tx_restart; 67 }; 68 69 #define OCT_IQ_STATS_SIZE (sizeof(struct oct_iq_stats)) 70 71 /** The instruction (input) queue. 72 * The input queue is used to post raw (instruction) mode data or packet 73 * data to Octeon device from the host. Each input queue (upto 4) for 74 * a Octeon device has one such structure to represent it. 75 */ 76 struct octeon_instr_queue { 77 struct octeon_device *oct_dev; 78 79 /** A spinlock to protect access to the input ring. */ 80 spinlock_t lock; 81 82 /** A spinlock to protect while posting on the ring. */ 83 spinlock_t post_lock; 84 85 u32 pkt_in_done; 86 87 u32 pkts_processed; 88 89 /** A spinlock to protect access to the input ring.*/ 90 spinlock_t iq_flush_running_lock; 91 92 /** Flag that indicates if the queue uses 64 byte commands. */ 93 u32 iqcmd_64B:1; 94 95 /** Queue info. */ 96 union oct_txpciq txpciq; 97 98 u32 rsvd:17; 99 100 /* Controls whether extra flushing of IQ is done on Tx */ 101 u32 do_auto_flush:1; 102 103 u32 status:8; 104 105 /** Maximum no. of instructions in this queue. */ 106 u32 max_count; 107 108 /** Index in input ring where the driver should write the next packet */ 109 u32 host_write_index; 110 111 /** Index in input ring where Octeon is expected to read the next 112 * packet. 113 */ 114 u32 octeon_read_index; 115 116 /** This index aids in finding the window in the queue where Octeon 117 * has read the commands. 118 */ 119 u32 flush_index; 120 121 /** This field keeps track of the instructions pending in this queue. */ 122 atomic_t instr_pending; 123 124 u32 reset_instr_cnt; 125 126 /** Pointer to the Virtual Base addr of the input ring. */ 127 u8 *base_addr; 128 129 struct octeon_request_list *request_list; 130 131 /** Octeon doorbell register for the ring. */ 132 void __iomem *doorbell_reg; 133 134 /** Octeon instruction count register for this ring. */ 135 void __iomem *inst_cnt_reg; 136 137 /** Number of instructions pending to be posted to Octeon. */ 138 u32 fill_cnt; 139 140 /** The max. number of instructions that can be held pending by the 141 * driver. 142 */ 143 u32 fill_threshold; 144 145 /** The last time that the doorbell was rung. */ 146 u64 last_db_time; 147 148 /** The doorbell timeout. If the doorbell was not rung for this time and 149 * fill_cnt is non-zero, ring the doorbell again. 150 */ 151 u32 db_timeout; 152 153 /** Statistics for this input queue. */ 154 struct oct_iq_stats stats; 155 156 /** DMA mapped base address of the input descriptor ring. */ 157 dma_addr_t base_addr_dma; 158 159 /** Application context */ 160 void *app_ctx; 161 162 /* network stack queue index */ 163 int q_index; 164 165 /*os ifidx associated with this queue */ 166 int ifidx; 167 168 }; 169 170 /*---------------------- INSTRUCTION FORMAT ----------------------------*/ 171 172 /** 32-byte instruction format. 173 * Format of instruction for a 32-byte mode input queue. 174 */ 175 struct octeon_instr_32B { 176 /** Pointer where the input data is available. */ 177 u64 dptr; 178 179 /** Instruction Header. */ 180 u64 ih; 181 182 /** Pointer where the response for a RAW mode packet will be written 183 * by Octeon. 184 */ 185 u64 rptr; 186 187 /** Input Request Header. Additional info about the input. */ 188 u64 irh; 189 190 }; 191 192 #define OCT_32B_INSTR_SIZE (sizeof(struct octeon_instr_32B)) 193 194 /** 64-byte instruction format. 195 * Format of instruction for a 64-byte mode input queue. 196 */ 197 struct octeon_instr2_64B { 198 /** Pointer where the input data is available. */ 199 u64 dptr; 200 201 /** Instruction Header. */ 202 u64 ih2; 203 204 /** Input Request Header. */ 205 u64 irh; 206 207 /** opcode/subcode specific parameters */ 208 u64 ossp[2]; 209 210 /** Return Data Parameters */ 211 u64 rdp; 212 213 /** Pointer where the response for a RAW mode packet will be written 214 * by Octeon. 215 */ 216 u64 rptr; 217 218 u64 reserved; 219 }; 220 221 struct octeon_instr3_64B { 222 /** Pointer where the input data is available. */ 223 u64 dptr; 224 225 /** Instruction Header. */ 226 u64 ih3; 227 228 /** Instruction Header. */ 229 u64 pki_ih3; 230 231 /** Input Request Header. */ 232 u64 irh; 233 234 /** opcode/subcode specific parameters */ 235 u64 ossp[2]; 236 237 /** Return Data Parameters */ 238 u64 rdp; 239 240 /** Pointer where the response for a RAW mode packet will be written 241 * by Octeon. 242 */ 243 u64 rptr; 244 245 }; 246 247 union octeon_instr_64B { 248 struct octeon_instr2_64B cmd2; 249 struct octeon_instr3_64B cmd3; 250 }; 251 252 #define OCT_64B_INSTR_SIZE (sizeof(union octeon_instr_64B)) 253 254 /** The size of each buffer in soft command buffer pool 255 */ 256 #define SOFT_COMMAND_BUFFER_SIZE 2048 257 258 struct octeon_soft_command { 259 /** Soft command buffer info. */ 260 struct list_head node; 261 u64 dma_addr; 262 u32 size; 263 264 /** Command and return status */ 265 union octeon_instr_64B cmd; 266 267 #define COMPLETION_WORD_INIT 0xffffffffffffffffULL 268 u64 *status_word; 269 270 /** Data buffer info */ 271 void *virtdptr; 272 u64 dmadptr; 273 u32 datasize; 274 275 /** Return buffer info */ 276 void *virtrptr; 277 u64 dmarptr; 278 u32 rdatasize; 279 280 /** Context buffer info */ 281 void *ctxptr; 282 u32 ctxsize; 283 284 /** Time out and callback */ 285 size_t wait_time; 286 size_t timeout; 287 u32 iq_no; 288 void (*callback)(struct octeon_device *, u32, void *); 289 void *callback_arg; 290 }; 291 292 /** Maximum number of buffers to allocate into soft command buffer pool 293 */ 294 #define MAX_SOFT_COMMAND_BUFFERS 256 295 296 /** Head of a soft command buffer pool. 297 */ 298 struct octeon_sc_buffer_pool { 299 /** List structure to add delete pending entries to */ 300 struct list_head head; 301 302 /** A lock for this response list */ 303 spinlock_t lock; 304 305 atomic_t alloc_buf_count; 306 }; 307 308 #define INCR_INSTRQUEUE_PKT_COUNT(octeon_dev_ptr, iq_no, field, count) \ 309 (((octeon_dev_ptr)->instr_queue[iq_no]->stats.field) += count) 310 311 int octeon_setup_sc_buffer_pool(struct octeon_device *oct); 312 int octeon_free_sc_buffer_pool(struct octeon_device *oct); 313 struct octeon_soft_command * 314 octeon_alloc_soft_command(struct octeon_device *oct, 315 u32 datasize, u32 rdatasize, 316 u32 ctxsize); 317 void octeon_free_soft_command(struct octeon_device *oct, 318 struct octeon_soft_command *sc); 319 320 /** 321 * octeon_init_instr_queue() 322 * @param octeon_dev - pointer to the octeon device structure. 323 * @param txpciq - queue to be initialized (0 <= q_no <= 3). 324 * 325 * Called at driver init time for each input queue. iq_conf has the 326 * configuration parameters for the queue. 327 * 328 * @return Success: 0 Failure: 1 329 */ 330 int octeon_init_instr_queue(struct octeon_device *octeon_dev, 331 union oct_txpciq txpciq, 332 u32 num_descs); 333 334 /** 335 * octeon_delete_instr_queue() 336 * @param octeon_dev - pointer to the octeon device structure. 337 * @param iq_no - queue to be deleted (0 <= q_no <= 3). 338 * 339 * Called at driver unload time for each input queue. Deletes all 340 * allocated resources for the input queue. 341 * 342 * @return Success: 0 Failure: 1 343 */ 344 int octeon_delete_instr_queue(struct octeon_device *octeon_dev, u32 iq_no); 345 346 int lio_wait_for_instr_fetch(struct octeon_device *oct); 347 348 int 349 octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype, 350 void (*fn)(void *)); 351 352 int 353 lio_process_iq_request_list(struct octeon_device *oct, 354 struct octeon_instr_queue *iq, u32 napi_budget); 355 356 int octeon_send_command(struct octeon_device *oct, u32 iq_no, 357 u32 force_db, void *cmd, void *buf, 358 u32 datasize, u32 reqtype); 359 360 void octeon_prepare_soft_command(struct octeon_device *oct, 361 struct octeon_soft_command *sc, 362 u8 opcode, u8 subcode, 363 u32 irh_ossp, u64 ossp0, 364 u64 ossp1); 365 366 int octeon_send_soft_command(struct octeon_device *oct, 367 struct octeon_soft_command *sc); 368 369 int octeon_setup_iq(struct octeon_device *oct, int ifidx, 370 int q_index, union oct_txpciq iq_no, u32 num_descs, 371 void *app_ctx); 372 int 373 octeon_flush_iq(struct octeon_device *oct, struct octeon_instr_queue *iq, 374 u32 napi_budget); 375 #endif /* __OCTEON_IQ_H__ */ 376