1 /*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
9 #include <linux/module.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/etherdevice.h>
13 #include <linux/of.h>
14 #include <linux/if_vlan.h>
15
16 #include "nic_reg.h"
17 #include "nic.h"
18 #include "q_struct.h"
19 #include "thunder_bgx.h"
20
21 #define DRV_NAME "thunder-nic"
22 #define DRV_VERSION "1.0"
23
24 struct hw_info {
25 u8 bgx_cnt;
26 u8 chans_per_lmac;
27 u8 chans_per_bgx; /* Rx/Tx chans */
28 u8 chans_per_rgx;
29 u8 chans_per_lbk;
30 u16 cpi_cnt;
31 u16 rssi_cnt;
32 u16 rss_ind_tbl_size;
33 u16 tl4_cnt;
34 u16 tl3_cnt;
35 u8 tl2_cnt;
36 u8 tl1_cnt;
37 bool tl1_per_bgx; /* TL1 per BGX or per LMAC */
38 };
39
40 struct nicpf {
41 struct pci_dev *pdev;
42 struct hw_info *hw;
43 u8 node;
44 unsigned int flags;
45 u8 num_vf_en; /* No of VF enabled */
46 bool vf_enabled[MAX_NUM_VFS_SUPPORTED];
47 void __iomem *reg_base; /* Register start address */
48 u8 num_sqs_en; /* Secondary qsets enabled */
49 u64 nicvf[MAX_NUM_VFS_SUPPORTED];
50 u8 vf_sqs[MAX_NUM_VFS_SUPPORTED][MAX_SQS_PER_VF];
51 u8 pqs_vf[MAX_NUM_VFS_SUPPORTED];
52 bool sqs_used[MAX_NUM_VFS_SUPPORTED];
53 struct pkind_cfg pkind;
54 #define NIC_SET_VF_LMAC_MAP(bgx, lmac) (((bgx & 0xF) << 4) | (lmac & 0xF))
55 #define NIC_GET_BGX_FROM_VF_LMAC_MAP(map) ((map >> 4) & 0xF)
56 #define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map) (map & 0xF)
57 u8 *vf_lmac_map;
58 struct delayed_work dwork;
59 struct workqueue_struct *check_link;
60 u8 *link;
61 u8 *duplex;
62 u32 *speed;
63 u16 cpi_base[MAX_NUM_VFS_SUPPORTED];
64 u16 rssi_base[MAX_NUM_VFS_SUPPORTED];
65 bool mbx_lock[MAX_NUM_VFS_SUPPORTED];
66
67 /* MSI-X */
68 u8 num_vec;
69 bool irq_allocated[NIC_PF_MSIX_VECTORS];
70 char irq_name[NIC_PF_MSIX_VECTORS][20];
71 };
72
73 /* Supported devices */
74 static const struct pci_device_id nic_id_table[] = {
75 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_NIC_PF) },
76 { 0, } /* end of table */
77 };
78
79 MODULE_AUTHOR("Sunil Goutham");
80 MODULE_DESCRIPTION("Cavium Thunder NIC Physical Function Driver");
81 MODULE_LICENSE("GPL v2");
82 MODULE_VERSION(DRV_VERSION);
83 MODULE_DEVICE_TABLE(pci, nic_id_table);
84
85 /* The Cavium ThunderX network controller can *only* be found in SoCs
86 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
87 * registers on this platform are implicitly strongly ordered with respect
88 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
89 * with no memory barriers in this driver. The readq()/writeq() functions add
90 * explicit ordering operation which in this case are redundant, and only
91 * add overhead.
92 */
93
94 /* Register read/write APIs */
nic_reg_write(struct nicpf * nic,u64 offset,u64 val)95 static void nic_reg_write(struct nicpf *nic, u64 offset, u64 val)
96 {
97 writeq_relaxed(val, nic->reg_base + offset);
98 }
99
nic_reg_read(struct nicpf * nic,u64 offset)100 static u64 nic_reg_read(struct nicpf *nic, u64 offset)
101 {
102 return readq_relaxed(nic->reg_base + offset);
103 }
104
105 /* PF -> VF mailbox communication APIs */
nic_enable_mbx_intr(struct nicpf * nic)106 static void nic_enable_mbx_intr(struct nicpf *nic)
107 {
108 int vf_cnt = pci_sriov_get_totalvfs(nic->pdev);
109
110 #define INTR_MASK(vfs) ((vfs < 64) ? (BIT_ULL(vfs) - 1) : (~0ull))
111
112 /* Clear it, to avoid spurious interrupts (if any) */
113 nic_reg_write(nic, NIC_PF_MAILBOX_INT, INTR_MASK(vf_cnt));
114
115 /* Enable mailbox interrupt for all VFs */
116 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, INTR_MASK(vf_cnt));
117 /* One mailbox intr enable reg per 64 VFs */
118 if (vf_cnt > 64) {
119 nic_reg_write(nic, NIC_PF_MAILBOX_INT + sizeof(u64),
120 INTR_MASK(vf_cnt - 64));
121 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(u64),
122 INTR_MASK(vf_cnt - 64));
123 }
124 }
125
nic_clear_mbx_intr(struct nicpf * nic,int vf,int mbx_reg)126 static void nic_clear_mbx_intr(struct nicpf *nic, int vf, int mbx_reg)
127 {
128 nic_reg_write(nic, NIC_PF_MAILBOX_INT + (mbx_reg << 3), BIT_ULL(vf));
129 }
130
nic_get_mbx_addr(int vf)131 static u64 nic_get_mbx_addr(int vf)
132 {
133 return NIC_PF_VF_0_127_MAILBOX_0_1 + (vf << NIC_VF_NUM_SHIFT);
134 }
135
136 /* Send a mailbox message to VF
137 * @vf: vf to which this message to be sent
138 * @mbx: Message to be sent
139 */
nic_send_msg_to_vf(struct nicpf * nic,int vf,union nic_mbx * mbx)140 static void nic_send_msg_to_vf(struct nicpf *nic, int vf, union nic_mbx *mbx)
141 {
142 void __iomem *mbx_addr = nic->reg_base + nic_get_mbx_addr(vf);
143 u64 *msg = (u64 *)mbx;
144
145 /* In first revision HW, mbox interrupt is triggerred
146 * when PF writes to MBOX(1), in next revisions when
147 * PF writes to MBOX(0)
148 */
149 if (pass1_silicon(nic->pdev)) {
150 /* see the comment for nic_reg_write()/nic_reg_read()
151 * functions above
152 */
153 writeq_relaxed(msg[0], mbx_addr);
154 writeq_relaxed(msg[1], mbx_addr + 8);
155 } else {
156 writeq_relaxed(msg[1], mbx_addr + 8);
157 writeq_relaxed(msg[0], mbx_addr);
158 }
159 }
160
161 /* Responds to VF's READY message with VF's
162 * ID, node, MAC address e.t.c
163 * @vf: VF which sent READY message
164 */
nic_mbx_send_ready(struct nicpf * nic,int vf)165 static void nic_mbx_send_ready(struct nicpf *nic, int vf)
166 {
167 union nic_mbx mbx = {};
168 int bgx_idx, lmac;
169 const char *mac;
170
171 mbx.nic_cfg.msg = NIC_MBOX_MSG_READY;
172 mbx.nic_cfg.vf_id = vf;
173
174 mbx.nic_cfg.tns_mode = NIC_TNS_BYPASS_MODE;
175
176 if (vf < nic->num_vf_en) {
177 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
178 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
179
180 mac = bgx_get_lmac_mac(nic->node, bgx_idx, lmac);
181 if (mac)
182 ether_addr_copy((u8 *)&mbx.nic_cfg.mac_addr, mac);
183 }
184 mbx.nic_cfg.sqs_mode = (vf >= nic->num_vf_en) ? true : false;
185 mbx.nic_cfg.node_id = nic->node;
186
187 mbx.nic_cfg.loopback_supported = vf < nic->num_vf_en;
188
189 nic_send_msg_to_vf(nic, vf, &mbx);
190 }
191
192 /* ACKs VF's mailbox message
193 * @vf: VF to which ACK to be sent
194 */
nic_mbx_send_ack(struct nicpf * nic,int vf)195 static void nic_mbx_send_ack(struct nicpf *nic, int vf)
196 {
197 union nic_mbx mbx = {};
198
199 mbx.msg.msg = NIC_MBOX_MSG_ACK;
200 nic_send_msg_to_vf(nic, vf, &mbx);
201 }
202
203 /* NACKs VF's mailbox message that PF is not able to
204 * complete the action
205 * @vf: VF to which ACK to be sent
206 */
nic_mbx_send_nack(struct nicpf * nic,int vf)207 static void nic_mbx_send_nack(struct nicpf *nic, int vf)
208 {
209 union nic_mbx mbx = {};
210
211 mbx.msg.msg = NIC_MBOX_MSG_NACK;
212 nic_send_msg_to_vf(nic, vf, &mbx);
213 }
214
215 /* Flush all in flight receive packets to memory and
216 * bring down an active RQ
217 */
nic_rcv_queue_sw_sync(struct nicpf * nic)218 static int nic_rcv_queue_sw_sync(struct nicpf *nic)
219 {
220 u16 timeout = ~0x00;
221
222 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x01);
223 /* Wait till sync cycle is finished */
224 while (timeout) {
225 if (nic_reg_read(nic, NIC_PF_SW_SYNC_RX_DONE) & 0x1)
226 break;
227 timeout--;
228 }
229 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x00);
230 if (!timeout) {
231 dev_err(&nic->pdev->dev, "Receive queue software sync failed");
232 return 1;
233 }
234 return 0;
235 }
236
237 /* Get BGX Rx/Tx stats and respond to VF's request */
nic_get_bgx_stats(struct nicpf * nic,struct bgx_stats_msg * bgx)238 static void nic_get_bgx_stats(struct nicpf *nic, struct bgx_stats_msg *bgx)
239 {
240 int bgx_idx, lmac;
241 union nic_mbx mbx = {};
242
243 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]);
244 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]);
245
246 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS;
247 mbx.bgx_stats.vf_id = bgx->vf_id;
248 mbx.bgx_stats.rx = bgx->rx;
249 mbx.bgx_stats.idx = bgx->idx;
250 if (bgx->rx)
251 mbx.bgx_stats.stats = bgx_get_rx_stats(nic->node, bgx_idx,
252 lmac, bgx->idx);
253 else
254 mbx.bgx_stats.stats = bgx_get_tx_stats(nic->node, bgx_idx,
255 lmac, bgx->idx);
256 nic_send_msg_to_vf(nic, bgx->vf_id, &mbx);
257 }
258
259 /* Update hardware min/max frame size */
nic_update_hw_frs(struct nicpf * nic,int new_frs,int vf)260 static int nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf)
261 {
262 int bgx, lmac, lmac_cnt;
263 u64 lmac_credits;
264
265 if ((new_frs > NIC_HW_MAX_FRS) || (new_frs < NIC_HW_MIN_FRS))
266 return 1;
267
268 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
269 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
270 lmac += bgx * MAX_LMAC_PER_BGX;
271
272 new_frs += VLAN_ETH_HLEN + ETH_FCS_LEN + 4;
273
274 /* Update corresponding LMAC credits */
275 lmac_cnt = bgx_get_lmac_count(nic->node, bgx);
276 lmac_credits = nic_reg_read(nic, NIC_PF_LMAC_0_7_CREDIT + (lmac * 8));
277 lmac_credits &= ~(0xFFFFFULL << 12);
278 lmac_credits |= (((((48 * 1024) / lmac_cnt) - new_frs) / 16) << 12);
279 nic_reg_write(nic, NIC_PF_LMAC_0_7_CREDIT + (lmac * 8), lmac_credits);
280
281 /* Enforce MTU in HW
282 * This config is supported only from 88xx pass 2.0 onwards.
283 */
284 if (!pass1_silicon(nic->pdev))
285 nic_reg_write(nic,
286 NIC_PF_LMAC_0_7_CFG2 + (lmac * 8), new_frs);
287 return 0;
288 }
289
290 /* Set minimum transmit packet size */
nic_set_tx_pkt_pad(struct nicpf * nic,int size)291 static void nic_set_tx_pkt_pad(struct nicpf *nic, int size)
292 {
293 int lmac, max_lmac;
294 u16 sdevid;
295 u64 lmac_cfg;
296
297 /* There is a issue in HW where-in while sending GSO sized
298 * pkts as part of TSO, if pkt len falls below this size
299 * NIC will zero PAD packet and also updates IP total length.
300 * Hence set this value to lessthan min pkt size of MAC+IP+TCP
301 * headers, BGX will do the padding to transmit 64 byte pkt.
302 */
303 if (size > 52)
304 size = 52;
305
306 pci_read_config_word(nic->pdev, PCI_SUBSYSTEM_ID, &sdevid);
307 /* 81xx's RGX has only one LMAC */
308 if (sdevid == PCI_SUBSYS_DEVID_81XX_NIC_PF)
309 max_lmac = ((nic->hw->bgx_cnt - 1) * MAX_LMAC_PER_BGX) + 1;
310 else
311 max_lmac = nic->hw->bgx_cnt * MAX_LMAC_PER_BGX;
312
313 for (lmac = 0; lmac < max_lmac; lmac++) {
314 lmac_cfg = nic_reg_read(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3));
315 lmac_cfg &= ~(0xF << 2);
316 lmac_cfg |= ((size / 4) << 2);
317 nic_reg_write(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3), lmac_cfg);
318 }
319 }
320
321 /* Function to check number of LMACs present and set VF::LMAC mapping.
322 * Mapping will be used while initializing channels.
323 */
nic_set_lmac_vf_mapping(struct nicpf * nic)324 static void nic_set_lmac_vf_mapping(struct nicpf *nic)
325 {
326 unsigned bgx_map = bgx_get_map(nic->node);
327 int bgx, next_bgx_lmac = 0;
328 int lmac, lmac_cnt = 0;
329 u64 lmac_credit;
330
331 nic->num_vf_en = 0;
332
333 for (bgx = 0; bgx < nic->hw->bgx_cnt; bgx++) {
334 if (!(bgx_map & (1 << bgx)))
335 continue;
336 lmac_cnt = bgx_get_lmac_count(nic->node, bgx);
337 for (lmac = 0; lmac < lmac_cnt; lmac++)
338 nic->vf_lmac_map[next_bgx_lmac++] =
339 NIC_SET_VF_LMAC_MAP(bgx, lmac);
340 nic->num_vf_en += lmac_cnt;
341
342 /* Program LMAC credits */
343 lmac_credit = (1ull << 1); /* channel credit enable */
344 lmac_credit |= (0x1ff << 2); /* Max outstanding pkt count */
345 /* 48KB BGX Tx buffer size, each unit is of size 16bytes */
346 lmac_credit |= (((((48 * 1024) / lmac_cnt) -
347 NIC_HW_MAX_FRS) / 16) << 12);
348 lmac = bgx * MAX_LMAC_PER_BGX;
349 for (; lmac < lmac_cnt + (bgx * MAX_LMAC_PER_BGX); lmac++)
350 nic_reg_write(nic,
351 NIC_PF_LMAC_0_7_CREDIT + (lmac * 8),
352 lmac_credit);
353
354 /* On CN81XX there are only 8 VFs but max possible no of
355 * interfaces are 9.
356 */
357 if (nic->num_vf_en >= pci_sriov_get_totalvfs(nic->pdev)) {
358 nic->num_vf_en = pci_sriov_get_totalvfs(nic->pdev);
359 break;
360 }
361 }
362 }
363
nic_free_lmacmem(struct nicpf * nic)364 static void nic_free_lmacmem(struct nicpf *nic)
365 {
366 kfree(nic->vf_lmac_map);
367 kfree(nic->link);
368 kfree(nic->duplex);
369 kfree(nic->speed);
370 }
371
nic_get_hw_info(struct nicpf * nic)372 static int nic_get_hw_info(struct nicpf *nic)
373 {
374 u8 max_lmac;
375 u16 sdevid;
376 struct hw_info *hw = nic->hw;
377
378 pci_read_config_word(nic->pdev, PCI_SUBSYSTEM_ID, &sdevid);
379
380 switch (sdevid) {
381 case PCI_SUBSYS_DEVID_88XX_NIC_PF:
382 hw->bgx_cnt = MAX_BGX_PER_CN88XX;
383 hw->chans_per_lmac = 16;
384 hw->chans_per_bgx = 128;
385 hw->cpi_cnt = 2048;
386 hw->rssi_cnt = 4096;
387 hw->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE;
388 hw->tl3_cnt = 256;
389 hw->tl2_cnt = 64;
390 hw->tl1_cnt = 2;
391 hw->tl1_per_bgx = true;
392 break;
393 case PCI_SUBSYS_DEVID_81XX_NIC_PF:
394 hw->bgx_cnt = MAX_BGX_PER_CN81XX;
395 hw->chans_per_lmac = 8;
396 hw->chans_per_bgx = 32;
397 hw->chans_per_rgx = 8;
398 hw->chans_per_lbk = 24;
399 hw->cpi_cnt = 512;
400 hw->rssi_cnt = 256;
401 hw->rss_ind_tbl_size = 32; /* Max RSSI / Max interfaces */
402 hw->tl3_cnt = 64;
403 hw->tl2_cnt = 16;
404 hw->tl1_cnt = 10;
405 hw->tl1_per_bgx = false;
406 break;
407 case PCI_SUBSYS_DEVID_83XX_NIC_PF:
408 hw->bgx_cnt = MAX_BGX_PER_CN83XX;
409 hw->chans_per_lmac = 8;
410 hw->chans_per_bgx = 32;
411 hw->chans_per_lbk = 64;
412 hw->cpi_cnt = 2048;
413 hw->rssi_cnt = 1024;
414 hw->rss_ind_tbl_size = 64; /* Max RSSI / Max interfaces */
415 hw->tl3_cnt = 256;
416 hw->tl2_cnt = 64;
417 hw->tl1_cnt = 18;
418 hw->tl1_per_bgx = false;
419 break;
420 }
421 hw->tl4_cnt = MAX_QUEUES_PER_QSET * pci_sriov_get_totalvfs(nic->pdev);
422
423 /* Allocate memory for LMAC tracking elements */
424 max_lmac = hw->bgx_cnt * MAX_LMAC_PER_BGX;
425 nic->vf_lmac_map = kmalloc_array(max_lmac, sizeof(u8), GFP_KERNEL);
426 if (!nic->vf_lmac_map)
427 goto error;
428 nic->link = kmalloc_array(max_lmac, sizeof(u8), GFP_KERNEL);
429 if (!nic->link)
430 goto error;
431 nic->duplex = kmalloc_array(max_lmac, sizeof(u8), GFP_KERNEL);
432 if (!nic->duplex)
433 goto error;
434 nic->speed = kmalloc_array(max_lmac, sizeof(u32), GFP_KERNEL);
435 if (!nic->speed)
436 goto error;
437 return 0;
438
439 error:
440 nic_free_lmacmem(nic);
441 return -ENOMEM;
442 }
443
444 #define BGX0_BLOCK 8
445 #define BGX1_BLOCK 9
446
nic_init_hw(struct nicpf * nic)447 static int nic_init_hw(struct nicpf *nic)
448 {
449 int i, err;
450 u64 cqm_cfg;
451
452 /* Get HW capability info */
453 err = nic_get_hw_info(nic);
454 if (err)
455 return err;
456
457 /* Enable NIC HW block */
458 nic_reg_write(nic, NIC_PF_CFG, 0x3);
459
460 /* Enable backpressure */
461 nic_reg_write(nic, NIC_PF_BP_CFG, (1ULL << 6) | 0x03);
462
463 /* TNS and TNS bypass modes are present only on 88xx */
464 if (nic->pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF) {
465 /* Disable TNS mode on both interfaces */
466 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG,
467 (NIC_TNS_BYPASS_MODE << 7) | BGX0_BLOCK);
468 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8),
469 (NIC_TNS_BYPASS_MODE << 7) | BGX1_BLOCK);
470 }
471
472 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG,
473 (1ULL << 63) | BGX0_BLOCK);
474 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8),
475 (1ULL << 63) | BGX1_BLOCK);
476
477 /* PKIND configuration */
478 nic->pkind.minlen = 0;
479 nic->pkind.maxlen = NIC_HW_MAX_FRS + VLAN_ETH_HLEN + ETH_FCS_LEN + 4;
480 nic->pkind.lenerr_en = 1;
481 nic->pkind.rx_hdr = 0;
482 nic->pkind.hdr_sl = 0;
483
484 for (i = 0; i < NIC_MAX_PKIND; i++)
485 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (i << 3),
486 *(u64 *)&nic->pkind);
487
488 nic_set_tx_pkt_pad(nic, NIC_HW_MIN_FRS);
489
490 /* Timer config */
491 nic_reg_write(nic, NIC_PF_INTR_TIMER_CFG, NICPF_CLK_PER_INT_TICK);
492
493 /* Enable VLAN ethertype matching and stripping */
494 nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7,
495 (2 << 19) | (ETYPE_ALG_VLAN_STRIP << 16) | ETH_P_8021Q);
496
497 /* Check if HW expected value is higher (could be in future chips) */
498 cqm_cfg = nic_reg_read(nic, NIC_PF_CQM_CFG);
499 if (cqm_cfg < NICPF_CQM_MIN_DROP_LEVEL)
500 nic_reg_write(nic, NIC_PF_CQM_CFG, NICPF_CQM_MIN_DROP_LEVEL);
501
502 return 0;
503 }
504
505 /* Channel parse index configuration */
nic_config_cpi(struct nicpf * nic,struct cpi_cfg_msg * cfg)506 static void nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg)
507 {
508 struct hw_info *hw = nic->hw;
509 u32 vnic, bgx, lmac, chan;
510 u32 padd, cpi_count = 0;
511 u64 cpi_base, cpi, rssi_base, rssi;
512 u8 qset, rq_idx = 0;
513
514 vnic = cfg->vf_id;
515 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
516 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
517
518 chan = (lmac * hw->chans_per_lmac) + (bgx * hw->chans_per_bgx);
519 cpi_base = vnic * NIC_MAX_CPI_PER_LMAC;
520 rssi_base = vnic * hw->rss_ind_tbl_size;
521
522 /* Rx channel configuration */
523 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_BP_CFG | (chan << 3),
524 (1ull << 63) | (vnic << 0));
525 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_CFG | (chan << 3),
526 ((u64)cfg->cpi_alg << 62) | (cpi_base << 48));
527
528 if (cfg->cpi_alg == CPI_ALG_NONE)
529 cpi_count = 1;
530 else if (cfg->cpi_alg == CPI_ALG_VLAN) /* 3 bits of PCP */
531 cpi_count = 8;
532 else if (cfg->cpi_alg == CPI_ALG_VLAN16) /* 3 bits PCP + DEI */
533 cpi_count = 16;
534 else if (cfg->cpi_alg == CPI_ALG_DIFF) /* 6bits DSCP */
535 cpi_count = NIC_MAX_CPI_PER_LMAC;
536
537 /* RSS Qset, Qidx mapping */
538 qset = cfg->vf_id;
539 rssi = rssi_base;
540 for (; rssi < (rssi_base + cfg->rq_cnt); rssi++) {
541 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3),
542 (qset << 3) | rq_idx);
543 rq_idx++;
544 }
545
546 rssi = 0;
547 cpi = cpi_base;
548 for (; cpi < (cpi_base + cpi_count); cpi++) {
549 /* Determine port to channel adder */
550 if (cfg->cpi_alg != CPI_ALG_DIFF)
551 padd = cpi % cpi_count;
552 else
553 padd = cpi % 8; /* 3 bits CS out of 6bits DSCP */
554
555 /* Leave RSS_SIZE as '0' to disable RSS */
556 if (pass1_silicon(nic->pdev)) {
557 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3),
558 (vnic << 24) | (padd << 16) |
559 (rssi_base + rssi));
560 } else {
561 /* Set MPI_ALG to '0' to disable MCAM parsing */
562 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3),
563 (padd << 16));
564 /* MPI index is same as CPI if MPI_ALG is not enabled */
565 nic_reg_write(nic, NIC_PF_MPI_0_2047_CFG | (cpi << 3),
566 (vnic << 24) | (rssi_base + rssi));
567 }
568
569 if ((rssi + 1) >= cfg->rq_cnt)
570 continue;
571
572 if (cfg->cpi_alg == CPI_ALG_VLAN)
573 rssi++;
574 else if (cfg->cpi_alg == CPI_ALG_VLAN16)
575 rssi = ((cpi - cpi_base) & 0xe) >> 1;
576 else if (cfg->cpi_alg == CPI_ALG_DIFF)
577 rssi = ((cpi - cpi_base) & 0x38) >> 3;
578 }
579 nic->cpi_base[cfg->vf_id] = cpi_base;
580 nic->rssi_base[cfg->vf_id] = rssi_base;
581 }
582
583 /* Responsds to VF with its RSS indirection table size */
nic_send_rss_size(struct nicpf * nic,int vf)584 static void nic_send_rss_size(struct nicpf *nic, int vf)
585 {
586 union nic_mbx mbx = {};
587 u64 *msg;
588
589 msg = (u64 *)&mbx;
590
591 mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE;
592 mbx.rss_size.ind_tbl_size = nic->hw->rss_ind_tbl_size;
593 nic_send_msg_to_vf(nic, vf, &mbx);
594 }
595
596 /* Receive side scaling configuration
597 * configure:
598 * - RSS index
599 * - indir table i.e hash::RQ mapping
600 * - no of hash bits to consider
601 */
nic_config_rss(struct nicpf * nic,struct rss_cfg_msg * cfg)602 static void nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg)
603 {
604 u8 qset, idx = 0;
605 u64 cpi_cfg, cpi_base, rssi_base, rssi;
606 u64 idx_addr;
607
608 rssi_base = nic->rssi_base[cfg->vf_id] + cfg->tbl_offset;
609
610 rssi = rssi_base;
611 qset = cfg->vf_id;
612
613 for (; rssi < (rssi_base + cfg->tbl_len); rssi++) {
614 u8 svf = cfg->ind_tbl[idx] >> 3;
615
616 if (svf)
617 qset = nic->vf_sqs[cfg->vf_id][svf - 1];
618 else
619 qset = cfg->vf_id;
620 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3),
621 (qset << 3) | (cfg->ind_tbl[idx] & 0x7));
622 idx++;
623 }
624
625 cpi_base = nic->cpi_base[cfg->vf_id];
626 if (pass1_silicon(nic->pdev))
627 idx_addr = NIC_PF_CPI_0_2047_CFG;
628 else
629 idx_addr = NIC_PF_MPI_0_2047_CFG;
630 cpi_cfg = nic_reg_read(nic, idx_addr | (cpi_base << 3));
631 cpi_cfg &= ~(0xFULL << 20);
632 cpi_cfg |= (cfg->hash_bits << 20);
633 nic_reg_write(nic, idx_addr | (cpi_base << 3), cpi_cfg);
634 }
635
636 /* 4 level transmit side scheduler configutation
637 * for TNS bypass mode
638 *
639 * Sample configuration for SQ0 on 88xx
640 * VNIC0-SQ0 -> TL4(0) -> TL3[0] -> TL2[0] -> TL1[0] -> BGX0
641 * VNIC1-SQ0 -> TL4(8) -> TL3[2] -> TL2[0] -> TL1[0] -> BGX0
642 * VNIC2-SQ0 -> TL4(16) -> TL3[4] -> TL2[1] -> TL1[0] -> BGX0
643 * VNIC3-SQ0 -> TL4(24) -> TL3[6] -> TL2[1] -> TL1[0] -> BGX0
644 * VNIC4-SQ0 -> TL4(512) -> TL3[128] -> TL2[32] -> TL1[1] -> BGX1
645 * VNIC5-SQ0 -> TL4(520) -> TL3[130] -> TL2[32] -> TL1[1] -> BGX1
646 * VNIC6-SQ0 -> TL4(528) -> TL3[132] -> TL2[33] -> TL1[1] -> BGX1
647 * VNIC7-SQ0 -> TL4(536) -> TL3[134] -> TL2[33] -> TL1[1] -> BGX1
648 */
nic_tx_channel_cfg(struct nicpf * nic,u8 vnic,struct sq_cfg_msg * sq)649 static void nic_tx_channel_cfg(struct nicpf *nic, u8 vnic,
650 struct sq_cfg_msg *sq)
651 {
652 struct hw_info *hw = nic->hw;
653 u32 bgx, lmac, chan;
654 u32 tl2, tl3, tl4;
655 u32 rr_quantum;
656 u8 sq_idx = sq->sq_num;
657 u8 pqs_vnic;
658 int svf;
659
660 if (sq->sqs_mode)
661 pqs_vnic = nic->pqs_vf[vnic];
662 else
663 pqs_vnic = vnic;
664
665 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]);
666 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]);
667
668 /* 24 bytes for FCS, IPG and preamble */
669 rr_quantum = ((NIC_HW_MAX_FRS + 24) / 4);
670
671 /* For 88xx 0-511 TL4 transmits via BGX0 and
672 * 512-1023 TL4s transmit via BGX1.
673 */
674 if (hw->tl1_per_bgx) {
675 tl4 = bgx * (hw->tl4_cnt / hw->bgx_cnt);
676 if (!sq->sqs_mode) {
677 tl4 += (lmac * MAX_QUEUES_PER_QSET);
678 } else {
679 for (svf = 0; svf < MAX_SQS_PER_VF; svf++) {
680 if (nic->vf_sqs[pqs_vnic][svf] == vnic)
681 break;
682 }
683 tl4 += (MAX_LMAC_PER_BGX * MAX_QUEUES_PER_QSET);
684 tl4 += (lmac * MAX_QUEUES_PER_QSET * MAX_SQS_PER_VF);
685 tl4 += (svf * MAX_QUEUES_PER_QSET);
686 }
687 } else {
688 tl4 = (vnic * MAX_QUEUES_PER_QSET);
689 }
690 tl4 += sq_idx;
691
692 tl3 = tl4 / (hw->tl4_cnt / hw->tl3_cnt);
693 nic_reg_write(nic, NIC_PF_QSET_0_127_SQ_0_7_CFG2 |
694 ((u64)vnic << NIC_QS_ID_SHIFT) |
695 ((u32)sq_idx << NIC_Q_NUM_SHIFT), tl4);
696 nic_reg_write(nic, NIC_PF_TL4_0_1023_CFG | (tl4 << 3),
697 ((u64)vnic << 27) | ((u32)sq_idx << 24) | rr_quantum);
698
699 nic_reg_write(nic, NIC_PF_TL3_0_255_CFG | (tl3 << 3), rr_quantum);
700
701 /* On 88xx 0-127 channels are for BGX0 and
702 * 127-255 channels for BGX1.
703 *
704 * On 81xx/83xx TL3_CHAN reg should be configured with channel
705 * within LMAC i.e 0-7 and not the actual channel number like on 88xx
706 */
707 chan = (lmac * hw->chans_per_lmac) + (bgx * hw->chans_per_bgx);
708 if (hw->tl1_per_bgx)
709 nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan);
710 else
711 nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), 0);
712
713 /* Enable backpressure on the channel */
714 nic_reg_write(nic, NIC_PF_CHAN_0_255_TX_CFG | (chan << 3), 1);
715
716 tl2 = tl3 >> 2;
717 nic_reg_write(nic, NIC_PF_TL3A_0_63_CFG | (tl2 << 3), tl2);
718 nic_reg_write(nic, NIC_PF_TL2_0_63_CFG | (tl2 << 3), rr_quantum);
719 /* No priorities as of now */
720 nic_reg_write(nic, NIC_PF_TL2_0_63_PRI | (tl2 << 3), 0x00);
721
722 /* Unlike 88xx where TL2s 0-31 transmits to TL1 '0' and rest to TL1 '1'
723 * on 81xx/83xx TL2 needs to be configured to transmit to one of the
724 * possible LMACs.
725 *
726 * This register doesn't exist on 88xx.
727 */
728 if (!hw->tl1_per_bgx)
729 nic_reg_write(nic, NIC_PF_TL2_LMAC | (tl2 << 3),
730 lmac + (bgx * MAX_LMAC_PER_BGX));
731 }
732
733 /* Send primary nicvf pointer to secondary QS's VF */
nic_send_pnicvf(struct nicpf * nic,int sqs)734 static void nic_send_pnicvf(struct nicpf *nic, int sqs)
735 {
736 union nic_mbx mbx = {};
737
738 mbx.nicvf.msg = NIC_MBOX_MSG_PNICVF_PTR;
739 mbx.nicvf.nicvf = nic->nicvf[nic->pqs_vf[sqs]];
740 nic_send_msg_to_vf(nic, sqs, &mbx);
741 }
742
743 /* Send SQS's nicvf pointer to primary QS's VF */
nic_send_snicvf(struct nicpf * nic,struct nicvf_ptr * nicvf)744 static void nic_send_snicvf(struct nicpf *nic, struct nicvf_ptr *nicvf)
745 {
746 union nic_mbx mbx = {};
747 int sqs_id = nic->vf_sqs[nicvf->vf_id][nicvf->sqs_id];
748
749 mbx.nicvf.msg = NIC_MBOX_MSG_SNICVF_PTR;
750 mbx.nicvf.sqs_id = nicvf->sqs_id;
751 mbx.nicvf.nicvf = nic->nicvf[sqs_id];
752 nic_send_msg_to_vf(nic, nicvf->vf_id, &mbx);
753 }
754
755 /* Find next available Qset that can be assigned as a
756 * secondary Qset to a VF.
757 */
nic_nxt_avail_sqs(struct nicpf * nic)758 static int nic_nxt_avail_sqs(struct nicpf *nic)
759 {
760 int sqs;
761
762 for (sqs = 0; sqs < nic->num_sqs_en; sqs++) {
763 if (!nic->sqs_used[sqs])
764 nic->sqs_used[sqs] = true;
765 else
766 continue;
767 return sqs + nic->num_vf_en;
768 }
769 return -1;
770 }
771
772 /* Allocate additional Qsets for requested VF */
nic_alloc_sqs(struct nicpf * nic,struct sqs_alloc * sqs)773 static void nic_alloc_sqs(struct nicpf *nic, struct sqs_alloc *sqs)
774 {
775 union nic_mbx mbx = {};
776 int idx, alloc_qs = 0;
777 int sqs_id;
778
779 if (!nic->num_sqs_en)
780 goto send_mbox;
781
782 for (idx = 0; idx < sqs->qs_count; idx++) {
783 sqs_id = nic_nxt_avail_sqs(nic);
784 if (sqs_id < 0)
785 break;
786 nic->vf_sqs[sqs->vf_id][idx] = sqs_id;
787 nic->pqs_vf[sqs_id] = sqs->vf_id;
788 alloc_qs++;
789 }
790
791 send_mbox:
792 mbx.sqs_alloc.msg = NIC_MBOX_MSG_ALLOC_SQS;
793 mbx.sqs_alloc.vf_id = sqs->vf_id;
794 mbx.sqs_alloc.qs_count = alloc_qs;
795 nic_send_msg_to_vf(nic, sqs->vf_id, &mbx);
796 }
797
nic_config_loopback(struct nicpf * nic,struct set_loopback * lbk)798 static int nic_config_loopback(struct nicpf *nic, struct set_loopback *lbk)
799 {
800 int bgx_idx, lmac_idx;
801
802 if (lbk->vf_id >= nic->num_vf_en)
803 return -1;
804
805 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]);
806 lmac_idx = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]);
807
808 bgx_lmac_internal_loopback(nic->node, bgx_idx, lmac_idx, lbk->enable);
809
810 /* Enable moving average calculation.
811 * Keep the LVL/AVG delay to HW enforced minimum so that, not too many
812 * packets sneek in between average calculations.
813 */
814 nic_reg_write(nic, NIC_PF_CQ_AVG_CFG,
815 (BIT_ULL(20) | 0x2ull << 14 | 0x1));
816 nic_reg_write(nic, NIC_PF_RRM_AVG_CFG,
817 (BIT_ULL(20) | 0x3ull << 14 | 0x1));
818
819 return 0;
820 }
821
822 /* Reset statistics counters */
nic_reset_stat_counters(struct nicpf * nic,int vf,struct reset_stat_cfg * cfg)823 static int nic_reset_stat_counters(struct nicpf *nic,
824 int vf, struct reset_stat_cfg *cfg)
825 {
826 int i, stat, qnum;
827 u64 reg_addr;
828
829 for (i = 0; i < RX_STATS_ENUM_LAST; i++) {
830 if (cfg->rx_stat_mask & BIT(i)) {
831 reg_addr = NIC_PF_VNIC_0_127_RX_STAT_0_13 |
832 (vf << NIC_QS_ID_SHIFT) |
833 (i << 3);
834 nic_reg_write(nic, reg_addr, 0);
835 }
836 }
837
838 for (i = 0; i < TX_STATS_ENUM_LAST; i++) {
839 if (cfg->tx_stat_mask & BIT(i)) {
840 reg_addr = NIC_PF_VNIC_0_127_TX_STAT_0_4 |
841 (vf << NIC_QS_ID_SHIFT) |
842 (i << 3);
843 nic_reg_write(nic, reg_addr, 0);
844 }
845 }
846
847 for (i = 0; i <= 15; i++) {
848 qnum = i >> 1;
849 stat = i & 1 ? 1 : 0;
850 reg_addr = (vf << NIC_QS_ID_SHIFT) |
851 (qnum << NIC_Q_NUM_SHIFT) | (stat << 3);
852 if (cfg->rq_stat_mask & BIT(i)) {
853 reg_addr |= NIC_PF_QSET_0_127_RQ_0_7_STAT_0_1;
854 nic_reg_write(nic, reg_addr, 0);
855 }
856 if (cfg->sq_stat_mask & BIT(i)) {
857 reg_addr |= NIC_PF_QSET_0_127_SQ_0_7_STAT_0_1;
858 nic_reg_write(nic, reg_addr, 0);
859 }
860 }
861
862 return 0;
863 }
864
nic_enable_tunnel_parsing(struct nicpf * nic,int vf)865 static void nic_enable_tunnel_parsing(struct nicpf *nic, int vf)
866 {
867 u64 prot_def = (IPV6_PROT << 32) | (IPV4_PROT << 16) | ET_PROT;
868 u64 vxlan_prot_def = (IPV6_PROT_DEF << 32) |
869 (IPV4_PROT_DEF) << 16 | ET_PROT_DEF;
870
871 /* Configure tunnel parsing parameters */
872 nic_reg_write(nic, NIC_PF_RX_GENEVE_DEF,
873 (1ULL << 63 | UDP_GENEVE_PORT_NUM));
874 nic_reg_write(nic, NIC_PF_RX_GENEVE_PROT_DEF,
875 ((7ULL << 61) | prot_def));
876 nic_reg_write(nic, NIC_PF_RX_NVGRE_PROT_DEF,
877 ((7ULL << 61) | prot_def));
878 nic_reg_write(nic, NIC_PF_RX_VXLAN_DEF_0_1,
879 ((1ULL << 63) | UDP_VXLAN_PORT_NUM));
880 nic_reg_write(nic, NIC_PF_RX_VXLAN_PROT_DEF,
881 ((0xfULL << 60) | vxlan_prot_def));
882 }
883
nic_enable_vf(struct nicpf * nic,int vf,bool enable)884 static void nic_enable_vf(struct nicpf *nic, int vf, bool enable)
885 {
886 int bgx, lmac;
887
888 nic->vf_enabled[vf] = enable;
889
890 if (vf >= nic->num_vf_en)
891 return;
892
893 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
894 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
895
896 bgx_lmac_rx_tx_enable(nic->node, bgx, lmac, enable);
897 }
898
nic_pause_frame(struct nicpf * nic,int vf,struct pfc * cfg)899 static void nic_pause_frame(struct nicpf *nic, int vf, struct pfc *cfg)
900 {
901 int bgx, lmac;
902 struct pfc pfc;
903 union nic_mbx mbx = {};
904
905 if (vf >= nic->num_vf_en)
906 return;
907 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
908 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
909
910 if (cfg->get) {
911 bgx_lmac_get_pfc(nic->node, bgx, lmac, &pfc);
912 mbx.pfc.msg = NIC_MBOX_MSG_PFC;
913 mbx.pfc.autoneg = pfc.autoneg;
914 mbx.pfc.fc_rx = pfc.fc_rx;
915 mbx.pfc.fc_tx = pfc.fc_tx;
916 nic_send_msg_to_vf(nic, vf, &mbx);
917 } else {
918 bgx_lmac_set_pfc(nic->node, bgx, lmac, cfg);
919 nic_mbx_send_ack(nic, vf);
920 }
921 }
922
923 /* Interrupt handler to handle mailbox messages from VFs */
nic_handle_mbx_intr(struct nicpf * nic,int vf)924 static void nic_handle_mbx_intr(struct nicpf *nic, int vf)
925 {
926 union nic_mbx mbx = {};
927 u64 *mbx_data;
928 u64 mbx_addr;
929 u64 reg_addr;
930 u64 cfg;
931 int bgx, lmac;
932 int i;
933 int ret = 0;
934
935 nic->mbx_lock[vf] = true;
936
937 mbx_addr = nic_get_mbx_addr(vf);
938 mbx_data = (u64 *)&mbx;
939
940 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) {
941 *mbx_data = nic_reg_read(nic, mbx_addr);
942 mbx_data++;
943 mbx_addr += sizeof(u64);
944 }
945
946 dev_dbg(&nic->pdev->dev, "%s: Mailbox msg 0x%02x from VF%d\n",
947 __func__, mbx.msg.msg, vf);
948 switch (mbx.msg.msg) {
949 case NIC_MBOX_MSG_READY:
950 nic_mbx_send_ready(nic, vf);
951 if (vf < nic->num_vf_en) {
952 nic->link[vf] = 0;
953 nic->duplex[vf] = 0;
954 nic->speed[vf] = 0;
955 }
956 goto unlock;
957 case NIC_MBOX_MSG_QS_CFG:
958 reg_addr = NIC_PF_QSET_0_127_CFG |
959 (mbx.qs.num << NIC_QS_ID_SHIFT);
960 cfg = mbx.qs.cfg;
961 /* Check if its a secondary Qset */
962 if (vf >= nic->num_vf_en) {
963 cfg = cfg & (~0x7FULL);
964 /* Assign this Qset to primary Qset's VF */
965 cfg |= nic->pqs_vf[vf];
966 }
967 nic_reg_write(nic, reg_addr, cfg);
968 break;
969 case NIC_MBOX_MSG_RQ_CFG:
970 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_CFG |
971 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
972 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
973 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
974 /* Enable CQE_RX2_S extension in CQE_RX descriptor.
975 * This gets appended by default on 81xx/83xx chips,
976 * for consistency enabling the same on 88xx pass2
977 * where this is introduced.
978 */
979 if (pass2_silicon(nic->pdev))
980 nic_reg_write(nic, NIC_PF_RX_CFG, 0x01);
981 if (!pass1_silicon(nic->pdev))
982 nic_enable_tunnel_parsing(nic, vf);
983 break;
984 case NIC_MBOX_MSG_RQ_BP_CFG:
985 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_BP_CFG |
986 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
987 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
988 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
989 break;
990 case NIC_MBOX_MSG_RQ_SW_SYNC:
991 ret = nic_rcv_queue_sw_sync(nic);
992 break;
993 case NIC_MBOX_MSG_RQ_DROP_CFG:
994 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG |
995 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
996 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
997 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
998 break;
999 case NIC_MBOX_MSG_SQ_CFG:
1000 reg_addr = NIC_PF_QSET_0_127_SQ_0_7_CFG |
1001 (mbx.sq.qs_num << NIC_QS_ID_SHIFT) |
1002 (mbx.sq.sq_num << NIC_Q_NUM_SHIFT);
1003 nic_reg_write(nic, reg_addr, mbx.sq.cfg);
1004 nic_tx_channel_cfg(nic, mbx.qs.num, &mbx.sq);
1005 break;
1006 case NIC_MBOX_MSG_SET_MAC:
1007 if (vf >= nic->num_vf_en) {
1008 ret = -1; /* NACK */
1009 break;
1010 }
1011 lmac = mbx.mac.vf_id;
1012 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]);
1013 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]);
1014 bgx_set_lmac_mac(nic->node, bgx, lmac, mbx.mac.mac_addr);
1015 break;
1016 case NIC_MBOX_MSG_SET_MAX_FRS:
1017 ret = nic_update_hw_frs(nic, mbx.frs.max_frs,
1018 mbx.frs.vf_id);
1019 break;
1020 case NIC_MBOX_MSG_CPI_CFG:
1021 nic_config_cpi(nic, &mbx.cpi_cfg);
1022 break;
1023 case NIC_MBOX_MSG_RSS_SIZE:
1024 nic_send_rss_size(nic, vf);
1025 goto unlock;
1026 case NIC_MBOX_MSG_RSS_CFG:
1027 case NIC_MBOX_MSG_RSS_CFG_CONT:
1028 nic_config_rss(nic, &mbx.rss_cfg);
1029 break;
1030 case NIC_MBOX_MSG_CFG_DONE:
1031 /* Last message of VF config msg sequence */
1032 nic_enable_vf(nic, vf, true);
1033 break;
1034 case NIC_MBOX_MSG_SHUTDOWN:
1035 /* First msg in VF teardown sequence */
1036 if (vf >= nic->num_vf_en)
1037 nic->sqs_used[vf - nic->num_vf_en] = false;
1038 nic->pqs_vf[vf] = 0;
1039 nic_enable_vf(nic, vf, false);
1040 break;
1041 case NIC_MBOX_MSG_ALLOC_SQS:
1042 nic_alloc_sqs(nic, &mbx.sqs_alloc);
1043 goto unlock;
1044 case NIC_MBOX_MSG_NICVF_PTR:
1045 nic->nicvf[vf] = mbx.nicvf.nicvf;
1046 break;
1047 case NIC_MBOX_MSG_PNICVF_PTR:
1048 nic_send_pnicvf(nic, vf);
1049 goto unlock;
1050 case NIC_MBOX_MSG_SNICVF_PTR:
1051 nic_send_snicvf(nic, &mbx.nicvf);
1052 goto unlock;
1053 case NIC_MBOX_MSG_BGX_STATS:
1054 nic_get_bgx_stats(nic, &mbx.bgx_stats);
1055 goto unlock;
1056 case NIC_MBOX_MSG_LOOPBACK:
1057 ret = nic_config_loopback(nic, &mbx.lbk);
1058 break;
1059 case NIC_MBOX_MSG_RESET_STAT_COUNTER:
1060 ret = nic_reset_stat_counters(nic, vf, &mbx.reset_stat);
1061 break;
1062 case NIC_MBOX_MSG_PFC:
1063 nic_pause_frame(nic, vf, &mbx.pfc);
1064 goto unlock;
1065 default:
1066 dev_err(&nic->pdev->dev,
1067 "Invalid msg from VF%d, msg 0x%x\n", vf, mbx.msg.msg);
1068 break;
1069 }
1070
1071 if (!ret) {
1072 nic_mbx_send_ack(nic, vf);
1073 } else if (mbx.msg.msg != NIC_MBOX_MSG_READY) {
1074 dev_err(&nic->pdev->dev, "NACK for MBOX 0x%02x from VF %d\n",
1075 mbx.msg.msg, vf);
1076 nic_mbx_send_nack(nic, vf);
1077 }
1078 unlock:
1079 nic->mbx_lock[vf] = false;
1080 }
1081
nic_mbx_intr_handler(int irq,void * nic_irq)1082 static irqreturn_t nic_mbx_intr_handler(int irq, void *nic_irq)
1083 {
1084 struct nicpf *nic = (struct nicpf *)nic_irq;
1085 int mbx;
1086 u64 intr;
1087 u8 vf, vf_per_mbx_reg = 64;
1088
1089 if (irq == pci_irq_vector(nic->pdev, NIC_PF_INTR_ID_MBOX0))
1090 mbx = 0;
1091 else
1092 mbx = 1;
1093
1094 intr = nic_reg_read(nic, NIC_PF_MAILBOX_INT + (mbx << 3));
1095 dev_dbg(&nic->pdev->dev, "PF interrupt Mbox%d 0x%llx\n", mbx, intr);
1096 for (vf = 0; vf < vf_per_mbx_reg; vf++) {
1097 if (intr & (1ULL << vf)) {
1098 dev_dbg(&nic->pdev->dev, "Intr from VF %d\n",
1099 vf + (mbx * vf_per_mbx_reg));
1100
1101 nic_handle_mbx_intr(nic, vf + (mbx * vf_per_mbx_reg));
1102 nic_clear_mbx_intr(nic, vf, mbx);
1103 }
1104 }
1105 return IRQ_HANDLED;
1106 }
1107
nic_free_all_interrupts(struct nicpf * nic)1108 static void nic_free_all_interrupts(struct nicpf *nic)
1109 {
1110 int irq;
1111
1112 for (irq = 0; irq < nic->num_vec; irq++) {
1113 if (nic->irq_allocated[irq])
1114 free_irq(pci_irq_vector(nic->pdev, irq), nic);
1115 nic->irq_allocated[irq] = false;
1116 }
1117 }
1118
nic_register_interrupts(struct nicpf * nic)1119 static int nic_register_interrupts(struct nicpf *nic)
1120 {
1121 int i, ret;
1122 nic->num_vec = pci_msix_vec_count(nic->pdev);
1123
1124 /* Enable MSI-X */
1125 ret = pci_alloc_irq_vectors(nic->pdev, nic->num_vec, nic->num_vec,
1126 PCI_IRQ_MSIX);
1127 if (ret < 0) {
1128 dev_err(&nic->pdev->dev,
1129 "Request for #%d msix vectors failed, returned %d\n",
1130 nic->num_vec, ret);
1131 return 1;
1132 }
1133
1134 /* Register mailbox interrupt handler */
1135 for (i = NIC_PF_INTR_ID_MBOX0; i < nic->num_vec; i++) {
1136 sprintf(nic->irq_name[i],
1137 "NICPF Mbox%d", (i - NIC_PF_INTR_ID_MBOX0));
1138
1139 ret = request_irq(pci_irq_vector(nic->pdev, i),
1140 nic_mbx_intr_handler, 0,
1141 nic->irq_name[i], nic);
1142 if (ret)
1143 goto fail;
1144
1145 nic->irq_allocated[i] = true;
1146 }
1147
1148 /* Enable mailbox interrupt */
1149 nic_enable_mbx_intr(nic);
1150 return 0;
1151
1152 fail:
1153 dev_err(&nic->pdev->dev, "Request irq failed\n");
1154 nic_free_all_interrupts(nic);
1155 pci_free_irq_vectors(nic->pdev);
1156 nic->num_vec = 0;
1157 return ret;
1158 }
1159
nic_unregister_interrupts(struct nicpf * nic)1160 static void nic_unregister_interrupts(struct nicpf *nic)
1161 {
1162 nic_free_all_interrupts(nic);
1163 pci_free_irq_vectors(nic->pdev);
1164 nic->num_vec = 0;
1165 }
1166
nic_num_sqs_en(struct nicpf * nic,int vf_en)1167 static int nic_num_sqs_en(struct nicpf *nic, int vf_en)
1168 {
1169 int pos, sqs_per_vf = MAX_SQS_PER_VF_SINGLE_NODE;
1170 u16 total_vf;
1171
1172 /* Secondary Qsets are needed only if CPU count is
1173 * morethan MAX_QUEUES_PER_QSET.
1174 */
1175 if (num_online_cpus() <= MAX_QUEUES_PER_QSET)
1176 return 0;
1177
1178 /* Check if its a multi-node environment */
1179 if (nr_node_ids > 1)
1180 sqs_per_vf = MAX_SQS_PER_VF;
1181
1182 pos = pci_find_ext_capability(nic->pdev, PCI_EXT_CAP_ID_SRIOV);
1183 pci_read_config_word(nic->pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf);
1184 return min(total_vf - vf_en, vf_en * sqs_per_vf);
1185 }
1186
nic_sriov_init(struct pci_dev * pdev,struct nicpf * nic)1187 static int nic_sriov_init(struct pci_dev *pdev, struct nicpf *nic)
1188 {
1189 int pos = 0;
1190 int vf_en;
1191 int err;
1192 u16 total_vf_cnt;
1193
1194 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1195 if (!pos) {
1196 dev_err(&pdev->dev, "SRIOV capability is not found in PCIe config space\n");
1197 return -ENODEV;
1198 }
1199
1200 pci_read_config_word(pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf_cnt);
1201 if (total_vf_cnt < nic->num_vf_en)
1202 nic->num_vf_en = total_vf_cnt;
1203
1204 if (!total_vf_cnt)
1205 return 0;
1206
1207 vf_en = nic->num_vf_en;
1208 nic->num_sqs_en = nic_num_sqs_en(nic, nic->num_vf_en);
1209 vf_en += nic->num_sqs_en;
1210
1211 err = pci_enable_sriov(pdev, vf_en);
1212 if (err) {
1213 dev_err(&pdev->dev, "SRIOV enable failed, num VF is %d\n",
1214 vf_en);
1215 nic->num_vf_en = 0;
1216 return err;
1217 }
1218
1219 dev_info(&pdev->dev, "SRIOV enabled, number of VF available %d\n",
1220 vf_en);
1221
1222 nic->flags |= NIC_SRIOV_ENABLED;
1223 return 0;
1224 }
1225
1226 /* Poll for BGX LMAC link status and update corresponding VF
1227 * if there is a change, valid only if internal L2 switch
1228 * is not present otherwise VF link is always treated as up
1229 */
nic_poll_for_link(struct work_struct * work)1230 static void nic_poll_for_link(struct work_struct *work)
1231 {
1232 union nic_mbx mbx = {};
1233 struct nicpf *nic;
1234 struct bgx_link_status link;
1235 u8 vf, bgx, lmac;
1236
1237 nic = container_of(work, struct nicpf, dwork.work);
1238
1239 mbx.link_status.msg = NIC_MBOX_MSG_BGX_LINK_CHANGE;
1240
1241 for (vf = 0; vf < nic->num_vf_en; vf++) {
1242 /* Poll only if VF is UP */
1243 if (!nic->vf_enabled[vf])
1244 continue;
1245
1246 /* Get BGX, LMAC indices for the VF */
1247 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
1248 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
1249 /* Get interface link status */
1250 bgx_get_lmac_link_state(nic->node, bgx, lmac, &link);
1251
1252 /* Inform VF only if link status changed */
1253 if (nic->link[vf] == link.link_up)
1254 continue;
1255
1256 if (!nic->mbx_lock[vf]) {
1257 nic->link[vf] = link.link_up;
1258 nic->duplex[vf] = link.duplex;
1259 nic->speed[vf] = link.speed;
1260
1261 /* Send a mbox message to VF with current link status */
1262 mbx.link_status.link_up = link.link_up;
1263 mbx.link_status.duplex = link.duplex;
1264 mbx.link_status.speed = link.speed;
1265 mbx.link_status.mac_type = link.mac_type;
1266 nic_send_msg_to_vf(nic, vf, &mbx);
1267 }
1268 }
1269 queue_delayed_work(nic->check_link, &nic->dwork, HZ * 2);
1270 }
1271
nic_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1272 static int nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1273 {
1274 struct device *dev = &pdev->dev;
1275 struct nicpf *nic;
1276 int err;
1277
1278 BUILD_BUG_ON(sizeof(union nic_mbx) > 16);
1279
1280 nic = devm_kzalloc(dev, sizeof(*nic), GFP_KERNEL);
1281 if (!nic)
1282 return -ENOMEM;
1283
1284 nic->hw = devm_kzalloc(dev, sizeof(struct hw_info), GFP_KERNEL);
1285 if (!nic->hw) {
1286 devm_kfree(dev, nic);
1287 return -ENOMEM;
1288 }
1289
1290 pci_set_drvdata(pdev, nic);
1291
1292 nic->pdev = pdev;
1293
1294 err = pci_enable_device(pdev);
1295 if (err) {
1296 dev_err(dev, "Failed to enable PCI device\n");
1297 pci_set_drvdata(pdev, NULL);
1298 return err;
1299 }
1300
1301 err = pci_request_regions(pdev, DRV_NAME);
1302 if (err) {
1303 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1304 goto err_disable_device;
1305 }
1306
1307 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48));
1308 if (err) {
1309 dev_err(dev, "Unable to get usable DMA configuration\n");
1310 goto err_release_regions;
1311 }
1312
1313 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48));
1314 if (err) {
1315 dev_err(dev, "Unable to get 48-bit DMA for consistent allocations\n");
1316 goto err_release_regions;
1317 }
1318
1319 /* MAP PF's configuration registers */
1320 nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1321 if (!nic->reg_base) {
1322 dev_err(dev, "Cannot map config register space, aborting\n");
1323 err = -ENOMEM;
1324 goto err_release_regions;
1325 }
1326
1327 nic->node = nic_get_node_id(pdev);
1328
1329 /* Initialize hardware */
1330 err = nic_init_hw(nic);
1331 if (err)
1332 goto err_release_regions;
1333
1334 nic_set_lmac_vf_mapping(nic);
1335
1336 /* Register interrupts */
1337 err = nic_register_interrupts(nic);
1338 if (err)
1339 goto err_release_regions;
1340
1341 /* Configure SRIOV */
1342 err = nic_sriov_init(pdev, nic);
1343 if (err)
1344 goto err_unregister_interrupts;
1345
1346 /* Register a physical link status poll fn() */
1347 nic->check_link = alloc_workqueue("check_link_status",
1348 WQ_UNBOUND | WQ_MEM_RECLAIM, 1);
1349 if (!nic->check_link) {
1350 err = -ENOMEM;
1351 goto err_disable_sriov;
1352 }
1353
1354 INIT_DELAYED_WORK(&nic->dwork, nic_poll_for_link);
1355 queue_delayed_work(nic->check_link, &nic->dwork, 0);
1356
1357 return 0;
1358
1359 err_disable_sriov:
1360 if (nic->flags & NIC_SRIOV_ENABLED)
1361 pci_disable_sriov(pdev);
1362 err_unregister_interrupts:
1363 nic_unregister_interrupts(nic);
1364 err_release_regions:
1365 pci_release_regions(pdev);
1366 err_disable_device:
1367 nic_free_lmacmem(nic);
1368 devm_kfree(dev, nic->hw);
1369 devm_kfree(dev, nic);
1370 pci_disable_device(pdev);
1371 pci_set_drvdata(pdev, NULL);
1372 return err;
1373 }
1374
nic_remove(struct pci_dev * pdev)1375 static void nic_remove(struct pci_dev *pdev)
1376 {
1377 struct nicpf *nic = pci_get_drvdata(pdev);
1378
1379 if (!nic)
1380 return;
1381
1382 if (nic->flags & NIC_SRIOV_ENABLED)
1383 pci_disable_sriov(pdev);
1384
1385 if (nic->check_link) {
1386 /* Destroy work Queue */
1387 cancel_delayed_work_sync(&nic->dwork);
1388 destroy_workqueue(nic->check_link);
1389 }
1390
1391 nic_unregister_interrupts(nic);
1392 pci_release_regions(pdev);
1393
1394 nic_free_lmacmem(nic);
1395 devm_kfree(&pdev->dev, nic->hw);
1396 devm_kfree(&pdev->dev, nic);
1397
1398 pci_disable_device(pdev);
1399 pci_set_drvdata(pdev, NULL);
1400 }
1401
1402 static struct pci_driver nic_driver = {
1403 .name = DRV_NAME,
1404 .id_table = nic_id_table,
1405 .probe = nic_probe,
1406 .remove = nic_remove,
1407 };
1408
nic_init_module(void)1409 static int __init nic_init_module(void)
1410 {
1411 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1412
1413 return pci_register_driver(&nic_driver);
1414 }
1415
nic_cleanup_module(void)1416 static void __exit nic_cleanup_module(void)
1417 {
1418 pci_unregister_driver(&nic_driver);
1419 }
1420
1421 module_init(nic_init_module);
1422 module_exit(nic_cleanup_module);
1423