1 /* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
2 *
3 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, see <http://www.gnu.org/licenses/>.
17 */
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/pci.h>
21 #include <linux/ptp_classify.h>
22
23 #include "igb.h"
24
25 #define INCVALUE_MASK 0x7fffffff
26 #define ISGN 0x80000000
27
28 /* The 82580 timesync updates the system timer every 8ns by 8ns,
29 * and this update value cannot be reprogrammed.
30 *
31 * Neither the 82576 nor the 82580 offer registers wide enough to hold
32 * nanoseconds time values for very long. For the 82580, SYSTIM always
33 * counts nanoseconds, but the upper 24 bits are not available. The
34 * frequency is adjusted by changing the 32 bit fractional nanoseconds
35 * register, TIMINCA.
36 *
37 * For the 82576, the SYSTIM register time unit is affect by the
38 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
39 * field are needed to provide the nominal 16 nanosecond period,
40 * leaving 19 bits for fractional nanoseconds.
41 *
42 * We scale the NIC clock cycle by a large factor so that relatively
43 * small clock corrections can be added or subtracted at each clock
44 * tick. The drawbacks of a large factor are a) that the clock
45 * register overflows more quickly (not such a big deal) and b) that
46 * the increment per tick has to fit into 24 bits. As a result we
47 * need to use a shift of 19 so we can fit a value of 16 into the
48 * TIMINCA register.
49 *
50 *
51 * SYSTIMH SYSTIML
52 * +--------------+ +---+---+------+
53 * 82576 | 32 | | 8 | 5 | 19 |
54 * +--------------+ +---+---+------+
55 * \________ 45 bits _______/ fract
56 *
57 * +----------+---+ +--------------+
58 * 82580 | 24 | 8 | | 32 |
59 * +----------+---+ +--------------+
60 * reserved \______ 40 bits _____/
61 *
62 *
63 * The 45 bit 82576 SYSTIM overflows every
64 * 2^45 * 10^-9 / 3600 = 9.77 hours.
65 *
66 * The 40 bit 82580 SYSTIM overflows every
67 * 2^40 * 10^-9 / 60 = 18.3 minutes.
68 *
69 * SYSTIM is converted to real time using a timecounter. As
70 * timecounter_cyc2time() allows old timestamps, the timecounter
71 * needs to be updated at least once per half of the SYSTIM interval.
72 * Scheduling of delayed work is not very accurate, so we aim for 8
73 * minutes to be sure the actual interval is shorter than 9.16 minutes.
74 */
75
76 #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 8)
77 #define IGB_PTP_TX_TIMEOUT (HZ * 15)
78 #define INCPERIOD_82576 BIT(E1000_TIMINCA_16NS_SHIFT)
79 #define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)
80 #define INCVALUE_82576 (16u << IGB_82576_TSYNC_SHIFT)
81 #define IGB_NBITS_82580 40
82
83 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
84
85 /* SYSTIM read access for the 82576 */
igb_ptp_read_82576(const struct cyclecounter * cc)86 static u64 igb_ptp_read_82576(const struct cyclecounter *cc)
87 {
88 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
89 struct e1000_hw *hw = &igb->hw;
90 u64 val;
91 u32 lo, hi;
92
93 lo = rd32(E1000_SYSTIML);
94 hi = rd32(E1000_SYSTIMH);
95
96 val = ((u64) hi) << 32;
97 val |= lo;
98
99 return val;
100 }
101
102 /* SYSTIM read access for the 82580 */
igb_ptp_read_82580(const struct cyclecounter * cc)103 static u64 igb_ptp_read_82580(const struct cyclecounter *cc)
104 {
105 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
106 struct e1000_hw *hw = &igb->hw;
107 u32 lo, hi;
108 u64 val;
109
110 /* The timestamp latches on lowest register read. For the 82580
111 * the lowest register is SYSTIMR instead of SYSTIML. However we only
112 * need to provide nanosecond resolution, so we just ignore it.
113 */
114 rd32(E1000_SYSTIMR);
115 lo = rd32(E1000_SYSTIML);
116 hi = rd32(E1000_SYSTIMH);
117
118 val = ((u64) hi) << 32;
119 val |= lo;
120
121 return val;
122 }
123
124 /* SYSTIM read access for I210/I211 */
igb_ptp_read_i210(struct igb_adapter * adapter,struct timespec64 * ts)125 static void igb_ptp_read_i210(struct igb_adapter *adapter,
126 struct timespec64 *ts)
127 {
128 struct e1000_hw *hw = &adapter->hw;
129 u32 sec, nsec;
130
131 /* The timestamp latches on lowest register read. For I210/I211, the
132 * lowest register is SYSTIMR. Since we only need to provide nanosecond
133 * resolution, we can ignore it.
134 */
135 rd32(E1000_SYSTIMR);
136 nsec = rd32(E1000_SYSTIML);
137 sec = rd32(E1000_SYSTIMH);
138
139 ts->tv_sec = sec;
140 ts->tv_nsec = nsec;
141 }
142
igb_ptp_write_i210(struct igb_adapter * adapter,const struct timespec64 * ts)143 static void igb_ptp_write_i210(struct igb_adapter *adapter,
144 const struct timespec64 *ts)
145 {
146 struct e1000_hw *hw = &adapter->hw;
147
148 /* Writing the SYSTIMR register is not necessary as it only provides
149 * sub-nanosecond resolution.
150 */
151 wr32(E1000_SYSTIML, ts->tv_nsec);
152 wr32(E1000_SYSTIMH, (u32)ts->tv_sec);
153 }
154
155 /**
156 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
157 * @adapter: board private structure
158 * @hwtstamps: timestamp structure to update
159 * @systim: unsigned 64bit system time value.
160 *
161 * We need to convert the system time value stored in the RX/TXSTMP registers
162 * into a hwtstamp which can be used by the upper level timestamping functions.
163 *
164 * The 'tmreg_lock' spinlock is used to protect the consistency of the
165 * system time value. This is needed because reading the 64 bit time
166 * value involves reading two (or three) 32 bit registers. The first
167 * read latches the value. Ditto for writing.
168 *
169 * In addition, here have extended the system time with an overflow
170 * counter in software.
171 **/
igb_ptp_systim_to_hwtstamp(struct igb_adapter * adapter,struct skb_shared_hwtstamps * hwtstamps,u64 systim)172 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
173 struct skb_shared_hwtstamps *hwtstamps,
174 u64 systim)
175 {
176 unsigned long flags;
177 u64 ns;
178
179 switch (adapter->hw.mac.type) {
180 case e1000_82576:
181 case e1000_82580:
182 case e1000_i354:
183 case e1000_i350:
184 spin_lock_irqsave(&adapter->tmreg_lock, flags);
185
186 ns = timecounter_cyc2time(&adapter->tc, systim);
187
188 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
189
190 memset(hwtstamps, 0, sizeof(*hwtstamps));
191 hwtstamps->hwtstamp = ns_to_ktime(ns);
192 break;
193 case e1000_i210:
194 case e1000_i211:
195 memset(hwtstamps, 0, sizeof(*hwtstamps));
196 /* Upper 32 bits contain s, lower 32 bits contain ns. */
197 hwtstamps->hwtstamp = ktime_set(systim >> 32,
198 systim & 0xFFFFFFFF);
199 break;
200 default:
201 break;
202 }
203 }
204
205 /* PTP clock operations */
igb_ptp_adjfreq_82576(struct ptp_clock_info * ptp,s32 ppb)206 static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb)
207 {
208 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
209 ptp_caps);
210 struct e1000_hw *hw = &igb->hw;
211 int neg_adj = 0;
212 u64 rate;
213 u32 incvalue;
214
215 if (ppb < 0) {
216 neg_adj = 1;
217 ppb = -ppb;
218 }
219 rate = ppb;
220 rate <<= 14;
221 rate = div_u64(rate, 1953125);
222
223 incvalue = 16 << IGB_82576_TSYNC_SHIFT;
224
225 if (neg_adj)
226 incvalue -= rate;
227 else
228 incvalue += rate;
229
230 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
231
232 return 0;
233 }
234
igb_ptp_adjfine_82580(struct ptp_clock_info * ptp,long scaled_ppm)235 static int igb_ptp_adjfine_82580(struct ptp_clock_info *ptp, long scaled_ppm)
236 {
237 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
238 ptp_caps);
239 struct e1000_hw *hw = &igb->hw;
240 int neg_adj = 0;
241 u64 rate;
242 u32 inca;
243
244 if (scaled_ppm < 0) {
245 neg_adj = 1;
246 scaled_ppm = -scaled_ppm;
247 }
248 rate = scaled_ppm;
249 rate <<= 13;
250 rate = div_u64(rate, 15625);
251
252 inca = rate & INCVALUE_MASK;
253 if (neg_adj)
254 inca |= ISGN;
255
256 wr32(E1000_TIMINCA, inca);
257
258 return 0;
259 }
260
igb_ptp_adjtime_82576(struct ptp_clock_info * ptp,s64 delta)261 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)
262 {
263 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
264 ptp_caps);
265 unsigned long flags;
266
267 spin_lock_irqsave(&igb->tmreg_lock, flags);
268 timecounter_adjtime(&igb->tc, delta);
269 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
270
271 return 0;
272 }
273
igb_ptp_adjtime_i210(struct ptp_clock_info * ptp,s64 delta)274 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)
275 {
276 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
277 ptp_caps);
278 unsigned long flags;
279 struct timespec64 now, then = ns_to_timespec64(delta);
280
281 spin_lock_irqsave(&igb->tmreg_lock, flags);
282
283 igb_ptp_read_i210(igb, &now);
284 now = timespec64_add(now, then);
285 igb_ptp_write_i210(igb, (const struct timespec64 *)&now);
286
287 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
288
289 return 0;
290 }
291
igb_ptp_gettime_82576(struct ptp_clock_info * ptp,struct timespec64 * ts)292 static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp,
293 struct timespec64 *ts)
294 {
295 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
296 ptp_caps);
297 unsigned long flags;
298 u64 ns;
299
300 spin_lock_irqsave(&igb->tmreg_lock, flags);
301
302 ns = timecounter_read(&igb->tc);
303
304 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
305
306 *ts = ns_to_timespec64(ns);
307
308 return 0;
309 }
310
igb_ptp_gettime_i210(struct ptp_clock_info * ptp,struct timespec64 * ts)311 static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp,
312 struct timespec64 *ts)
313 {
314 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
315 ptp_caps);
316 unsigned long flags;
317
318 spin_lock_irqsave(&igb->tmreg_lock, flags);
319
320 igb_ptp_read_i210(igb, ts);
321
322 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
323
324 return 0;
325 }
326
igb_ptp_settime_82576(struct ptp_clock_info * ptp,const struct timespec64 * ts)327 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp,
328 const struct timespec64 *ts)
329 {
330 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
331 ptp_caps);
332 unsigned long flags;
333 u64 ns;
334
335 ns = timespec64_to_ns(ts);
336
337 spin_lock_irqsave(&igb->tmreg_lock, flags);
338
339 timecounter_init(&igb->tc, &igb->cc, ns);
340
341 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
342
343 return 0;
344 }
345
igb_ptp_settime_i210(struct ptp_clock_info * ptp,const struct timespec64 * ts)346 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp,
347 const struct timespec64 *ts)
348 {
349 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
350 ptp_caps);
351 unsigned long flags;
352
353 spin_lock_irqsave(&igb->tmreg_lock, flags);
354
355 igb_ptp_write_i210(igb, ts);
356
357 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
358
359 return 0;
360 }
361
igb_pin_direction(int pin,int input,u32 * ctrl,u32 * ctrl_ext)362 static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
363 {
364 u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
365 static const u32 mask[IGB_N_SDP] = {
366 E1000_CTRL_SDP0_DIR,
367 E1000_CTRL_SDP1_DIR,
368 E1000_CTRL_EXT_SDP2_DIR,
369 E1000_CTRL_EXT_SDP3_DIR,
370 };
371
372 if (input)
373 *ptr &= ~mask[pin];
374 else
375 *ptr |= mask[pin];
376 }
377
igb_pin_extts(struct igb_adapter * igb,int chan,int pin)378 static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin)
379 {
380 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
381 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
382 };
383 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
384 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
385 };
386 static const u32 ts_sdp_en[IGB_N_SDP] = {
387 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
388 };
389 struct e1000_hw *hw = &igb->hw;
390 u32 ctrl, ctrl_ext, tssdp = 0;
391
392 ctrl = rd32(E1000_CTRL);
393 ctrl_ext = rd32(E1000_CTRL_EXT);
394 tssdp = rd32(E1000_TSSDP);
395
396 igb_pin_direction(pin, 1, &ctrl, &ctrl_ext);
397
398 /* Make sure this pin is not enabled as an output. */
399 tssdp &= ~ts_sdp_en[pin];
400
401 if (chan == 1) {
402 tssdp &= ~AUX1_SEL_SDP3;
403 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN;
404 } else {
405 tssdp &= ~AUX0_SEL_SDP3;
406 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN;
407 }
408
409 wr32(E1000_TSSDP, tssdp);
410 wr32(E1000_CTRL, ctrl);
411 wr32(E1000_CTRL_EXT, ctrl_ext);
412 }
413
igb_pin_perout(struct igb_adapter * igb,int chan,int pin,int freq)414 static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq)
415 {
416 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
417 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
418 };
419 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
420 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
421 };
422 static const u32 ts_sdp_en[IGB_N_SDP] = {
423 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
424 };
425 static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = {
426 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0,
427 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0,
428 };
429 static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = {
430 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1,
431 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1,
432 };
433 static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = {
434 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0,
435 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0,
436 };
437 static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = {
438 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
439 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
440 };
441 static const u32 ts_sdp_sel_clr[IGB_N_SDP] = {
442 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
443 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
444 };
445 struct e1000_hw *hw = &igb->hw;
446 u32 ctrl, ctrl_ext, tssdp = 0;
447
448 ctrl = rd32(E1000_CTRL);
449 ctrl_ext = rd32(E1000_CTRL_EXT);
450 tssdp = rd32(E1000_TSSDP);
451
452 igb_pin_direction(pin, 0, &ctrl, &ctrl_ext);
453
454 /* Make sure this pin is not enabled as an input. */
455 if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin])
456 tssdp &= ~AUX0_TS_SDP_EN;
457
458 if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin])
459 tssdp &= ~AUX1_TS_SDP_EN;
460
461 tssdp &= ~ts_sdp_sel_clr[pin];
462 if (freq) {
463 if (chan == 1)
464 tssdp |= ts_sdp_sel_fc1[pin];
465 else
466 tssdp |= ts_sdp_sel_fc0[pin];
467 } else {
468 if (chan == 1)
469 tssdp |= ts_sdp_sel_tt1[pin];
470 else
471 tssdp |= ts_sdp_sel_tt0[pin];
472 }
473 tssdp |= ts_sdp_en[pin];
474
475 wr32(E1000_TSSDP, tssdp);
476 wr32(E1000_CTRL, ctrl);
477 wr32(E1000_CTRL_EXT, ctrl_ext);
478 }
479
igb_ptp_feature_enable_i210(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)480 static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp,
481 struct ptp_clock_request *rq, int on)
482 {
483 struct igb_adapter *igb =
484 container_of(ptp, struct igb_adapter, ptp_caps);
485 struct e1000_hw *hw = &igb->hw;
486 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
487 unsigned long flags;
488 struct timespec64 ts;
489 int use_freq = 0, pin = -1;
490 s64 ns;
491
492 switch (rq->type) {
493 case PTP_CLK_REQ_EXTTS:
494 if (on) {
495 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS,
496 rq->extts.index);
497 if (pin < 0)
498 return -EBUSY;
499 }
500 if (rq->extts.index == 1) {
501 tsauxc_mask = TSAUXC_EN_TS1;
502 tsim_mask = TSINTR_AUTT1;
503 } else {
504 tsauxc_mask = TSAUXC_EN_TS0;
505 tsim_mask = TSINTR_AUTT0;
506 }
507 spin_lock_irqsave(&igb->tmreg_lock, flags);
508 tsauxc = rd32(E1000_TSAUXC);
509 tsim = rd32(E1000_TSIM);
510 if (on) {
511 igb_pin_extts(igb, rq->extts.index, pin);
512 tsauxc |= tsauxc_mask;
513 tsim |= tsim_mask;
514 } else {
515 tsauxc &= ~tsauxc_mask;
516 tsim &= ~tsim_mask;
517 }
518 wr32(E1000_TSAUXC, tsauxc);
519 wr32(E1000_TSIM, tsim);
520 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
521 return 0;
522
523 case PTP_CLK_REQ_PEROUT:
524 if (on) {
525 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT,
526 rq->perout.index);
527 if (pin < 0)
528 return -EBUSY;
529 }
530 ts.tv_sec = rq->perout.period.sec;
531 ts.tv_nsec = rq->perout.period.nsec;
532 ns = timespec64_to_ns(&ts);
533 ns = ns >> 1;
534 if (on && ((ns <= 70000000LL) || (ns == 125000000LL) ||
535 (ns == 250000000LL) || (ns == 500000000LL))) {
536 if (ns < 8LL)
537 return -EINVAL;
538 use_freq = 1;
539 }
540 ts = ns_to_timespec64(ns);
541 if (rq->perout.index == 1) {
542 if (use_freq) {
543 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1;
544 tsim_mask = 0;
545 } else {
546 tsauxc_mask = TSAUXC_EN_TT1;
547 tsim_mask = TSINTR_TT1;
548 }
549 trgttiml = E1000_TRGTTIML1;
550 trgttimh = E1000_TRGTTIMH1;
551 freqout = E1000_FREQOUT1;
552 } else {
553 if (use_freq) {
554 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0;
555 tsim_mask = 0;
556 } else {
557 tsauxc_mask = TSAUXC_EN_TT0;
558 tsim_mask = TSINTR_TT0;
559 }
560 trgttiml = E1000_TRGTTIML0;
561 trgttimh = E1000_TRGTTIMH0;
562 freqout = E1000_FREQOUT0;
563 }
564 spin_lock_irqsave(&igb->tmreg_lock, flags);
565 tsauxc = rd32(E1000_TSAUXC);
566 tsim = rd32(E1000_TSIM);
567 if (rq->perout.index == 1) {
568 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1);
569 tsim &= ~TSINTR_TT1;
570 } else {
571 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0);
572 tsim &= ~TSINTR_TT0;
573 }
574 if (on) {
575 int i = rq->perout.index;
576 igb_pin_perout(igb, i, pin, use_freq);
577 igb->perout[i].start.tv_sec = rq->perout.start.sec;
578 igb->perout[i].start.tv_nsec = rq->perout.start.nsec;
579 igb->perout[i].period.tv_sec = ts.tv_sec;
580 igb->perout[i].period.tv_nsec = ts.tv_nsec;
581 wr32(trgttimh, rq->perout.start.sec);
582 wr32(trgttiml, rq->perout.start.nsec);
583 if (use_freq)
584 wr32(freqout, ns);
585 tsauxc |= tsauxc_mask;
586 tsim |= tsim_mask;
587 }
588 wr32(E1000_TSAUXC, tsauxc);
589 wr32(E1000_TSIM, tsim);
590 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
591 return 0;
592
593 case PTP_CLK_REQ_PPS:
594 spin_lock_irqsave(&igb->tmreg_lock, flags);
595 tsim = rd32(E1000_TSIM);
596 if (on)
597 tsim |= TSINTR_SYS_WRAP;
598 else
599 tsim &= ~TSINTR_SYS_WRAP;
600 igb->pps_sys_wrap_on = !!on;
601 wr32(E1000_TSIM, tsim);
602 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
603 return 0;
604 }
605
606 return -EOPNOTSUPP;
607 }
608
igb_ptp_feature_enable(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)609 static int igb_ptp_feature_enable(struct ptp_clock_info *ptp,
610 struct ptp_clock_request *rq, int on)
611 {
612 return -EOPNOTSUPP;
613 }
614
igb_ptp_verify_pin(struct ptp_clock_info * ptp,unsigned int pin,enum ptp_pin_function func,unsigned int chan)615 static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
616 enum ptp_pin_function func, unsigned int chan)
617 {
618 switch (func) {
619 case PTP_PF_NONE:
620 case PTP_PF_EXTTS:
621 case PTP_PF_PEROUT:
622 break;
623 case PTP_PF_PHYSYNC:
624 return -1;
625 }
626 return 0;
627 }
628
629 /**
630 * igb_ptp_tx_work
631 * @work: pointer to work struct
632 *
633 * This work function polls the TSYNCTXCTL valid bit to determine when a
634 * timestamp has been taken for the current stored skb.
635 **/
igb_ptp_tx_work(struct work_struct * work)636 static void igb_ptp_tx_work(struct work_struct *work)
637 {
638 struct igb_adapter *adapter = container_of(work, struct igb_adapter,
639 ptp_tx_work);
640 struct e1000_hw *hw = &adapter->hw;
641 u32 tsynctxctl;
642
643 if (!adapter->ptp_tx_skb)
644 return;
645
646 if (time_is_before_jiffies(adapter->ptp_tx_start +
647 IGB_PTP_TX_TIMEOUT)) {
648 dev_kfree_skb_any(adapter->ptp_tx_skb);
649 adapter->ptp_tx_skb = NULL;
650 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
651 adapter->tx_hwtstamp_timeouts++;
652 /* Clear the tx valid bit in TSYNCTXCTL register to enable
653 * interrupt
654 */
655 rd32(E1000_TXSTMPH);
656 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
657 return;
658 }
659
660 tsynctxctl = rd32(E1000_TSYNCTXCTL);
661 if (tsynctxctl & E1000_TSYNCTXCTL_VALID)
662 igb_ptp_tx_hwtstamp(adapter);
663 else
664 /* reschedule to check later */
665 schedule_work(&adapter->ptp_tx_work);
666 }
667
igb_ptp_overflow_check(struct work_struct * work)668 static void igb_ptp_overflow_check(struct work_struct *work)
669 {
670 struct igb_adapter *igb =
671 container_of(work, struct igb_adapter, ptp_overflow_work.work);
672 struct timespec64 ts;
673
674 igb->ptp_caps.gettime64(&igb->ptp_caps, &ts);
675
676 pr_debug("igb overflow check at %lld.%09lu\n",
677 (long long) ts.tv_sec, ts.tv_nsec);
678
679 schedule_delayed_work(&igb->ptp_overflow_work,
680 IGB_SYSTIM_OVERFLOW_PERIOD);
681 }
682
683 /**
684 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
685 * @adapter: private network adapter structure
686 *
687 * This watchdog task is scheduled to detect error case where hardware has
688 * dropped an Rx packet that was timestamped when the ring is full. The
689 * particular error is rare but leaves the device in a state unable to timestamp
690 * any future packets.
691 **/
igb_ptp_rx_hang(struct igb_adapter * adapter)692 void igb_ptp_rx_hang(struct igb_adapter *adapter)
693 {
694 struct e1000_hw *hw = &adapter->hw;
695 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL);
696 unsigned long rx_event;
697
698 /* Other hardware uses per-packet timestamps */
699 if (hw->mac.type != e1000_82576)
700 return;
701
702 /* If we don't have a valid timestamp in the registers, just update the
703 * timeout counter and exit
704 */
705 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {
706 adapter->last_rx_ptp_check = jiffies;
707 return;
708 }
709
710 /* Determine the most recent watchdog or rx_timestamp event */
711 rx_event = adapter->last_rx_ptp_check;
712 if (time_after(adapter->last_rx_timestamp, rx_event))
713 rx_event = adapter->last_rx_timestamp;
714
715 /* Only need to read the high RXSTMP register to clear the lock */
716 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
717 rd32(E1000_RXSTMPH);
718 adapter->last_rx_ptp_check = jiffies;
719 adapter->rx_hwtstamp_cleared++;
720 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n");
721 }
722 }
723
724 /**
725 * igb_ptp_tx_hang - detect error case where Tx timestamp never finishes
726 * @adapter: private network adapter structure
727 */
igb_ptp_tx_hang(struct igb_adapter * adapter)728 void igb_ptp_tx_hang(struct igb_adapter *adapter)
729 {
730 struct e1000_hw *hw = &adapter->hw;
731 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
732 IGB_PTP_TX_TIMEOUT);
733
734 if (!adapter->ptp_tx_skb)
735 return;
736
737 if (!test_bit(__IGB_PTP_TX_IN_PROGRESS, &adapter->state))
738 return;
739
740 /* If we haven't received a timestamp within the timeout, it is
741 * reasonable to assume that it will never occur, so we can unlock the
742 * timestamp bit when this occurs.
743 */
744 if (timeout) {
745 cancel_work_sync(&adapter->ptp_tx_work);
746 dev_kfree_skb_any(adapter->ptp_tx_skb);
747 adapter->ptp_tx_skb = NULL;
748 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
749 adapter->tx_hwtstamp_timeouts++;
750 /* Clear the tx valid bit in TSYNCTXCTL register to enable
751 * interrupt
752 */
753 rd32(E1000_TXSTMPH);
754 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
755 }
756 }
757
758 /**
759 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
760 * @adapter: Board private structure.
761 *
762 * If we were asked to do hardware stamping and such a time stamp is
763 * available, then it must have been for this skb here because we only
764 * allow only one such packet into the queue.
765 **/
igb_ptp_tx_hwtstamp(struct igb_adapter * adapter)766 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
767 {
768 struct sk_buff *skb = adapter->ptp_tx_skb;
769 struct e1000_hw *hw = &adapter->hw;
770 struct skb_shared_hwtstamps shhwtstamps;
771 u64 regval;
772 int adjust = 0;
773
774 regval = rd32(E1000_TXSTMPL);
775 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
776
777 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
778 /* adjust timestamp for the TX latency based on link speed */
779 if (adapter->hw.mac.type == e1000_i210) {
780 switch (adapter->link_speed) {
781 case SPEED_10:
782 adjust = IGB_I210_TX_LATENCY_10;
783 break;
784 case SPEED_100:
785 adjust = IGB_I210_TX_LATENCY_100;
786 break;
787 case SPEED_1000:
788 adjust = IGB_I210_TX_LATENCY_1000;
789 break;
790 }
791 }
792
793 shhwtstamps.hwtstamp =
794 ktime_add_ns(shhwtstamps.hwtstamp, adjust);
795
796 /* Clear the lock early before calling skb_tstamp_tx so that
797 * applications are not woken up before the lock bit is clear. We use
798 * a copy of the skb pointer to ensure other threads can't change it
799 * while we're notifying the stack.
800 */
801 adapter->ptp_tx_skb = NULL;
802 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
803
804 /* Notify the stack and free the skb after we've unlocked */
805 skb_tstamp_tx(skb, &shhwtstamps);
806 dev_kfree_skb_any(skb);
807 }
808
809 /**
810 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
811 * @q_vector: Pointer to interrupt specific structure
812 * @va: Pointer to address containing Rx buffer
813 * @skb: Buffer containing timestamp and packet
814 *
815 * This function is meant to retrieve a timestamp from the first buffer of an
816 * incoming frame. The value is stored in little endian format starting on
817 * byte 8.
818 **/
igb_ptp_rx_pktstamp(struct igb_q_vector * q_vector,void * va,struct sk_buff * skb)819 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va,
820 struct sk_buff *skb)
821 {
822 __le64 *regval = (__le64 *)va;
823 struct igb_adapter *adapter = q_vector->adapter;
824 int adjust = 0;
825
826 /* The timestamp is recorded in little endian format.
827 * DWORD: 0 1 2 3
828 * Field: Reserved Reserved SYSTIML SYSTIMH
829 */
830 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb),
831 le64_to_cpu(regval[1]));
832
833 /* adjust timestamp for the RX latency based on link speed */
834 if (adapter->hw.mac.type == e1000_i210) {
835 switch (adapter->link_speed) {
836 case SPEED_10:
837 adjust = IGB_I210_RX_LATENCY_10;
838 break;
839 case SPEED_100:
840 adjust = IGB_I210_RX_LATENCY_100;
841 break;
842 case SPEED_1000:
843 adjust = IGB_I210_RX_LATENCY_1000;
844 break;
845 }
846 }
847 skb_hwtstamps(skb)->hwtstamp =
848 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust);
849 }
850
851 /**
852 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
853 * @q_vector: Pointer to interrupt specific structure
854 * @skb: Buffer containing timestamp and packet
855 *
856 * This function is meant to retrieve a timestamp from the internal registers
857 * of the adapter and store it in the skb.
858 **/
igb_ptp_rx_rgtstamp(struct igb_q_vector * q_vector,struct sk_buff * skb)859 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
860 struct sk_buff *skb)
861 {
862 struct igb_adapter *adapter = q_vector->adapter;
863 struct e1000_hw *hw = &adapter->hw;
864 u64 regval;
865 int adjust = 0;
866
867 /* If this bit is set, then the RX registers contain the time stamp. No
868 * other packet will be time stamped until we read these registers, so
869 * read the registers to make them available again. Because only one
870 * packet can be time stamped at a time, we know that the register
871 * values must belong to this one here and therefore we don't need to
872 * compare any of the additional attributes stored for it.
873 *
874 * If nothing went wrong, then it should have a shared tx_flags that we
875 * can turn into a skb_shared_hwtstamps.
876 */
877 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
878 return;
879
880 regval = rd32(E1000_RXSTMPL);
881 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
882
883 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
884
885 /* adjust timestamp for the RX latency based on link speed */
886 if (adapter->hw.mac.type == e1000_i210) {
887 switch (adapter->link_speed) {
888 case SPEED_10:
889 adjust = IGB_I210_RX_LATENCY_10;
890 break;
891 case SPEED_100:
892 adjust = IGB_I210_RX_LATENCY_100;
893 break;
894 case SPEED_1000:
895 adjust = IGB_I210_RX_LATENCY_1000;
896 break;
897 }
898 }
899 skb_hwtstamps(skb)->hwtstamp =
900 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust);
901
902 /* Update the last_rx_timestamp timer in order to enable watchdog check
903 * for error case of latched timestamp on a dropped packet.
904 */
905 adapter->last_rx_timestamp = jiffies;
906 }
907
908 /**
909 * igb_ptp_get_ts_config - get hardware time stamping config
910 * @netdev:
911 * @ifreq:
912 *
913 * Get the hwtstamp_config settings to return to the user. Rather than attempt
914 * to deconstruct the settings from the registers, just return a shadow copy
915 * of the last known settings.
916 **/
igb_ptp_get_ts_config(struct net_device * netdev,struct ifreq * ifr)917 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
918 {
919 struct igb_adapter *adapter = netdev_priv(netdev);
920 struct hwtstamp_config *config = &adapter->tstamp_config;
921
922 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
923 -EFAULT : 0;
924 }
925
926 /**
927 * igb_ptp_set_timestamp_mode - setup hardware for timestamping
928 * @adapter: networking device structure
929 * @config: hwtstamp configuration
930 *
931 * Outgoing time stamping can be enabled and disabled. Play nice and
932 * disable it when requested, although it shouldn't case any overhead
933 * when no packet needs it. At most one packet in the queue may be
934 * marked for time stamping, otherwise it would be impossible to tell
935 * for sure to which packet the hardware time stamp belongs.
936 *
937 * Incoming time stamping has to be configured via the hardware
938 * filters. Not all combinations are supported, in particular event
939 * type has to be specified. Matching the kind of event packet is
940 * not supported, with the exception of "all V2 events regardless of
941 * level 2 or 4".
942 */
igb_ptp_set_timestamp_mode(struct igb_adapter * adapter,struct hwtstamp_config * config)943 static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter,
944 struct hwtstamp_config *config)
945 {
946 struct e1000_hw *hw = &adapter->hw;
947 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
948 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
949 u32 tsync_rx_cfg = 0;
950 bool is_l4 = false;
951 bool is_l2 = false;
952 u32 regval;
953
954 /* reserved for future extensions */
955 if (config->flags)
956 return -EINVAL;
957
958 switch (config->tx_type) {
959 case HWTSTAMP_TX_OFF:
960 tsync_tx_ctl = 0;
961 case HWTSTAMP_TX_ON:
962 break;
963 default:
964 return -ERANGE;
965 }
966
967 switch (config->rx_filter) {
968 case HWTSTAMP_FILTER_NONE:
969 tsync_rx_ctl = 0;
970 break;
971 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
972 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
973 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
974 is_l4 = true;
975 break;
976 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
977 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
978 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
979 is_l4 = true;
980 break;
981 case HWTSTAMP_FILTER_PTP_V2_EVENT:
982 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
983 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
984 case HWTSTAMP_FILTER_PTP_V2_SYNC:
985 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
986 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
987 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
988 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
989 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
990 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
991 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
992 is_l2 = true;
993 is_l4 = true;
994 break;
995 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
996 case HWTSTAMP_FILTER_NTP_ALL:
997 case HWTSTAMP_FILTER_ALL:
998 /* 82576 cannot timestamp all packets, which it needs to do to
999 * support both V1 Sync and Delay_Req messages
1000 */
1001 if (hw->mac.type != e1000_82576) {
1002 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
1003 config->rx_filter = HWTSTAMP_FILTER_ALL;
1004 break;
1005 }
1006 /* fall through */
1007 default:
1008 config->rx_filter = HWTSTAMP_FILTER_NONE;
1009 return -ERANGE;
1010 }
1011
1012 if (hw->mac.type == e1000_82575) {
1013 if (tsync_rx_ctl | tsync_tx_ctl)
1014 return -EINVAL;
1015 return 0;
1016 }
1017
1018 /* Per-packet timestamping only works if all packets are
1019 * timestamped, so enable timestamping in all packets as
1020 * long as one Rx filter was configured.
1021 */
1022 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
1023 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
1024 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
1025 config->rx_filter = HWTSTAMP_FILTER_ALL;
1026 is_l2 = true;
1027 is_l4 = true;
1028
1029 if ((hw->mac.type == e1000_i210) ||
1030 (hw->mac.type == e1000_i211)) {
1031 regval = rd32(E1000_RXPBS);
1032 regval |= E1000_RXPBS_CFG_TS_EN;
1033 wr32(E1000_RXPBS, regval);
1034 }
1035 }
1036
1037 /* enable/disable TX */
1038 regval = rd32(E1000_TSYNCTXCTL);
1039 regval &= ~E1000_TSYNCTXCTL_ENABLED;
1040 regval |= tsync_tx_ctl;
1041 wr32(E1000_TSYNCTXCTL, regval);
1042
1043 /* enable/disable RX */
1044 regval = rd32(E1000_TSYNCRXCTL);
1045 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
1046 regval |= tsync_rx_ctl;
1047 wr32(E1000_TSYNCRXCTL, regval);
1048
1049 /* define which PTP packets are time stamped */
1050 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
1051
1052 /* define ethertype filter for timestamped packets */
1053 if (is_l2)
1054 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588),
1055 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
1056 E1000_ETQF_1588 | /* enable timestamping */
1057 ETH_P_1588)); /* 1588 eth protocol type */
1058 else
1059 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 0);
1060
1061 /* L4 Queue Filter[3]: filter by destination port and protocol */
1062 if (is_l4) {
1063 u32 ftqf = (IPPROTO_UDP /* UDP */
1064 | E1000_FTQF_VF_BP /* VF not compared */
1065 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
1066 | E1000_FTQF_MASK); /* mask all inputs */
1067 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
1068
1069 wr32(E1000_IMIR(3), htons(PTP_EV_PORT));
1070 wr32(E1000_IMIREXT(3),
1071 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
1072 if (hw->mac.type == e1000_82576) {
1073 /* enable source port check */
1074 wr32(E1000_SPQF(3), htons(PTP_EV_PORT));
1075 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
1076 }
1077 wr32(E1000_FTQF(3), ftqf);
1078 } else {
1079 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
1080 }
1081 wrfl();
1082
1083 /* clear TX/RX time stamp registers, just to be sure */
1084 regval = rd32(E1000_TXSTMPL);
1085 regval = rd32(E1000_TXSTMPH);
1086 regval = rd32(E1000_RXSTMPL);
1087 regval = rd32(E1000_RXSTMPH);
1088
1089 return 0;
1090 }
1091
1092 /**
1093 * igb_ptp_set_ts_config - set hardware time stamping config
1094 * @netdev:
1095 * @ifreq:
1096 *
1097 **/
igb_ptp_set_ts_config(struct net_device * netdev,struct ifreq * ifr)1098 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
1099 {
1100 struct igb_adapter *adapter = netdev_priv(netdev);
1101 struct hwtstamp_config config;
1102 int err;
1103
1104 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1105 return -EFAULT;
1106
1107 err = igb_ptp_set_timestamp_mode(adapter, &config);
1108 if (err)
1109 return err;
1110
1111 /* save these settings for future reference */
1112 memcpy(&adapter->tstamp_config, &config,
1113 sizeof(adapter->tstamp_config));
1114
1115 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1116 -EFAULT : 0;
1117 }
1118
1119 /**
1120 * igb_ptp_init - Initialize PTP functionality
1121 * @adapter: Board private structure
1122 *
1123 * This function is called at device probe to initialize the PTP
1124 * functionality.
1125 */
igb_ptp_init(struct igb_adapter * adapter)1126 void igb_ptp_init(struct igb_adapter *adapter)
1127 {
1128 struct e1000_hw *hw = &adapter->hw;
1129 struct net_device *netdev = adapter->netdev;
1130 int i;
1131
1132 switch (hw->mac.type) {
1133 case e1000_82576:
1134 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1135 adapter->ptp_caps.owner = THIS_MODULE;
1136 adapter->ptp_caps.max_adj = 999999881;
1137 adapter->ptp_caps.n_ext_ts = 0;
1138 adapter->ptp_caps.pps = 0;
1139 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576;
1140 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1141 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1142 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1143 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1144 adapter->cc.read = igb_ptp_read_82576;
1145 adapter->cc.mask = CYCLECOUNTER_MASK(64);
1146 adapter->cc.mult = 1;
1147 adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
1148 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1149 break;
1150 case e1000_82580:
1151 case e1000_i354:
1152 case e1000_i350:
1153 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1154 adapter->ptp_caps.owner = THIS_MODULE;
1155 adapter->ptp_caps.max_adj = 62499999;
1156 adapter->ptp_caps.n_ext_ts = 0;
1157 adapter->ptp_caps.pps = 0;
1158 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580;
1159 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1160 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1161 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1162 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1163 adapter->cc.read = igb_ptp_read_82580;
1164 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580);
1165 adapter->cc.mult = 1;
1166 adapter->cc.shift = 0;
1167 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1168 break;
1169 case e1000_i210:
1170 case e1000_i211:
1171 for (i = 0; i < IGB_N_SDP; i++) {
1172 struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
1173
1174 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
1175 ppd->index = i;
1176 ppd->func = PTP_PF_NONE;
1177 }
1178 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1179 adapter->ptp_caps.owner = THIS_MODULE;
1180 adapter->ptp_caps.max_adj = 62499999;
1181 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS;
1182 adapter->ptp_caps.n_per_out = IGB_N_PEROUT;
1183 adapter->ptp_caps.n_pins = IGB_N_SDP;
1184 adapter->ptp_caps.pps = 1;
1185 adapter->ptp_caps.pin_config = adapter->sdp_config;
1186 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580;
1187 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;
1188 adapter->ptp_caps.gettime64 = igb_ptp_gettime_i210;
1189 adapter->ptp_caps.settime64 = igb_ptp_settime_i210;
1190 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210;
1191 adapter->ptp_caps.verify = igb_ptp_verify_pin;
1192 break;
1193 default:
1194 adapter->ptp_clock = NULL;
1195 return;
1196 }
1197
1198 spin_lock_init(&adapter->tmreg_lock);
1199 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);
1200
1201 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1202 INIT_DELAYED_WORK(&adapter->ptp_overflow_work,
1203 igb_ptp_overflow_check);
1204
1205 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1206 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1207
1208 igb_ptp_reset(adapter);
1209
1210 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1211 &adapter->pdev->dev);
1212 if (IS_ERR(adapter->ptp_clock)) {
1213 adapter->ptp_clock = NULL;
1214 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
1215 } else if (adapter->ptp_clock) {
1216 dev_info(&adapter->pdev->dev, "added PHC on %s\n",
1217 adapter->netdev->name);
1218 adapter->ptp_flags |= IGB_PTP_ENABLED;
1219 }
1220 }
1221
1222 /**
1223 * igb_ptp_suspend - Disable PTP work items and prepare for suspend
1224 * @adapter: Board private structure
1225 *
1226 * This function stops the overflow check work and PTP Tx timestamp work, and
1227 * will prepare the device for OS suspend.
1228 */
igb_ptp_suspend(struct igb_adapter * adapter)1229 void igb_ptp_suspend(struct igb_adapter *adapter)
1230 {
1231 if (!(adapter->ptp_flags & IGB_PTP_ENABLED))
1232 return;
1233
1234 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1235 cancel_delayed_work_sync(&adapter->ptp_overflow_work);
1236
1237 cancel_work_sync(&adapter->ptp_tx_work);
1238 if (adapter->ptp_tx_skb) {
1239 dev_kfree_skb_any(adapter->ptp_tx_skb);
1240 adapter->ptp_tx_skb = NULL;
1241 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
1242 }
1243 }
1244
1245 /**
1246 * igb_ptp_stop - Disable PTP device and stop the overflow check.
1247 * @adapter: Board private structure.
1248 *
1249 * This function stops the PTP support and cancels the delayed work.
1250 **/
igb_ptp_stop(struct igb_adapter * adapter)1251 void igb_ptp_stop(struct igb_adapter *adapter)
1252 {
1253 igb_ptp_suspend(adapter);
1254
1255 if (adapter->ptp_clock) {
1256 ptp_clock_unregister(adapter->ptp_clock);
1257 dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
1258 adapter->netdev->name);
1259 adapter->ptp_flags &= ~IGB_PTP_ENABLED;
1260 }
1261 }
1262
1263 /**
1264 * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
1265 * @adapter: Board private structure.
1266 *
1267 * This function handles the reset work required to re-enable the PTP device.
1268 **/
igb_ptp_reset(struct igb_adapter * adapter)1269 void igb_ptp_reset(struct igb_adapter *adapter)
1270 {
1271 struct e1000_hw *hw = &adapter->hw;
1272 unsigned long flags;
1273
1274 /* reset the tstamp_config */
1275 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1276
1277 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1278
1279 switch (adapter->hw.mac.type) {
1280 case e1000_82576:
1281 /* Dial the nominal frequency. */
1282 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1283 break;
1284 case e1000_82580:
1285 case e1000_i354:
1286 case e1000_i350:
1287 case e1000_i210:
1288 case e1000_i211:
1289 wr32(E1000_TSAUXC, 0x0);
1290 wr32(E1000_TSSDP, 0x0);
1291 wr32(E1000_TSIM,
1292 TSYNC_INTERRUPTS |
1293 (adapter->pps_sys_wrap_on ? TSINTR_SYS_WRAP : 0));
1294 wr32(E1000_IMS, E1000_IMS_TS);
1295 break;
1296 default:
1297 /* No work to do. */
1298 goto out;
1299 }
1300
1301 /* Re-initialize the timer. */
1302 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1303 struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1304
1305 igb_ptp_write_i210(adapter, &ts);
1306 } else {
1307 timecounter_init(&adapter->tc, &adapter->cc,
1308 ktime_to_ns(ktime_get_real()));
1309 }
1310 out:
1311 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1312
1313 wrfl();
1314
1315 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1316 schedule_delayed_work(&adapter->ptp_overflow_work,
1317 IGB_SYSTIM_OVERFLOW_PERIOD);
1318 }
1319