1 /*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #ifndef _MLX4_EN_H_
35 #define _MLX4_EN_H_
36
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/netdevice.h>
42 #include <linux/if_vlan.h>
43 #include <linux/net_tstamp.h>
44 #ifdef CONFIG_MLX4_EN_DCB
45 #include <linux/dcbnl.h>
46 #endif
47 #include <linux/cpu_rmap.h>
48 #include <linux/ptp_clock_kernel.h>
49
50 #include <linux/mlx4/device.h>
51 #include <linux/mlx4/qp.h>
52 #include <linux/mlx4/cq.h>
53 #include <linux/mlx4/srq.h>
54 #include <linux/mlx4/doorbell.h>
55 #include <linux/mlx4/cmd.h>
56
57 #include "en_port.h"
58 #include "mlx4_stats.h"
59
60 #define DRV_NAME "mlx4_en"
61 #define DRV_VERSION "4.0-0"
62
63 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
64
65 /*
66 * Device constants
67 */
68
69
70 #define MLX4_EN_PAGE_SHIFT 12
71 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
72 #define DEF_RX_RINGS 16
73 #define MAX_RX_RINGS 128
74 #define MIN_RX_RINGS 4
75 #define LOG_TXBB_SIZE 6
76 #define TXBB_SIZE BIT(LOG_TXBB_SIZE)
77 #define HEADROOM (2048 / TXBB_SIZE + 1)
78 #define STAMP_STRIDE 64
79 #define STAMP_DWORDS (STAMP_STRIDE / 4)
80 #define STAMP_SHIFT 31
81 #define STAMP_VAL 0x7fffffff
82 #define STATS_DELAY (HZ / 4)
83 #define SERVICE_TASK_DELAY (HZ / 4)
84 #define MAX_NUM_OF_FS_RULES 256
85
86 #define MLX4_EN_FILTER_HASH_SHIFT 4
87 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
88
89 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
90 #define MAX_DESC_SIZE 512
91 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
92
93 /*
94 * OS related constants and tunables
95 */
96
97 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1
98 #define MLX4_EN_PRIV_FLAGS_PHV 2
99
100 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
101
102 /* Use the maximum between 16384 and a single page */
103 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
104
105 #define MLX4_EN_MAX_RX_FRAGS 4
106
107 /* Maximum ring sizes */
108 #define MLX4_EN_MAX_TX_SIZE 8192
109 #define MLX4_EN_MAX_RX_SIZE 8192
110
111 /* Minimum ring size for our page-allocation scheme to work */
112 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
113 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
114
115 #define MLX4_EN_SMALL_PKT_SIZE 64
116 #define MLX4_EN_MIN_TX_RING_P_UP 1
117 #define MLX4_EN_MAX_TX_RING_P_UP 32
118 #define MLX4_EN_NUM_UP_LOW 1
119 #define MLX4_EN_NUM_UP_HIGH 8
120 #define MLX4_EN_DEF_RX_RING_SIZE 1024
121 #define MLX4_EN_DEF_TX_RING_SIZE MLX4_EN_DEF_RX_RING_SIZE
122 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
123 MLX4_EN_NUM_UP_HIGH)
124
125 #define MLX4_EN_DEFAULT_TX_WORK 256
126
127 /* Target number of packets to coalesce with interrupt moderation */
128 #define MLX4_EN_RX_COAL_TARGET 44
129 #define MLX4_EN_RX_COAL_TIME 0x10
130
131 #define MLX4_EN_TX_COAL_PKTS 16
132 #define MLX4_EN_TX_COAL_TIME 0x10
133
134 #define MLX4_EN_MAX_COAL_PKTS U16_MAX
135 #define MLX4_EN_MAX_COAL_TIME U16_MAX
136
137 #define MLX4_EN_RX_RATE_LOW 400000
138 #define MLX4_EN_RX_COAL_TIME_LOW 0
139 #define MLX4_EN_RX_RATE_HIGH 450000
140 #define MLX4_EN_RX_COAL_TIME_HIGH 128
141 #define MLX4_EN_RX_SIZE_THRESH 1024
142 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
143 #define MLX4_EN_SAMPLE_INTERVAL 0
144 #define MLX4_EN_AVG_PKT_SMALL 256
145
146 #define MLX4_EN_AUTO_CONF 0xffff
147
148 #define MLX4_EN_DEF_RX_PAUSE 1
149 #define MLX4_EN_DEF_TX_PAUSE 1
150
151 /* Interval between successive polls in the Tx routine when polling is used
152 instead of interrupts (in per-core Tx rings) - should be power of 2 */
153 #define MLX4_EN_TX_POLL_MODER 16
154 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
155
156 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
157 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
158 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
159
160 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
161 * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
162 */
163 #define MLX4_EN_EFF_MTU(mtu) ((mtu) + ETH_HLEN + (2 * VLAN_HLEN))
164 #define ETH_BCAST 0xffffffffffffULL
165
166 #define MLX4_EN_LOOPBACK_RETRIES 5
167 #define MLX4_EN_LOOPBACK_TIMEOUT 100
168
169 #ifdef MLX4_EN_PERF_STAT
170 /* Number of samples to 'average' */
171 #define AVG_SIZE 128
172 #define AVG_FACTOR 1024
173
174 #define INC_PERF_COUNTER(cnt) (++(cnt))
175 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
176 #define AVG_PERF_COUNTER(cnt, sample) \
177 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
178 #define GET_PERF_COUNTER(cnt) (cnt)
179 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
180
181 #else
182
183 #define INC_PERF_COUNTER(cnt) do {} while (0)
184 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
185 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
186 #define GET_PERF_COUNTER(cnt) (0)
187 #define GET_AVG_PERF_COUNTER(cnt) (0)
188 #endif /* MLX4_EN_PERF_STAT */
189
190 /* Constants for TX flow */
191 enum {
192 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
193 MAX_BF = 256,
194 MIN_PKT_LEN = 17,
195 };
196
197 /*
198 * Configurables
199 */
200
201 enum cq_type {
202 /* keep tx types first */
203 TX,
204 TX_XDP,
205 #define MLX4_EN_NUM_TX_TYPES (TX_XDP + 1)
206 RX,
207 };
208
209
210 /*
211 * Useful macros
212 */
213 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
214 #define XNOR(x, y) (!(x) == !(y))
215
216
217 struct mlx4_en_tx_info {
218 union {
219 struct sk_buff *skb;
220 struct page *page;
221 };
222 dma_addr_t map0_dma;
223 u32 map0_byte_count;
224 u32 nr_txbb;
225 u32 nr_bytes;
226 u8 linear;
227 u8 data_offset;
228 u8 inl;
229 u8 ts_requested;
230 u8 nr_maps;
231 } ____cacheline_aligned_in_smp;
232
233
234 #define MLX4_EN_BIT_DESC_OWN 0x80000000
235 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
236 #define MLX4_EN_MEMTYPE_PAD 0x100
237 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
238
239
240 struct mlx4_en_tx_desc {
241 struct mlx4_wqe_ctrl_seg ctrl;
242 union {
243 struct mlx4_wqe_data_seg data; /* at least one data segment */
244 struct mlx4_wqe_lso_seg lso;
245 struct mlx4_wqe_inline_seg inl;
246 };
247 };
248
249 #define MLX4_EN_USE_SRQ 0x01000000
250
251 #define MLX4_EN_CX3_LOW_ID 0x1000
252 #define MLX4_EN_CX3_HIGH_ID 0x1005
253
254 struct mlx4_en_rx_alloc {
255 struct page *page;
256 dma_addr_t dma;
257 u32 page_offset;
258 };
259
260 #define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT)
261
262 struct mlx4_en_page_cache {
263 u32 index;
264 struct {
265 struct page *page;
266 dma_addr_t dma;
267 } buf[MLX4_EN_CACHE_SIZE];
268 };
269
270 struct mlx4_en_priv;
271
272 struct mlx4_en_tx_ring {
273 /* cache line used and dirtied in tx completion
274 * (mlx4_en_free_tx_buf())
275 */
276 u32 last_nr_txbb;
277 u32 cons;
278 unsigned long wake_queue;
279 struct netdev_queue *tx_queue;
280 u32 (*free_tx_desc)(struct mlx4_en_priv *priv,
281 struct mlx4_en_tx_ring *ring,
282 int index,
283 u64 timestamp, int napi_mode);
284 struct mlx4_en_rx_ring *recycle_ring;
285
286 /* cache line used and dirtied in mlx4_en_xmit() */
287 u32 prod ____cacheline_aligned_in_smp;
288 unsigned int tx_dropped;
289 unsigned long bytes;
290 unsigned long packets;
291 unsigned long tx_csum;
292 unsigned long tso_packets;
293 unsigned long xmit_more;
294 struct mlx4_bf bf;
295
296 /* Following part should be mostly read */
297 __be32 doorbell_qpn;
298 __be32 mr_key;
299 u32 size; /* number of TXBBs */
300 u32 size_mask;
301 u32 full_size;
302 u32 buf_size;
303 void *buf;
304 struct mlx4_en_tx_info *tx_info;
305 int qpn;
306 u8 queue_index;
307 bool bf_enabled;
308 bool bf_alloced;
309 u8 hwtstamp_tx_type;
310 u8 *bounce_buf;
311
312 /* Not used in fast path
313 * Only queue_stopped might be used if BQL is not properly working.
314 */
315 unsigned long queue_stopped;
316 struct mlx4_hwq_resources sp_wqres;
317 struct mlx4_qp sp_qp;
318 struct mlx4_qp_context sp_context;
319 cpumask_t sp_affinity_mask;
320 enum mlx4_qp_state sp_qp_state;
321 u16 sp_stride;
322 u16 sp_cqn; /* index of port CQ associated with this ring */
323 } ____cacheline_aligned_in_smp;
324
325 struct mlx4_en_rx_desc {
326 /* actual number of entries depends on rx ring stride */
327 struct mlx4_wqe_data_seg data[0];
328 };
329
330 struct mlx4_en_rx_ring {
331 struct mlx4_hwq_resources wqres;
332 u32 size ; /* number of Rx descs*/
333 u32 actual_size;
334 u32 size_mask;
335 u16 stride;
336 u16 log_stride;
337 u16 cqn; /* index of port CQ associated with this ring */
338 u32 prod;
339 u32 cons;
340 u32 buf_size;
341 u8 fcs_del;
342 void *buf;
343 void *rx_info;
344 struct bpf_prog __rcu *xdp_prog;
345 struct mlx4_en_page_cache page_cache;
346 unsigned long bytes;
347 unsigned long packets;
348 unsigned long csum_ok;
349 unsigned long csum_none;
350 unsigned long csum_complete;
351 unsigned long rx_alloc_pages;
352 unsigned long xdp_drop;
353 unsigned long xdp_tx;
354 unsigned long xdp_tx_full;
355 unsigned long dropped;
356 int hwtstamp_rx_filter;
357 cpumask_var_t affinity_mask;
358 };
359
360 struct mlx4_en_cq {
361 struct mlx4_cq mcq;
362 struct mlx4_hwq_resources wqres;
363 int ring;
364 struct net_device *dev;
365 union {
366 struct napi_struct napi;
367 bool xdp_busy;
368 };
369 int size;
370 int buf_size;
371 int vector;
372 enum cq_type type;
373 u16 moder_time;
374 u16 moder_cnt;
375 struct mlx4_cqe *buf;
376 #define MLX4_EN_OPCODE_ERROR 0x1e
377
378 struct irq_desc *irq_desc;
379 };
380
381 struct mlx4_en_port_profile {
382 u32 flags;
383 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
384 u32 rx_ring_num;
385 u32 tx_ring_size;
386 u32 rx_ring_size;
387 u8 num_tx_rings_p_up;
388 u8 rx_pause;
389 u8 rx_ppp;
390 u8 tx_pause;
391 u8 tx_ppp;
392 u8 num_up;
393 int rss_rings;
394 int inline_thold;
395 struct hwtstamp_config hwtstamp_config;
396 };
397
398 struct mlx4_en_profile {
399 int udp_rss;
400 u8 rss_mask;
401 u32 active_ports;
402 u32 small_pkt_int;
403 u8 no_reset;
404 u8 num_tx_rings_p_up;
405 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
406 };
407
408 struct mlx4_en_dev {
409 struct mlx4_dev *dev;
410 struct pci_dev *pdev;
411 struct mutex state_lock;
412 struct net_device *pndev[MLX4_MAX_PORTS + 1];
413 struct net_device *upper[MLX4_MAX_PORTS + 1];
414 u32 port_cnt;
415 bool device_up;
416 struct mlx4_en_profile profile;
417 u32 LSO_support;
418 struct workqueue_struct *workqueue;
419 struct device *dma_device;
420 void __iomem *uar_map;
421 struct mlx4_uar priv_uar;
422 struct mlx4_mr mr;
423 u32 priv_pdn;
424 spinlock_t uar_lock;
425 u8 mac_removed[MLX4_MAX_PORTS + 1];
426 u32 nominal_c_mult;
427 struct cyclecounter cycles;
428 seqlock_t clock_lock;
429 struct timecounter clock;
430 unsigned long last_overflow_check;
431 struct ptp_clock *ptp_clock;
432 struct ptp_clock_info ptp_clock_info;
433 struct notifier_block nb;
434 };
435
436
437 struct mlx4_en_rss_map {
438 int base_qpn;
439 struct mlx4_qp qps[MAX_RX_RINGS];
440 enum mlx4_qp_state state[MAX_RX_RINGS];
441 struct mlx4_qp *indir_qp;
442 enum mlx4_qp_state indir_state;
443 };
444
445 enum mlx4_en_port_flag {
446 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
447 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
448 };
449
450 struct mlx4_en_port_state {
451 int link_state;
452 int link_speed;
453 int transceiver;
454 u32 flags;
455 };
456
457 enum mlx4_en_mclist_act {
458 MCLIST_NONE,
459 MCLIST_REM,
460 MCLIST_ADD,
461 };
462
463 struct mlx4_en_mc_list {
464 struct list_head list;
465 enum mlx4_en_mclist_act action;
466 u8 addr[ETH_ALEN];
467 u64 reg_id;
468 u64 tunnel_reg_id;
469 };
470
471 struct mlx4_en_frag_info {
472 u16 frag_size;
473 u32 frag_stride;
474 };
475
476 #ifdef CONFIG_MLX4_EN_DCB
477 /* Minimal TC BW - setting to 0 will block traffic */
478 #define MLX4_EN_BW_MIN 1
479 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
480
481 #define MLX4_EN_TC_VENDOR 0
482 #define MLX4_EN_TC_ETS 7
483
484 enum dcb_pfc_type {
485 pfc_disabled = 0,
486 pfc_enabled_full,
487 pfc_enabled_tx,
488 pfc_enabled_rx
489 };
490
491 struct mlx4_en_cee_config {
492 bool pfc_state;
493 enum dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP_HIGH];
494 };
495 #endif
496
497 struct ethtool_flow_id {
498 struct list_head list;
499 struct ethtool_rx_flow_spec flow_spec;
500 u64 id;
501 };
502
503 enum {
504 MLX4_EN_FLAG_PROMISC = (1 << 0),
505 MLX4_EN_FLAG_MC_PROMISC = (1 << 1),
506 /* whether we need to enable hardware loopback by putting dmac
507 * in Tx WQE
508 */
509 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
510 /* whether we need to drop packets that hardware loopback-ed */
511 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3),
512 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4),
513 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5),
514 #ifdef CONFIG_MLX4_EN_DCB
515 MLX4_EN_FLAG_DCB_ENABLED = (1 << 6),
516 #endif
517 };
518
519 #define PORT_BEACON_MAX_LIMIT (65535)
520 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
521 #define MLX4_EN_MAC_HASH_IDX 5
522
523 struct mlx4_en_stats_bitmap {
524 DECLARE_BITMAP(bitmap, NUM_ALL_STATS);
525 struct mutex mutex; /* for mutual access to stats bitmap */
526 };
527
528 struct mlx4_en_priv {
529 struct mlx4_en_dev *mdev;
530 struct mlx4_en_port_profile *prof;
531 struct net_device *dev;
532 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
533 struct mlx4_en_port_state port_state;
534 spinlock_t stats_lock;
535 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
536 /* To allow rules removal while port is going down */
537 struct list_head ethtool_list;
538
539 unsigned long last_moder_packets[MAX_RX_RINGS];
540 unsigned long last_moder_tx_packets;
541 unsigned long last_moder_bytes[MAX_RX_RINGS];
542 unsigned long last_moder_jiffies;
543 int last_moder_time[MAX_RX_RINGS];
544 u16 rx_usecs;
545 u16 rx_frames;
546 u16 tx_usecs;
547 u16 tx_frames;
548 u32 pkt_rate_low;
549 u16 rx_usecs_low;
550 u32 pkt_rate_high;
551 u16 rx_usecs_high;
552 u32 sample_interval;
553 u32 adaptive_rx_coal;
554 u32 msg_enable;
555 u32 loopback_ok;
556 u32 validate_loopback;
557
558 struct mlx4_hwq_resources res;
559 int link_state;
560 int last_link_state;
561 bool port_up;
562 int port;
563 int registered;
564 int allocated;
565 int stride;
566 unsigned char current_mac[ETH_ALEN + 2];
567 int mac_index;
568 unsigned max_mtu;
569 int base_qpn;
570 int cqe_factor;
571 int cqe_size;
572
573 struct mlx4_en_rss_map rss_map;
574 __be32 ctrl_flags;
575 u32 flags;
576 u8 num_tx_rings_p_up;
577 u32 tx_work_limit;
578 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
579 u32 rx_ring_num;
580 u32 rx_skb_size;
581 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
582 u8 num_frags;
583 u8 log_rx_info;
584 u8 dma_dir;
585 u16 rx_headroom;
586
587 struct mlx4_en_tx_ring **tx_ring[MLX4_EN_NUM_TX_TYPES];
588 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
589 struct mlx4_en_cq **tx_cq[MLX4_EN_NUM_TX_TYPES];
590 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
591 struct mlx4_qp drop_qp;
592 struct work_struct rx_mode_task;
593 struct work_struct watchdog_task;
594 struct work_struct linkstate_task;
595 struct delayed_work stats_task;
596 struct delayed_work service_task;
597 struct work_struct vxlan_add_task;
598 struct work_struct vxlan_del_task;
599 struct mlx4_en_perf_stats pstats;
600 struct mlx4_en_pkt_stats pkstats;
601 struct mlx4_en_counter_stats pf_stats;
602 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
603 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
604 struct mlx4_en_flow_stats_rx rx_flowstats;
605 struct mlx4_en_flow_stats_tx tx_flowstats;
606 struct mlx4_en_port_stats port_stats;
607 struct mlx4_en_xdp_stats xdp_stats;
608 struct mlx4_en_stats_bitmap stats_bitmap;
609 struct list_head mc_list;
610 struct list_head curr_list;
611 u64 broadcast_id;
612 struct mlx4_en_stat_out_mbox hw_stats;
613 int vids[128];
614 bool wol;
615 struct device *ddev;
616 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
617 struct hwtstamp_config hwtstamp_config;
618 u32 counter_index;
619
620 #ifdef CONFIG_MLX4_EN_DCB
621 #define MLX4_EN_DCB_ENABLED 0x3
622 struct ieee_ets ets;
623 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
624 enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS];
625 struct mlx4_en_cee_config cee_config;
626 u8 dcbx_cap;
627 #endif
628 #ifdef CONFIG_RFS_ACCEL
629 spinlock_t filters_lock;
630 int last_filter_id;
631 struct list_head filters;
632 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
633 #endif
634 u64 tunnel_reg_id;
635 __be16 vxlan_port;
636
637 u32 pflags;
638 u8 rss_key[MLX4_EN_RSS_KEY_SIZE];
639 u8 rss_hash_fn;
640 };
641
642 enum mlx4_en_wol {
643 MLX4_EN_WOL_MAGIC = (1ULL << 61),
644 MLX4_EN_WOL_ENABLED = (1ULL << 62),
645 };
646
647 struct mlx4_mac_entry {
648 struct hlist_node hlist;
649 unsigned char mac[ETH_ALEN + 2];
650 u64 reg_id;
651 struct rcu_head rcu;
652 };
653
mlx4_en_get_cqe(void * buf,int idx,int cqe_sz)654 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz)
655 {
656 return buf + idx * cqe_sz;
657 }
658
659 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
660
661 void mlx4_en_init_ptys2ethtool_map(void);
662 void mlx4_en_update_loopback_state(struct net_device *dev,
663 netdev_features_t features);
664
665 void mlx4_en_destroy_netdev(struct net_device *dev);
666 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
667 struct mlx4_en_port_profile *prof);
668
669 int mlx4_en_start_port(struct net_device *dev);
670 void mlx4_en_stop_port(struct net_device *dev, int detach);
671
672 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
673 struct mlx4_en_stats_bitmap *stats_bitmap,
674 u8 rx_ppp, u8 rx_pause,
675 u8 tx_ppp, u8 tx_pause);
676
677 int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv,
678 struct mlx4_en_priv *tmp,
679 struct mlx4_en_port_profile *prof,
680 bool carry_xdp_prog);
681 void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv,
682 struct mlx4_en_priv *tmp);
683
684 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
685 int entries, int ring, enum cq_type mode, int node);
686 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
687 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
688 int cq_idx);
689 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
690 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
691 void mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
692
693 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
694 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
695 void *accel_priv, select_queue_fallback_t fallback);
696 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
697 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring,
698 struct mlx4_en_rx_alloc *frame,
699 struct net_device *dev, unsigned int length,
700 int tx_ind, bool *doorbell_pending);
701 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring);
702 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
703 struct mlx4_en_rx_alloc *frame);
704
705 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
706 struct mlx4_en_tx_ring **pring,
707 u32 size, u16 stride,
708 int node, int queue_index);
709 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
710 struct mlx4_en_tx_ring **pring);
711 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
712 struct mlx4_en_tx_ring *ring,
713 int cq, int user_prio);
714 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
715 struct mlx4_en_tx_ring *ring);
716 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
717 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv);
718 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
719 struct mlx4_en_rx_ring **pring,
720 u32 size, u16 stride, int node);
721 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
722 struct mlx4_en_rx_ring **pring,
723 u32 size, u16 stride);
724 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
725 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
726 struct mlx4_en_rx_ring *ring);
727 int mlx4_en_process_rx_cq(struct net_device *dev,
728 struct mlx4_en_cq *cq,
729 int budget);
730 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
731 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
732 bool mlx4_en_process_tx_cq(struct net_device *dev,
733 struct mlx4_en_cq *cq, int napi_budget);
734 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
735 struct mlx4_en_tx_ring *ring,
736 int index, u64 timestamp,
737 int napi_mode);
738 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
739 struct mlx4_en_tx_ring *ring,
740 int index, u64 timestamp,
741 int napi_mode);
742 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
743 int is_tx, int rss, int qpn, int cqn, int user_prio,
744 struct mlx4_qp_context *context);
745 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
746 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp,
747 int loopback);
748 void mlx4_en_calc_rx_buf(struct net_device *dev);
749 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
750 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
751 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
752 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
753 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
754 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
755
756 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
757 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
758
759 void mlx4_en_fold_software_stats(struct net_device *dev);
760 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
761 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
762
763 #ifdef CONFIG_MLX4_EN_DCB
764 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
765 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
766 #endif
767
768 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
769 int mlx4_en_alloc_tx_queue_per_tc(struct net_device *dev, u8 tc);
770
771 #ifdef CONFIG_RFS_ACCEL
772 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
773 #endif
774
775 #define MLX4_EN_NUM_SELF_TEST 5
776 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
777 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
778
779 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \
780 ((dev->features & feature) ^ (new_features & feature))
781
782 int mlx4_en_reset_config(struct net_device *dev,
783 struct hwtstamp_config ts_config,
784 netdev_features_t new_features);
785 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
786 struct mlx4_en_stats_bitmap *stats_bitmap,
787 u8 rx_ppp, u8 rx_pause,
788 u8 tx_ppp, u8 tx_pause);
789 int mlx4_en_netdev_event(struct notifier_block *this,
790 unsigned long event, void *ptr);
791
792 /*
793 * Functions for time stamping
794 */
795 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
796 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
797 struct skb_shared_hwtstamps *hwts,
798 u64 timestamp);
799 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
800 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
801
802 /* Globals
803 */
804 extern const struct ethtool_ops mlx4_en_ethtool_ops;
805
806
807
808 /*
809 * printk / logging functions
810 */
811
812 __printf(3, 4)
813 void en_print(const char *level, const struct mlx4_en_priv *priv,
814 const char *format, ...);
815
816 #define en_dbg(mlevel, priv, format, ...) \
817 do { \
818 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \
819 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \
820 } while (0)
821 #define en_warn(priv, format, ...) \
822 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)
823 #define en_err(priv, format, ...) \
824 en_print(KERN_ERR, priv, format, ##__VA_ARGS__)
825 #define en_info(priv, format, ...) \
826 en_print(KERN_INFO, priv, format, ##__VA_ARGS__)
827
828 #define mlx4_err(mdev, format, ...) \
829 pr_err(DRV_NAME " %s: " format, \
830 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
831 #define mlx4_info(mdev, format, ...) \
832 pr_info(DRV_NAME " %s: " format, \
833 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
834 #define mlx4_warn(mdev, format, ...) \
835 pr_warn(DRV_NAME " %s: " format, \
836 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
837
838 #endif
839