1 /*
2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef __MLX5_FPGA_CORE_H__
34 #define __MLX5_FPGA_CORE_H__
35
36 #ifdef CONFIG_MLX5_FPGA
37
38 #include "fpga/cmd.h"
39
40 /* Represents an Innova device */
41 struct mlx5_fpga_device {
42 struct mlx5_core_dev *mdev;
43 spinlock_t state_lock; /* Protects state transitions */
44 enum mlx5_fpga_status state;
45 enum mlx5_fpga_image last_admin_image;
46 enum mlx5_fpga_image last_oper_image;
47
48 /* QP Connection resources */
49 struct {
50 u32 pdn;
51 struct mlx5_core_mkey mkey;
52 struct mlx5_uars_page *uar;
53 } conn_res;
54
55 struct mlx5_fpga_ipsec *ipsec;
56 };
57
58 #define mlx5_fpga_dbg(__adev, format, ...) \
59 dev_dbg(&(__adev)->mdev->pdev->dev, "FPGA: %s:%d:(pid %d): " format, \
60 __func__, __LINE__, current->pid, ##__VA_ARGS__)
61
62 #define mlx5_fpga_err(__adev, format, ...) \
63 dev_err(&(__adev)->mdev->pdev->dev, "FPGA: %s:%d:(pid %d): " format, \
64 __func__, __LINE__, current->pid, ##__VA_ARGS__)
65
66 #define mlx5_fpga_warn(__adev, format, ...) \
67 dev_warn(&(__adev)->mdev->pdev->dev, "FPGA: %s:%d:(pid %d): " format, \
68 __func__, __LINE__, current->pid, ##__VA_ARGS__)
69
70 #define mlx5_fpga_warn_ratelimited(__adev, format, ...) \
71 dev_warn_ratelimited(&(__adev)->mdev->pdev->dev, "FPGA: %s:%d: " \
72 format, __func__, __LINE__, ##__VA_ARGS__)
73
74 #define mlx5_fpga_notice(__adev, format, ...) \
75 dev_notice(&(__adev)->mdev->pdev->dev, "FPGA: " format, ##__VA_ARGS__)
76
77 #define mlx5_fpga_info(__adev, format, ...) \
78 dev_info(&(__adev)->mdev->pdev->dev, "FPGA: " format, ##__VA_ARGS__)
79
80 int mlx5_fpga_init(struct mlx5_core_dev *mdev);
81 void mlx5_fpga_cleanup(struct mlx5_core_dev *mdev);
82 int mlx5_fpga_device_start(struct mlx5_core_dev *mdev);
83 void mlx5_fpga_device_stop(struct mlx5_core_dev *mdev);
84 void mlx5_fpga_event(struct mlx5_core_dev *mdev, u8 event, void *data);
85
86 #else
87
mlx5_fpga_init(struct mlx5_core_dev * mdev)88 static inline int mlx5_fpga_init(struct mlx5_core_dev *mdev)
89 {
90 return 0;
91 }
92
mlx5_fpga_cleanup(struct mlx5_core_dev * mdev)93 static inline void mlx5_fpga_cleanup(struct mlx5_core_dev *mdev)
94 {
95 }
96
mlx5_fpga_device_start(struct mlx5_core_dev * mdev)97 static inline int mlx5_fpga_device_start(struct mlx5_core_dev *mdev)
98 {
99 return 0;
100 }
101
mlx5_fpga_device_stop(struct mlx5_core_dev * mdev)102 static inline void mlx5_fpga_device_stop(struct mlx5_core_dev *mdev)
103 {
104 }
105
mlx5_fpga_event(struct mlx5_core_dev * mdev,u8 event,void * data)106 static inline void mlx5_fpga_event(struct mlx5_core_dev *mdev, u8 event,
107 void *data)
108 {
109 }
110
111 #endif
112
113 #endif /* __MLX5_FPGA_CORE_H__ */
114