1 /*
2 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
3 *
4 * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/clk.h>
18 #include <linux/io.h>
19 #include <linux/iopoll.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/module.h>
22 #include <linux/of_device.h>
23 #include <linux/of_mdio.h>
24 #include <linux/of_net.h>
25 #include <linux/phy.h>
26 #include <linux/platform_device.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/regmap.h>
29 #include <linux/stmmac.h>
30
31 #include "stmmac.h"
32 #include "stmmac_platform.h"
33
34 /* General notes on dwmac-sun8i:
35 * Locking: no locking is necessary in this file because all necessary locking
36 * is done in the "stmmac files"
37 */
38
39 /* struct emac_variant - Descrive dwmac-sun8i hardware variant
40 * @default_syscon_value: The default value of the EMAC register in syscon
41 * This value is used for disabling properly EMAC
42 * and used as a good starting value in case of the
43 * boot process(uboot) leave some stuff.
44 * @internal_phy: Does the MAC embed an internal PHY
45 * @support_mii: Does the MAC handle MII
46 * @support_rmii: Does the MAC handle RMII
47 * @support_rgmii: Does the MAC handle RGMII
48 */
49 struct emac_variant {
50 u32 default_syscon_value;
51 int internal_phy;
52 bool support_mii;
53 bool support_rmii;
54 bool support_rgmii;
55 };
56
57 /* struct sunxi_priv_data - hold all sunxi private data
58 * @tx_clk: reference to MAC TX clock
59 * @ephy_clk: reference to the optional EPHY clock for the internal PHY
60 * @regulator: reference to the optional regulator
61 * @rst_ephy: reference to the optional EPHY reset for the internal PHY
62 * @variant: reference to the current board variant
63 * @regmap: regmap for using the syscon
64 * @use_internal_phy: Does the current PHY choice imply using the internal PHY
65 */
66 struct sunxi_priv_data {
67 struct clk *tx_clk;
68 struct clk *ephy_clk;
69 struct regulator *regulator;
70 struct reset_control *rst_ephy;
71 const struct emac_variant *variant;
72 struct regmap *regmap;
73 bool use_internal_phy;
74 };
75
76 static const struct emac_variant emac_variant_h3 = {
77 .default_syscon_value = 0x58000,
78 .internal_phy = PHY_INTERFACE_MODE_MII,
79 .support_mii = true,
80 .support_rmii = true,
81 .support_rgmii = true
82 };
83
84 static const struct emac_variant emac_variant_v3s = {
85 .default_syscon_value = 0x38000,
86 .internal_phy = PHY_INTERFACE_MODE_MII,
87 .support_mii = true
88 };
89
90 static const struct emac_variant emac_variant_a83t = {
91 .default_syscon_value = 0,
92 .internal_phy = 0,
93 .support_mii = true,
94 .support_rgmii = true
95 };
96
97 static const struct emac_variant emac_variant_a64 = {
98 .default_syscon_value = 0,
99 .internal_phy = 0,
100 .support_mii = true,
101 .support_rmii = true,
102 .support_rgmii = true
103 };
104
105 #define EMAC_BASIC_CTL0 0x00
106 #define EMAC_BASIC_CTL1 0x04
107 #define EMAC_INT_STA 0x08
108 #define EMAC_INT_EN 0x0C
109 #define EMAC_TX_CTL0 0x10
110 #define EMAC_TX_CTL1 0x14
111 #define EMAC_TX_FLOW_CTL 0x1C
112 #define EMAC_TX_DESC_LIST 0x20
113 #define EMAC_RX_CTL0 0x24
114 #define EMAC_RX_CTL1 0x28
115 #define EMAC_RX_DESC_LIST 0x34
116 #define EMAC_RX_FRM_FLT 0x38
117 #define EMAC_MDIO_CMD 0x48
118 #define EMAC_MDIO_DATA 0x4C
119 #define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8)
120 #define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8)
121 #define EMAC_TX_DMA_STA 0xB0
122 #define EMAC_TX_CUR_DESC 0xB4
123 #define EMAC_TX_CUR_BUF 0xB8
124 #define EMAC_RX_DMA_STA 0xC0
125 #define EMAC_RX_CUR_DESC 0xC4
126 #define EMAC_RX_CUR_BUF 0xC8
127
128 /* Use in EMAC_BASIC_CTL0 */
129 #define EMAC_DUPLEX_FULL BIT(0)
130 #define EMAC_LOOPBACK BIT(1)
131 #define EMAC_SPEED_1000 0
132 #define EMAC_SPEED_100 (0x03 << 2)
133 #define EMAC_SPEED_10 (0x02 << 2)
134
135 /* Use in EMAC_BASIC_CTL1 */
136 #define EMAC_BURSTLEN_SHIFT 24
137
138 /* Used in EMAC_RX_FRM_FLT */
139 #define EMAC_FRM_FLT_RXALL BIT(0)
140 #define EMAC_FRM_FLT_CTL BIT(13)
141 #define EMAC_FRM_FLT_MULTICAST BIT(16)
142
143 /* Used in RX_CTL1*/
144 #define EMAC_RX_MD BIT(1)
145 #define EMAC_RX_TH_MASK GENMASK(4, 5)
146 #define EMAC_RX_TH_32 0
147 #define EMAC_RX_TH_64 (0x1 << 4)
148 #define EMAC_RX_TH_96 (0x2 << 4)
149 #define EMAC_RX_TH_128 (0x3 << 4)
150 #define EMAC_RX_DMA_EN BIT(30)
151 #define EMAC_RX_DMA_START BIT(31)
152
153 /* Used in TX_CTL1*/
154 #define EMAC_TX_MD BIT(1)
155 #define EMAC_TX_NEXT_FRM BIT(2)
156 #define EMAC_TX_TH_MASK GENMASK(8, 10)
157 #define EMAC_TX_TH_64 0
158 #define EMAC_TX_TH_128 (0x1 << 8)
159 #define EMAC_TX_TH_192 (0x2 << 8)
160 #define EMAC_TX_TH_256 (0x3 << 8)
161 #define EMAC_TX_DMA_EN BIT(30)
162 #define EMAC_TX_DMA_START BIT(31)
163
164 /* Used in RX_CTL0 */
165 #define EMAC_RX_RECEIVER_EN BIT(31)
166 #define EMAC_RX_DO_CRC BIT(27)
167 #define EMAC_RX_FLOW_CTL_EN BIT(16)
168
169 /* Used in TX_CTL0 */
170 #define EMAC_TX_TRANSMITTER_EN BIT(31)
171
172 /* Used in EMAC_TX_FLOW_CTL */
173 #define EMAC_TX_FLOW_CTL_EN BIT(0)
174
175 /* Used in EMAC_INT_STA */
176 #define EMAC_TX_INT BIT(0)
177 #define EMAC_TX_DMA_STOP_INT BIT(1)
178 #define EMAC_TX_BUF_UA_INT BIT(2)
179 #define EMAC_TX_TIMEOUT_INT BIT(3)
180 #define EMAC_TX_UNDERFLOW_INT BIT(4)
181 #define EMAC_TX_EARLY_INT BIT(5)
182 #define EMAC_RX_INT BIT(8)
183 #define EMAC_RX_BUF_UA_INT BIT(9)
184 #define EMAC_RX_DMA_STOP_INT BIT(10)
185 #define EMAC_RX_TIMEOUT_INT BIT(11)
186 #define EMAC_RX_OVERFLOW_INT BIT(12)
187 #define EMAC_RX_EARLY_INT BIT(13)
188 #define EMAC_RGMII_STA_INT BIT(16)
189
190 #define MAC_ADDR_TYPE_DST BIT(31)
191
192 /* H3 specific bits for EPHY */
193 #define H3_EPHY_ADDR_SHIFT 20
194 #define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */
195 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
196 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
197 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
198
199 /* H3/A64 specific bits */
200 #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */
201
202 /* Generic system control EMAC_CLK bits */
203 #define SYSCON_ETXDC_MASK GENMASK(2, 0)
204 #define SYSCON_ETXDC_SHIFT 10
205 #define SYSCON_ERXDC_MASK GENMASK(4, 0)
206 #define SYSCON_ERXDC_SHIFT 5
207 /* EMAC PHY Interface Type */
208 #define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */
209 #define SYSCON_ETCS_MASK GENMASK(1, 0)
210 #define SYSCON_ETCS_MII 0x0
211 #define SYSCON_ETCS_EXT_GMII 0x1
212 #define SYSCON_ETCS_INT_GMII 0x2
213 #define SYSCON_EMAC_REG 0x30
214
215 /* sun8i_dwmac_dma_reset() - reset the EMAC
216 * Called from stmmac via stmmac_dma_ops->reset
217 */
sun8i_dwmac_dma_reset(void __iomem * ioaddr)218 static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
219 {
220 writel(0, ioaddr + EMAC_RX_CTL1);
221 writel(0, ioaddr + EMAC_TX_CTL1);
222 writel(0, ioaddr + EMAC_RX_FRM_FLT);
223 writel(0, ioaddr + EMAC_RX_DESC_LIST);
224 writel(0, ioaddr + EMAC_TX_DESC_LIST);
225 writel(0, ioaddr + EMAC_INT_EN);
226 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
227 return 0;
228 }
229
230 /* sun8i_dwmac_dma_init() - initialize the EMAC
231 * Called from stmmac via stmmac_dma_ops->init
232 */
sun8i_dwmac_dma_init(void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,u32 dma_tx,u32 dma_rx,int atds)233 static void sun8i_dwmac_dma_init(void __iomem *ioaddr,
234 struct stmmac_dma_cfg *dma_cfg,
235 u32 dma_tx, u32 dma_rx, int atds)
236 {
237 /* Write TX and RX descriptors address */
238 writel(dma_rx, ioaddr + EMAC_RX_DESC_LIST);
239 writel(dma_tx, ioaddr + EMAC_TX_DESC_LIST);
240
241 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
242 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
243 }
244
245 /* sun8i_dwmac_dump_regs() - Dump EMAC address space
246 * Called from stmmac_dma_ops->dump_regs
247 * Used for ethtool
248 */
sun8i_dwmac_dump_regs(void __iomem * ioaddr,u32 * reg_space)249 static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space)
250 {
251 int i;
252
253 for (i = 0; i < 0xC8; i += 4) {
254 if (i == 0x32 || i == 0x3C)
255 continue;
256 reg_space[i / 4] = readl(ioaddr + i);
257 }
258 }
259
260 /* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space
261 * Called from stmmac_ops->dump_regs
262 * Used for ethtool
263 */
sun8i_dwmac_dump_mac_regs(struct mac_device_info * hw,u32 * reg_space)264 static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw,
265 u32 *reg_space)
266 {
267 int i;
268 void __iomem *ioaddr = hw->pcsr;
269
270 for (i = 0; i < 0xC8; i += 4) {
271 if (i == 0x32 || i == 0x3C)
272 continue;
273 reg_space[i / 4] = readl(ioaddr + i);
274 }
275 }
276
sun8i_dwmac_enable_dma_irq(void __iomem * ioaddr,u32 chan)277 static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan)
278 {
279 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
280 }
281
sun8i_dwmac_disable_dma_irq(void __iomem * ioaddr,u32 chan)282 static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan)
283 {
284 writel(0, ioaddr + EMAC_INT_EN);
285 }
286
sun8i_dwmac_dma_start_tx(void __iomem * ioaddr,u32 chan)287 static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan)
288 {
289 u32 v;
290
291 v = readl(ioaddr + EMAC_TX_CTL1);
292 v |= EMAC_TX_DMA_START;
293 v |= EMAC_TX_DMA_EN;
294 writel(v, ioaddr + EMAC_TX_CTL1);
295 }
296
sun8i_dwmac_enable_dma_transmission(void __iomem * ioaddr)297 static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)
298 {
299 u32 v;
300
301 v = readl(ioaddr + EMAC_TX_CTL1);
302 v |= EMAC_TX_DMA_START;
303 v |= EMAC_TX_DMA_EN;
304 writel(v, ioaddr + EMAC_TX_CTL1);
305 }
306
sun8i_dwmac_dma_stop_tx(void __iomem * ioaddr,u32 chan)307 static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan)
308 {
309 u32 v;
310
311 v = readl(ioaddr + EMAC_TX_CTL1);
312 v &= ~EMAC_TX_DMA_EN;
313 writel(v, ioaddr + EMAC_TX_CTL1);
314 }
315
sun8i_dwmac_dma_start_rx(void __iomem * ioaddr,u32 chan)316 static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan)
317 {
318 u32 v;
319
320 v = readl(ioaddr + EMAC_RX_CTL1);
321 v |= EMAC_RX_DMA_START;
322 v |= EMAC_RX_DMA_EN;
323 writel(v, ioaddr + EMAC_RX_CTL1);
324 }
325
sun8i_dwmac_dma_stop_rx(void __iomem * ioaddr,u32 chan)326 static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan)
327 {
328 u32 v;
329
330 v = readl(ioaddr + EMAC_RX_CTL1);
331 v &= ~EMAC_RX_DMA_EN;
332 writel(v, ioaddr + EMAC_RX_CTL1);
333 }
334
sun8i_dwmac_dma_interrupt(void __iomem * ioaddr,struct stmmac_extra_stats * x,u32 chan)335 static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr,
336 struct stmmac_extra_stats *x, u32 chan)
337 {
338 u32 v;
339 int ret = 0;
340
341 v = readl(ioaddr + EMAC_INT_STA);
342
343 if (v & EMAC_TX_INT) {
344 ret |= handle_tx;
345 x->tx_normal_irq_n++;
346 }
347
348 if (v & EMAC_TX_DMA_STOP_INT)
349 x->tx_process_stopped_irq++;
350
351 if (v & EMAC_TX_BUF_UA_INT)
352 x->tx_process_stopped_irq++;
353
354 if (v & EMAC_TX_TIMEOUT_INT)
355 ret |= tx_hard_error;
356
357 if (v & EMAC_TX_UNDERFLOW_INT) {
358 ret |= tx_hard_error;
359 x->tx_undeflow_irq++;
360 }
361
362 if (v & EMAC_TX_EARLY_INT)
363 x->tx_early_irq++;
364
365 if (v & EMAC_RX_INT) {
366 ret |= handle_rx;
367 x->rx_normal_irq_n++;
368 }
369
370 if (v & EMAC_RX_BUF_UA_INT)
371 x->rx_buf_unav_irq++;
372
373 if (v & EMAC_RX_DMA_STOP_INT)
374 x->rx_process_stopped_irq++;
375
376 if (v & EMAC_RX_TIMEOUT_INT)
377 ret |= tx_hard_error;
378
379 if (v & EMAC_RX_OVERFLOW_INT) {
380 ret |= tx_hard_error;
381 x->rx_overflow_irq++;
382 }
383
384 if (v & EMAC_RX_EARLY_INT)
385 x->rx_early_irq++;
386
387 if (v & EMAC_RGMII_STA_INT)
388 x->irq_rgmii_n++;
389
390 writel(v, ioaddr + EMAC_INT_STA);
391
392 return ret;
393 }
394
sun8i_dwmac_dma_operation_mode(void __iomem * ioaddr,int txmode,int rxmode,int rxfifosz)395 static void sun8i_dwmac_dma_operation_mode(void __iomem *ioaddr, int txmode,
396 int rxmode, int rxfifosz)
397 {
398 u32 v;
399
400 v = readl(ioaddr + EMAC_TX_CTL1);
401 if (txmode == SF_DMA_MODE) {
402 v |= EMAC_TX_MD;
403 /* Undocumented bit (called TX_NEXT_FRM in BSP), the original
404 * comment is
405 * "Operating on second frame increase the performance
406 * especially when transmit store-and-forward is used."
407 */
408 v |= EMAC_TX_NEXT_FRM;
409 } else {
410 v &= ~EMAC_TX_MD;
411 v &= ~EMAC_TX_TH_MASK;
412 if (txmode < 64)
413 v |= EMAC_TX_TH_64;
414 else if (txmode < 128)
415 v |= EMAC_TX_TH_128;
416 else if (txmode < 192)
417 v |= EMAC_TX_TH_192;
418 else if (txmode < 256)
419 v |= EMAC_TX_TH_256;
420 }
421 writel(v, ioaddr + EMAC_TX_CTL1);
422
423 v = readl(ioaddr + EMAC_RX_CTL1);
424 if (rxmode == SF_DMA_MODE) {
425 v |= EMAC_RX_MD;
426 } else {
427 v &= ~EMAC_RX_MD;
428 v &= ~EMAC_RX_TH_MASK;
429 if (rxmode < 32)
430 v |= EMAC_RX_TH_32;
431 else if (rxmode < 64)
432 v |= EMAC_RX_TH_64;
433 else if (rxmode < 96)
434 v |= EMAC_RX_TH_96;
435 else if (rxmode < 128)
436 v |= EMAC_RX_TH_128;
437 }
438 writel(v, ioaddr + EMAC_RX_CTL1);
439 }
440
441 static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = {
442 .reset = sun8i_dwmac_dma_reset,
443 .init = sun8i_dwmac_dma_init,
444 .dump_regs = sun8i_dwmac_dump_regs,
445 .dma_mode = sun8i_dwmac_dma_operation_mode,
446 .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission,
447 .enable_dma_irq = sun8i_dwmac_enable_dma_irq,
448 .disable_dma_irq = sun8i_dwmac_disable_dma_irq,
449 .start_tx = sun8i_dwmac_dma_start_tx,
450 .stop_tx = sun8i_dwmac_dma_stop_tx,
451 .start_rx = sun8i_dwmac_dma_start_rx,
452 .stop_rx = sun8i_dwmac_dma_stop_rx,
453 .dma_interrupt = sun8i_dwmac_dma_interrupt,
454 };
455
sun8i_dwmac_init(struct platform_device * pdev,void * priv)456 static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
457 {
458 struct sunxi_priv_data *gmac = priv;
459 int ret;
460
461 if (gmac->regulator) {
462 ret = regulator_enable(gmac->regulator);
463 if (ret) {
464 dev_err(&pdev->dev, "Fail to enable regulator\n");
465 return ret;
466 }
467 }
468
469 ret = clk_prepare_enable(gmac->tx_clk);
470 if (ret) {
471 if (gmac->regulator)
472 regulator_disable(gmac->regulator);
473 dev_err(&pdev->dev, "Could not enable AHB clock\n");
474 return ret;
475 }
476
477 return 0;
478 }
479
sun8i_dwmac_core_init(struct mac_device_info * hw,struct net_device * dev)480 static void sun8i_dwmac_core_init(struct mac_device_info *hw,
481 struct net_device *dev)
482 {
483 void __iomem *ioaddr = hw->pcsr;
484 u32 v;
485
486 v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */
487 writel(v, ioaddr + EMAC_BASIC_CTL1);
488 }
489
sun8i_dwmac_set_mac(void __iomem * ioaddr,bool enable)490 static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable)
491 {
492 u32 t, r;
493
494 t = readl(ioaddr + EMAC_TX_CTL0);
495 r = readl(ioaddr + EMAC_RX_CTL0);
496 if (enable) {
497 t |= EMAC_TX_TRANSMITTER_EN;
498 r |= EMAC_RX_RECEIVER_EN;
499 } else {
500 t &= ~EMAC_TX_TRANSMITTER_EN;
501 r &= ~EMAC_RX_RECEIVER_EN;
502 }
503 writel(t, ioaddr + EMAC_TX_CTL0);
504 writel(r, ioaddr + EMAC_RX_CTL0);
505 }
506
507 /* Set MAC address at slot reg_n
508 * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST
509 * If addr is NULL, clear the slot
510 */
sun8i_dwmac_set_umac_addr(struct mac_device_info * hw,unsigned char * addr,unsigned int reg_n)511 static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
512 unsigned char *addr,
513 unsigned int reg_n)
514 {
515 void __iomem *ioaddr = hw->pcsr;
516 u32 v;
517
518 if (!addr) {
519 writel(0, ioaddr + EMAC_MACADDR_HI(reg_n));
520 return;
521 }
522
523 stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
524 EMAC_MACADDR_LO(reg_n));
525 if (reg_n > 0) {
526 v = readl(ioaddr + EMAC_MACADDR_HI(reg_n));
527 v |= MAC_ADDR_TYPE_DST;
528 writel(v, ioaddr + EMAC_MACADDR_HI(reg_n));
529 }
530 }
531
sun8i_dwmac_get_umac_addr(struct mac_device_info * hw,unsigned char * addr,unsigned int reg_n)532 static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw,
533 unsigned char *addr,
534 unsigned int reg_n)
535 {
536 void __iomem *ioaddr = hw->pcsr;
537
538 stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
539 EMAC_MACADDR_LO(reg_n));
540 }
541
542 /* caution this function must return non 0 to work */
sun8i_dwmac_rx_ipc_enable(struct mac_device_info * hw)543 static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)
544 {
545 void __iomem *ioaddr = hw->pcsr;
546 u32 v;
547
548 v = readl(ioaddr + EMAC_RX_CTL0);
549 v |= EMAC_RX_DO_CRC;
550 writel(v, ioaddr + EMAC_RX_CTL0);
551
552 return 1;
553 }
554
sun8i_dwmac_set_filter(struct mac_device_info * hw,struct net_device * dev)555 static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
556 struct net_device *dev)
557 {
558 void __iomem *ioaddr = hw->pcsr;
559 u32 v;
560 int i = 1;
561 struct netdev_hw_addr *ha;
562 int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1;
563
564 v = EMAC_FRM_FLT_CTL;
565
566 if (dev->flags & IFF_PROMISC) {
567 v = EMAC_FRM_FLT_RXALL;
568 } else if (dev->flags & IFF_ALLMULTI) {
569 v |= EMAC_FRM_FLT_MULTICAST;
570 } else if (macaddrs <= hw->unicast_filter_entries) {
571 if (!netdev_mc_empty(dev)) {
572 netdev_for_each_mc_addr(ha, dev) {
573 sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
574 i++;
575 }
576 }
577 if (!netdev_uc_empty(dev)) {
578 netdev_for_each_uc_addr(ha, dev) {
579 sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
580 i++;
581 }
582 }
583 } else {
584 netdev_info(dev, "Too many address, switching to promiscuous\n");
585 v = EMAC_FRM_FLT_RXALL;
586 }
587
588 /* Disable unused address filter slots */
589 while (i < hw->unicast_filter_entries)
590 sun8i_dwmac_set_umac_addr(hw, NULL, i++);
591
592 writel(v, ioaddr + EMAC_RX_FRM_FLT);
593 }
594
sun8i_dwmac_flow_ctrl(struct mac_device_info * hw,unsigned int duplex,unsigned int fc,unsigned int pause_time,u32 tx_cnt)595 static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw,
596 unsigned int duplex, unsigned int fc,
597 unsigned int pause_time, u32 tx_cnt)
598 {
599 void __iomem *ioaddr = hw->pcsr;
600 u32 v;
601
602 v = readl(ioaddr + EMAC_RX_CTL0);
603 if (fc == FLOW_AUTO)
604 v |= EMAC_RX_FLOW_CTL_EN;
605 else
606 v &= ~EMAC_RX_FLOW_CTL_EN;
607 writel(v, ioaddr + EMAC_RX_CTL0);
608
609 v = readl(ioaddr + EMAC_TX_FLOW_CTL);
610 if (fc == FLOW_AUTO)
611 v |= EMAC_TX_FLOW_CTL_EN;
612 else
613 v &= ~EMAC_TX_FLOW_CTL_EN;
614 writel(v, ioaddr + EMAC_TX_FLOW_CTL);
615 }
616
sun8i_dwmac_reset(struct stmmac_priv * priv)617 static int sun8i_dwmac_reset(struct stmmac_priv *priv)
618 {
619 u32 v;
620 int err;
621
622 v = readl(priv->ioaddr + EMAC_BASIC_CTL1);
623 writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1);
624
625 /* The timeout was previoulsy set to 10ms, but some board (OrangePI0)
626 * need more if no cable plugged. 100ms seems OK
627 */
628 err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v,
629 !(v & 0x01), 100, 100000);
630
631 if (err) {
632 dev_err(priv->device, "EMAC reset timeout\n");
633 return -EFAULT;
634 }
635 return 0;
636 }
637
sun8i_dwmac_set_syscon(struct stmmac_priv * priv)638 static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
639 {
640 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
641 struct device_node *node = priv->device->of_node;
642 int ret;
643 u32 reg, val;
644
645 regmap_read(gmac->regmap, SYSCON_EMAC_REG, &val);
646 reg = gmac->variant->default_syscon_value;
647 if (reg != val)
648 dev_warn(priv->device,
649 "Current syscon value is not the default %x (expect %x)\n",
650 val, reg);
651
652 if (gmac->variant->internal_phy) {
653 if (!gmac->use_internal_phy) {
654 /* switch to external PHY interface */
655 reg &= ~H3_EPHY_SELECT;
656 } else {
657 reg |= H3_EPHY_SELECT;
658 reg &= ~H3_EPHY_SHUTDOWN;
659 dev_dbg(priv->device, "Select internal_phy %x\n", reg);
660
661 if (of_property_read_bool(priv->plat->phy_node,
662 "allwinner,leds-active-low"))
663 reg |= H3_EPHY_LED_POL;
664 else
665 reg &= ~H3_EPHY_LED_POL;
666
667 /* Force EPHY xtal frequency to 24MHz. */
668 reg |= H3_EPHY_CLK_SEL;
669
670 ret = of_mdio_parse_addr(priv->device,
671 priv->plat->phy_node);
672 if (ret < 0) {
673 dev_err(priv->device, "Could not parse MDIO addr\n");
674 return ret;
675 }
676 /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
677 * address. No need to mask it again.
678 */
679 reg |= ret << H3_EPHY_ADDR_SHIFT;
680 }
681 }
682
683 if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) {
684 if (val % 100) {
685 dev_err(priv->device, "tx-delay must be a multiple of 100\n");
686 return -EINVAL;
687 }
688 val /= 100;
689 dev_dbg(priv->device, "set tx-delay to %x\n", val);
690 if (val <= SYSCON_ETXDC_MASK) {
691 reg &= ~(SYSCON_ETXDC_MASK << SYSCON_ETXDC_SHIFT);
692 reg |= (val << SYSCON_ETXDC_SHIFT);
693 } else {
694 dev_err(priv->device, "Invalid TX clock delay: %d\n",
695 val);
696 return -EINVAL;
697 }
698 }
699
700 if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) {
701 if (val % 100) {
702 dev_err(priv->device, "rx-delay must be a multiple of 100\n");
703 return -EINVAL;
704 }
705 val /= 100;
706 dev_dbg(priv->device, "set rx-delay to %x\n", val);
707 if (val <= SYSCON_ERXDC_MASK) {
708 reg &= ~(SYSCON_ERXDC_MASK << SYSCON_ERXDC_SHIFT);
709 reg |= (val << SYSCON_ERXDC_SHIFT);
710 } else {
711 dev_err(priv->device, "Invalid RX clock delay: %d\n",
712 val);
713 return -EINVAL;
714 }
715 }
716
717 /* Clear interface mode bits */
718 reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT);
719 if (gmac->variant->support_rmii)
720 reg &= ~SYSCON_RMII_EN;
721
722 switch (priv->plat->interface) {
723 case PHY_INTERFACE_MODE_MII:
724 /* default */
725 break;
726 case PHY_INTERFACE_MODE_RGMII:
727 case PHY_INTERFACE_MODE_RGMII_ID:
728 case PHY_INTERFACE_MODE_RGMII_RXID:
729 case PHY_INTERFACE_MODE_RGMII_TXID:
730 reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII;
731 break;
732 case PHY_INTERFACE_MODE_RMII:
733 reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII;
734 break;
735 default:
736 dev_err(priv->device, "Unsupported interface mode: %s",
737 phy_modes(priv->plat->interface));
738 return -EINVAL;
739 }
740
741 regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg);
742
743 return 0;
744 }
745
sun8i_dwmac_unset_syscon(struct sunxi_priv_data * gmac)746 static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac)
747 {
748 u32 reg = gmac->variant->default_syscon_value;
749
750 regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg);
751 }
752
sun8i_dwmac_power_internal_phy(struct stmmac_priv * priv)753 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)
754 {
755 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
756 int ret;
757
758 if (!gmac->use_internal_phy)
759 return 0;
760
761 ret = clk_prepare_enable(gmac->ephy_clk);
762 if (ret) {
763 dev_err(priv->device, "Cannot enable ephy\n");
764 return ret;
765 }
766
767 /* Make sure the EPHY is properly reseted, as U-Boot may leave
768 * it at deasserted state, and thus it may fail to reset EMAC.
769 */
770 reset_control_assert(gmac->rst_ephy);
771
772 ret = reset_control_deassert(gmac->rst_ephy);
773 if (ret) {
774 dev_err(priv->device, "Cannot deassert ephy\n");
775 clk_disable_unprepare(gmac->ephy_clk);
776 return ret;
777 }
778
779 return 0;
780 }
781
sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data * gmac)782 static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)
783 {
784 if (!gmac->use_internal_phy)
785 return 0;
786
787 clk_disable_unprepare(gmac->ephy_clk);
788 reset_control_assert(gmac->rst_ephy);
789 return 0;
790 }
791
792 /* sun8i_power_phy() - Activate the PHY:
793 * In case of error, no need to call sun8i_unpower_phy(),
794 * it will be called anyway by sun8i_dwmac_exit()
795 */
sun8i_power_phy(struct stmmac_priv * priv)796 static int sun8i_power_phy(struct stmmac_priv *priv)
797 {
798 int ret;
799
800 ret = sun8i_dwmac_power_internal_phy(priv);
801 if (ret)
802 return ret;
803
804 ret = sun8i_dwmac_set_syscon(priv);
805 if (ret)
806 return ret;
807
808 /* After changing syscon value, the MAC need reset or it will use
809 * the last value (and so the last PHY set.
810 */
811 ret = sun8i_dwmac_reset(priv);
812 if (ret)
813 return ret;
814 return 0;
815 }
816
sun8i_unpower_phy(struct sunxi_priv_data * gmac)817 static void sun8i_unpower_phy(struct sunxi_priv_data *gmac)
818 {
819 sun8i_dwmac_unset_syscon(gmac);
820 sun8i_dwmac_unpower_internal_phy(gmac);
821 }
822
sun8i_dwmac_exit(struct platform_device * pdev,void * priv)823 static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
824 {
825 struct sunxi_priv_data *gmac = priv;
826
827 sun8i_unpower_phy(gmac);
828
829 clk_disable_unprepare(gmac->tx_clk);
830
831 if (gmac->regulator)
832 regulator_disable(gmac->regulator);
833 }
834
835 static const struct stmmac_ops sun8i_dwmac_ops = {
836 .core_init = sun8i_dwmac_core_init,
837 .set_mac = sun8i_dwmac_set_mac,
838 .dump_regs = sun8i_dwmac_dump_mac_regs,
839 .rx_ipc = sun8i_dwmac_rx_ipc_enable,
840 .set_filter = sun8i_dwmac_set_filter,
841 .flow_ctrl = sun8i_dwmac_flow_ctrl,
842 .set_umac_addr = sun8i_dwmac_set_umac_addr,
843 .get_umac_addr = sun8i_dwmac_get_umac_addr,
844 };
845
sun8i_dwmac_setup(void * ppriv)846 static struct mac_device_info *sun8i_dwmac_setup(void *ppriv)
847 {
848 struct mac_device_info *mac;
849 struct stmmac_priv *priv = ppriv;
850 int ret;
851
852 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL);
853 if (!mac)
854 return NULL;
855
856 ret = sun8i_power_phy(priv);
857 if (ret)
858 return NULL;
859
860 mac->pcsr = priv->ioaddr;
861 mac->mac = &sun8i_dwmac_ops;
862 mac->dma = &sun8i_dwmac_dma_ops;
863
864 priv->dev->priv_flags |= IFF_UNICAST_FLT;
865
866 /* The loopback bit seems to be re-set when link change
867 * Simply mask it each time
868 * Speed 10/100/1000 are set in BIT(2)/BIT(3)
869 */
870 mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK;
871 mac->link.speed10 = EMAC_SPEED_10;
872 mac->link.speed100 = EMAC_SPEED_100;
873 mac->link.speed1000 = EMAC_SPEED_1000;
874 mac->link.duplex = EMAC_DUPLEX_FULL;
875 mac->mii.addr = EMAC_MDIO_CMD;
876 mac->mii.data = EMAC_MDIO_DATA;
877 mac->mii.reg_shift = 4;
878 mac->mii.reg_mask = GENMASK(8, 4);
879 mac->mii.addr_shift = 12;
880 mac->mii.addr_mask = GENMASK(16, 12);
881 mac->mii.clk_csr_shift = 20;
882 mac->mii.clk_csr_mask = GENMASK(22, 20);
883 mac->unicast_filter_entries = 8;
884
885 /* Synopsys Id is not available */
886 priv->synopsys_id = 0;
887
888 return mac;
889 }
890
sun8i_dwmac_probe(struct platform_device * pdev)891 static int sun8i_dwmac_probe(struct platform_device *pdev)
892 {
893 struct plat_stmmacenet_data *plat_dat;
894 struct stmmac_resources stmmac_res;
895 struct sunxi_priv_data *gmac;
896 struct device *dev = &pdev->dev;
897 int ret;
898
899 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
900 if (ret)
901 return ret;
902
903 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
904 if (IS_ERR(plat_dat))
905 return PTR_ERR(plat_dat);
906
907 gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
908 if (!gmac)
909 return -ENOMEM;
910
911 gmac->variant = of_device_get_match_data(&pdev->dev);
912 if (!gmac->variant) {
913 dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n");
914 return -EINVAL;
915 }
916
917 gmac->tx_clk = devm_clk_get(dev, "stmmaceth");
918 if (IS_ERR(gmac->tx_clk)) {
919 dev_err(dev, "Could not get TX clock\n");
920 return PTR_ERR(gmac->tx_clk);
921 }
922
923 /* Optional regulator for PHY */
924 gmac->regulator = devm_regulator_get_optional(dev, "phy");
925 if (IS_ERR(gmac->regulator)) {
926 if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER)
927 return -EPROBE_DEFER;
928 dev_info(dev, "No regulator found\n");
929 gmac->regulator = NULL;
930 }
931
932 gmac->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
933 "syscon");
934 if (IS_ERR(gmac->regmap)) {
935 ret = PTR_ERR(gmac->regmap);
936 dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret);
937 return ret;
938 }
939
940 plat_dat->interface = of_get_phy_mode(dev->of_node);
941 if (plat_dat->interface == gmac->variant->internal_phy) {
942 dev_info(&pdev->dev, "Will use internal PHY\n");
943 gmac->use_internal_phy = true;
944 gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0);
945 if (IS_ERR(gmac->ephy_clk)) {
946 ret = PTR_ERR(gmac->ephy_clk);
947 dev_err(&pdev->dev, "Cannot get EPHY clock: %d\n", ret);
948 return -EINVAL;
949 }
950
951 gmac->rst_ephy = of_reset_control_get(plat_dat->phy_node, NULL);
952 if (IS_ERR(gmac->rst_ephy)) {
953 ret = PTR_ERR(gmac->rst_ephy);
954 if (ret == -EPROBE_DEFER)
955 return ret;
956 dev_err(&pdev->dev, "No EPHY reset control found %d\n",
957 ret);
958 return -EINVAL;
959 }
960 } else {
961 dev_info(&pdev->dev, "Will use external PHY\n");
962 gmac->use_internal_phy = false;
963 }
964
965 /* platform data specifying hardware features and callbacks.
966 * hardware features were copied from Allwinner drivers.
967 */
968 plat_dat->rx_coe = STMMAC_RX_COE_TYPE2;
969 plat_dat->tx_coe = 1;
970 plat_dat->has_sun8i = true;
971 plat_dat->bsp_priv = gmac;
972 plat_dat->init = sun8i_dwmac_init;
973 plat_dat->exit = sun8i_dwmac_exit;
974 plat_dat->setup = sun8i_dwmac_setup;
975
976 ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv);
977 if (ret)
978 return ret;
979
980 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
981 if (ret)
982 sun8i_dwmac_exit(pdev, plat_dat->bsp_priv);
983
984 return ret;
985 }
986
987 static const struct of_device_id sun8i_dwmac_match[] = {
988 { }
989 };
990 MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
991
992 static struct platform_driver sun8i_dwmac_driver = {
993 .probe = sun8i_dwmac_probe,
994 .remove = stmmac_pltfr_remove,
995 .driver = {
996 .name = "dwmac-sun8i",
997 .pm = &stmmac_pltfr_pm_ops,
998 .of_match_table = sun8i_dwmac_match,
999 },
1000 };
1001 module_platform_driver(sun8i_dwmac_driver);
1002
1003 MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>");
1004 MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer");
1005 MODULE_LICENSE("GPL");
1006