1 /*
2 * Copyright 2016 Broadcom
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License, version 2, as
6 * published by the Free Software Foundation (the "GPL").
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License version 2 (GPLv2) for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * version 2 (GPLv2) along with this source code.
15 */
16
17 #include <linux/platform_device.h>
18 #include <linux/device.h>
19 #include <linux/of_mdio.h>
20 #include <linux/module.h>
21 #include <linux/phy.h>
22 #include <linux/mdio-mux.h>
23 #include <linux/delay.h>
24
25 #define MDIO_PARAM_OFFSET 0x23c
26 #define MDIO_PARAM_MIIM_CYCLE 29
27 #define MDIO_PARAM_INTERNAL_SEL 25
28 #define MDIO_PARAM_BUS_ID 22
29 #define MDIO_PARAM_C45_SEL 21
30 #define MDIO_PARAM_PHY_ID 16
31 #define MDIO_PARAM_PHY_DATA 0
32
33 #define MDIO_READ_OFFSET 0x240
34 #define MDIO_READ_DATA_MASK 0xffff
35 #define MDIO_ADDR_OFFSET 0x244
36
37 #define MDIO_CTRL_OFFSET 0x248
38 #define MDIO_CTRL_WRITE_OP 0x1
39 #define MDIO_CTRL_READ_OP 0x2
40
41 #define MDIO_STAT_OFFSET 0x24c
42 #define MDIO_STAT_DONE 1
43
44 #define BUS_MAX_ADDR 32
45 #define EXT_BUS_START_ADDR 16
46
47 #define MDIO_REG_ADDR_SPACE_SIZE 0x250
48
49 struct iproc_mdiomux_desc {
50 void *mux_handle;
51 void __iomem *base;
52 struct device *dev;
53 struct mii_bus *mii_bus;
54 };
55
iproc_mdio_wait_for_idle(void __iomem * base,bool result)56 static int iproc_mdio_wait_for_idle(void __iomem *base, bool result)
57 {
58 unsigned int timeout = 1000; /* loop for 1s */
59 u32 val;
60
61 do {
62 val = readl(base + MDIO_STAT_OFFSET);
63 if ((val & MDIO_STAT_DONE) == result)
64 return 0;
65
66 usleep_range(1000, 2000);
67 } while (timeout--);
68
69 return -ETIMEDOUT;
70 }
71
72 /* start_miim_ops- Program and start MDIO transaction over mdio bus.
73 * @base: Base address
74 * @phyid: phyid of the selected bus.
75 * @reg: register offset to be read/written.
76 * @val :0 if read op else value to be written in @reg;
77 * @op: Operation that need to be carried out.
78 * MDIO_CTRL_READ_OP: Read transaction.
79 * MDIO_CTRL_WRITE_OP: Write transaction.
80 *
81 * Return value: Successful Read operation returns read reg values and write
82 * operation returns 0. Failure operation returns negative error code.
83 */
start_miim_ops(void __iomem * base,u16 phyid,u32 reg,u16 val,u32 op)84 static int start_miim_ops(void __iomem *base,
85 u16 phyid, u32 reg, u16 val, u32 op)
86 {
87 u32 param;
88 int ret;
89
90 writel(0, base + MDIO_CTRL_OFFSET);
91 ret = iproc_mdio_wait_for_idle(base, 0);
92 if (ret)
93 goto err;
94
95 param = readl(base + MDIO_PARAM_OFFSET);
96 param |= phyid << MDIO_PARAM_PHY_ID;
97 param |= val << MDIO_PARAM_PHY_DATA;
98 if (reg & MII_ADDR_C45)
99 param |= BIT(MDIO_PARAM_C45_SEL);
100
101 writel(param, base + MDIO_PARAM_OFFSET);
102
103 writel(reg, base + MDIO_ADDR_OFFSET);
104
105 writel(op, base + MDIO_CTRL_OFFSET);
106
107 ret = iproc_mdio_wait_for_idle(base, 1);
108 if (ret)
109 goto err;
110
111 if (op == MDIO_CTRL_READ_OP)
112 ret = readl(base + MDIO_READ_OFFSET) & MDIO_READ_DATA_MASK;
113 err:
114 return ret;
115 }
116
iproc_mdiomux_read(struct mii_bus * bus,int phyid,int reg)117 static int iproc_mdiomux_read(struct mii_bus *bus, int phyid, int reg)
118 {
119 struct iproc_mdiomux_desc *md = bus->priv;
120 int ret;
121
122 ret = start_miim_ops(md->base, phyid, reg, 0, MDIO_CTRL_READ_OP);
123 if (ret < 0)
124 dev_err(&bus->dev, "mdiomux read operation failed!!!");
125
126 return ret;
127 }
128
iproc_mdiomux_write(struct mii_bus * bus,int phyid,int reg,u16 val)129 static int iproc_mdiomux_write(struct mii_bus *bus,
130 int phyid, int reg, u16 val)
131 {
132 struct iproc_mdiomux_desc *md = bus->priv;
133 int ret;
134
135 /* Write val at reg offset */
136 ret = start_miim_ops(md->base, phyid, reg, val, MDIO_CTRL_WRITE_OP);
137 if (ret < 0)
138 dev_err(&bus->dev, "mdiomux write operation failed!!!");
139
140 return ret;
141 }
142
mdio_mux_iproc_switch_fn(int current_child,int desired_child,void * data)143 static int mdio_mux_iproc_switch_fn(int current_child, int desired_child,
144 void *data)
145 {
146 struct iproc_mdiomux_desc *md = data;
147 u32 param, bus_id;
148 bool bus_dir;
149
150 /* select bus and its properties */
151 bus_dir = (desired_child < EXT_BUS_START_ADDR);
152 bus_id = bus_dir ? desired_child : (desired_child - EXT_BUS_START_ADDR);
153
154 param = (bus_dir ? 1 : 0) << MDIO_PARAM_INTERNAL_SEL;
155 param |= (bus_id << MDIO_PARAM_BUS_ID);
156
157 writel(param, md->base + MDIO_PARAM_OFFSET);
158 return 0;
159 }
160
mdio_mux_iproc_probe(struct platform_device * pdev)161 static int mdio_mux_iproc_probe(struct platform_device *pdev)
162 {
163 struct iproc_mdiomux_desc *md;
164 struct mii_bus *bus;
165 struct resource *res;
166 int rc;
167
168 md = devm_kzalloc(&pdev->dev, sizeof(*md), GFP_KERNEL);
169 if (!md)
170 return -ENOMEM;
171 md->dev = &pdev->dev;
172
173 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
174 if (res->start & 0xfff) {
175 /* For backward compatibility in case the
176 * base address is specified with an offset.
177 */
178 dev_info(&pdev->dev, "fix base address in dt-blob\n");
179 res->start &= ~0xfff;
180 res->end = res->start + MDIO_REG_ADDR_SPACE_SIZE - 1;
181 }
182 md->base = devm_ioremap_resource(&pdev->dev, res);
183 if (IS_ERR(md->base)) {
184 dev_err(&pdev->dev, "failed to ioremap register\n");
185 return PTR_ERR(md->base);
186 }
187
188 md->mii_bus = mdiobus_alloc();
189 if (!md->mii_bus) {
190 dev_err(&pdev->dev, "mdiomux bus alloc failed\n");
191 return -ENOMEM;
192 }
193
194 bus = md->mii_bus;
195 bus->priv = md;
196 bus->name = "iProc MDIO mux bus";
197 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", pdev->name, pdev->id);
198 bus->parent = &pdev->dev;
199 bus->read = iproc_mdiomux_read;
200 bus->write = iproc_mdiomux_write;
201
202 bus->phy_mask = ~0;
203 bus->dev.of_node = pdev->dev.of_node;
204 rc = mdiobus_register(bus);
205 if (rc) {
206 dev_err(&pdev->dev, "mdiomux registration failed\n");
207 goto out;
208 }
209
210 platform_set_drvdata(pdev, md);
211
212 rc = mdio_mux_init(md->dev, md->dev->of_node, mdio_mux_iproc_switch_fn,
213 &md->mux_handle, md, md->mii_bus);
214 if (rc) {
215 dev_info(md->dev, "mdiomux initialization failed\n");
216 goto out_register;
217 }
218
219 dev_info(md->dev, "iProc mdiomux registered\n");
220 return 0;
221
222 out_register:
223 mdiobus_unregister(bus);
224 out:
225 mdiobus_free(bus);
226 return rc;
227 }
228
mdio_mux_iproc_remove(struct platform_device * pdev)229 static int mdio_mux_iproc_remove(struct platform_device *pdev)
230 {
231 struct iproc_mdiomux_desc *md = platform_get_drvdata(pdev);
232
233 mdio_mux_uninit(md->mux_handle);
234 mdiobus_unregister(md->mii_bus);
235 mdiobus_free(md->mii_bus);
236
237 return 0;
238 }
239
240 static const struct of_device_id mdio_mux_iproc_match[] = {
241 {
242 .compatible = "brcm,mdio-mux-iproc",
243 },
244 {},
245 };
246 MODULE_DEVICE_TABLE(of, mdio_mux_iproc_match);
247
248 static struct platform_driver mdiomux_iproc_driver = {
249 .driver = {
250 .name = "mdio-mux-iproc",
251 .of_match_table = mdio_mux_iproc_match,
252 },
253 .probe = mdio_mux_iproc_probe,
254 .remove = mdio_mux_iproc_remove,
255 };
256
257 module_platform_driver(mdiomux_iproc_driver);
258
259 MODULE_DESCRIPTION("iProc MDIO Mux Bus Driver");
260 MODULE_AUTHOR("Pramod Kumar <pramod.kumar@broadcom.com>");
261 MODULE_LICENSE("GPL v2");
262