1 /*
2 * Amlogic Meson GXL Internal PHY Driver
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 * Copyright (C) 2016 BayLibre, SAS. All rights reserved.
6 * Author: Neil Armstrong <narmstrong@baylibre.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 */
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/mii.h>
22 #include <linux/ethtool.h>
23 #include <linux/phy.h>
24 #include <linux/netdevice.h>
25
meson_gxl_config_init(struct phy_device * phydev)26 static int meson_gxl_config_init(struct phy_device *phydev)
27 {
28 int ret;
29
30 /* Enable Analog and DSP register Bank access by */
31 ret = phy_write(phydev, 0x14, 0x0000);
32 if (ret)
33 return ret;
34 ret = phy_write(phydev, 0x14, 0x0400);
35 if (ret)
36 return ret;
37 ret = phy_write(phydev, 0x14, 0x0000);
38 if (ret)
39 return ret;
40 ret = phy_write(phydev, 0x14, 0x0400);
41 if (ret)
42 return ret;
43
44 /* Write Analog register 23 */
45 ret = phy_write(phydev, 0x17, 0x8E0D);
46 if (ret)
47 return ret;
48 ret = phy_write(phydev, 0x14, 0x4417);
49 if (ret)
50 return ret;
51
52 /* Enable fractional PLL */
53 ret = phy_write(phydev, 0x17, 0x0005);
54 if (ret)
55 return ret;
56 ret = phy_write(phydev, 0x14, 0x5C1B);
57 if (ret)
58 return ret;
59
60 /* Program fraction FR_PLL_DIV1 */
61 ret = phy_write(phydev, 0x17, 0x029A);
62 if (ret)
63 return ret;
64 ret = phy_write(phydev, 0x14, 0x5C1D);
65 if (ret)
66 return ret;
67
68 /* Program fraction FR_PLL_DIV1 */
69 ret = phy_write(phydev, 0x17, 0xAAAA);
70 if (ret)
71 return ret;
72 ret = phy_write(phydev, 0x14, 0x5C1C);
73 if (ret)
74 return ret;
75
76 return 0;
77 }
78
79 static struct phy_driver meson_gxl_phy[] = {
80 {
81 .phy_id = 0x01814400,
82 .phy_id_mask = 0xfffffff0,
83 .name = "Meson GXL Internal PHY",
84 .features = PHY_BASIC_FEATURES,
85 .flags = PHY_IS_INTERNAL,
86 .config_init = meson_gxl_config_init,
87 .config_aneg = genphy_config_aneg,
88 .aneg_done = genphy_aneg_done,
89 .read_status = genphy_read_status,
90 .suspend = genphy_suspend,
91 .resume = genphy_resume,
92 },
93 };
94
95 static struct mdio_device_id __maybe_unused meson_gxl_tbl[] = {
96 { 0x01814400, 0xfffffff0 },
97 { }
98 };
99
100 module_phy_driver(meson_gxl_phy);
101
102 MODULE_DEVICE_TABLE(mdio, meson_gxl_tbl);
103
104 MODULE_DESCRIPTION("Amlogic Meson GXL Internal PHY driver");
105 MODULE_AUTHOR("Baoqi wang");
106 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
107 MODULE_LICENSE("GPL");
108