1 /*
2 * drivers/net/phy/micrel.c
3 *
4 * Driver for Micrel PHYs
5 *
6 * Author: David J. Choi
7 *
8 * Copyright (c) 2010-2013 Micrel, Inc.
9 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * Support : Micrel Phys:
17 * Giga phys: ksz9021, ksz9031
18 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
19 * ksz8021, ksz8031, ksz8051,
20 * ksz8081, ksz8091,
21 * ksz8061,
22 * Switch : ksz8873, ksz886x
23 * ksz9477
24 */
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/phy.h>
29 #include <linux/micrel_phy.h>
30 #include <linux/of.h>
31 #include <linux/clk.h>
32
33 /* Operation Mode Strap Override */
34 #define MII_KSZPHY_OMSO 0x16
35 #define KSZPHY_OMSO_B_CAST_OFF BIT(9)
36 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
37 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
38 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
39
40 /* general Interrupt control/status reg in vendor specific block. */
41 #define MII_KSZPHY_INTCS 0x1B
42 #define KSZPHY_INTCS_JABBER BIT(15)
43 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
44 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
45 #define KSZPHY_INTCS_PARELLEL BIT(12)
46 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
47 #define KSZPHY_INTCS_LINK_DOWN BIT(10)
48 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
49 #define KSZPHY_INTCS_LINK_UP BIT(8)
50 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
51 KSZPHY_INTCS_LINK_DOWN)
52
53 /* PHY Control 1 */
54 #define MII_KSZPHY_CTRL_1 0x1e
55
56 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
57 #define MII_KSZPHY_CTRL_2 0x1f
58 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
59 /* bitmap of PHY register to set interrupt mode */
60 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
61 #define KSZPHY_RMII_REF_CLK_SEL BIT(7)
62
63 /* Write/read to/from extended registers */
64 #define MII_KSZPHY_EXTREG 0x0b
65 #define KSZPHY_EXTREG_WRITE 0x8000
66
67 #define MII_KSZPHY_EXTREG_WRITE 0x0c
68 #define MII_KSZPHY_EXTREG_READ 0x0d
69
70 /* Extended registers */
71 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
72 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
73 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
74
75 #define PS_TO_REG 200
76
77 struct kszphy_hw_stat {
78 const char *string;
79 u8 reg;
80 u8 bits;
81 };
82
83 static struct kszphy_hw_stat kszphy_hw_stats[] = {
84 { "phy_receive_errors", 21, 16},
85 { "phy_idle_errors", 10, 8 },
86 };
87
88 struct kszphy_type {
89 u32 led_mode_reg;
90 u16 interrupt_level_mask;
91 bool has_broadcast_disable;
92 bool has_nand_tree_disable;
93 bool has_rmii_ref_clk_sel;
94 };
95
96 struct kszphy_priv {
97 const struct kszphy_type *type;
98 int led_mode;
99 bool rmii_ref_clk_sel;
100 bool rmii_ref_clk_sel_val;
101 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
102 };
103
104 static const struct kszphy_type ksz8021_type = {
105 .led_mode_reg = MII_KSZPHY_CTRL_2,
106 .has_broadcast_disable = true,
107 .has_nand_tree_disable = true,
108 .has_rmii_ref_clk_sel = true,
109 };
110
111 static const struct kszphy_type ksz8041_type = {
112 .led_mode_reg = MII_KSZPHY_CTRL_1,
113 };
114
115 static const struct kszphy_type ksz8051_type = {
116 .led_mode_reg = MII_KSZPHY_CTRL_2,
117 .has_nand_tree_disable = true,
118 };
119
120 static const struct kszphy_type ksz8081_type = {
121 .led_mode_reg = MII_KSZPHY_CTRL_2,
122 .has_broadcast_disable = true,
123 .has_nand_tree_disable = true,
124 .has_rmii_ref_clk_sel = true,
125 };
126
127 static const struct kszphy_type ks8737_type = {
128 .interrupt_level_mask = BIT(14),
129 };
130
131 static const struct kszphy_type ksz9021_type = {
132 .interrupt_level_mask = BIT(14),
133 };
134
kszphy_extended_write(struct phy_device * phydev,u32 regnum,u16 val)135 static int kszphy_extended_write(struct phy_device *phydev,
136 u32 regnum, u16 val)
137 {
138 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
139 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
140 }
141
kszphy_extended_read(struct phy_device * phydev,u32 regnum)142 static int kszphy_extended_read(struct phy_device *phydev,
143 u32 regnum)
144 {
145 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
146 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
147 }
148
kszphy_ack_interrupt(struct phy_device * phydev)149 static int kszphy_ack_interrupt(struct phy_device *phydev)
150 {
151 /* bit[7..0] int status, which is a read and clear register. */
152 int rc;
153
154 rc = phy_read(phydev, MII_KSZPHY_INTCS);
155
156 return (rc < 0) ? rc : 0;
157 }
158
kszphy_config_intr(struct phy_device * phydev)159 static int kszphy_config_intr(struct phy_device *phydev)
160 {
161 const struct kszphy_type *type = phydev->drv->driver_data;
162 int temp;
163 u16 mask;
164
165 if (type && type->interrupt_level_mask)
166 mask = type->interrupt_level_mask;
167 else
168 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
169
170 /* set the interrupt pin active low */
171 temp = phy_read(phydev, MII_KSZPHY_CTRL);
172 if (temp < 0)
173 return temp;
174 temp &= ~mask;
175 phy_write(phydev, MII_KSZPHY_CTRL, temp);
176
177 /* enable / disable interrupts */
178 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
179 temp = KSZPHY_INTCS_ALL;
180 else
181 temp = 0;
182
183 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
184 }
185
kszphy_rmii_clk_sel(struct phy_device * phydev,bool val)186 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
187 {
188 int ctrl;
189
190 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
191 if (ctrl < 0)
192 return ctrl;
193
194 if (val)
195 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
196 else
197 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
198
199 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
200 }
201
kszphy_setup_led(struct phy_device * phydev,u32 reg,int val)202 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
203 {
204 int rc, temp, shift;
205
206 switch (reg) {
207 case MII_KSZPHY_CTRL_1:
208 shift = 14;
209 break;
210 case MII_KSZPHY_CTRL_2:
211 shift = 4;
212 break;
213 default:
214 return -EINVAL;
215 }
216
217 temp = phy_read(phydev, reg);
218 if (temp < 0) {
219 rc = temp;
220 goto out;
221 }
222
223 temp &= ~(3 << shift);
224 temp |= val << shift;
225 rc = phy_write(phydev, reg, temp);
226 out:
227 if (rc < 0)
228 phydev_err(phydev, "failed to set led mode\n");
229
230 return rc;
231 }
232
233 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
234 * unique (non-broadcast) address on a shared bus.
235 */
kszphy_broadcast_disable(struct phy_device * phydev)236 static int kszphy_broadcast_disable(struct phy_device *phydev)
237 {
238 int ret;
239
240 ret = phy_read(phydev, MII_KSZPHY_OMSO);
241 if (ret < 0)
242 goto out;
243
244 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
245 out:
246 if (ret)
247 phydev_err(phydev, "failed to disable broadcast address\n");
248
249 return ret;
250 }
251
kszphy_nand_tree_disable(struct phy_device * phydev)252 static int kszphy_nand_tree_disable(struct phy_device *phydev)
253 {
254 int ret;
255
256 ret = phy_read(phydev, MII_KSZPHY_OMSO);
257 if (ret < 0)
258 goto out;
259
260 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
261 return 0;
262
263 ret = phy_write(phydev, MII_KSZPHY_OMSO,
264 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
265 out:
266 if (ret)
267 phydev_err(phydev, "failed to disable NAND tree mode\n");
268
269 return ret;
270 }
271
272 /* Some config bits need to be set again on resume, handle them here. */
kszphy_config_reset(struct phy_device * phydev)273 static int kszphy_config_reset(struct phy_device *phydev)
274 {
275 struct kszphy_priv *priv = phydev->priv;
276 int ret;
277
278 if (priv->rmii_ref_clk_sel) {
279 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
280 if (ret) {
281 phydev_err(phydev,
282 "failed to set rmii reference clock\n");
283 return ret;
284 }
285 }
286
287 if (priv->led_mode >= 0)
288 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
289
290 return 0;
291 }
292
kszphy_config_init(struct phy_device * phydev)293 static int kszphy_config_init(struct phy_device *phydev)
294 {
295 struct kszphy_priv *priv = phydev->priv;
296 const struct kszphy_type *type;
297
298 if (!priv)
299 return 0;
300
301 type = priv->type;
302
303 if (type->has_broadcast_disable)
304 kszphy_broadcast_disable(phydev);
305
306 if (type->has_nand_tree_disable)
307 kszphy_nand_tree_disable(phydev);
308
309 return kszphy_config_reset(phydev);
310 }
311
ksz8041_config_init(struct phy_device * phydev)312 static int ksz8041_config_init(struct phy_device *phydev)
313 {
314 struct device_node *of_node = phydev->mdio.dev.of_node;
315
316 /* Limit supported and advertised modes in fiber mode */
317 if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
318 phydev->dev_flags |= MICREL_PHY_FXEN;
319 phydev->supported &= SUPPORTED_100baseT_Full |
320 SUPPORTED_100baseT_Half;
321 phydev->supported |= SUPPORTED_FIBRE;
322 phydev->advertising &= ADVERTISED_100baseT_Full |
323 ADVERTISED_100baseT_Half;
324 phydev->advertising |= ADVERTISED_FIBRE;
325 phydev->autoneg = AUTONEG_DISABLE;
326 }
327
328 return kszphy_config_init(phydev);
329 }
330
ksz8041_config_aneg(struct phy_device * phydev)331 static int ksz8041_config_aneg(struct phy_device *phydev)
332 {
333 /* Skip auto-negotiation in fiber mode */
334 if (phydev->dev_flags & MICREL_PHY_FXEN) {
335 phydev->speed = SPEED_100;
336 return 0;
337 }
338
339 return genphy_config_aneg(phydev);
340 }
341
ksz8061_config_init(struct phy_device * phydev)342 static int ksz8061_config_init(struct phy_device *phydev)
343 {
344 int ret;
345
346 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
347 if (ret)
348 return ret;
349
350 return kszphy_config_init(phydev);
351 }
352
ksz9021_load_values_from_of(struct phy_device * phydev,const struct device_node * of_node,u16 reg,const char * field1,const char * field2,const char * field3,const char * field4)353 static int ksz9021_load_values_from_of(struct phy_device *phydev,
354 const struct device_node *of_node,
355 u16 reg,
356 const char *field1, const char *field2,
357 const char *field3, const char *field4)
358 {
359 int val1 = -1;
360 int val2 = -2;
361 int val3 = -3;
362 int val4 = -4;
363 int newval;
364 int matches = 0;
365
366 if (!of_property_read_u32(of_node, field1, &val1))
367 matches++;
368
369 if (!of_property_read_u32(of_node, field2, &val2))
370 matches++;
371
372 if (!of_property_read_u32(of_node, field3, &val3))
373 matches++;
374
375 if (!of_property_read_u32(of_node, field4, &val4))
376 matches++;
377
378 if (!matches)
379 return 0;
380
381 if (matches < 4)
382 newval = kszphy_extended_read(phydev, reg);
383 else
384 newval = 0;
385
386 if (val1 != -1)
387 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
388
389 if (val2 != -2)
390 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
391
392 if (val3 != -3)
393 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
394
395 if (val4 != -4)
396 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
397
398 return kszphy_extended_write(phydev, reg, newval);
399 }
400
ksz9021_config_init(struct phy_device * phydev)401 static int ksz9021_config_init(struct phy_device *phydev)
402 {
403 const struct device *dev = &phydev->mdio.dev;
404 const struct device_node *of_node = dev->of_node;
405 const struct device *dev_walker;
406
407 /* The Micrel driver has a deprecated option to place phy OF
408 * properties in the MAC node. Walk up the tree of devices to
409 * find a device with an OF node.
410 */
411 dev_walker = &phydev->mdio.dev;
412 do {
413 of_node = dev_walker->of_node;
414 dev_walker = dev_walker->parent;
415
416 } while (!of_node && dev_walker);
417
418 if (of_node) {
419 ksz9021_load_values_from_of(phydev, of_node,
420 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
421 "txen-skew-ps", "txc-skew-ps",
422 "rxdv-skew-ps", "rxc-skew-ps");
423 ksz9021_load_values_from_of(phydev, of_node,
424 MII_KSZPHY_RX_DATA_PAD_SKEW,
425 "rxd0-skew-ps", "rxd1-skew-ps",
426 "rxd2-skew-ps", "rxd3-skew-ps");
427 ksz9021_load_values_from_of(phydev, of_node,
428 MII_KSZPHY_TX_DATA_PAD_SKEW,
429 "txd0-skew-ps", "txd1-skew-ps",
430 "txd2-skew-ps", "txd3-skew-ps");
431 }
432 return 0;
433 }
434
435 #define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
436 #define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
437 #define OP_DATA 1
438 #define KSZ9031_PS_TO_REG 60
439
440 /* Extended registers */
441 /* MMD Address 0x0 */
442 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3
443 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4
444
445 /* MMD Address 0x2 */
446 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
447 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
448 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
449 #define MII_KSZ9031RN_CLK_PAD_SKEW 8
450
451 /* MMD Address 0x1C */
452 #define MII_KSZ9031RN_EDPD 0x23
453 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
454
ksz9031_extended_write(struct phy_device * phydev,u8 mode,u32 dev_addr,u32 regnum,u16 val)455 static int ksz9031_extended_write(struct phy_device *phydev,
456 u8 mode, u32 dev_addr, u32 regnum, u16 val)
457 {
458 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
459 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
460 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
461 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
462 }
463
ksz9031_extended_read(struct phy_device * phydev,u8 mode,u32 dev_addr,u32 regnum)464 static int ksz9031_extended_read(struct phy_device *phydev,
465 u8 mode, u32 dev_addr, u32 regnum)
466 {
467 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
468 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
469 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
470 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
471 }
472
ksz9031_of_load_skew_values(struct phy_device * phydev,const struct device_node * of_node,u16 reg,size_t field_sz,const char * field[],u8 numfields)473 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
474 const struct device_node *of_node,
475 u16 reg, size_t field_sz,
476 const char *field[], u8 numfields)
477 {
478 int val[4] = {-1, -2, -3, -4};
479 int matches = 0;
480 u16 mask;
481 u16 maxval;
482 u16 newval;
483 int i;
484
485 for (i = 0; i < numfields; i++)
486 if (!of_property_read_u32(of_node, field[i], val + i))
487 matches++;
488
489 if (!matches)
490 return 0;
491
492 if (matches < numfields)
493 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
494 else
495 newval = 0;
496
497 maxval = (field_sz == 4) ? 0xf : 0x1f;
498 for (i = 0; i < numfields; i++)
499 if (val[i] != -(i + 1)) {
500 mask = 0xffff;
501 mask ^= maxval << (field_sz * i);
502 newval = (newval & mask) |
503 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
504 << (field_sz * i));
505 }
506
507 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
508 }
509
ksz9031_center_flp_timing(struct phy_device * phydev)510 static int ksz9031_center_flp_timing(struct phy_device *phydev)
511 {
512 int result;
513
514 /* Center KSZ9031RNX FLP timing at 16ms. */
515 result = ksz9031_extended_write(phydev, OP_DATA, 0,
516 MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
517 result = ksz9031_extended_write(phydev, OP_DATA, 0,
518 MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
519
520 if (result)
521 return result;
522
523 return genphy_restart_aneg(phydev);
524 }
525
526 /* Enable energy-detect power-down mode */
ksz9031_enable_edpd(struct phy_device * phydev)527 static int ksz9031_enable_edpd(struct phy_device *phydev)
528 {
529 int reg;
530
531 reg = ksz9031_extended_read(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD);
532 if (reg < 0)
533 return reg;
534 return ksz9031_extended_write(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD,
535 reg | MII_KSZ9031RN_EDPD_ENABLE);
536 }
537
ksz9031_config_init(struct phy_device * phydev)538 static int ksz9031_config_init(struct phy_device *phydev)
539 {
540 const struct device *dev = &phydev->mdio.dev;
541 const struct device_node *of_node = dev->of_node;
542 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
543 static const char *rx_data_skews[4] = {
544 "rxd0-skew-ps", "rxd1-skew-ps",
545 "rxd2-skew-ps", "rxd3-skew-ps"
546 };
547 static const char *tx_data_skews[4] = {
548 "txd0-skew-ps", "txd1-skew-ps",
549 "txd2-skew-ps", "txd3-skew-ps"
550 };
551 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
552 const struct device *dev_walker;
553 int result;
554
555 result = ksz9031_enable_edpd(phydev);
556 if (result < 0)
557 return result;
558
559 /* The Micrel driver has a deprecated option to place phy OF
560 * properties in the MAC node. Walk up the tree of devices to
561 * find a device with an OF node.
562 */
563 dev_walker = &phydev->mdio.dev;
564 do {
565 of_node = dev_walker->of_node;
566 dev_walker = dev_walker->parent;
567 } while (!of_node && dev_walker);
568
569 if (of_node) {
570 ksz9031_of_load_skew_values(phydev, of_node,
571 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
572 clk_skews, 2);
573
574 ksz9031_of_load_skew_values(phydev, of_node,
575 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
576 control_skews, 2);
577
578 ksz9031_of_load_skew_values(phydev, of_node,
579 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
580 rx_data_skews, 4);
581
582 ksz9031_of_load_skew_values(phydev, of_node,
583 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
584 tx_data_skews, 4);
585 }
586
587 return ksz9031_center_flp_timing(phydev);
588 }
589
590 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
591 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
592 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
ksz8873mll_read_status(struct phy_device * phydev)593 static int ksz8873mll_read_status(struct phy_device *phydev)
594 {
595 int regval;
596
597 /* dummy read */
598 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
599
600 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
601
602 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
603 phydev->duplex = DUPLEX_HALF;
604 else
605 phydev->duplex = DUPLEX_FULL;
606
607 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
608 phydev->speed = SPEED_10;
609 else
610 phydev->speed = SPEED_100;
611
612 phydev->link = 1;
613 phydev->pause = phydev->asym_pause = 0;
614
615 return 0;
616 }
617
ksz9031_read_status(struct phy_device * phydev)618 static int ksz9031_read_status(struct phy_device *phydev)
619 {
620 int err;
621 int regval;
622
623 err = genphy_read_status(phydev);
624 if (err)
625 return err;
626
627 /* Make sure the PHY is not broken. Read idle error count,
628 * and reset the PHY if it is maxed out.
629 */
630 regval = phy_read(phydev, MII_STAT1000);
631 if ((regval & 0xFF) == 0xFF) {
632 phy_init_hw(phydev);
633 phydev->link = 0;
634 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
635 phydev->drv->config_intr(phydev);
636 return genphy_config_aneg(phydev);
637 }
638
639 return 0;
640 }
641
ksz8873mll_config_aneg(struct phy_device * phydev)642 static int ksz8873mll_config_aneg(struct phy_device *phydev)
643 {
644 return 0;
645 }
646
647 /* This routine returns -1 as an indication to the caller that the
648 * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
649 * MMD extended PHY registers.
650 */
651 static int
ksz9021_rd_mmd_phyreg(struct phy_device * phydev,int devad,u16 regnum)652 ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int devad, u16 regnum)
653 {
654 return -1;
655 }
656
657 /* This routine does nothing since the Micrel ksz9021 does not support
658 * standard IEEE MMD extended PHY registers.
659 */
660 static int
ksz9021_wr_mmd_phyreg(struct phy_device * phydev,int devad,u16 regnum,u16 val)661 ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int devad, u16 regnum, u16 val)
662 {
663 return -1;
664 }
665
kszphy_get_sset_count(struct phy_device * phydev)666 static int kszphy_get_sset_count(struct phy_device *phydev)
667 {
668 return ARRAY_SIZE(kszphy_hw_stats);
669 }
670
kszphy_get_strings(struct phy_device * phydev,u8 * data)671 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
672 {
673 int i;
674
675 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
676 memcpy(data + i * ETH_GSTRING_LEN,
677 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
678 }
679 }
680
681 #ifndef UINT64_MAX
682 #define UINT64_MAX (u64)(~((u64)0))
683 #endif
kszphy_get_stat(struct phy_device * phydev,int i)684 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
685 {
686 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
687 struct kszphy_priv *priv = phydev->priv;
688 int val;
689 u64 ret;
690
691 val = phy_read(phydev, stat.reg);
692 if (val < 0) {
693 ret = UINT64_MAX;
694 } else {
695 val = val & ((1 << stat.bits) - 1);
696 priv->stats[i] += val;
697 ret = priv->stats[i];
698 }
699
700 return ret;
701 }
702
kszphy_get_stats(struct phy_device * phydev,struct ethtool_stats * stats,u64 * data)703 static void kszphy_get_stats(struct phy_device *phydev,
704 struct ethtool_stats *stats, u64 *data)
705 {
706 int i;
707
708 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
709 data[i] = kszphy_get_stat(phydev, i);
710 }
711
kszphy_suspend(struct phy_device * phydev)712 static int kszphy_suspend(struct phy_device *phydev)
713 {
714 /* Disable PHY Interrupts */
715 if (phy_interrupt_is_valid(phydev)) {
716 phydev->interrupts = PHY_INTERRUPT_DISABLED;
717 if (phydev->drv->config_intr)
718 phydev->drv->config_intr(phydev);
719 }
720
721 return genphy_suspend(phydev);
722 }
723
kszphy_resume(struct phy_device * phydev)724 static int kszphy_resume(struct phy_device *phydev)
725 {
726 int ret;
727
728 genphy_resume(phydev);
729
730 ret = kszphy_config_reset(phydev);
731 if (ret)
732 return ret;
733
734 /* Enable PHY Interrupts */
735 if (phy_interrupt_is_valid(phydev)) {
736 phydev->interrupts = PHY_INTERRUPT_ENABLED;
737 if (phydev->drv->config_intr)
738 phydev->drv->config_intr(phydev);
739 }
740
741 return 0;
742 }
743
kszphy_probe(struct phy_device * phydev)744 static int kszphy_probe(struct phy_device *phydev)
745 {
746 const struct kszphy_type *type = phydev->drv->driver_data;
747 const struct device_node *np = phydev->mdio.dev.of_node;
748 struct kszphy_priv *priv;
749 struct clk *clk;
750 int ret;
751
752 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
753 if (!priv)
754 return -ENOMEM;
755
756 phydev->priv = priv;
757
758 priv->type = type;
759
760 if (type->led_mode_reg) {
761 ret = of_property_read_u32(np, "micrel,led-mode",
762 &priv->led_mode);
763 if (ret)
764 priv->led_mode = -1;
765
766 if (priv->led_mode > 3) {
767 phydev_err(phydev, "invalid led mode: 0x%02x\n",
768 priv->led_mode);
769 priv->led_mode = -1;
770 }
771 } else {
772 priv->led_mode = -1;
773 }
774
775 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
776 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
777 if (!IS_ERR_OR_NULL(clk)) {
778 unsigned long rate = clk_get_rate(clk);
779 bool rmii_ref_clk_sel_25_mhz;
780
781 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
782 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
783 "micrel,rmii-reference-clock-select-25-mhz");
784
785 if (rate > 24500000 && rate < 25500000) {
786 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
787 } else if (rate > 49500000 && rate < 50500000) {
788 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
789 } else {
790 phydev_err(phydev, "Clock rate out of range: %ld\n",
791 rate);
792 return -EINVAL;
793 }
794 }
795
796 /* Support legacy board-file configuration */
797 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
798 priv->rmii_ref_clk_sel = true;
799 priv->rmii_ref_clk_sel_val = true;
800 }
801
802 return 0;
803 }
804
805 static struct phy_driver ksphy_driver[] = {
806 {
807 .phy_id = PHY_ID_KS8737,
808 .phy_id_mask = MICREL_PHY_ID_MASK,
809 .name = "Micrel KS8737",
810 .features = PHY_BASIC_FEATURES,
811 .flags = PHY_HAS_INTERRUPT,
812 .driver_data = &ks8737_type,
813 .config_init = kszphy_config_init,
814 .config_aneg = genphy_config_aneg,
815 .read_status = genphy_read_status,
816 .ack_interrupt = kszphy_ack_interrupt,
817 .config_intr = kszphy_config_intr,
818 .suspend = genphy_suspend,
819 .resume = genphy_resume,
820 }, {
821 .phy_id = PHY_ID_KSZ8021,
822 .phy_id_mask = 0x00ffffff,
823 .name = "Micrel KSZ8021 or KSZ8031",
824 .features = PHY_BASIC_FEATURES,
825 .flags = PHY_HAS_INTERRUPT,
826 .driver_data = &ksz8021_type,
827 .probe = kszphy_probe,
828 .config_init = kszphy_config_init,
829 .config_aneg = genphy_config_aneg,
830 .read_status = genphy_read_status,
831 .ack_interrupt = kszphy_ack_interrupt,
832 .config_intr = kszphy_config_intr,
833 .get_sset_count = kszphy_get_sset_count,
834 .get_strings = kszphy_get_strings,
835 .get_stats = kszphy_get_stats,
836 .suspend = genphy_suspend,
837 .resume = genphy_resume,
838 }, {
839 .phy_id = PHY_ID_KSZ8031,
840 .phy_id_mask = 0x00ffffff,
841 .name = "Micrel KSZ8031",
842 .features = PHY_BASIC_FEATURES,
843 .flags = PHY_HAS_INTERRUPT,
844 .driver_data = &ksz8021_type,
845 .probe = kszphy_probe,
846 .config_init = kszphy_config_init,
847 .config_aneg = genphy_config_aneg,
848 .read_status = genphy_read_status,
849 .ack_interrupt = kszphy_ack_interrupt,
850 .config_intr = kszphy_config_intr,
851 .get_sset_count = kszphy_get_sset_count,
852 .get_strings = kszphy_get_strings,
853 .get_stats = kszphy_get_stats,
854 .suspend = genphy_suspend,
855 .resume = genphy_resume,
856 }, {
857 .phy_id = PHY_ID_KSZ8041,
858 .phy_id_mask = MICREL_PHY_ID_MASK,
859 .name = "Micrel KSZ8041",
860 .features = PHY_BASIC_FEATURES,
861 .flags = PHY_HAS_INTERRUPT,
862 .driver_data = &ksz8041_type,
863 .probe = kszphy_probe,
864 .config_init = ksz8041_config_init,
865 .config_aneg = ksz8041_config_aneg,
866 .read_status = genphy_read_status,
867 .ack_interrupt = kszphy_ack_interrupt,
868 .config_intr = kszphy_config_intr,
869 .get_sset_count = kszphy_get_sset_count,
870 .get_strings = kszphy_get_strings,
871 .get_stats = kszphy_get_stats,
872 .suspend = genphy_suspend,
873 .resume = genphy_resume,
874 }, {
875 .phy_id = PHY_ID_KSZ8041RNLI,
876 .phy_id_mask = MICREL_PHY_ID_MASK,
877 .name = "Micrel KSZ8041RNLI",
878 .features = PHY_BASIC_FEATURES,
879 .flags = PHY_HAS_INTERRUPT,
880 .driver_data = &ksz8041_type,
881 .probe = kszphy_probe,
882 .config_init = kszphy_config_init,
883 .config_aneg = genphy_config_aneg,
884 .read_status = genphy_read_status,
885 .ack_interrupt = kszphy_ack_interrupt,
886 .config_intr = kszphy_config_intr,
887 .get_sset_count = kszphy_get_sset_count,
888 .get_strings = kszphy_get_strings,
889 .get_stats = kszphy_get_stats,
890 .suspend = genphy_suspend,
891 .resume = genphy_resume,
892 }, {
893 .phy_id = PHY_ID_KSZ8051,
894 .phy_id_mask = MICREL_PHY_ID_MASK,
895 .name = "Micrel KSZ8051",
896 .features = PHY_BASIC_FEATURES,
897 .flags = PHY_HAS_INTERRUPT,
898 .driver_data = &ksz8051_type,
899 .probe = kszphy_probe,
900 .config_init = kszphy_config_init,
901 .config_aneg = genphy_config_aneg,
902 .read_status = genphy_read_status,
903 .ack_interrupt = kszphy_ack_interrupt,
904 .config_intr = kszphy_config_intr,
905 .get_sset_count = kszphy_get_sset_count,
906 .get_strings = kszphy_get_strings,
907 .get_stats = kszphy_get_stats,
908 .suspend = genphy_suspend,
909 .resume = genphy_resume,
910 }, {
911 .phy_id = PHY_ID_KSZ8001,
912 .name = "Micrel KSZ8001 or KS8721",
913 .phy_id_mask = 0x00fffffc,
914 .features = PHY_BASIC_FEATURES,
915 .flags = PHY_HAS_INTERRUPT,
916 .driver_data = &ksz8041_type,
917 .probe = kszphy_probe,
918 .config_init = kszphy_config_init,
919 .config_aneg = genphy_config_aneg,
920 .read_status = genphy_read_status,
921 .ack_interrupt = kszphy_ack_interrupt,
922 .config_intr = kszphy_config_intr,
923 .get_sset_count = kszphy_get_sset_count,
924 .get_strings = kszphy_get_strings,
925 .get_stats = kszphy_get_stats,
926 .suspend = genphy_suspend,
927 .resume = genphy_resume,
928 }, {
929 .phy_id = PHY_ID_KSZ8081,
930 .name = "Micrel KSZ8081 or KSZ8091",
931 .phy_id_mask = MICREL_PHY_ID_MASK,
932 .features = PHY_BASIC_FEATURES,
933 .flags = PHY_HAS_INTERRUPT,
934 .driver_data = &ksz8081_type,
935 .probe = kszphy_probe,
936 .config_init = kszphy_config_init,
937 .config_aneg = genphy_config_aneg,
938 .read_status = genphy_read_status,
939 .ack_interrupt = kszphy_ack_interrupt,
940 .config_intr = kszphy_config_intr,
941 .get_sset_count = kszphy_get_sset_count,
942 .get_strings = kszphy_get_strings,
943 .get_stats = kszphy_get_stats,
944 .suspend = kszphy_suspend,
945 .resume = kszphy_resume,
946 }, {
947 .phy_id = PHY_ID_KSZ8061,
948 .name = "Micrel KSZ8061",
949 .phy_id_mask = MICREL_PHY_ID_MASK,
950 .features = PHY_BASIC_FEATURES,
951 .flags = PHY_HAS_INTERRUPT,
952 .config_init = ksz8061_config_init,
953 .config_aneg = genphy_config_aneg,
954 .read_status = genphy_read_status,
955 .ack_interrupt = kszphy_ack_interrupt,
956 .config_intr = kszphy_config_intr,
957 .suspend = genphy_suspend,
958 .resume = genphy_resume,
959 }, {
960 .phy_id = PHY_ID_KSZ9021,
961 .phy_id_mask = 0x000ffffe,
962 .name = "Micrel KSZ9021 Gigabit PHY",
963 .features = PHY_GBIT_FEATURES,
964 .flags = PHY_HAS_INTERRUPT,
965 .driver_data = &ksz9021_type,
966 .probe = kszphy_probe,
967 .config_init = ksz9021_config_init,
968 .config_aneg = genphy_config_aneg,
969 .read_status = genphy_read_status,
970 .ack_interrupt = kszphy_ack_interrupt,
971 .config_intr = kszphy_config_intr,
972 .get_sset_count = kszphy_get_sset_count,
973 .get_strings = kszphy_get_strings,
974 .get_stats = kszphy_get_stats,
975 .suspend = genphy_suspend,
976 .resume = genphy_resume,
977 .read_mmd = ksz9021_rd_mmd_phyreg,
978 .write_mmd = ksz9021_wr_mmd_phyreg,
979 }, {
980 .phy_id = PHY_ID_KSZ9031,
981 .phy_id_mask = MICREL_PHY_ID_MASK,
982 .name = "Micrel KSZ9031 Gigabit PHY",
983 .features = PHY_GBIT_FEATURES,
984 .flags = PHY_HAS_INTERRUPT,
985 .driver_data = &ksz9021_type,
986 .probe = kszphy_probe,
987 .config_init = ksz9031_config_init,
988 .config_aneg = genphy_config_aneg,
989 .read_status = ksz9031_read_status,
990 .ack_interrupt = kszphy_ack_interrupt,
991 .config_intr = kszphy_config_intr,
992 .get_sset_count = kszphy_get_sset_count,
993 .get_strings = kszphy_get_strings,
994 .get_stats = kszphy_get_stats,
995 .suspend = genphy_suspend,
996 .resume = kszphy_resume,
997 }, {
998 .phy_id = PHY_ID_KSZ8873MLL,
999 .phy_id_mask = MICREL_PHY_ID_MASK,
1000 .name = "Micrel KSZ8873MLL Switch",
1001 .config_init = kszphy_config_init,
1002 .config_aneg = ksz8873mll_config_aneg,
1003 .read_status = ksz8873mll_read_status,
1004 .suspend = genphy_suspend,
1005 .resume = genphy_resume,
1006 }, {
1007 .phy_id = PHY_ID_KSZ886X,
1008 .phy_id_mask = MICREL_PHY_ID_MASK,
1009 .name = "Micrel KSZ886X Switch",
1010 .features = PHY_BASIC_FEATURES,
1011 .flags = PHY_HAS_INTERRUPT,
1012 .config_init = kszphy_config_init,
1013 .config_aneg = genphy_config_aneg,
1014 .read_status = genphy_read_status,
1015 .suspend = genphy_suspend,
1016 .resume = genphy_resume,
1017 }, {
1018 .phy_id = PHY_ID_KSZ8795,
1019 .phy_id_mask = MICREL_PHY_ID_MASK,
1020 .name = "Micrel KSZ8795",
1021 .features = PHY_BASIC_FEATURES,
1022 .flags = PHY_HAS_INTERRUPT,
1023 .config_init = kszphy_config_init,
1024 .config_aneg = ksz8873mll_config_aneg,
1025 .read_status = ksz8873mll_read_status,
1026 .suspend = genphy_suspend,
1027 .resume = genphy_resume,
1028 }, {
1029 .phy_id = PHY_ID_KSZ9477,
1030 .phy_id_mask = MICREL_PHY_ID_MASK,
1031 .name = "Microchip KSZ9477",
1032 .features = PHY_GBIT_FEATURES,
1033 .config_init = kszphy_config_init,
1034 .config_aneg = genphy_config_aneg,
1035 .read_status = genphy_read_status,
1036 .suspend = genphy_suspend,
1037 .resume = genphy_resume,
1038 } };
1039
1040 module_phy_driver(ksphy_driver);
1041
1042 MODULE_DESCRIPTION("Micrel PHY driver");
1043 MODULE_AUTHOR("David J. Choi");
1044 MODULE_LICENSE("GPL");
1045
1046 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
1047 { PHY_ID_KSZ9021, 0x000ffffe },
1048 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
1049 { PHY_ID_KSZ8001, 0x00fffffc },
1050 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
1051 { PHY_ID_KSZ8021, 0x00ffffff },
1052 { PHY_ID_KSZ8031, 0x00ffffff },
1053 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1054 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1055 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1056 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1057 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1058 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
1059 { }
1060 };
1061
1062 MODULE_DEVICE_TABLE(mdio, micrel_tbl);
1063