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1 /*
2  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * version 2 as published by the Free Software Foundation.
7  *
8  */
9 
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27 #include <linux/usb/cdc.h>
28 #include <linux/suspend.h>
29 #include <linux/acpi.h>
30 
31 /* Information for net-next */
32 #define NETNEXT_VERSION		"09"
33 
34 /* Information for net */
35 #define NET_VERSION		"9"
36 
37 #define DRIVER_VERSION		"v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
41 
42 #define R8152_PHY_ID		32
43 
44 #define PLA_IDR			0xc000
45 #define PLA_RCR			0xc010
46 #define PLA_RMS			0xc016
47 #define PLA_RXFIFO_CTRL0	0xc0a0
48 #define PLA_RXFIFO_CTRL1	0xc0a4
49 #define PLA_RXFIFO_CTRL2	0xc0a8
50 #define PLA_DMY_REG0		0xc0b0
51 #define PLA_FMC			0xc0b4
52 #define PLA_CFG_WOL		0xc0b6
53 #define PLA_TEREDO_CFG		0xc0bc
54 #define PLA_TEREDO_WAKE_BASE	0xc0c4
55 #define PLA_MAR			0xcd00
56 #define PLA_BACKUP		0xd000
57 #define PAL_BDC_CR		0xd1a0
58 #define PLA_TEREDO_TIMER	0xd2cc
59 #define PLA_REALWOW_TIMER	0xd2e8
60 #define PLA_EFUSE_DATA		0xdd00
61 #define PLA_EFUSE_CMD		0xdd02
62 #define PLA_LEDSEL		0xdd90
63 #define PLA_LED_FEATURE		0xdd92
64 #define PLA_PHYAR		0xde00
65 #define PLA_BOOT_CTRL		0xe004
66 #define PLA_GPHY_INTR_IMR	0xe022
67 #define PLA_EEE_CR		0xe040
68 #define PLA_EEEP_CR		0xe080
69 #define PLA_MAC_PWR_CTRL	0xe0c0
70 #define PLA_MAC_PWR_CTRL2	0xe0ca
71 #define PLA_MAC_PWR_CTRL3	0xe0cc
72 #define PLA_MAC_PWR_CTRL4	0xe0ce
73 #define PLA_WDT6_CTRL		0xe428
74 #define PLA_TCR0		0xe610
75 #define PLA_TCR1		0xe612
76 #define PLA_MTPS		0xe615
77 #define PLA_TXFIFO_CTRL		0xe618
78 #define PLA_RSTTALLY		0xe800
79 #define PLA_CR			0xe813
80 #define PLA_CRWECR		0xe81c
81 #define PLA_CONFIG12		0xe81e	/* CONFIG1, CONFIG2 */
82 #define PLA_CONFIG34		0xe820	/* CONFIG3, CONFIG4 */
83 #define PLA_CONFIG5		0xe822
84 #define PLA_PHY_PWR		0xe84c
85 #define PLA_OOB_CTRL		0xe84f
86 #define PLA_CPCR		0xe854
87 #define PLA_MISC_0		0xe858
88 #define PLA_MISC_1		0xe85a
89 #define PLA_OCP_GPHY_BASE	0xe86c
90 #define PLA_TALLYCNT		0xe890
91 #define PLA_SFF_STS_7		0xe8de
92 #define PLA_PHYSTATUS		0xe908
93 #define PLA_BP_BA		0xfc26
94 #define PLA_BP_0		0xfc28
95 #define PLA_BP_1		0xfc2a
96 #define PLA_BP_2		0xfc2c
97 #define PLA_BP_3		0xfc2e
98 #define PLA_BP_4		0xfc30
99 #define PLA_BP_5		0xfc32
100 #define PLA_BP_6		0xfc34
101 #define PLA_BP_7		0xfc36
102 #define PLA_BP_EN		0xfc38
103 
104 #define USB_USB2PHY		0xb41e
105 #define USB_SSPHYLINK2		0xb428
106 #define USB_U2P3_CTRL		0xb460
107 #define USB_CSR_DUMMY1		0xb464
108 #define USB_CSR_DUMMY2		0xb466
109 #define USB_DEV_STAT		0xb808
110 #define USB_CONNECT_TIMER	0xcbf8
111 #define USB_MSC_TIMER		0xcbfc
112 #define USB_BURST_SIZE		0xcfc0
113 #define USB_LPM_CONFIG		0xcfd8
114 #define USB_USB_CTRL		0xd406
115 #define USB_PHY_CTRL		0xd408
116 #define USB_TX_AGG		0xd40a
117 #define USB_RX_BUF_TH		0xd40c
118 #define USB_USB_TIMER		0xd428
119 #define USB_RX_EARLY_TIMEOUT	0xd42c
120 #define USB_RX_EARLY_SIZE	0xd42e
121 #define USB_PM_CTRL_STATUS	0xd432	/* RTL8153A */
122 #define USB_RX_EXTRA_AGGR_TMR	0xd432	/* RTL8153B */
123 #define USB_TX_DMA		0xd434
124 #define USB_UPT_RXDMA_OWN	0xd437
125 #define USB_TOLERANCE		0xd490
126 #define USB_LPM_CTRL		0xd41a
127 #define USB_BMU_RESET		0xd4b0
128 #define USB_U1U2_TIMER		0xd4da
129 #define USB_UPS_CTRL		0xd800
130 #define USB_POWER_CUT		0xd80a
131 #define USB_MISC_0		0xd81a
132 #define USB_AFE_CTRL2		0xd824
133 #define USB_UPS_CFG		0xd842
134 #define USB_UPS_FLAGS		0xd848
135 #define USB_WDT11_CTRL		0xe43c
136 #define USB_BP_BA		0xfc26
137 #define USB_BP_0		0xfc28
138 #define USB_BP_1		0xfc2a
139 #define USB_BP_2		0xfc2c
140 #define USB_BP_3		0xfc2e
141 #define USB_BP_4		0xfc30
142 #define USB_BP_5		0xfc32
143 #define USB_BP_6		0xfc34
144 #define USB_BP_7		0xfc36
145 #define USB_BP_EN		0xfc38
146 #define USB_BP_8		0xfc38
147 #define USB_BP_9		0xfc3a
148 #define USB_BP_10		0xfc3c
149 #define USB_BP_11		0xfc3e
150 #define USB_BP_12		0xfc40
151 #define USB_BP_13		0xfc42
152 #define USB_BP_14		0xfc44
153 #define USB_BP_15		0xfc46
154 #define USB_BP2_EN		0xfc48
155 
156 /* OCP Registers */
157 #define OCP_ALDPS_CONFIG	0x2010
158 #define OCP_EEE_CONFIG1		0x2080
159 #define OCP_EEE_CONFIG2		0x2092
160 #define OCP_EEE_CONFIG3		0x2094
161 #define OCP_BASE_MII		0xa400
162 #define OCP_EEE_AR		0xa41a
163 #define OCP_EEE_DATA		0xa41c
164 #define OCP_PHY_STATUS		0xa420
165 #define OCP_NCTL_CFG		0xa42c
166 #define OCP_POWER_CFG		0xa430
167 #define OCP_EEE_CFG		0xa432
168 #define OCP_SRAM_ADDR		0xa436
169 #define OCP_SRAM_DATA		0xa438
170 #define OCP_DOWN_SPEED		0xa442
171 #define OCP_EEE_ABLE		0xa5c4
172 #define OCP_EEE_ADV		0xa5d0
173 #define OCP_EEE_LPABLE		0xa5d2
174 #define OCP_PHY_STATE		0xa708		/* nway state for 8153 */
175 #define OCP_PHY_PATCH_STAT	0xb800
176 #define OCP_PHY_PATCH_CMD	0xb820
177 #define OCP_ADC_IOFFSET		0xbcfc
178 #define OCP_ADC_CFG		0xbc06
179 #define OCP_SYSCLK_CFG		0xc416
180 
181 /* SRAM Register */
182 #define SRAM_GREEN_CFG		0x8011
183 #define SRAM_LPF_CFG		0x8012
184 #define SRAM_10M_AMP1		0x8080
185 #define SRAM_10M_AMP2		0x8082
186 #define SRAM_IMPEDANCE		0x8084
187 
188 /* PLA_RCR */
189 #define RCR_AAP			0x00000001
190 #define RCR_APM			0x00000002
191 #define RCR_AM			0x00000004
192 #define RCR_AB			0x00000008
193 #define RCR_ACPT_ALL		(RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
194 
195 /* PLA_RXFIFO_CTRL0 */
196 #define RXFIFO_THR1_NORMAL	0x00080002
197 #define RXFIFO_THR1_OOB		0x01800003
198 
199 /* PLA_RXFIFO_CTRL1 */
200 #define RXFIFO_THR2_FULL	0x00000060
201 #define RXFIFO_THR2_HIGH	0x00000038
202 #define RXFIFO_THR2_OOB		0x0000004a
203 #define RXFIFO_THR2_NORMAL	0x00a0
204 
205 /* PLA_RXFIFO_CTRL2 */
206 #define RXFIFO_THR3_FULL	0x00000078
207 #define RXFIFO_THR3_HIGH	0x00000048
208 #define RXFIFO_THR3_OOB		0x0000005a
209 #define RXFIFO_THR3_NORMAL	0x0110
210 
211 /* PLA_TXFIFO_CTRL */
212 #define TXFIFO_THR_NORMAL	0x00400008
213 #define TXFIFO_THR_NORMAL2	0x01000008
214 
215 /* PLA_DMY_REG0 */
216 #define ECM_ALDPS		0x0002
217 
218 /* PLA_FMC */
219 #define FMC_FCR_MCU_EN		0x0001
220 
221 /* PLA_EEEP_CR */
222 #define EEEP_CR_EEEP_TX		0x0002
223 
224 /* PLA_WDT6_CTRL */
225 #define WDT6_SET_MODE		0x0010
226 
227 /* PLA_TCR0 */
228 #define TCR0_TX_EMPTY		0x0800
229 #define TCR0_AUTO_FIFO		0x0080
230 
231 /* PLA_TCR1 */
232 #define VERSION_MASK		0x7cf0
233 
234 /* PLA_MTPS */
235 #define MTPS_JUMBO		(12 * 1024 / 64)
236 #define MTPS_DEFAULT		(6 * 1024 / 64)
237 
238 /* PLA_RSTTALLY */
239 #define TALLY_RESET		0x0001
240 
241 /* PLA_CR */
242 #define CR_RST			0x10
243 #define CR_RE			0x08
244 #define CR_TE			0x04
245 
246 /* PLA_CRWECR */
247 #define CRWECR_NORAML		0x00
248 #define CRWECR_CONFIG		0xc0
249 
250 /* PLA_OOB_CTRL */
251 #define NOW_IS_OOB		0x80
252 #define TXFIFO_EMPTY		0x20
253 #define RXFIFO_EMPTY		0x10
254 #define LINK_LIST_READY		0x02
255 #define DIS_MCU_CLROOB		0x01
256 #define FIFO_EMPTY		(TXFIFO_EMPTY | RXFIFO_EMPTY)
257 
258 /* PLA_MISC_1 */
259 #define RXDY_GATED_EN		0x0008
260 
261 /* PLA_SFF_STS_7 */
262 #define RE_INIT_LL		0x8000
263 #define MCU_BORW_EN		0x4000
264 
265 /* PLA_CPCR */
266 #define CPCR_RX_VLAN		0x0040
267 
268 /* PLA_CFG_WOL */
269 #define MAGIC_EN		0x0001
270 
271 /* PLA_TEREDO_CFG */
272 #define TEREDO_SEL		0x8000
273 #define TEREDO_WAKE_MASK	0x7f00
274 #define TEREDO_RS_EVENT_MASK	0x00fe
275 #define OOB_TEREDO_EN		0x0001
276 
277 /* PAL_BDC_CR */
278 #define ALDPS_PROXY_MODE	0x0001
279 
280 /* PLA_EFUSE_CMD */
281 #define EFUSE_READ_CMD		BIT(15)
282 #define EFUSE_DATA_BIT16	BIT(7)
283 
284 /* PLA_CONFIG34 */
285 #define LINK_ON_WAKE_EN		0x0010
286 #define LINK_OFF_WAKE_EN	0x0008
287 
288 /* PLA_CONFIG5 */
289 #define BWF_EN			0x0040
290 #define MWF_EN			0x0020
291 #define UWF_EN			0x0010
292 #define LAN_WAKE_EN		0x0002
293 
294 /* PLA_LED_FEATURE */
295 #define LED_MODE_MASK		0x0700
296 
297 /* PLA_PHY_PWR */
298 #define TX_10M_IDLE_EN		0x0080
299 #define PFM_PWM_SWITCH		0x0040
300 
301 /* PLA_MAC_PWR_CTRL */
302 #define D3_CLK_GATED_EN		0x00004000
303 #define MCU_CLK_RATIO		0x07010f07
304 #define MCU_CLK_RATIO_MASK	0x0f0f0f0f
305 #define ALDPS_SPDWN_RATIO	0x0f87
306 
307 /* PLA_MAC_PWR_CTRL2 */
308 #define EEE_SPDWN_RATIO		0x8007
309 #define MAC_CLK_SPDWN_EN	BIT(15)
310 
311 /* PLA_MAC_PWR_CTRL3 */
312 #define PKT_AVAIL_SPDWN_EN	0x0100
313 #define SUSPEND_SPDWN_EN	0x0004
314 #define U1U2_SPDWN_EN		0x0002
315 #define L1_SPDWN_EN		0x0001
316 
317 /* PLA_MAC_PWR_CTRL4 */
318 #define PWRSAVE_SPDWN_EN	0x1000
319 #define RXDV_SPDWN_EN		0x0800
320 #define TX10MIDLE_EN		0x0100
321 #define TP100_SPDWN_EN		0x0020
322 #define TP500_SPDWN_EN		0x0010
323 #define TP1000_SPDWN_EN		0x0008
324 #define EEE_SPDWN_EN		0x0001
325 
326 /* PLA_GPHY_INTR_IMR */
327 #define GPHY_STS_MSK		0x0001
328 #define SPEED_DOWN_MSK		0x0002
329 #define SPDWN_RXDV_MSK		0x0004
330 #define SPDWN_LINKCHG_MSK	0x0008
331 
332 /* PLA_PHYAR */
333 #define PHYAR_FLAG		0x80000000
334 
335 /* PLA_EEE_CR */
336 #define EEE_RX_EN		0x0001
337 #define EEE_TX_EN		0x0002
338 
339 /* PLA_BOOT_CTRL */
340 #define AUTOLOAD_DONE		0x0002
341 
342 /* USB_USB2PHY */
343 #define USB2PHY_SUSPEND		0x0001
344 #define USB2PHY_L1		0x0002
345 
346 /* USB_SSPHYLINK2 */
347 #define pwd_dn_scale_mask	0x3ffe
348 #define pwd_dn_scale(x)		((x) << 1)
349 
350 /* USB_CSR_DUMMY1 */
351 #define DYNAMIC_BURST		0x0001
352 
353 /* USB_CSR_DUMMY2 */
354 #define EP4_FULL_FC		0x0001
355 
356 /* USB_DEV_STAT */
357 #define STAT_SPEED_MASK		0x0006
358 #define STAT_SPEED_HIGH		0x0000
359 #define STAT_SPEED_FULL		0x0002
360 
361 /* USB_LPM_CONFIG */
362 #define LPM_U1U2_EN		BIT(0)
363 
364 /* USB_TX_AGG */
365 #define TX_AGG_MAX_THRESHOLD	0x03
366 
367 /* USB_RX_BUF_TH */
368 #define RX_THR_SUPPER		0x0c350180
369 #define RX_THR_HIGH		0x7a120180
370 #define RX_THR_SLOW		0xffff0180
371 #define RX_THR_B		0x00010001
372 
373 /* USB_TX_DMA */
374 #define TEST_MODE_DISABLE	0x00000001
375 #define TX_SIZE_ADJUST1		0x00000100
376 
377 /* USB_BMU_RESET */
378 #define BMU_RESET_EP_IN		0x01
379 #define BMU_RESET_EP_OUT	0x02
380 
381 /* USB_UPT_RXDMA_OWN */
382 #define OWN_UPDATE		BIT(0)
383 #define OWN_CLEAR		BIT(1)
384 
385 /* USB_UPS_CTRL */
386 #define POWER_CUT		0x0100
387 
388 /* USB_PM_CTRL_STATUS */
389 #define RESUME_INDICATE		0x0001
390 
391 /* USB_USB_CTRL */
392 #define RX_AGG_DISABLE		0x0010
393 #define RX_ZERO_EN		0x0080
394 
395 /* USB_U2P3_CTRL */
396 #define U2P3_ENABLE		0x0001
397 
398 /* USB_POWER_CUT */
399 #define PWR_EN			0x0001
400 #define PHASE2_EN		0x0008
401 #define UPS_EN			BIT(4)
402 #define USP_PREWAKE		BIT(5)
403 
404 /* USB_MISC_0 */
405 #define PCUT_STATUS		0x0001
406 
407 /* USB_RX_EARLY_TIMEOUT */
408 #define COALESCE_SUPER		 85000U
409 #define COALESCE_HIGH		250000U
410 #define COALESCE_SLOW		524280U
411 
412 /* USB_WDT11_CTRL */
413 #define TIMER11_EN		0x0001
414 
415 /* USB_LPM_CTRL */
416 /* bit 4 ~ 5: fifo empty boundary */
417 #define FIFO_EMPTY_1FB		0x30	/* 0x1fb * 64 = 32448 bytes */
418 /* bit 2 ~ 3: LMP timer */
419 #define LPM_TIMER_MASK		0x0c
420 #define LPM_TIMER_500MS		0x04	/* 500 ms */
421 #define LPM_TIMER_500US		0x0c	/* 500 us */
422 #define ROK_EXIT_LPM		0x02
423 
424 /* USB_AFE_CTRL2 */
425 #define SEN_VAL_MASK		0xf800
426 #define SEN_VAL_NORMAL		0xa000
427 #define SEL_RXIDLE		0x0100
428 
429 /* USB_UPS_CFG */
430 #define SAW_CNT_1MS_MASK	0x0fff
431 
432 /* USB_UPS_FLAGS */
433 #define UPS_FLAGS_R_TUNE		BIT(0)
434 #define UPS_FLAGS_EN_10M_CKDIV		BIT(1)
435 #define UPS_FLAGS_250M_CKDIV		BIT(2)
436 #define UPS_FLAGS_EN_ALDPS		BIT(3)
437 #define UPS_FLAGS_CTAP_SHORT_DIS	BIT(4)
438 #define UPS_FLAGS_SPEED_MASK		(0xf << 16)
439 #define ups_flags_speed(x)		((x) << 16)
440 #define UPS_FLAGS_EN_EEE		BIT(20)
441 #define UPS_FLAGS_EN_500M_EEE		BIT(21)
442 #define UPS_FLAGS_EN_EEE_CKDIV		BIT(22)
443 #define UPS_FLAGS_EEE_PLLOFF_GIGA	BIT(24)
444 #define UPS_FLAGS_EEE_CMOD_LV_EN	BIT(25)
445 #define UPS_FLAGS_EN_GREEN		BIT(26)
446 #define UPS_FLAGS_EN_FLOW_CTR		BIT(27)
447 
448 enum spd_duplex {
449 	NWAY_10M_HALF = 1,
450 	NWAY_10M_FULL,
451 	NWAY_100M_HALF,
452 	NWAY_100M_FULL,
453 	NWAY_1000M_FULL,
454 	FORCE_10M_HALF,
455 	FORCE_10M_FULL,
456 	FORCE_100M_HALF,
457 	FORCE_100M_FULL,
458 };
459 
460 /* OCP_ALDPS_CONFIG */
461 #define ENPWRSAVE		0x8000
462 #define ENPDNPS			0x0200
463 #define LINKENA			0x0100
464 #define DIS_SDSAVE		0x0010
465 
466 /* OCP_PHY_STATUS */
467 #define PHY_STAT_MASK		0x0007
468 #define PHY_STAT_EXT_INIT	2
469 #define PHY_STAT_LAN_ON		3
470 #define PHY_STAT_PWRDN		5
471 
472 /* OCP_NCTL_CFG */
473 #define PGA_RETURN_EN		BIT(1)
474 
475 /* OCP_POWER_CFG */
476 #define EEE_CLKDIV_EN		0x8000
477 #define EN_ALDPS		0x0004
478 #define EN_10M_PLLOFF		0x0001
479 
480 /* OCP_EEE_CONFIG1 */
481 #define RG_TXLPI_MSK_HFDUP	0x8000
482 #define RG_MATCLR_EN		0x4000
483 #define EEE_10_CAP		0x2000
484 #define EEE_NWAY_EN		0x1000
485 #define TX_QUIET_EN		0x0200
486 #define RX_QUIET_EN		0x0100
487 #define sd_rise_time_mask	0x0070
488 #define sd_rise_time(x)		(min(x, 7) << 4)	/* bit 4 ~ 6 */
489 #define RG_RXLPI_MSK_HFDUP	0x0008
490 #define SDFALLTIME		0x0007	/* bit 0 ~ 2 */
491 
492 /* OCP_EEE_CONFIG2 */
493 #define RG_LPIHYS_NUM		0x7000	/* bit 12 ~ 15 */
494 #define RG_DACQUIET_EN		0x0400
495 #define RG_LDVQUIET_EN		0x0200
496 #define RG_CKRSEL		0x0020
497 #define RG_EEEPRG_EN		0x0010
498 
499 /* OCP_EEE_CONFIG3 */
500 #define fast_snr_mask		0xff80
501 #define fast_snr(x)		(min(x, 0x1ff) << 7)	/* bit 7 ~ 15 */
502 #define RG_LFS_SEL		0x0060	/* bit 6 ~ 5 */
503 #define MSK_PH			0x0006	/* bit 0 ~ 3 */
504 
505 /* OCP_EEE_AR */
506 /* bit[15:14] function */
507 #define FUN_ADDR		0x0000
508 #define FUN_DATA		0x4000
509 /* bit[4:0] device addr */
510 
511 /* OCP_EEE_CFG */
512 #define CTAP_SHORT_EN		0x0040
513 #define EEE10_EN		0x0010
514 
515 /* OCP_DOWN_SPEED */
516 #define EN_EEE_CMODE		BIT(14)
517 #define EN_EEE_1000		BIT(13)
518 #define EN_EEE_100		BIT(12)
519 #define EN_10M_CLKDIV		BIT(11)
520 #define EN_10M_BGOFF		0x0080
521 
522 /* OCP_PHY_STATE */
523 #define TXDIS_STATE		0x01
524 #define ABD_STATE		0x02
525 
526 /* OCP_PHY_PATCH_STAT */
527 #define PATCH_READY		BIT(6)
528 
529 /* OCP_PHY_PATCH_CMD */
530 #define PATCH_REQUEST		BIT(4)
531 
532 /* OCP_ADC_CFG */
533 #define CKADSEL_L		0x0100
534 #define ADC_EN			0x0080
535 #define EN_EMI_L		0x0040
536 
537 /* OCP_SYSCLK_CFG */
538 #define clk_div_expo(x)		(min(x, 5) << 8)
539 
540 /* SRAM_GREEN_CFG */
541 #define GREEN_ETH_EN		BIT(15)
542 #define R_TUNE_EN		BIT(11)
543 
544 /* SRAM_LPF_CFG */
545 #define LPF_AUTO_TUNE		0x8000
546 
547 /* SRAM_10M_AMP1 */
548 #define GDAC_IB_UPALL		0x0008
549 
550 /* SRAM_10M_AMP2 */
551 #define AMP_DN			0x0200
552 
553 /* SRAM_IMPEDANCE */
554 #define RX_DRIVING_MASK		0x6000
555 
556 /* MAC PASSTHRU */
557 #define AD_MASK			0xfee0
558 #define EFUSE			0xcfdb
559 #define PASS_THRU_MASK		0x1
560 
561 enum rtl_register_content {
562 	_1000bps	= 0x10,
563 	_100bps		= 0x08,
564 	_10bps		= 0x04,
565 	LINK_STATUS	= 0x02,
566 	FULL_DUP	= 0x01,
567 };
568 
569 #define RTL8152_MAX_TX		4
570 #define RTL8152_MAX_RX		10
571 #define INTBUFSIZE		2
572 #define TX_ALIGN		4
573 #define RX_ALIGN		8
574 
575 #define INTR_LINK		0x0004
576 
577 #define RTL8152_REQT_READ	0xc0
578 #define RTL8152_REQT_WRITE	0x40
579 #define RTL8152_REQ_GET_REGS	0x05
580 #define RTL8152_REQ_SET_REGS	0x05
581 
582 #define BYTE_EN_DWORD		0xff
583 #define BYTE_EN_WORD		0x33
584 #define BYTE_EN_BYTE		0x11
585 #define BYTE_EN_SIX_BYTES	0x3f
586 #define BYTE_EN_START_MASK	0x0f
587 #define BYTE_EN_END_MASK	0xf0
588 
589 #define RTL8153_MAX_PACKET	9216 /* 9K */
590 #define RTL8153_MAX_MTU		(RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
591 				 ETH_FCS_LEN)
592 #define RTL8152_RMS		(VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
593 #define RTL8153_RMS		RTL8153_MAX_PACKET
594 #define RTL8152_TX_TIMEOUT	(5 * HZ)
595 #define RTL8152_NAPI_WEIGHT	64
596 #define rx_reserved_size(x)	((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
597 				 sizeof(struct rx_desc) + RX_ALIGN)
598 
599 /* rtl8152 flags */
600 enum rtl8152_flags {
601 	RTL8152_UNPLUG = 0,
602 	RTL8152_SET_RX_MODE,
603 	WORK_ENABLE,
604 	RTL8152_LINK_CHG,
605 	SELECTIVE_SUSPEND,
606 	PHY_RESET,
607 	SCHEDULE_NAPI,
608 	GREEN_ETHERNET,
609 };
610 
611 /* Define these values to match your device */
612 #define VENDOR_ID_REALTEK		0x0bda
613 #define VENDOR_ID_MICROSOFT		0x045e
614 #define VENDOR_ID_SAMSUNG		0x04e8
615 #define VENDOR_ID_LENOVO		0x17ef
616 #define VENDOR_ID_LINKSYS		0x13b1
617 #define VENDOR_ID_NVIDIA		0x0955
618 #define VENDOR_ID_TPLINK		0x2357
619 
620 #define MCU_TYPE_PLA			0x0100
621 #define MCU_TYPE_USB			0x0000
622 
623 struct tally_counter {
624 	__le64	tx_packets;
625 	__le64	rx_packets;
626 	__le64	tx_errors;
627 	__le32	rx_errors;
628 	__le16	rx_missed;
629 	__le16	align_errors;
630 	__le32	tx_one_collision;
631 	__le32	tx_multi_collision;
632 	__le64	rx_unicast;
633 	__le64	rx_broadcast;
634 	__le32	rx_multicast;
635 	__le16	tx_aborted;
636 	__le16	tx_underrun;
637 };
638 
639 struct rx_desc {
640 	__le32 opts1;
641 #define RX_LEN_MASK			0x7fff
642 
643 	__le32 opts2;
644 #define RD_UDP_CS			BIT(23)
645 #define RD_TCP_CS			BIT(22)
646 #define RD_IPV6_CS			BIT(20)
647 #define RD_IPV4_CS			BIT(19)
648 
649 	__le32 opts3;
650 #define IPF				BIT(23) /* IP checksum fail */
651 #define UDPF				BIT(22) /* UDP checksum fail */
652 #define TCPF				BIT(21) /* TCP checksum fail */
653 #define RX_VLAN_TAG			BIT(16)
654 
655 	__le32 opts4;
656 	__le32 opts5;
657 	__le32 opts6;
658 };
659 
660 struct tx_desc {
661 	__le32 opts1;
662 #define TX_FS			BIT(31) /* First segment of a packet */
663 #define TX_LS			BIT(30) /* Final segment of a packet */
664 #define GTSENDV4		BIT(28)
665 #define GTSENDV6		BIT(27)
666 #define GTTCPHO_SHIFT		18
667 #define GTTCPHO_MAX		0x7fU
668 #define TX_LEN_MAX		0x3ffffU
669 
670 	__le32 opts2;
671 #define UDP_CS			BIT(31) /* Calculate UDP/IP checksum */
672 #define TCP_CS			BIT(30) /* Calculate TCP/IP checksum */
673 #define IPV4_CS			BIT(29) /* Calculate IPv4 checksum */
674 #define IPV6_CS			BIT(28) /* Calculate IPv6 checksum */
675 #define MSS_SHIFT		17
676 #define MSS_MAX			0x7ffU
677 #define TCPHO_SHIFT		17
678 #define TCPHO_MAX		0x7ffU
679 #define TX_VLAN_TAG		BIT(16)
680 };
681 
682 struct r8152;
683 
684 struct rx_agg {
685 	struct list_head list;
686 	struct urb *urb;
687 	struct r8152 *context;
688 	void *buffer;
689 	void *head;
690 };
691 
692 struct tx_agg {
693 	struct list_head list;
694 	struct urb *urb;
695 	struct r8152 *context;
696 	void *buffer;
697 	void *head;
698 	u32 skb_num;
699 	u32 skb_len;
700 };
701 
702 struct r8152 {
703 	unsigned long flags;
704 	struct usb_device *udev;
705 	struct napi_struct napi;
706 	struct usb_interface *intf;
707 	struct net_device *netdev;
708 	struct urb *intr_urb;
709 	struct tx_agg tx_info[RTL8152_MAX_TX];
710 	struct rx_agg rx_info[RTL8152_MAX_RX];
711 	struct list_head rx_done, tx_free;
712 	struct sk_buff_head tx_queue, rx_queue;
713 	spinlock_t rx_lock, tx_lock;
714 	struct delayed_work schedule, hw_phy_work;
715 	struct mii_if_info mii;
716 	struct mutex control;	/* use for hw setting */
717 #ifdef CONFIG_PM_SLEEP
718 	struct notifier_block pm_notifier;
719 #endif
720 
721 	struct rtl_ops {
722 		void (*init)(struct r8152 *);
723 		int (*enable)(struct r8152 *);
724 		void (*disable)(struct r8152 *);
725 		void (*up)(struct r8152 *);
726 		void (*down)(struct r8152 *);
727 		void (*unload)(struct r8152 *);
728 		int (*eee_get)(struct r8152 *, struct ethtool_eee *);
729 		int (*eee_set)(struct r8152 *, struct ethtool_eee *);
730 		bool (*in_nway)(struct r8152 *);
731 		void (*hw_phy_cfg)(struct r8152 *);
732 		void (*autosuspend_en)(struct r8152 *tp, bool enable);
733 	} rtl_ops;
734 
735 	int intr_interval;
736 	u32 saved_wolopts;
737 	u32 msg_enable;
738 	u32 tx_qlen;
739 	u32 coalesce;
740 	u16 ocp_base;
741 	u16 speed;
742 	u8 *intr_buff;
743 	u8 version;
744 	u8 duplex;
745 	u8 autoneg;
746 };
747 
748 enum rtl_version {
749 	RTL_VER_UNKNOWN = 0,
750 	RTL_VER_01,
751 	RTL_VER_02,
752 	RTL_VER_03,
753 	RTL_VER_04,
754 	RTL_VER_05,
755 	RTL_VER_06,
756 	RTL_VER_07,
757 	RTL_VER_08,
758 	RTL_VER_09,
759 	RTL_VER_MAX
760 };
761 
762 enum tx_csum_stat {
763 	TX_CSUM_SUCCESS = 0,
764 	TX_CSUM_TSO,
765 	TX_CSUM_NONE
766 };
767 
768 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
769  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
770  */
771 static const int multicast_filter_limit = 32;
772 static unsigned int agg_buf_sz = 16384;
773 
774 #define RTL_LIMITED_TSO_SIZE	(agg_buf_sz - sizeof(struct tx_desc) - \
775 				 VLAN_ETH_HLEN - ETH_FCS_LEN)
776 
777 static
get_registers(struct r8152 * tp,u16 value,u16 index,u16 size,void * data)778 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
779 {
780 	int ret;
781 	void *tmp;
782 
783 	tmp = kmalloc(size, GFP_KERNEL);
784 	if (!tmp)
785 		return -ENOMEM;
786 
787 	ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
788 			      RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
789 			      value, index, tmp, size, 500);
790 	if (ret < 0)
791 		memset(data, 0xff, size);
792 	else
793 		memcpy(data, tmp, size);
794 
795 	kfree(tmp);
796 
797 	return ret;
798 }
799 
800 static
set_registers(struct r8152 * tp,u16 value,u16 index,u16 size,void * data)801 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
802 {
803 	int ret;
804 	void *tmp;
805 
806 	tmp = kmemdup(data, size, GFP_KERNEL);
807 	if (!tmp)
808 		return -ENOMEM;
809 
810 	ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
811 			      RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
812 			      value, index, tmp, size, 500);
813 
814 	kfree(tmp);
815 
816 	return ret;
817 }
818 
generic_ocp_read(struct r8152 * tp,u16 index,u16 size,void * data,u16 type)819 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
820 			    void *data, u16 type)
821 {
822 	u16 limit = 64;
823 	int ret = 0;
824 
825 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
826 		return -ENODEV;
827 
828 	/* both size and indix must be 4 bytes align */
829 	if ((size & 3) || !size || (index & 3) || !data)
830 		return -EPERM;
831 
832 	if ((u32)index + (u32)size > 0xffff)
833 		return -EPERM;
834 
835 	while (size) {
836 		if (size > limit) {
837 			ret = get_registers(tp, index, type, limit, data);
838 			if (ret < 0)
839 				break;
840 
841 			index += limit;
842 			data += limit;
843 			size -= limit;
844 		} else {
845 			ret = get_registers(tp, index, type, size, data);
846 			if (ret < 0)
847 				break;
848 
849 			index += size;
850 			data += size;
851 			size = 0;
852 			break;
853 		}
854 	}
855 
856 	if (ret == -ENODEV)
857 		set_bit(RTL8152_UNPLUG, &tp->flags);
858 
859 	return ret;
860 }
861 
generic_ocp_write(struct r8152 * tp,u16 index,u16 byteen,u16 size,void * data,u16 type)862 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
863 			     u16 size, void *data, u16 type)
864 {
865 	int ret;
866 	u16 byteen_start, byteen_end, byen;
867 	u16 limit = 512;
868 
869 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
870 		return -ENODEV;
871 
872 	/* both size and indix must be 4 bytes align */
873 	if ((size & 3) || !size || (index & 3) || !data)
874 		return -EPERM;
875 
876 	if ((u32)index + (u32)size > 0xffff)
877 		return -EPERM;
878 
879 	byteen_start = byteen & BYTE_EN_START_MASK;
880 	byteen_end = byteen & BYTE_EN_END_MASK;
881 
882 	byen = byteen_start | (byteen_start << 4);
883 	ret = set_registers(tp, index, type | byen, 4, data);
884 	if (ret < 0)
885 		goto error1;
886 
887 	index += 4;
888 	data += 4;
889 	size -= 4;
890 
891 	if (size) {
892 		size -= 4;
893 
894 		while (size) {
895 			if (size > limit) {
896 				ret = set_registers(tp, index,
897 						    type | BYTE_EN_DWORD,
898 						    limit, data);
899 				if (ret < 0)
900 					goto error1;
901 
902 				index += limit;
903 				data += limit;
904 				size -= limit;
905 			} else {
906 				ret = set_registers(tp, index,
907 						    type | BYTE_EN_DWORD,
908 						    size, data);
909 				if (ret < 0)
910 					goto error1;
911 
912 				index += size;
913 				data += size;
914 				size = 0;
915 				break;
916 			}
917 		}
918 
919 		byen = byteen_end | (byteen_end >> 4);
920 		ret = set_registers(tp, index, type | byen, 4, data);
921 		if (ret < 0)
922 			goto error1;
923 	}
924 
925 error1:
926 	if (ret == -ENODEV)
927 		set_bit(RTL8152_UNPLUG, &tp->flags);
928 
929 	return ret;
930 }
931 
932 static inline
pla_ocp_read(struct r8152 * tp,u16 index,u16 size,void * data)933 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
934 {
935 	return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
936 }
937 
938 static inline
pla_ocp_write(struct r8152 * tp,u16 index,u16 byteen,u16 size,void * data)939 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
940 {
941 	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
942 }
943 
944 static inline
usb_ocp_write(struct r8152 * tp,u16 index,u16 byteen,u16 size,void * data)945 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
946 {
947 	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
948 }
949 
ocp_read_dword(struct r8152 * tp,u16 type,u16 index)950 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
951 {
952 	__le32 data;
953 
954 	generic_ocp_read(tp, index, sizeof(data), &data, type);
955 
956 	return __le32_to_cpu(data);
957 }
958 
ocp_write_dword(struct r8152 * tp,u16 type,u16 index,u32 data)959 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
960 {
961 	__le32 tmp = __cpu_to_le32(data);
962 
963 	generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
964 }
965 
ocp_read_word(struct r8152 * tp,u16 type,u16 index)966 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
967 {
968 	u32 data;
969 	__le32 tmp;
970 	u16 byen = BYTE_EN_WORD;
971 	u8 shift = index & 2;
972 
973 	index &= ~3;
974 	byen <<= shift;
975 
976 	generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
977 
978 	data = __le32_to_cpu(tmp);
979 	data >>= (shift * 8);
980 	data &= 0xffff;
981 
982 	return (u16)data;
983 }
984 
ocp_write_word(struct r8152 * tp,u16 type,u16 index,u32 data)985 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
986 {
987 	u32 mask = 0xffff;
988 	__le32 tmp;
989 	u16 byen = BYTE_EN_WORD;
990 	u8 shift = index & 2;
991 
992 	data &= mask;
993 
994 	if (index & 2) {
995 		byen <<= shift;
996 		mask <<= (shift * 8);
997 		data <<= (shift * 8);
998 		index &= ~3;
999 	}
1000 
1001 	tmp = __cpu_to_le32(data);
1002 
1003 	generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1004 }
1005 
ocp_read_byte(struct r8152 * tp,u16 type,u16 index)1006 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1007 {
1008 	u32 data;
1009 	__le32 tmp;
1010 	u8 shift = index & 3;
1011 
1012 	index &= ~3;
1013 
1014 	generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1015 
1016 	data = __le32_to_cpu(tmp);
1017 	data >>= (shift * 8);
1018 	data &= 0xff;
1019 
1020 	return (u8)data;
1021 }
1022 
ocp_write_byte(struct r8152 * tp,u16 type,u16 index,u32 data)1023 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1024 {
1025 	u32 mask = 0xff;
1026 	__le32 tmp;
1027 	u16 byen = BYTE_EN_BYTE;
1028 	u8 shift = index & 3;
1029 
1030 	data &= mask;
1031 
1032 	if (index & 3) {
1033 		byen <<= shift;
1034 		mask <<= (shift * 8);
1035 		data <<= (shift * 8);
1036 		index &= ~3;
1037 	}
1038 
1039 	tmp = __cpu_to_le32(data);
1040 
1041 	generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1042 }
1043 
ocp_reg_read(struct r8152 * tp,u16 addr)1044 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1045 {
1046 	u16 ocp_base, ocp_index;
1047 
1048 	ocp_base = addr & 0xf000;
1049 	if (ocp_base != tp->ocp_base) {
1050 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1051 		tp->ocp_base = ocp_base;
1052 	}
1053 
1054 	ocp_index = (addr & 0x0fff) | 0xb000;
1055 	return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1056 }
1057 
ocp_reg_write(struct r8152 * tp,u16 addr,u16 data)1058 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1059 {
1060 	u16 ocp_base, ocp_index;
1061 
1062 	ocp_base = addr & 0xf000;
1063 	if (ocp_base != tp->ocp_base) {
1064 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1065 		tp->ocp_base = ocp_base;
1066 	}
1067 
1068 	ocp_index = (addr & 0x0fff) | 0xb000;
1069 	ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1070 }
1071 
r8152_mdio_write(struct r8152 * tp,u32 reg_addr,u32 value)1072 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1073 {
1074 	ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1075 }
1076 
r8152_mdio_read(struct r8152 * tp,u32 reg_addr)1077 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1078 {
1079 	return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1080 }
1081 
sram_write(struct r8152 * tp,u16 addr,u16 data)1082 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1083 {
1084 	ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1085 	ocp_reg_write(tp, OCP_SRAM_DATA, data);
1086 }
1087 
sram_read(struct r8152 * tp,u16 addr)1088 static u16 sram_read(struct r8152 *tp, u16 addr)
1089 {
1090 	ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1091 	return ocp_reg_read(tp, OCP_SRAM_DATA);
1092 }
1093 
read_mii_word(struct net_device * netdev,int phy_id,int reg)1094 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1095 {
1096 	struct r8152 *tp = netdev_priv(netdev);
1097 	int ret;
1098 
1099 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1100 		return -ENODEV;
1101 
1102 	if (phy_id != R8152_PHY_ID)
1103 		return -EINVAL;
1104 
1105 	ret = r8152_mdio_read(tp, reg);
1106 
1107 	return ret;
1108 }
1109 
1110 static
write_mii_word(struct net_device * netdev,int phy_id,int reg,int val)1111 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1112 {
1113 	struct r8152 *tp = netdev_priv(netdev);
1114 
1115 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1116 		return;
1117 
1118 	if (phy_id != R8152_PHY_ID)
1119 		return;
1120 
1121 	r8152_mdio_write(tp, reg, val);
1122 }
1123 
1124 static int
1125 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1126 
rtl8152_set_mac_address(struct net_device * netdev,void * p)1127 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1128 {
1129 	struct r8152 *tp = netdev_priv(netdev);
1130 	struct sockaddr *addr = p;
1131 	int ret = -EADDRNOTAVAIL;
1132 
1133 	if (!is_valid_ether_addr(addr->sa_data))
1134 		goto out1;
1135 
1136 	ret = usb_autopm_get_interface(tp->intf);
1137 	if (ret < 0)
1138 		goto out1;
1139 
1140 	mutex_lock(&tp->control);
1141 
1142 	memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1143 
1144 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1145 	pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1146 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1147 
1148 	mutex_unlock(&tp->control);
1149 
1150 	usb_autopm_put_interface(tp->intf);
1151 out1:
1152 	return ret;
1153 }
1154 
1155 /* Devices containing RTL8153-AD can support a persistent
1156  * host system provided MAC address.
1157  * Examples of this are Dell TB15 and Dell WD15 docks
1158  */
vendor_mac_passthru_addr_read(struct r8152 * tp,struct sockaddr * sa)1159 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1160 {
1161 	acpi_status status;
1162 	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1163 	union acpi_object *obj;
1164 	int ret = -EINVAL;
1165 	u32 ocp_data;
1166 	unsigned char buf[6];
1167 
1168 	/* test for -AD variant of RTL8153 */
1169 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1170 	if ((ocp_data & AD_MASK) != 0x1000)
1171 		return -ENODEV;
1172 
1173 	/* test for MAC address pass-through bit */
1174 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1175 	if ((ocp_data & PASS_THRU_MASK) != 1)
1176 		return -ENODEV;
1177 
1178 	/* returns _AUXMAC_#AABBCCDDEEFF# */
1179 	status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1180 	obj = (union acpi_object *)buffer.pointer;
1181 	if (!ACPI_SUCCESS(status))
1182 		return -ENODEV;
1183 	if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1184 		netif_warn(tp, probe, tp->netdev,
1185 			   "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1186 			   obj->type, obj->string.length);
1187 		goto amacout;
1188 	}
1189 	if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1190 	    strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1191 		netif_warn(tp, probe, tp->netdev,
1192 			   "Invalid header when reading pass-thru MAC addr\n");
1193 		goto amacout;
1194 	}
1195 	ret = hex2bin(buf, obj->string.pointer + 9, 6);
1196 	if (!(ret == 0 && is_valid_ether_addr(buf))) {
1197 		netif_warn(tp, probe, tp->netdev,
1198 			   "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1199 			   ret, buf);
1200 		ret = -EINVAL;
1201 		goto amacout;
1202 	}
1203 	memcpy(sa->sa_data, buf, 6);
1204 	ether_addr_copy(tp->netdev->dev_addr, sa->sa_data);
1205 	netif_info(tp, probe, tp->netdev,
1206 		   "Using pass-thru MAC addr %pM\n", sa->sa_data);
1207 
1208 amacout:
1209 	kfree(obj);
1210 	return ret;
1211 }
1212 
set_ethernet_addr(struct r8152 * tp)1213 static int set_ethernet_addr(struct r8152 *tp)
1214 {
1215 	struct net_device *dev = tp->netdev;
1216 	struct sockaddr sa;
1217 	int ret;
1218 
1219 	if (tp->version == RTL_VER_01) {
1220 		ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1221 	} else {
1222 		/* if this is not an RTL8153-AD, no eFuse mac pass thru set,
1223 		 * or system doesn't provide valid _SB.AMAC this will be
1224 		 * be expected to non-zero
1225 		 */
1226 		ret = vendor_mac_passthru_addr_read(tp, &sa);
1227 		if (ret < 0)
1228 			ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1229 	}
1230 
1231 	if (ret < 0) {
1232 		netif_err(tp, probe, dev, "Get ether addr fail\n");
1233 	} else if (!is_valid_ether_addr(sa.sa_data)) {
1234 		netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1235 			  sa.sa_data);
1236 		eth_hw_addr_random(dev);
1237 		ether_addr_copy(sa.sa_data, dev->dev_addr);
1238 		ret = rtl8152_set_mac_address(dev, &sa);
1239 		netif_info(tp, probe, dev, "Random ether addr %pM\n",
1240 			   sa.sa_data);
1241 	} else {
1242 		if (tp->version == RTL_VER_01)
1243 			ether_addr_copy(dev->dev_addr, sa.sa_data);
1244 		else
1245 			ret = rtl8152_set_mac_address(dev, &sa);
1246 	}
1247 
1248 	return ret;
1249 }
1250 
read_bulk_callback(struct urb * urb)1251 static void read_bulk_callback(struct urb *urb)
1252 {
1253 	struct net_device *netdev;
1254 	int status = urb->status;
1255 	struct rx_agg *agg;
1256 	struct r8152 *tp;
1257 
1258 	agg = urb->context;
1259 	if (!agg)
1260 		return;
1261 
1262 	tp = agg->context;
1263 	if (!tp)
1264 		return;
1265 
1266 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1267 		return;
1268 
1269 	if (!test_bit(WORK_ENABLE, &tp->flags))
1270 		return;
1271 
1272 	netdev = tp->netdev;
1273 
1274 	/* When link down, the driver would cancel all bulks. */
1275 	/* This avoid the re-submitting bulk */
1276 	if (!netif_carrier_ok(netdev))
1277 		return;
1278 
1279 	usb_mark_last_busy(tp->udev);
1280 
1281 	switch (status) {
1282 	case 0:
1283 		if (urb->actual_length < ETH_ZLEN)
1284 			break;
1285 
1286 		spin_lock(&tp->rx_lock);
1287 		list_add_tail(&agg->list, &tp->rx_done);
1288 		spin_unlock(&tp->rx_lock);
1289 		napi_schedule(&tp->napi);
1290 		return;
1291 	case -ESHUTDOWN:
1292 		set_bit(RTL8152_UNPLUG, &tp->flags);
1293 		netif_device_detach(tp->netdev);
1294 		return;
1295 	case -ENOENT:
1296 		return;	/* the urb is in unlink state */
1297 	case -ETIME:
1298 		if (net_ratelimit())
1299 			netdev_warn(netdev, "maybe reset is needed?\n");
1300 		break;
1301 	default:
1302 		if (net_ratelimit())
1303 			netdev_warn(netdev, "Rx status %d\n", status);
1304 		break;
1305 	}
1306 
1307 	r8152_submit_rx(tp, agg, GFP_ATOMIC);
1308 }
1309 
write_bulk_callback(struct urb * urb)1310 static void write_bulk_callback(struct urb *urb)
1311 {
1312 	struct net_device_stats *stats;
1313 	struct net_device *netdev;
1314 	struct tx_agg *agg;
1315 	struct r8152 *tp;
1316 	int status = urb->status;
1317 
1318 	agg = urb->context;
1319 	if (!agg)
1320 		return;
1321 
1322 	tp = agg->context;
1323 	if (!tp)
1324 		return;
1325 
1326 	netdev = tp->netdev;
1327 	stats = &netdev->stats;
1328 	if (status) {
1329 		if (net_ratelimit())
1330 			netdev_warn(netdev, "Tx status %d\n", status);
1331 		stats->tx_errors += agg->skb_num;
1332 	} else {
1333 		stats->tx_packets += agg->skb_num;
1334 		stats->tx_bytes += agg->skb_len;
1335 	}
1336 
1337 	spin_lock(&tp->tx_lock);
1338 	list_add_tail(&agg->list, &tp->tx_free);
1339 	spin_unlock(&tp->tx_lock);
1340 
1341 	usb_autopm_put_interface_async(tp->intf);
1342 
1343 	if (!netif_carrier_ok(netdev))
1344 		return;
1345 
1346 	if (!test_bit(WORK_ENABLE, &tp->flags))
1347 		return;
1348 
1349 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1350 		return;
1351 
1352 	if (!skb_queue_empty(&tp->tx_queue))
1353 		napi_schedule(&tp->napi);
1354 }
1355 
intr_callback(struct urb * urb)1356 static void intr_callback(struct urb *urb)
1357 {
1358 	struct r8152 *tp;
1359 	__le16 *d;
1360 	int status = urb->status;
1361 	int res;
1362 
1363 	tp = urb->context;
1364 	if (!tp)
1365 		return;
1366 
1367 	if (!test_bit(WORK_ENABLE, &tp->flags))
1368 		return;
1369 
1370 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1371 		return;
1372 
1373 	switch (status) {
1374 	case 0:			/* success */
1375 		break;
1376 	case -ECONNRESET:	/* unlink */
1377 	case -ESHUTDOWN:
1378 		netif_device_detach(tp->netdev);
1379 	case -ENOENT:
1380 	case -EPROTO:
1381 		netif_info(tp, intr, tp->netdev,
1382 			   "Stop submitting intr, status %d\n", status);
1383 		return;
1384 	case -EOVERFLOW:
1385 		netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1386 		goto resubmit;
1387 	/* -EPIPE:  should clear the halt */
1388 	default:
1389 		netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1390 		goto resubmit;
1391 	}
1392 
1393 	d = urb->transfer_buffer;
1394 	if (INTR_LINK & __le16_to_cpu(d[0])) {
1395 		if (!netif_carrier_ok(tp->netdev)) {
1396 			set_bit(RTL8152_LINK_CHG, &tp->flags);
1397 			schedule_delayed_work(&tp->schedule, 0);
1398 		}
1399 	} else {
1400 		if (netif_carrier_ok(tp->netdev)) {
1401 			netif_stop_queue(tp->netdev);
1402 			set_bit(RTL8152_LINK_CHG, &tp->flags);
1403 			schedule_delayed_work(&tp->schedule, 0);
1404 		}
1405 	}
1406 
1407 resubmit:
1408 	res = usb_submit_urb(urb, GFP_ATOMIC);
1409 	if (res == -ENODEV) {
1410 		set_bit(RTL8152_UNPLUG, &tp->flags);
1411 		netif_device_detach(tp->netdev);
1412 	} else if (res) {
1413 		netif_err(tp, intr, tp->netdev,
1414 			  "can't resubmit intr, status %d\n", res);
1415 	}
1416 }
1417 
rx_agg_align(void * data)1418 static inline void *rx_agg_align(void *data)
1419 {
1420 	return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1421 }
1422 
tx_agg_align(void * data)1423 static inline void *tx_agg_align(void *data)
1424 {
1425 	return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1426 }
1427 
free_all_mem(struct r8152 * tp)1428 static void free_all_mem(struct r8152 *tp)
1429 {
1430 	int i;
1431 
1432 	for (i = 0; i < RTL8152_MAX_RX; i++) {
1433 		usb_free_urb(tp->rx_info[i].urb);
1434 		tp->rx_info[i].urb = NULL;
1435 
1436 		kfree(tp->rx_info[i].buffer);
1437 		tp->rx_info[i].buffer = NULL;
1438 		tp->rx_info[i].head = NULL;
1439 	}
1440 
1441 	for (i = 0; i < RTL8152_MAX_TX; i++) {
1442 		usb_free_urb(tp->tx_info[i].urb);
1443 		tp->tx_info[i].urb = NULL;
1444 
1445 		kfree(tp->tx_info[i].buffer);
1446 		tp->tx_info[i].buffer = NULL;
1447 		tp->tx_info[i].head = NULL;
1448 	}
1449 
1450 	usb_free_urb(tp->intr_urb);
1451 	tp->intr_urb = NULL;
1452 
1453 	kfree(tp->intr_buff);
1454 	tp->intr_buff = NULL;
1455 }
1456 
alloc_all_mem(struct r8152 * tp)1457 static int alloc_all_mem(struct r8152 *tp)
1458 {
1459 	struct net_device *netdev = tp->netdev;
1460 	struct usb_interface *intf = tp->intf;
1461 	struct usb_host_interface *alt = intf->cur_altsetting;
1462 	struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1463 	struct urb *urb;
1464 	int node, i;
1465 	u8 *buf;
1466 
1467 	node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1468 
1469 	spin_lock_init(&tp->rx_lock);
1470 	spin_lock_init(&tp->tx_lock);
1471 	INIT_LIST_HEAD(&tp->tx_free);
1472 	INIT_LIST_HEAD(&tp->rx_done);
1473 	skb_queue_head_init(&tp->tx_queue);
1474 	skb_queue_head_init(&tp->rx_queue);
1475 
1476 	for (i = 0; i < RTL8152_MAX_RX; i++) {
1477 		buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1478 		if (!buf)
1479 			goto err1;
1480 
1481 		if (buf != rx_agg_align(buf)) {
1482 			kfree(buf);
1483 			buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1484 					   node);
1485 			if (!buf)
1486 				goto err1;
1487 		}
1488 
1489 		urb = usb_alloc_urb(0, GFP_KERNEL);
1490 		if (!urb) {
1491 			kfree(buf);
1492 			goto err1;
1493 		}
1494 
1495 		INIT_LIST_HEAD(&tp->rx_info[i].list);
1496 		tp->rx_info[i].context = tp;
1497 		tp->rx_info[i].urb = urb;
1498 		tp->rx_info[i].buffer = buf;
1499 		tp->rx_info[i].head = rx_agg_align(buf);
1500 	}
1501 
1502 	for (i = 0; i < RTL8152_MAX_TX; i++) {
1503 		buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1504 		if (!buf)
1505 			goto err1;
1506 
1507 		if (buf != tx_agg_align(buf)) {
1508 			kfree(buf);
1509 			buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1510 					   node);
1511 			if (!buf)
1512 				goto err1;
1513 		}
1514 
1515 		urb = usb_alloc_urb(0, GFP_KERNEL);
1516 		if (!urb) {
1517 			kfree(buf);
1518 			goto err1;
1519 		}
1520 
1521 		INIT_LIST_HEAD(&tp->tx_info[i].list);
1522 		tp->tx_info[i].context = tp;
1523 		tp->tx_info[i].urb = urb;
1524 		tp->tx_info[i].buffer = buf;
1525 		tp->tx_info[i].head = tx_agg_align(buf);
1526 
1527 		list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1528 	}
1529 
1530 	tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1531 	if (!tp->intr_urb)
1532 		goto err1;
1533 
1534 	tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1535 	if (!tp->intr_buff)
1536 		goto err1;
1537 
1538 	tp->intr_interval = (int)ep_intr->desc.bInterval;
1539 	usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1540 			 tp->intr_buff, INTBUFSIZE, intr_callback,
1541 			 tp, tp->intr_interval);
1542 
1543 	return 0;
1544 
1545 err1:
1546 	free_all_mem(tp);
1547 	return -ENOMEM;
1548 }
1549 
r8152_get_tx_agg(struct r8152 * tp)1550 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1551 {
1552 	struct tx_agg *agg = NULL;
1553 	unsigned long flags;
1554 
1555 	if (list_empty(&tp->tx_free))
1556 		return NULL;
1557 
1558 	spin_lock_irqsave(&tp->tx_lock, flags);
1559 	if (!list_empty(&tp->tx_free)) {
1560 		struct list_head *cursor;
1561 
1562 		cursor = tp->tx_free.next;
1563 		list_del_init(cursor);
1564 		agg = list_entry(cursor, struct tx_agg, list);
1565 	}
1566 	spin_unlock_irqrestore(&tp->tx_lock, flags);
1567 
1568 	return agg;
1569 }
1570 
1571 /* r8152_csum_workaround()
1572  * The hw limites the value the transport offset. When the offset is out of the
1573  * range, calculate the checksum by sw.
1574  */
r8152_csum_workaround(struct r8152 * tp,struct sk_buff * skb,struct sk_buff_head * list)1575 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1576 				  struct sk_buff_head *list)
1577 {
1578 	if (skb_shinfo(skb)->gso_size) {
1579 		netdev_features_t features = tp->netdev->features;
1580 		struct sk_buff_head seg_list;
1581 		struct sk_buff *segs, *nskb;
1582 
1583 		features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1584 		segs = skb_gso_segment(skb, features);
1585 		if (IS_ERR(segs) || !segs)
1586 			goto drop;
1587 
1588 		__skb_queue_head_init(&seg_list);
1589 
1590 		do {
1591 			nskb = segs;
1592 			segs = segs->next;
1593 			nskb->next = NULL;
1594 			__skb_queue_tail(&seg_list, nskb);
1595 		} while (segs);
1596 
1597 		skb_queue_splice(&seg_list, list);
1598 		dev_kfree_skb(skb);
1599 	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1600 		if (skb_checksum_help(skb) < 0)
1601 			goto drop;
1602 
1603 		__skb_queue_head(list, skb);
1604 	} else {
1605 		struct net_device_stats *stats;
1606 
1607 drop:
1608 		stats = &tp->netdev->stats;
1609 		stats->tx_dropped++;
1610 		dev_kfree_skb(skb);
1611 	}
1612 }
1613 
1614 /* msdn_giant_send_check()
1615  * According to the document of microsoft, the TCP Pseudo Header excludes the
1616  * packet length for IPv6 TCP large packets.
1617  */
msdn_giant_send_check(struct sk_buff * skb)1618 static int msdn_giant_send_check(struct sk_buff *skb)
1619 {
1620 	const struct ipv6hdr *ipv6h;
1621 	struct tcphdr *th;
1622 	int ret;
1623 
1624 	ret = skb_cow_head(skb, 0);
1625 	if (ret)
1626 		return ret;
1627 
1628 	ipv6h = ipv6_hdr(skb);
1629 	th = tcp_hdr(skb);
1630 
1631 	th->check = 0;
1632 	th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1633 
1634 	return ret;
1635 }
1636 
rtl_tx_vlan_tag(struct tx_desc * desc,struct sk_buff * skb)1637 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1638 {
1639 	if (skb_vlan_tag_present(skb)) {
1640 		u32 opts2;
1641 
1642 		opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1643 		desc->opts2 |= cpu_to_le32(opts2);
1644 	}
1645 }
1646 
rtl_rx_vlan_tag(struct rx_desc * desc,struct sk_buff * skb)1647 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1648 {
1649 	u32 opts2 = le32_to_cpu(desc->opts2);
1650 
1651 	if (opts2 & RX_VLAN_TAG)
1652 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1653 				       swab16(opts2 & 0xffff));
1654 }
1655 
r8152_tx_csum(struct r8152 * tp,struct tx_desc * desc,struct sk_buff * skb,u32 len,u32 transport_offset)1656 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1657 			 struct sk_buff *skb, u32 len, u32 transport_offset)
1658 {
1659 	u32 mss = skb_shinfo(skb)->gso_size;
1660 	u32 opts1, opts2 = 0;
1661 	int ret = TX_CSUM_SUCCESS;
1662 
1663 	WARN_ON_ONCE(len > TX_LEN_MAX);
1664 
1665 	opts1 = len | TX_FS | TX_LS;
1666 
1667 	if (mss) {
1668 		if (transport_offset > GTTCPHO_MAX) {
1669 			netif_warn(tp, tx_err, tp->netdev,
1670 				   "Invalid transport offset 0x%x for TSO\n",
1671 				   transport_offset);
1672 			ret = TX_CSUM_TSO;
1673 			goto unavailable;
1674 		}
1675 
1676 		switch (vlan_get_protocol(skb)) {
1677 		case htons(ETH_P_IP):
1678 			opts1 |= GTSENDV4;
1679 			break;
1680 
1681 		case htons(ETH_P_IPV6):
1682 			if (msdn_giant_send_check(skb)) {
1683 				ret = TX_CSUM_TSO;
1684 				goto unavailable;
1685 			}
1686 			opts1 |= GTSENDV6;
1687 			break;
1688 
1689 		default:
1690 			WARN_ON_ONCE(1);
1691 			break;
1692 		}
1693 
1694 		opts1 |= transport_offset << GTTCPHO_SHIFT;
1695 		opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1696 	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1697 		u8 ip_protocol;
1698 
1699 		if (transport_offset > TCPHO_MAX) {
1700 			netif_warn(tp, tx_err, tp->netdev,
1701 				   "Invalid transport offset 0x%x\n",
1702 				   transport_offset);
1703 			ret = TX_CSUM_NONE;
1704 			goto unavailable;
1705 		}
1706 
1707 		switch (vlan_get_protocol(skb)) {
1708 		case htons(ETH_P_IP):
1709 			opts2 |= IPV4_CS;
1710 			ip_protocol = ip_hdr(skb)->protocol;
1711 			break;
1712 
1713 		case htons(ETH_P_IPV6):
1714 			opts2 |= IPV6_CS;
1715 			ip_protocol = ipv6_hdr(skb)->nexthdr;
1716 			break;
1717 
1718 		default:
1719 			ip_protocol = IPPROTO_RAW;
1720 			break;
1721 		}
1722 
1723 		if (ip_protocol == IPPROTO_TCP)
1724 			opts2 |= TCP_CS;
1725 		else if (ip_protocol == IPPROTO_UDP)
1726 			opts2 |= UDP_CS;
1727 		else
1728 			WARN_ON_ONCE(1);
1729 
1730 		opts2 |= transport_offset << TCPHO_SHIFT;
1731 	}
1732 
1733 	desc->opts2 = cpu_to_le32(opts2);
1734 	desc->opts1 = cpu_to_le32(opts1);
1735 
1736 unavailable:
1737 	return ret;
1738 }
1739 
r8152_tx_agg_fill(struct r8152 * tp,struct tx_agg * agg)1740 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1741 {
1742 	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1743 	int remain, ret;
1744 	u8 *tx_data;
1745 
1746 	__skb_queue_head_init(&skb_head);
1747 	spin_lock(&tx_queue->lock);
1748 	skb_queue_splice_init(tx_queue, &skb_head);
1749 	spin_unlock(&tx_queue->lock);
1750 
1751 	tx_data = agg->head;
1752 	agg->skb_num = 0;
1753 	agg->skb_len = 0;
1754 	remain = agg_buf_sz;
1755 
1756 	while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1757 		struct tx_desc *tx_desc;
1758 		struct sk_buff *skb;
1759 		unsigned int len;
1760 		u32 offset;
1761 
1762 		skb = __skb_dequeue(&skb_head);
1763 		if (!skb)
1764 			break;
1765 
1766 		len = skb->len + sizeof(*tx_desc);
1767 
1768 		if (len > remain) {
1769 			__skb_queue_head(&skb_head, skb);
1770 			break;
1771 		}
1772 
1773 		tx_data = tx_agg_align(tx_data);
1774 		tx_desc = (struct tx_desc *)tx_data;
1775 
1776 		offset = (u32)skb_transport_offset(skb);
1777 
1778 		if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1779 			r8152_csum_workaround(tp, skb, &skb_head);
1780 			continue;
1781 		}
1782 
1783 		rtl_tx_vlan_tag(tx_desc, skb);
1784 
1785 		tx_data += sizeof(*tx_desc);
1786 
1787 		len = skb->len;
1788 		if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1789 			struct net_device_stats *stats = &tp->netdev->stats;
1790 
1791 			stats->tx_dropped++;
1792 			dev_kfree_skb_any(skb);
1793 			tx_data -= sizeof(*tx_desc);
1794 			continue;
1795 		}
1796 
1797 		tx_data += len;
1798 		agg->skb_len += len;
1799 		agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
1800 
1801 		dev_kfree_skb_any(skb);
1802 
1803 		remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1804 	}
1805 
1806 	if (!skb_queue_empty(&skb_head)) {
1807 		spin_lock(&tx_queue->lock);
1808 		skb_queue_splice(&skb_head, tx_queue);
1809 		spin_unlock(&tx_queue->lock);
1810 	}
1811 
1812 	netif_tx_lock(tp->netdev);
1813 
1814 	if (netif_queue_stopped(tp->netdev) &&
1815 	    skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1816 		netif_wake_queue(tp->netdev);
1817 
1818 	netif_tx_unlock(tp->netdev);
1819 
1820 	ret = usb_autopm_get_interface_async(tp->intf);
1821 	if (ret < 0)
1822 		goto out_tx_fill;
1823 
1824 	usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1825 			  agg->head, (int)(tx_data - (u8 *)agg->head),
1826 			  (usb_complete_t)write_bulk_callback, agg);
1827 
1828 	ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1829 	if (ret < 0)
1830 		usb_autopm_put_interface_async(tp->intf);
1831 
1832 out_tx_fill:
1833 	return ret;
1834 }
1835 
r8152_rx_csum(struct r8152 * tp,struct rx_desc * rx_desc)1836 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1837 {
1838 	u8 checksum = CHECKSUM_NONE;
1839 	u32 opts2, opts3;
1840 
1841 	if (!(tp->netdev->features & NETIF_F_RXCSUM))
1842 		goto return_result;
1843 
1844 	opts2 = le32_to_cpu(rx_desc->opts2);
1845 	opts3 = le32_to_cpu(rx_desc->opts3);
1846 
1847 	if (opts2 & RD_IPV4_CS) {
1848 		if (opts3 & IPF)
1849 			checksum = CHECKSUM_NONE;
1850 		else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1851 			checksum = CHECKSUM_NONE;
1852 		else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1853 			checksum = CHECKSUM_NONE;
1854 		else
1855 			checksum = CHECKSUM_UNNECESSARY;
1856 	} else if (opts2 & RD_IPV6_CS) {
1857 		if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1858 			checksum = CHECKSUM_UNNECESSARY;
1859 		else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1860 			checksum = CHECKSUM_UNNECESSARY;
1861 	}
1862 
1863 return_result:
1864 	return checksum;
1865 }
1866 
rx_bottom(struct r8152 * tp,int budget)1867 static int rx_bottom(struct r8152 *tp, int budget)
1868 {
1869 	unsigned long flags;
1870 	struct list_head *cursor, *next, rx_queue;
1871 	int ret = 0, work_done = 0;
1872 	struct napi_struct *napi = &tp->napi;
1873 
1874 	if (!skb_queue_empty(&tp->rx_queue)) {
1875 		while (work_done < budget) {
1876 			struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1877 			struct net_device *netdev = tp->netdev;
1878 			struct net_device_stats *stats = &netdev->stats;
1879 			unsigned int pkt_len;
1880 
1881 			if (!skb)
1882 				break;
1883 
1884 			pkt_len = skb->len;
1885 			napi_gro_receive(napi, skb);
1886 			work_done++;
1887 			stats->rx_packets++;
1888 			stats->rx_bytes += pkt_len;
1889 		}
1890 	}
1891 
1892 	if (list_empty(&tp->rx_done))
1893 		goto out1;
1894 
1895 	INIT_LIST_HEAD(&rx_queue);
1896 	spin_lock_irqsave(&tp->rx_lock, flags);
1897 	list_splice_init(&tp->rx_done, &rx_queue);
1898 	spin_unlock_irqrestore(&tp->rx_lock, flags);
1899 
1900 	list_for_each_safe(cursor, next, &rx_queue) {
1901 		struct rx_desc *rx_desc;
1902 		struct rx_agg *agg;
1903 		int len_used = 0;
1904 		struct urb *urb;
1905 		u8 *rx_data;
1906 
1907 		list_del_init(cursor);
1908 
1909 		agg = list_entry(cursor, struct rx_agg, list);
1910 		urb = agg->urb;
1911 		if (urb->actual_length < ETH_ZLEN)
1912 			goto submit;
1913 
1914 		rx_desc = agg->head;
1915 		rx_data = agg->head;
1916 		len_used += sizeof(struct rx_desc);
1917 
1918 		while (urb->actual_length > len_used) {
1919 			struct net_device *netdev = tp->netdev;
1920 			struct net_device_stats *stats = &netdev->stats;
1921 			unsigned int pkt_len;
1922 			struct sk_buff *skb;
1923 
1924 			/* limite the skb numbers for rx_queue */
1925 			if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
1926 				break;
1927 
1928 			pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1929 			if (pkt_len < ETH_ZLEN)
1930 				break;
1931 
1932 			len_used += pkt_len;
1933 			if (urb->actual_length < len_used)
1934 				break;
1935 
1936 			pkt_len -= ETH_FCS_LEN;
1937 			rx_data += sizeof(struct rx_desc);
1938 
1939 			skb = napi_alloc_skb(napi, pkt_len);
1940 			if (!skb) {
1941 				stats->rx_dropped++;
1942 				goto find_next_rx;
1943 			}
1944 
1945 			skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1946 			memcpy(skb->data, rx_data, pkt_len);
1947 			skb_put(skb, pkt_len);
1948 			skb->protocol = eth_type_trans(skb, netdev);
1949 			rtl_rx_vlan_tag(rx_desc, skb);
1950 			if (work_done < budget) {
1951 				napi_gro_receive(napi, skb);
1952 				work_done++;
1953 				stats->rx_packets++;
1954 				stats->rx_bytes += pkt_len;
1955 			} else {
1956 				__skb_queue_tail(&tp->rx_queue, skb);
1957 			}
1958 
1959 find_next_rx:
1960 			rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
1961 			rx_desc = (struct rx_desc *)rx_data;
1962 			len_used = (int)(rx_data - (u8 *)agg->head);
1963 			len_used += sizeof(struct rx_desc);
1964 		}
1965 
1966 submit:
1967 		if (!ret) {
1968 			ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1969 		} else {
1970 			urb->actual_length = 0;
1971 			list_add_tail(&agg->list, next);
1972 		}
1973 	}
1974 
1975 	if (!list_empty(&rx_queue)) {
1976 		spin_lock_irqsave(&tp->rx_lock, flags);
1977 		list_splice_tail(&rx_queue, &tp->rx_done);
1978 		spin_unlock_irqrestore(&tp->rx_lock, flags);
1979 	}
1980 
1981 out1:
1982 	return work_done;
1983 }
1984 
tx_bottom(struct r8152 * tp)1985 static void tx_bottom(struct r8152 *tp)
1986 {
1987 	int res;
1988 
1989 	do {
1990 		struct tx_agg *agg;
1991 
1992 		if (skb_queue_empty(&tp->tx_queue))
1993 			break;
1994 
1995 		agg = r8152_get_tx_agg(tp);
1996 		if (!agg)
1997 			break;
1998 
1999 		res = r8152_tx_agg_fill(tp, agg);
2000 		if (res) {
2001 			struct net_device *netdev = tp->netdev;
2002 
2003 			if (res == -ENODEV) {
2004 				set_bit(RTL8152_UNPLUG, &tp->flags);
2005 				netif_device_detach(netdev);
2006 			} else {
2007 				struct net_device_stats *stats = &netdev->stats;
2008 				unsigned long flags;
2009 
2010 				netif_warn(tp, tx_err, netdev,
2011 					   "failed tx_urb %d\n", res);
2012 				stats->tx_dropped += agg->skb_num;
2013 
2014 				spin_lock_irqsave(&tp->tx_lock, flags);
2015 				list_add_tail(&agg->list, &tp->tx_free);
2016 				spin_unlock_irqrestore(&tp->tx_lock, flags);
2017 			}
2018 		}
2019 	} while (res == 0);
2020 }
2021 
bottom_half(struct r8152 * tp)2022 static void bottom_half(struct r8152 *tp)
2023 {
2024 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
2025 		return;
2026 
2027 	if (!test_bit(WORK_ENABLE, &tp->flags))
2028 		return;
2029 
2030 	/* When link down, the driver would cancel all bulks. */
2031 	/* This avoid the re-submitting bulk */
2032 	if (!netif_carrier_ok(tp->netdev))
2033 		return;
2034 
2035 	clear_bit(SCHEDULE_NAPI, &tp->flags);
2036 
2037 	tx_bottom(tp);
2038 }
2039 
r8152_poll(struct napi_struct * napi,int budget)2040 static int r8152_poll(struct napi_struct *napi, int budget)
2041 {
2042 	struct r8152 *tp = container_of(napi, struct r8152, napi);
2043 	int work_done;
2044 
2045 	work_done = rx_bottom(tp, budget);
2046 	bottom_half(tp);
2047 
2048 	if (work_done < budget) {
2049 		if (!napi_complete_done(napi, work_done))
2050 			goto out;
2051 		if (!list_empty(&tp->rx_done))
2052 			napi_schedule(napi);
2053 		else if (!skb_queue_empty(&tp->tx_queue) &&
2054 			 !list_empty(&tp->tx_free))
2055 			napi_schedule(napi);
2056 	}
2057 
2058 out:
2059 	return work_done;
2060 }
2061 
2062 static
r8152_submit_rx(struct r8152 * tp,struct rx_agg * agg,gfp_t mem_flags)2063 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2064 {
2065 	int ret;
2066 
2067 	/* The rx would be stopped, so skip submitting */
2068 	if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2069 	    !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2070 		return 0;
2071 
2072 	usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2073 			  agg->head, agg_buf_sz,
2074 			  (usb_complete_t)read_bulk_callback, agg);
2075 
2076 	ret = usb_submit_urb(agg->urb, mem_flags);
2077 	if (ret == -ENODEV) {
2078 		set_bit(RTL8152_UNPLUG, &tp->flags);
2079 		netif_device_detach(tp->netdev);
2080 	} else if (ret) {
2081 		struct urb *urb = agg->urb;
2082 		unsigned long flags;
2083 
2084 		urb->actual_length = 0;
2085 		spin_lock_irqsave(&tp->rx_lock, flags);
2086 		list_add_tail(&agg->list, &tp->rx_done);
2087 		spin_unlock_irqrestore(&tp->rx_lock, flags);
2088 
2089 		netif_err(tp, rx_err, tp->netdev,
2090 			  "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2091 
2092 		napi_schedule(&tp->napi);
2093 	}
2094 
2095 	return ret;
2096 }
2097 
rtl_drop_queued_tx(struct r8152 * tp)2098 static void rtl_drop_queued_tx(struct r8152 *tp)
2099 {
2100 	struct net_device_stats *stats = &tp->netdev->stats;
2101 	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2102 	struct sk_buff *skb;
2103 
2104 	if (skb_queue_empty(tx_queue))
2105 		return;
2106 
2107 	__skb_queue_head_init(&skb_head);
2108 	spin_lock_bh(&tx_queue->lock);
2109 	skb_queue_splice_init(tx_queue, &skb_head);
2110 	spin_unlock_bh(&tx_queue->lock);
2111 
2112 	while ((skb = __skb_dequeue(&skb_head))) {
2113 		dev_kfree_skb(skb);
2114 		stats->tx_dropped++;
2115 	}
2116 }
2117 
rtl8152_tx_timeout(struct net_device * netdev)2118 static void rtl8152_tx_timeout(struct net_device *netdev)
2119 {
2120 	struct r8152 *tp = netdev_priv(netdev);
2121 
2122 	netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2123 
2124 	usb_queue_reset_device(tp->intf);
2125 }
2126 
rtl8152_set_rx_mode(struct net_device * netdev)2127 static void rtl8152_set_rx_mode(struct net_device *netdev)
2128 {
2129 	struct r8152 *tp = netdev_priv(netdev);
2130 
2131 	if (netif_carrier_ok(netdev)) {
2132 		set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2133 		schedule_delayed_work(&tp->schedule, 0);
2134 	}
2135 }
2136 
_rtl8152_set_rx_mode(struct net_device * netdev)2137 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2138 {
2139 	struct r8152 *tp = netdev_priv(netdev);
2140 	u32 mc_filter[2];	/* Multicast hash filter */
2141 	__le32 tmp[2];
2142 	u32 ocp_data;
2143 
2144 	netif_stop_queue(netdev);
2145 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2146 	ocp_data &= ~RCR_ACPT_ALL;
2147 	ocp_data |= RCR_AB | RCR_APM;
2148 
2149 	if (netdev->flags & IFF_PROMISC) {
2150 		/* Unconditionally log net taps. */
2151 		netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2152 		ocp_data |= RCR_AM | RCR_AAP;
2153 		mc_filter[1] = 0xffffffff;
2154 		mc_filter[0] = 0xffffffff;
2155 	} else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2156 		   (netdev->flags & IFF_ALLMULTI)) {
2157 		/* Too many to filter perfectly -- accept all multicasts. */
2158 		ocp_data |= RCR_AM;
2159 		mc_filter[1] = 0xffffffff;
2160 		mc_filter[0] = 0xffffffff;
2161 	} else {
2162 		struct netdev_hw_addr *ha;
2163 
2164 		mc_filter[1] = 0;
2165 		mc_filter[0] = 0;
2166 		netdev_for_each_mc_addr(ha, netdev) {
2167 			int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2168 
2169 			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2170 			ocp_data |= RCR_AM;
2171 		}
2172 	}
2173 
2174 	tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2175 	tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2176 
2177 	pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2178 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2179 	netif_wake_queue(netdev);
2180 }
2181 
2182 static netdev_features_t
rtl8152_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)2183 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2184 		       netdev_features_t features)
2185 {
2186 	u32 mss = skb_shinfo(skb)->gso_size;
2187 	int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2188 	int offset = skb_transport_offset(skb);
2189 
2190 	if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2191 		features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2192 	else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2193 		features &= ~NETIF_F_GSO_MASK;
2194 
2195 	return features;
2196 }
2197 
rtl8152_start_xmit(struct sk_buff * skb,struct net_device * netdev)2198 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2199 				      struct net_device *netdev)
2200 {
2201 	struct r8152 *tp = netdev_priv(netdev);
2202 
2203 	skb_tx_timestamp(skb);
2204 
2205 	skb_queue_tail(&tp->tx_queue, skb);
2206 
2207 	if (!list_empty(&tp->tx_free)) {
2208 		if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2209 			set_bit(SCHEDULE_NAPI, &tp->flags);
2210 			schedule_delayed_work(&tp->schedule, 0);
2211 		} else {
2212 			usb_mark_last_busy(tp->udev);
2213 			napi_schedule(&tp->napi);
2214 		}
2215 	} else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2216 		netif_stop_queue(netdev);
2217 	}
2218 
2219 	return NETDEV_TX_OK;
2220 }
2221 
r8152b_reset_packet_filter(struct r8152 * tp)2222 static void r8152b_reset_packet_filter(struct r8152 *tp)
2223 {
2224 	u32	ocp_data;
2225 
2226 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2227 	ocp_data &= ~FMC_FCR_MCU_EN;
2228 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2229 	ocp_data |= FMC_FCR_MCU_EN;
2230 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2231 }
2232 
rtl8152_nic_reset(struct r8152 * tp)2233 static void rtl8152_nic_reset(struct r8152 *tp)
2234 {
2235 	int	i;
2236 
2237 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2238 
2239 	for (i = 0; i < 1000; i++) {
2240 		if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2241 			break;
2242 		usleep_range(100, 400);
2243 	}
2244 }
2245 
set_tx_qlen(struct r8152 * tp)2246 static void set_tx_qlen(struct r8152 *tp)
2247 {
2248 	struct net_device *netdev = tp->netdev;
2249 
2250 	tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2251 				    sizeof(struct tx_desc));
2252 }
2253 
rtl8152_get_speed(struct r8152 * tp)2254 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2255 {
2256 	return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2257 }
2258 
rtl_set_eee_plus(struct r8152 * tp)2259 static void rtl_set_eee_plus(struct r8152 *tp)
2260 {
2261 	u32 ocp_data;
2262 	u8 speed;
2263 
2264 	speed = rtl8152_get_speed(tp);
2265 	if (speed & _10bps) {
2266 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2267 		ocp_data |= EEEP_CR_EEEP_TX;
2268 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2269 	} else {
2270 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2271 		ocp_data &= ~EEEP_CR_EEEP_TX;
2272 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2273 	}
2274 }
2275 
rxdy_gated_en(struct r8152 * tp,bool enable)2276 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2277 {
2278 	u32 ocp_data;
2279 
2280 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2281 	if (enable)
2282 		ocp_data |= RXDY_GATED_EN;
2283 	else
2284 		ocp_data &= ~RXDY_GATED_EN;
2285 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2286 }
2287 
rtl_start_rx(struct r8152 * tp)2288 static int rtl_start_rx(struct r8152 *tp)
2289 {
2290 	int i, ret = 0;
2291 
2292 	INIT_LIST_HEAD(&tp->rx_done);
2293 	for (i = 0; i < RTL8152_MAX_RX; i++) {
2294 		INIT_LIST_HEAD(&tp->rx_info[i].list);
2295 		ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2296 		if (ret)
2297 			break;
2298 	}
2299 
2300 	if (ret && ++i < RTL8152_MAX_RX) {
2301 		struct list_head rx_queue;
2302 		unsigned long flags;
2303 
2304 		INIT_LIST_HEAD(&rx_queue);
2305 
2306 		do {
2307 			struct rx_agg *agg = &tp->rx_info[i++];
2308 			struct urb *urb = agg->urb;
2309 
2310 			urb->actual_length = 0;
2311 			list_add_tail(&agg->list, &rx_queue);
2312 		} while (i < RTL8152_MAX_RX);
2313 
2314 		spin_lock_irqsave(&tp->rx_lock, flags);
2315 		list_splice_tail(&rx_queue, &tp->rx_done);
2316 		spin_unlock_irqrestore(&tp->rx_lock, flags);
2317 	}
2318 
2319 	return ret;
2320 }
2321 
rtl_stop_rx(struct r8152 * tp)2322 static int rtl_stop_rx(struct r8152 *tp)
2323 {
2324 	int i;
2325 
2326 	for (i = 0; i < RTL8152_MAX_RX; i++)
2327 		usb_kill_urb(tp->rx_info[i].urb);
2328 
2329 	while (!skb_queue_empty(&tp->rx_queue))
2330 		dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2331 
2332 	return 0;
2333 }
2334 
rtl_enable(struct r8152 * tp)2335 static int rtl_enable(struct r8152 *tp)
2336 {
2337 	u32 ocp_data;
2338 
2339 	r8152b_reset_packet_filter(tp);
2340 
2341 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2342 	ocp_data |= CR_RE | CR_TE;
2343 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2344 
2345 	rxdy_gated_en(tp, false);
2346 
2347 	return 0;
2348 }
2349 
rtl8152_enable(struct r8152 * tp)2350 static int rtl8152_enable(struct r8152 *tp)
2351 {
2352 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
2353 		return -ENODEV;
2354 
2355 	set_tx_qlen(tp);
2356 	rtl_set_eee_plus(tp);
2357 
2358 	return rtl_enable(tp);
2359 }
2360 
r8153b_rx_agg_chg_indicate(struct r8152 * tp)2361 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2362 {
2363 	ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2364 		       OWN_UPDATE | OWN_CLEAR);
2365 }
2366 
r8153_set_rx_early_timeout(struct r8152 * tp)2367 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2368 {
2369 	u32 ocp_data = tp->coalesce / 8;
2370 
2371 	switch (tp->version) {
2372 	case RTL_VER_03:
2373 	case RTL_VER_04:
2374 	case RTL_VER_05:
2375 	case RTL_VER_06:
2376 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2377 			       ocp_data);
2378 		break;
2379 
2380 	case RTL_VER_08:
2381 	case RTL_VER_09:
2382 		/* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2383 		 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2384 		 */
2385 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2386 			       128 / 8);
2387 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2388 			       ocp_data);
2389 		r8153b_rx_agg_chg_indicate(tp);
2390 		break;
2391 
2392 	default:
2393 		break;
2394 	}
2395 }
2396 
r8153_set_rx_early_size(struct r8152 * tp)2397 static void r8153_set_rx_early_size(struct r8152 *tp)
2398 {
2399 	u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu);
2400 
2401 	switch (tp->version) {
2402 	case RTL_VER_03:
2403 	case RTL_VER_04:
2404 	case RTL_VER_05:
2405 	case RTL_VER_06:
2406 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2407 			       ocp_data / 4);
2408 		break;
2409 	case RTL_VER_08:
2410 	case RTL_VER_09:
2411 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2412 			       ocp_data / 8);
2413 		r8153b_rx_agg_chg_indicate(tp);
2414 		break;
2415 	default:
2416 		WARN_ON_ONCE(1);
2417 		break;
2418 	}
2419 }
2420 
rtl8153_enable(struct r8152 * tp)2421 static int rtl8153_enable(struct r8152 *tp)
2422 {
2423 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
2424 		return -ENODEV;
2425 
2426 	set_tx_qlen(tp);
2427 	rtl_set_eee_plus(tp);
2428 	r8153_set_rx_early_timeout(tp);
2429 	r8153_set_rx_early_size(tp);
2430 
2431 	return rtl_enable(tp);
2432 }
2433 
rtl_disable(struct r8152 * tp)2434 static void rtl_disable(struct r8152 *tp)
2435 {
2436 	u32 ocp_data;
2437 	int i;
2438 
2439 	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2440 		rtl_drop_queued_tx(tp);
2441 		return;
2442 	}
2443 
2444 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2445 	ocp_data &= ~RCR_ACPT_ALL;
2446 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2447 
2448 	rtl_drop_queued_tx(tp);
2449 
2450 	for (i = 0; i < RTL8152_MAX_TX; i++)
2451 		usb_kill_urb(tp->tx_info[i].urb);
2452 
2453 	rxdy_gated_en(tp, true);
2454 
2455 	for (i = 0; i < 1000; i++) {
2456 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2457 		if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2458 			break;
2459 		usleep_range(1000, 2000);
2460 	}
2461 
2462 	for (i = 0; i < 1000; i++) {
2463 		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2464 			break;
2465 		usleep_range(1000, 2000);
2466 	}
2467 
2468 	rtl_stop_rx(tp);
2469 
2470 	rtl8152_nic_reset(tp);
2471 }
2472 
r8152_power_cut_en(struct r8152 * tp,bool enable)2473 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2474 {
2475 	u32 ocp_data;
2476 
2477 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2478 	if (enable)
2479 		ocp_data |= POWER_CUT;
2480 	else
2481 		ocp_data &= ~POWER_CUT;
2482 	ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2483 
2484 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2485 	ocp_data &= ~RESUME_INDICATE;
2486 	ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2487 }
2488 
rtl_rx_vlan_en(struct r8152 * tp,bool enable)2489 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2490 {
2491 	u32 ocp_data;
2492 
2493 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2494 	if (enable)
2495 		ocp_data |= CPCR_RX_VLAN;
2496 	else
2497 		ocp_data &= ~CPCR_RX_VLAN;
2498 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2499 }
2500 
rtl8152_set_features(struct net_device * dev,netdev_features_t features)2501 static int rtl8152_set_features(struct net_device *dev,
2502 				netdev_features_t features)
2503 {
2504 	netdev_features_t changed = features ^ dev->features;
2505 	struct r8152 *tp = netdev_priv(dev);
2506 	int ret;
2507 
2508 	ret = usb_autopm_get_interface(tp->intf);
2509 	if (ret < 0)
2510 		goto out;
2511 
2512 	mutex_lock(&tp->control);
2513 
2514 	if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2515 		if (features & NETIF_F_HW_VLAN_CTAG_RX)
2516 			rtl_rx_vlan_en(tp, true);
2517 		else
2518 			rtl_rx_vlan_en(tp, false);
2519 	}
2520 
2521 	mutex_unlock(&tp->control);
2522 
2523 	usb_autopm_put_interface(tp->intf);
2524 
2525 out:
2526 	return ret;
2527 }
2528 
2529 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2530 
__rtl_get_wol(struct r8152 * tp)2531 static u32 __rtl_get_wol(struct r8152 *tp)
2532 {
2533 	u32 ocp_data;
2534 	u32 wolopts = 0;
2535 
2536 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2537 	if (ocp_data & LINK_ON_WAKE_EN)
2538 		wolopts |= WAKE_PHY;
2539 
2540 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2541 	if (ocp_data & UWF_EN)
2542 		wolopts |= WAKE_UCAST;
2543 	if (ocp_data & BWF_EN)
2544 		wolopts |= WAKE_BCAST;
2545 	if (ocp_data & MWF_EN)
2546 		wolopts |= WAKE_MCAST;
2547 
2548 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2549 	if (ocp_data & MAGIC_EN)
2550 		wolopts |= WAKE_MAGIC;
2551 
2552 	return wolopts;
2553 }
2554 
__rtl_set_wol(struct r8152 * tp,u32 wolopts)2555 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2556 {
2557 	u32 ocp_data;
2558 
2559 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2560 
2561 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2562 	ocp_data &= ~LINK_ON_WAKE_EN;
2563 	if (wolopts & WAKE_PHY)
2564 		ocp_data |= LINK_ON_WAKE_EN;
2565 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2566 
2567 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2568 	ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
2569 	if (wolopts & WAKE_UCAST)
2570 		ocp_data |= UWF_EN;
2571 	if (wolopts & WAKE_BCAST)
2572 		ocp_data |= BWF_EN;
2573 	if (wolopts & WAKE_MCAST)
2574 		ocp_data |= MWF_EN;
2575 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2576 
2577 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2578 
2579 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2580 	ocp_data &= ~MAGIC_EN;
2581 	if (wolopts & WAKE_MAGIC)
2582 		ocp_data |= MAGIC_EN;
2583 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2584 
2585 	if (wolopts & WAKE_ANY)
2586 		device_set_wakeup_enable(&tp->udev->dev, true);
2587 	else
2588 		device_set_wakeup_enable(&tp->udev->dev, false);
2589 }
2590 
r8153_mac_clk_spd(struct r8152 * tp,bool enable)2591 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable)
2592 {
2593 	/* MAC clock speed down */
2594 	if (enable) {
2595 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
2596 			       ALDPS_SPDWN_RATIO);
2597 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
2598 			       EEE_SPDWN_RATIO);
2599 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
2600 			       PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
2601 			       U1U2_SPDWN_EN | L1_SPDWN_EN);
2602 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
2603 			       PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
2604 			       TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN |
2605 			       TP1000_SPDWN_EN);
2606 	} else {
2607 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
2608 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
2609 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
2610 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
2611 	}
2612 }
2613 
r8153_u1u2en(struct r8152 * tp,bool enable)2614 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2615 {
2616 	u8 u1u2[8];
2617 
2618 	if (enable)
2619 		memset(u1u2, 0xff, sizeof(u1u2));
2620 	else
2621 		memset(u1u2, 0x00, sizeof(u1u2));
2622 
2623 	usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2624 }
2625 
r8153b_u1u2en(struct r8152 * tp,bool enable)2626 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
2627 {
2628 	u32 ocp_data;
2629 
2630 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
2631 	if (enable)
2632 		ocp_data |= LPM_U1U2_EN;
2633 	else
2634 		ocp_data &= ~LPM_U1U2_EN;
2635 
2636 	ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
2637 }
2638 
r8153_u2p3en(struct r8152 * tp,bool enable)2639 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2640 {
2641 	u32 ocp_data;
2642 
2643 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2644 	if (enable)
2645 		ocp_data |= U2P3_ENABLE;
2646 	else
2647 		ocp_data &= ~U2P3_ENABLE;
2648 	ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2649 }
2650 
r8153b_ups_flags_w1w0(struct r8152 * tp,u32 set,u32 clear)2651 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear)
2652 {
2653 	u32 ocp_data;
2654 
2655 	ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS);
2656 	ocp_data &= ~clear;
2657 	ocp_data |= set;
2658 	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data);
2659 }
2660 
r8153b_green_en(struct r8152 * tp,bool enable)2661 static void r8153b_green_en(struct r8152 *tp, bool enable)
2662 {
2663 	u16 data;
2664 
2665 	if (enable) {
2666 		sram_write(tp, 0x8045, 0);	/* 10M abiq&ldvbias */
2667 		sram_write(tp, 0x804d, 0x1222);	/* 100M short abiq&ldvbias */
2668 		sram_write(tp, 0x805d, 0x0022);	/* 1000M short abiq&ldvbias */
2669 	} else {
2670 		sram_write(tp, 0x8045, 0x2444);	/* 10M abiq&ldvbias */
2671 		sram_write(tp, 0x804d, 0x2444);	/* 100M short abiq&ldvbias */
2672 		sram_write(tp, 0x805d, 0x2444);	/* 1000M short abiq&ldvbias */
2673 	}
2674 
2675 	data = sram_read(tp, SRAM_GREEN_CFG);
2676 	data |= GREEN_ETH_EN;
2677 	sram_write(tp, SRAM_GREEN_CFG, data);
2678 
2679 	r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0);
2680 }
2681 
r8153_phy_status(struct r8152 * tp,u16 desired)2682 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
2683 {
2684 	u16 data;
2685 	int i;
2686 
2687 	for (i = 0; i < 500; i++) {
2688 		data = ocp_reg_read(tp, OCP_PHY_STATUS);
2689 		data &= PHY_STAT_MASK;
2690 		if (desired) {
2691 			if (data == desired)
2692 				break;
2693 		} else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
2694 			   data == PHY_STAT_EXT_INIT) {
2695 			break;
2696 		}
2697 
2698 		msleep(20);
2699 		if (test_bit(RTL8152_UNPLUG, &tp->flags))
2700 			break;
2701 	}
2702 
2703 	return data;
2704 }
2705 
r8153b_ups_en(struct r8152 * tp,bool enable)2706 static void r8153b_ups_en(struct r8152 *tp, bool enable)
2707 {
2708 	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
2709 
2710 	if (enable) {
2711 		ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
2712 		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2713 
2714 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2715 		ocp_data |= BIT(0);
2716 		ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2717 	} else {
2718 		u16 data;
2719 
2720 		ocp_data &= ~(UPS_EN | USP_PREWAKE);
2721 		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2722 
2723 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2724 		ocp_data &= ~BIT(0);
2725 		ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2726 
2727 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2728 		ocp_data &= ~PCUT_STATUS;
2729 		ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2730 
2731 		data = r8153_phy_status(tp, 0);
2732 
2733 		switch (data) {
2734 		case PHY_STAT_PWRDN:
2735 		case PHY_STAT_EXT_INIT:
2736 			r8153b_green_en(tp,
2737 					test_bit(GREEN_ETHERNET, &tp->flags));
2738 
2739 			data = r8152_mdio_read(tp, MII_BMCR);
2740 			data &= ~BMCR_PDOWN;
2741 			data |= BMCR_RESET;
2742 			r8152_mdio_write(tp, MII_BMCR, data);
2743 
2744 			data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
2745 
2746 		default:
2747 			if (data != PHY_STAT_LAN_ON)
2748 				netif_warn(tp, link, tp->netdev,
2749 					   "PHY not ready");
2750 			break;
2751 		}
2752 	}
2753 }
2754 
r8153_power_cut_en(struct r8152 * tp,bool enable)2755 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2756 {
2757 	u32 ocp_data;
2758 
2759 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2760 	if (enable)
2761 		ocp_data |= PWR_EN | PHASE2_EN;
2762 	else
2763 		ocp_data &= ~(PWR_EN | PHASE2_EN);
2764 	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2765 
2766 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2767 	ocp_data &= ~PCUT_STATUS;
2768 	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2769 }
2770 
r8153b_power_cut_en(struct r8152 * tp,bool enable)2771 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
2772 {
2773 	u32 ocp_data;
2774 
2775 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2776 	if (enable)
2777 		ocp_data |= PWR_EN | PHASE2_EN;
2778 	else
2779 		ocp_data &= ~PWR_EN;
2780 	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2781 
2782 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2783 	ocp_data &= ~PCUT_STATUS;
2784 	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2785 }
2786 
r8153b_queue_wake(struct r8152 * tp,bool enable)2787 static void r8153b_queue_wake(struct r8152 *tp, bool enable)
2788 {
2789 	u32 ocp_data;
2790 
2791 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38a);
2792 	if (enable)
2793 		ocp_data |= BIT(0);
2794 	else
2795 		ocp_data &= ~BIT(0);
2796 	ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38a, ocp_data);
2797 
2798 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38c);
2799 	ocp_data &= ~BIT(0);
2800 	ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38c, ocp_data);
2801 }
2802 
rtl_can_wakeup(struct r8152 * tp)2803 static bool rtl_can_wakeup(struct r8152 *tp)
2804 {
2805 	struct usb_device *udev = tp->udev;
2806 
2807 	return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2808 }
2809 
rtl_runtime_suspend_enable(struct r8152 * tp,bool enable)2810 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2811 {
2812 	if (enable) {
2813 		u32 ocp_data;
2814 
2815 		__rtl_set_wol(tp, WAKE_ANY);
2816 
2817 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2818 
2819 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2820 		ocp_data |= LINK_OFF_WAKE_EN;
2821 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2822 
2823 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2824 	} else {
2825 		u32 ocp_data;
2826 
2827 		__rtl_set_wol(tp, tp->saved_wolopts);
2828 
2829 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2830 
2831 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2832 		ocp_data &= ~LINK_OFF_WAKE_EN;
2833 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2834 
2835 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2836 	}
2837 }
2838 
rtl8153_runtime_enable(struct r8152 * tp,bool enable)2839 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
2840 {
2841 	if (enable) {
2842 		r8153_u1u2en(tp, false);
2843 		r8153_u2p3en(tp, false);
2844 		r8153_mac_clk_spd(tp, true);
2845 		rtl_runtime_suspend_enable(tp, true);
2846 	} else {
2847 		rtl_runtime_suspend_enable(tp, false);
2848 		r8153_mac_clk_spd(tp, false);
2849 
2850 		switch (tp->version) {
2851 		case RTL_VER_03:
2852 		case RTL_VER_04:
2853 			break;
2854 		case RTL_VER_05:
2855 		case RTL_VER_06:
2856 		default:
2857 			r8153_u2p3en(tp, true);
2858 			break;
2859 		}
2860 
2861 		r8153_u1u2en(tp, true);
2862 	}
2863 }
2864 
rtl8153b_runtime_enable(struct r8152 * tp,bool enable)2865 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
2866 {
2867 	if (enable) {
2868 		r8153b_queue_wake(tp, true);
2869 		r8153b_u1u2en(tp, false);
2870 		r8153_u2p3en(tp, false);
2871 		rtl_runtime_suspend_enable(tp, true);
2872 		r8153b_ups_en(tp, true);
2873 	} else {
2874 		r8153b_ups_en(tp, false);
2875 		r8153b_queue_wake(tp, false);
2876 		rtl_runtime_suspend_enable(tp, false);
2877 		r8153_u2p3en(tp, true);
2878 		r8153b_u1u2en(tp, true);
2879 	}
2880 }
2881 
r8153_teredo_off(struct r8152 * tp)2882 static void r8153_teredo_off(struct r8152 *tp)
2883 {
2884 	u32 ocp_data;
2885 
2886 	switch (tp->version) {
2887 	case RTL_VER_01:
2888 	case RTL_VER_02:
2889 	case RTL_VER_03:
2890 	case RTL_VER_04:
2891 	case RTL_VER_05:
2892 	case RTL_VER_06:
2893 	case RTL_VER_07:
2894 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2895 		ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
2896 			      OOB_TEREDO_EN);
2897 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2898 		break;
2899 
2900 	case RTL_VER_08:
2901 	case RTL_VER_09:
2902 		/* The bit 0 ~ 7 are relative with teredo settings. They are
2903 		 * W1C (write 1 to clear), so set all 1 to disable it.
2904 		 */
2905 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
2906 		break;
2907 
2908 	default:
2909 		break;
2910 	}
2911 
2912 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2913 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2914 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2915 }
2916 
rtl_reset_bmu(struct r8152 * tp)2917 static void rtl_reset_bmu(struct r8152 *tp)
2918 {
2919 	u32 ocp_data;
2920 
2921 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
2922 	ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
2923 	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2924 	ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
2925 	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2926 }
2927 
r8152_aldps_en(struct r8152 * tp,bool enable)2928 static void r8152_aldps_en(struct r8152 *tp, bool enable)
2929 {
2930 	if (enable) {
2931 		ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2932 						    LINKENA | DIS_SDSAVE);
2933 	} else {
2934 		ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
2935 						    DIS_SDSAVE);
2936 		msleep(20);
2937 	}
2938 }
2939 
r8152_mmd_indirect(struct r8152 * tp,u16 dev,u16 reg)2940 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2941 {
2942 	ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2943 	ocp_reg_write(tp, OCP_EEE_DATA, reg);
2944 	ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2945 }
2946 
r8152_mmd_read(struct r8152 * tp,u16 dev,u16 reg)2947 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2948 {
2949 	u16 data;
2950 
2951 	r8152_mmd_indirect(tp, dev, reg);
2952 	data = ocp_reg_read(tp, OCP_EEE_DATA);
2953 	ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2954 
2955 	return data;
2956 }
2957 
r8152_mmd_write(struct r8152 * tp,u16 dev,u16 reg,u16 data)2958 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
2959 {
2960 	r8152_mmd_indirect(tp, dev, reg);
2961 	ocp_reg_write(tp, OCP_EEE_DATA, data);
2962 	ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2963 }
2964 
r8152_eee_en(struct r8152 * tp,bool enable)2965 static void r8152_eee_en(struct r8152 *tp, bool enable)
2966 {
2967 	u16 config1, config2, config3;
2968 	u32 ocp_data;
2969 
2970 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2971 	config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
2972 	config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
2973 	config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
2974 
2975 	if (enable) {
2976 		ocp_data |= EEE_RX_EN | EEE_TX_EN;
2977 		config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
2978 		config1 |= sd_rise_time(1);
2979 		config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
2980 		config3 |= fast_snr(42);
2981 	} else {
2982 		ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2983 		config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
2984 			     RX_QUIET_EN);
2985 		config1 |= sd_rise_time(7);
2986 		config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
2987 		config3 |= fast_snr(511);
2988 	}
2989 
2990 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2991 	ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
2992 	ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
2993 	ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
2994 }
2995 
r8152b_enable_eee(struct r8152 * tp)2996 static void r8152b_enable_eee(struct r8152 *tp)
2997 {
2998 	r8152_eee_en(tp, true);
2999 	r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3000 }
3001 
r8152b_enable_fc(struct r8152 * tp)3002 static void r8152b_enable_fc(struct r8152 *tp)
3003 {
3004 	u16 anar;
3005 
3006 	anar = r8152_mdio_read(tp, MII_ADVERTISE);
3007 	anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3008 	r8152_mdio_write(tp, MII_ADVERTISE, anar);
3009 }
3010 
rtl8152_disable(struct r8152 * tp)3011 static void rtl8152_disable(struct r8152 *tp)
3012 {
3013 	r8152_aldps_en(tp, false);
3014 	rtl_disable(tp);
3015 	r8152_aldps_en(tp, true);
3016 }
3017 
r8152b_hw_phy_cfg(struct r8152 * tp)3018 static void r8152b_hw_phy_cfg(struct r8152 *tp)
3019 {
3020 	r8152b_enable_eee(tp);
3021 	r8152_aldps_en(tp, true);
3022 	r8152b_enable_fc(tp);
3023 
3024 	set_bit(PHY_RESET, &tp->flags);
3025 }
3026 
r8152b_exit_oob(struct r8152 * tp)3027 static void r8152b_exit_oob(struct r8152 *tp)
3028 {
3029 	u32 ocp_data;
3030 	int i;
3031 
3032 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3033 	ocp_data &= ~RCR_ACPT_ALL;
3034 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3035 
3036 	rxdy_gated_en(tp, true);
3037 	r8153_teredo_off(tp);
3038 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3039 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
3040 
3041 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3042 	ocp_data &= ~NOW_IS_OOB;
3043 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3044 
3045 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3046 	ocp_data &= ~MCU_BORW_EN;
3047 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3048 
3049 	for (i = 0; i < 1000; i++) {
3050 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3051 		if (ocp_data & LINK_LIST_READY)
3052 			break;
3053 		usleep_range(1000, 2000);
3054 	}
3055 
3056 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3057 	ocp_data |= RE_INIT_LL;
3058 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3059 
3060 	for (i = 0; i < 1000; i++) {
3061 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3062 		if (ocp_data & LINK_LIST_READY)
3063 			break;
3064 		usleep_range(1000, 2000);
3065 	}
3066 
3067 	rtl8152_nic_reset(tp);
3068 
3069 	/* rx share fifo credit full threshold */
3070 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3071 
3072 	if (tp->udev->speed == USB_SPEED_FULL ||
3073 	    tp->udev->speed == USB_SPEED_LOW) {
3074 		/* rx share fifo credit near full threshold */
3075 		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3076 				RXFIFO_THR2_FULL);
3077 		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3078 				RXFIFO_THR3_FULL);
3079 	} else {
3080 		/* rx share fifo credit near full threshold */
3081 		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3082 				RXFIFO_THR2_HIGH);
3083 		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3084 				RXFIFO_THR3_HIGH);
3085 	}
3086 
3087 	/* TX share fifo free credit full threshold */
3088 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
3089 
3090 	ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
3091 	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
3092 	ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
3093 			TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
3094 
3095 	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3096 
3097 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3098 
3099 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3100 	ocp_data |= TCR0_AUTO_FIFO;
3101 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3102 }
3103 
r8152b_enter_oob(struct r8152 * tp)3104 static void r8152b_enter_oob(struct r8152 *tp)
3105 {
3106 	u32 ocp_data;
3107 	int i;
3108 
3109 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3110 	ocp_data &= ~NOW_IS_OOB;
3111 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3112 
3113 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
3114 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
3115 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
3116 
3117 	rtl_disable(tp);
3118 
3119 	for (i = 0; i < 1000; i++) {
3120 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3121 		if (ocp_data & LINK_LIST_READY)
3122 			break;
3123 		usleep_range(1000, 2000);
3124 	}
3125 
3126 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3127 	ocp_data |= RE_INIT_LL;
3128 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3129 
3130 	for (i = 0; i < 1000; i++) {
3131 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3132 		if (ocp_data & LINK_LIST_READY)
3133 			break;
3134 		usleep_range(1000, 2000);
3135 	}
3136 
3137 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3138 
3139 	rtl_rx_vlan_en(tp, true);
3140 
3141 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3142 	ocp_data |= ALDPS_PROXY_MODE;
3143 	ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3144 
3145 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3146 	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3147 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3148 
3149 	rxdy_gated_en(tp, false);
3150 
3151 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3152 	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3153 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3154 }
3155 
r8153_patch_request(struct r8152 * tp,bool request)3156 static int r8153_patch_request(struct r8152 *tp, bool request)
3157 {
3158 	u16 data;
3159 	int i;
3160 
3161 	data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3162 	if (request)
3163 		data |= PATCH_REQUEST;
3164 	else
3165 		data &= ~PATCH_REQUEST;
3166 	ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3167 
3168 	for (i = 0; request && i < 5000; i++) {
3169 		usleep_range(1000, 2000);
3170 		if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3171 			break;
3172 	}
3173 
3174 	if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3175 		netif_err(tp, drv, tp->netdev, "patch request fail\n");
3176 		r8153_patch_request(tp, false);
3177 		return -ETIME;
3178 	} else {
3179 		return 0;
3180 	}
3181 }
3182 
r8153_aldps_en(struct r8152 * tp,bool enable)3183 static void r8153_aldps_en(struct r8152 *tp, bool enable)
3184 {
3185 	u16 data;
3186 
3187 	data = ocp_reg_read(tp, OCP_POWER_CFG);
3188 	if (enable) {
3189 		data |= EN_ALDPS;
3190 		ocp_reg_write(tp, OCP_POWER_CFG, data);
3191 	} else {
3192 		int i;
3193 
3194 		data &= ~EN_ALDPS;
3195 		ocp_reg_write(tp, OCP_POWER_CFG, data);
3196 		for (i = 0; i < 20; i++) {
3197 			usleep_range(1000, 2000);
3198 			if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
3199 				break;
3200 		}
3201 	}
3202 }
3203 
r8153b_aldps_en(struct r8152 * tp,bool enable)3204 static void r8153b_aldps_en(struct r8152 *tp, bool enable)
3205 {
3206 	r8153_aldps_en(tp, enable);
3207 
3208 	if (enable)
3209 		r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0);
3210 	else
3211 		r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS);
3212 }
3213 
r8153_eee_en(struct r8152 * tp,bool enable)3214 static void r8153_eee_en(struct r8152 *tp, bool enable)
3215 {
3216 	u32 ocp_data;
3217 	u16 config;
3218 
3219 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3220 	config = ocp_reg_read(tp, OCP_EEE_CFG);
3221 
3222 	if (enable) {
3223 		ocp_data |= EEE_RX_EN | EEE_TX_EN;
3224 		config |= EEE10_EN;
3225 	} else {
3226 		ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3227 		config &= ~EEE10_EN;
3228 	}
3229 
3230 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3231 	ocp_reg_write(tp, OCP_EEE_CFG, config);
3232 }
3233 
r8153b_eee_en(struct r8152 * tp,bool enable)3234 static void r8153b_eee_en(struct r8152 *tp, bool enable)
3235 {
3236 	r8153_eee_en(tp, enable);
3237 
3238 	if (enable)
3239 		r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0);
3240 	else
3241 		r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE);
3242 }
3243 
r8153b_enable_fc(struct r8152 * tp)3244 static void r8153b_enable_fc(struct r8152 *tp)
3245 {
3246 	r8152b_enable_fc(tp);
3247 	r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0);
3248 }
3249 
r8153_hw_phy_cfg(struct r8152 * tp)3250 static void r8153_hw_phy_cfg(struct r8152 *tp)
3251 {
3252 	u32 ocp_data;
3253 	u16 data;
3254 
3255 	/* disable ALDPS before updating the PHY parameters */
3256 	r8153_aldps_en(tp, false);
3257 
3258 	/* disable EEE before updating the PHY parameters */
3259 	r8153_eee_en(tp, false);
3260 	ocp_reg_write(tp, OCP_EEE_ADV, 0);
3261 
3262 	if (tp->version == RTL_VER_03) {
3263 		data = ocp_reg_read(tp, OCP_EEE_CFG);
3264 		data &= ~CTAP_SHORT_EN;
3265 		ocp_reg_write(tp, OCP_EEE_CFG, data);
3266 	}
3267 
3268 	data = ocp_reg_read(tp, OCP_POWER_CFG);
3269 	data |= EEE_CLKDIV_EN;
3270 	ocp_reg_write(tp, OCP_POWER_CFG, data);
3271 
3272 	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3273 	data |= EN_10M_BGOFF;
3274 	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3275 	data = ocp_reg_read(tp, OCP_POWER_CFG);
3276 	data |= EN_10M_PLLOFF;
3277 	ocp_reg_write(tp, OCP_POWER_CFG, data);
3278 	sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
3279 
3280 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3281 	ocp_data |= PFM_PWM_SWITCH;
3282 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3283 
3284 	/* Enable LPF corner auto tune */
3285 	sram_write(tp, SRAM_LPF_CFG, 0xf70f);
3286 
3287 	/* Adjust 10M Amplitude */
3288 	sram_write(tp, SRAM_10M_AMP1, 0x00af);
3289 	sram_write(tp, SRAM_10M_AMP2, 0x0208);
3290 
3291 	r8153_eee_en(tp, true);
3292 	ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3293 
3294 	r8153_aldps_en(tp, true);
3295 	r8152b_enable_fc(tp);
3296 
3297 	switch (tp->version) {
3298 	case RTL_VER_03:
3299 	case RTL_VER_04:
3300 		break;
3301 	case RTL_VER_05:
3302 	case RTL_VER_06:
3303 	default:
3304 		r8153_u2p3en(tp, true);
3305 		break;
3306 	}
3307 
3308 	set_bit(PHY_RESET, &tp->flags);
3309 }
3310 
r8152_efuse_read(struct r8152 * tp,u8 addr)3311 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
3312 {
3313 	u32 ocp_data;
3314 
3315 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
3316 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
3317 	ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9;	/* data of bit16 */
3318 	ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
3319 
3320 	return ocp_data;
3321 }
3322 
r8153b_hw_phy_cfg(struct r8152 * tp)3323 static void r8153b_hw_phy_cfg(struct r8152 *tp)
3324 {
3325 	u32 ocp_data, ups_flags = 0;
3326 	u16 data;
3327 
3328 	/* disable ALDPS before updating the PHY parameters */
3329 	r8153b_aldps_en(tp, false);
3330 
3331 	/* disable EEE before updating the PHY parameters */
3332 	r8153b_eee_en(tp, false);
3333 	ocp_reg_write(tp, OCP_EEE_ADV, 0);
3334 
3335 	r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
3336 
3337 	data = sram_read(tp, SRAM_GREEN_CFG);
3338 	data |= R_TUNE_EN;
3339 	sram_write(tp, SRAM_GREEN_CFG, data);
3340 	data = ocp_reg_read(tp, OCP_NCTL_CFG);
3341 	data |= PGA_RETURN_EN;
3342 	ocp_reg_write(tp, OCP_NCTL_CFG, data);
3343 
3344 	/* ADC Bias Calibration:
3345 	 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
3346 	 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
3347 	 * ADC ioffset.
3348 	 */
3349 	ocp_data = r8152_efuse_read(tp, 0x7d);
3350 	data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
3351 	if (data != 0xffff)
3352 		ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
3353 
3354 	/* ups mode tx-link-pulse timing adjustment:
3355 	 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
3356 	 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
3357 	 */
3358 	ocp_data = ocp_reg_read(tp, 0xc426);
3359 	ocp_data &= 0x3fff;
3360 	if (ocp_data) {
3361 		u32 swr_cnt_1ms_ini;
3362 
3363 		swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
3364 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
3365 		ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
3366 		ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
3367 	}
3368 
3369 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3370 	ocp_data |= PFM_PWM_SWITCH;
3371 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3372 
3373 	/* Advnace EEE */
3374 	if (!r8153_patch_request(tp, true)) {
3375 		data = ocp_reg_read(tp, OCP_POWER_CFG);
3376 		data |= EEE_CLKDIV_EN;
3377 		ocp_reg_write(tp, OCP_POWER_CFG, data);
3378 
3379 		data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3380 		data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
3381 		ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3382 
3383 		ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
3384 		ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
3385 
3386 		ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV |
3387 			     UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN |
3388 			     UPS_FLAGS_EEE_PLLOFF_GIGA;
3389 
3390 		r8153_patch_request(tp, false);
3391 	}
3392 
3393 	r8153b_ups_flags_w1w0(tp, ups_flags, 0);
3394 
3395 	r8153b_eee_en(tp, true);
3396 	ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3397 
3398 	r8153b_aldps_en(tp, true);
3399 	r8153b_enable_fc(tp);
3400 	r8153_u2p3en(tp, true);
3401 
3402 	set_bit(PHY_RESET, &tp->flags);
3403 }
3404 
r8153_first_init(struct r8152 * tp)3405 static void r8153_first_init(struct r8152 *tp)
3406 {
3407 	u32 ocp_data;
3408 	int i;
3409 
3410 	r8153_mac_clk_spd(tp, false);
3411 	rxdy_gated_en(tp, true);
3412 	r8153_teredo_off(tp);
3413 
3414 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3415 	ocp_data &= ~RCR_ACPT_ALL;
3416 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3417 
3418 	rtl8152_nic_reset(tp);
3419 	rtl_reset_bmu(tp);
3420 
3421 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3422 	ocp_data &= ~NOW_IS_OOB;
3423 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3424 
3425 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3426 	ocp_data &= ~MCU_BORW_EN;
3427 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3428 
3429 	for (i = 0; i < 1000; i++) {
3430 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3431 		if (ocp_data & LINK_LIST_READY)
3432 			break;
3433 		usleep_range(1000, 2000);
3434 	}
3435 
3436 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3437 	ocp_data |= RE_INIT_LL;
3438 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3439 
3440 	for (i = 0; i < 1000; i++) {
3441 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3442 		if (ocp_data & LINK_LIST_READY)
3443 			break;
3444 		usleep_range(1000, 2000);
3445 	}
3446 
3447 	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3448 
3449 	ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3450 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3451 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
3452 
3453 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3454 	ocp_data |= TCR0_AUTO_FIFO;
3455 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3456 
3457 	rtl8152_nic_reset(tp);
3458 
3459 	/* rx share fifo credit full threshold */
3460 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3461 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
3462 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
3463 	/* TX share fifo free credit full threshold */
3464 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
3465 }
3466 
r8153_enter_oob(struct r8152 * tp)3467 static void r8153_enter_oob(struct r8152 *tp)
3468 {
3469 	u32 ocp_data;
3470 	int i;
3471 
3472 	r8153_mac_clk_spd(tp, true);
3473 
3474 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3475 	ocp_data &= ~NOW_IS_OOB;
3476 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3477 
3478 	rtl_disable(tp);
3479 	rtl_reset_bmu(tp);
3480 
3481 	for (i = 0; i < 1000; i++) {
3482 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3483 		if (ocp_data & LINK_LIST_READY)
3484 			break;
3485 		usleep_range(1000, 2000);
3486 	}
3487 
3488 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3489 	ocp_data |= RE_INIT_LL;
3490 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3491 
3492 	for (i = 0; i < 1000; i++) {
3493 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3494 		if (ocp_data & LINK_LIST_READY)
3495 			break;
3496 		usleep_range(1000, 2000);
3497 	}
3498 
3499 	ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3500 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3501 
3502 	switch (tp->version) {
3503 	case RTL_VER_03:
3504 	case RTL_VER_04:
3505 	case RTL_VER_05:
3506 	case RTL_VER_06:
3507 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3508 		ocp_data &= ~TEREDO_WAKE_MASK;
3509 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3510 		break;
3511 
3512 	case RTL_VER_08:
3513 	case RTL_VER_09:
3514 		/* Clear teredo wake event. bit[15:8] is the teredo wakeup
3515 		 * type. Set it to zero. bits[7:0] are the W1C bits about
3516 		 * the events. Set them to all 1 to clear them.
3517 		 */
3518 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
3519 		break;
3520 
3521 	default:
3522 		break;
3523 	}
3524 
3525 	rtl_rx_vlan_en(tp, true);
3526 
3527 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3528 	ocp_data |= ALDPS_PROXY_MODE;
3529 	ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3530 
3531 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3532 	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3533 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3534 
3535 	rxdy_gated_en(tp, false);
3536 
3537 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3538 	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3539 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3540 }
3541 
rtl8153_disable(struct r8152 * tp)3542 static void rtl8153_disable(struct r8152 *tp)
3543 {
3544 	r8153_aldps_en(tp, false);
3545 	rtl_disable(tp);
3546 	rtl_reset_bmu(tp);
3547 	r8153_aldps_en(tp, true);
3548 }
3549 
rtl8153b_disable(struct r8152 * tp)3550 static void rtl8153b_disable(struct r8152 *tp)
3551 {
3552 	r8153b_aldps_en(tp, false);
3553 	rtl_disable(tp);
3554 	rtl_reset_bmu(tp);
3555 	r8153b_aldps_en(tp, true);
3556 }
3557 
rtl8152_set_speed(struct r8152 * tp,u8 autoneg,u16 speed,u8 duplex)3558 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
3559 {
3560 	u16 bmcr, anar, gbcr;
3561 	enum spd_duplex speed_duplex;
3562 	int ret = 0;
3563 
3564 	anar = r8152_mdio_read(tp, MII_ADVERTISE);
3565 	anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
3566 		  ADVERTISE_100HALF | ADVERTISE_100FULL);
3567 	if (tp->mii.supports_gmii) {
3568 		gbcr = r8152_mdio_read(tp, MII_CTRL1000);
3569 		gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3570 	} else {
3571 		gbcr = 0;
3572 	}
3573 
3574 	if (autoneg == AUTONEG_DISABLE) {
3575 		if (speed == SPEED_10) {
3576 			bmcr = 0;
3577 			anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3578 			speed_duplex = FORCE_10M_HALF;
3579 		} else if (speed == SPEED_100) {
3580 			bmcr = BMCR_SPEED100;
3581 			anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3582 			speed_duplex = FORCE_100M_HALF;
3583 		} else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3584 			bmcr = BMCR_SPEED1000;
3585 			gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3586 			speed_duplex = NWAY_1000M_FULL;
3587 		} else {
3588 			ret = -EINVAL;
3589 			goto out;
3590 		}
3591 
3592 		if (duplex == DUPLEX_FULL) {
3593 			bmcr |= BMCR_FULLDPLX;
3594 			if (speed != SPEED_1000)
3595 				speed_duplex++;
3596 		}
3597 	} else {
3598 		if (speed == SPEED_10) {
3599 			if (duplex == DUPLEX_FULL) {
3600 				anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3601 				speed_duplex = NWAY_10M_FULL;
3602 			} else {
3603 				anar |= ADVERTISE_10HALF;
3604 				speed_duplex = NWAY_10M_HALF;
3605 			}
3606 		} else if (speed == SPEED_100) {
3607 			if (duplex == DUPLEX_FULL) {
3608 				anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3609 				anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3610 				speed_duplex = NWAY_100M_FULL;
3611 			} else {
3612 				anar |= ADVERTISE_10HALF;
3613 				anar |= ADVERTISE_100HALF;
3614 				speed_duplex = NWAY_100M_HALF;
3615 			}
3616 		} else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3617 			if (duplex == DUPLEX_FULL) {
3618 				anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3619 				anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3620 				gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3621 			} else {
3622 				anar |= ADVERTISE_10HALF;
3623 				anar |= ADVERTISE_100HALF;
3624 				gbcr |= ADVERTISE_1000HALF;
3625 			}
3626 			speed_duplex = NWAY_1000M_FULL;
3627 		} else {
3628 			ret = -EINVAL;
3629 			goto out;
3630 		}
3631 
3632 		bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
3633 	}
3634 
3635 	if (test_and_clear_bit(PHY_RESET, &tp->flags))
3636 		bmcr |= BMCR_RESET;
3637 
3638 	if (tp->mii.supports_gmii)
3639 		r8152_mdio_write(tp, MII_CTRL1000, gbcr);
3640 
3641 	r8152_mdio_write(tp, MII_ADVERTISE, anar);
3642 	r8152_mdio_write(tp, MII_BMCR, bmcr);
3643 
3644 	switch (tp->version) {
3645 	case RTL_VER_08:
3646 	case RTL_VER_09:
3647 		r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex),
3648 				      UPS_FLAGS_SPEED_MASK);
3649 		break;
3650 
3651 	default:
3652 		break;
3653 	}
3654 
3655 	if (bmcr & BMCR_RESET) {
3656 		int i;
3657 
3658 		for (i = 0; i < 50; i++) {
3659 			msleep(20);
3660 			if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
3661 				break;
3662 		}
3663 	}
3664 
3665 out:
3666 	return ret;
3667 }
3668 
rtl8152_up(struct r8152 * tp)3669 static void rtl8152_up(struct r8152 *tp)
3670 {
3671 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
3672 		return;
3673 
3674 	r8152_aldps_en(tp, false);
3675 	r8152b_exit_oob(tp);
3676 	r8152_aldps_en(tp, true);
3677 }
3678 
rtl8152_down(struct r8152 * tp)3679 static void rtl8152_down(struct r8152 *tp)
3680 {
3681 	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3682 		rtl_drop_queued_tx(tp);
3683 		return;
3684 	}
3685 
3686 	r8152_power_cut_en(tp, false);
3687 	r8152_aldps_en(tp, false);
3688 	r8152b_enter_oob(tp);
3689 	r8152_aldps_en(tp, true);
3690 }
3691 
rtl8153_up(struct r8152 * tp)3692 static void rtl8153_up(struct r8152 *tp)
3693 {
3694 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
3695 		return;
3696 
3697 	r8153_u1u2en(tp, false);
3698 	r8153_u2p3en(tp, false);
3699 	r8153_aldps_en(tp, false);
3700 	r8153_first_init(tp);
3701 	r8153_aldps_en(tp, true);
3702 
3703 	switch (tp->version) {
3704 	case RTL_VER_03:
3705 	case RTL_VER_04:
3706 		break;
3707 	case RTL_VER_05:
3708 	case RTL_VER_06:
3709 	default:
3710 		r8153_u2p3en(tp, true);
3711 		break;
3712 	}
3713 
3714 	r8153_u1u2en(tp, true);
3715 }
3716 
rtl8153_down(struct r8152 * tp)3717 static void rtl8153_down(struct r8152 *tp)
3718 {
3719 	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3720 		rtl_drop_queued_tx(tp);
3721 		return;
3722 	}
3723 
3724 	r8153_u1u2en(tp, false);
3725 	r8153_u2p3en(tp, false);
3726 	r8153_power_cut_en(tp, false);
3727 	r8153_aldps_en(tp, false);
3728 	r8153_enter_oob(tp);
3729 	r8153_aldps_en(tp, true);
3730 }
3731 
rtl8153b_up(struct r8152 * tp)3732 static void rtl8153b_up(struct r8152 *tp)
3733 {
3734 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
3735 		return;
3736 
3737 	r8153b_u1u2en(tp, false);
3738 	r8153_u2p3en(tp, false);
3739 	r8153b_aldps_en(tp, false);
3740 
3741 	r8153_first_init(tp);
3742 	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
3743 
3744 	r8153b_aldps_en(tp, true);
3745 	r8153_u2p3en(tp, true);
3746 	r8153b_u1u2en(tp, true);
3747 }
3748 
rtl8153b_down(struct r8152 * tp)3749 static void rtl8153b_down(struct r8152 *tp)
3750 {
3751 	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3752 		rtl_drop_queued_tx(tp);
3753 		return;
3754 	}
3755 
3756 	r8153b_u1u2en(tp, false);
3757 	r8153_u2p3en(tp, false);
3758 	r8153b_power_cut_en(tp, false);
3759 	r8153b_aldps_en(tp, false);
3760 	r8153_enter_oob(tp);
3761 	r8153b_aldps_en(tp, true);
3762 }
3763 
rtl8152_in_nway(struct r8152 * tp)3764 static bool rtl8152_in_nway(struct r8152 *tp)
3765 {
3766 	u16 nway_state;
3767 
3768 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
3769 	tp->ocp_base = 0x2000;
3770 	ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c);		/* phy state */
3771 	nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
3772 
3773 	/* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
3774 	if (nway_state & 0xc000)
3775 		return false;
3776 	else
3777 		return true;
3778 }
3779 
rtl8153_in_nway(struct r8152 * tp)3780 static bool rtl8153_in_nway(struct r8152 *tp)
3781 {
3782 	u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
3783 
3784 	if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
3785 		return false;
3786 	else
3787 		return true;
3788 }
3789 
set_carrier(struct r8152 * tp)3790 static void set_carrier(struct r8152 *tp)
3791 {
3792 	struct net_device *netdev = tp->netdev;
3793 	struct napi_struct *napi = &tp->napi;
3794 	u8 speed;
3795 
3796 	speed = rtl8152_get_speed(tp);
3797 
3798 	if (speed & LINK_STATUS) {
3799 		if (!netif_carrier_ok(netdev)) {
3800 			tp->rtl_ops.enable(tp);
3801 			set_bit(RTL8152_SET_RX_MODE, &tp->flags);
3802 			netif_stop_queue(netdev);
3803 			napi_disable(napi);
3804 			netif_carrier_on(netdev);
3805 			rtl_start_rx(tp);
3806 			napi_enable(&tp->napi);
3807 			netif_wake_queue(netdev);
3808 			netif_info(tp, link, netdev, "carrier on\n");
3809 		} else if (netif_queue_stopped(netdev) &&
3810 			   skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
3811 			netif_wake_queue(netdev);
3812 		}
3813 	} else {
3814 		if (netif_carrier_ok(netdev)) {
3815 			netif_carrier_off(netdev);
3816 			napi_disable(napi);
3817 			tp->rtl_ops.disable(tp);
3818 			napi_enable(napi);
3819 			netif_info(tp, link, netdev, "carrier off\n");
3820 		}
3821 	}
3822 }
3823 
rtl_work_func_t(struct work_struct * work)3824 static void rtl_work_func_t(struct work_struct *work)
3825 {
3826 	struct r8152 *tp = container_of(work, struct r8152, schedule.work);
3827 
3828 	/* If the device is unplugged or !netif_running(), the workqueue
3829 	 * doesn't need to wake the device, and could return directly.
3830 	 */
3831 	if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
3832 		return;
3833 
3834 	if (usb_autopm_get_interface(tp->intf) < 0)
3835 		return;
3836 
3837 	if (!test_bit(WORK_ENABLE, &tp->flags))
3838 		goto out1;
3839 
3840 	if (!mutex_trylock(&tp->control)) {
3841 		schedule_delayed_work(&tp->schedule, 0);
3842 		goto out1;
3843 	}
3844 
3845 	if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
3846 		set_carrier(tp);
3847 
3848 	if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
3849 		_rtl8152_set_rx_mode(tp->netdev);
3850 
3851 	/* don't schedule napi before linking */
3852 	if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
3853 	    netif_carrier_ok(tp->netdev))
3854 		napi_schedule(&tp->napi);
3855 
3856 	mutex_unlock(&tp->control);
3857 
3858 out1:
3859 	usb_autopm_put_interface(tp->intf);
3860 }
3861 
rtl_hw_phy_work_func_t(struct work_struct * work)3862 static void rtl_hw_phy_work_func_t(struct work_struct *work)
3863 {
3864 	struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
3865 
3866 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
3867 		return;
3868 
3869 	if (usb_autopm_get_interface(tp->intf) < 0)
3870 		return;
3871 
3872 	mutex_lock(&tp->control);
3873 
3874 	tp->rtl_ops.hw_phy_cfg(tp);
3875 
3876 	rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
3877 
3878 	mutex_unlock(&tp->control);
3879 
3880 	usb_autopm_put_interface(tp->intf);
3881 }
3882 
3883 #ifdef CONFIG_PM_SLEEP
rtl_notifier(struct notifier_block * nb,unsigned long action,void * data)3884 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
3885 			void *data)
3886 {
3887 	struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
3888 
3889 	switch (action) {
3890 	case PM_HIBERNATION_PREPARE:
3891 	case PM_SUSPEND_PREPARE:
3892 		usb_autopm_get_interface(tp->intf);
3893 		break;
3894 
3895 	case PM_POST_HIBERNATION:
3896 	case PM_POST_SUSPEND:
3897 		usb_autopm_put_interface(tp->intf);
3898 		break;
3899 
3900 	case PM_POST_RESTORE:
3901 	case PM_RESTORE_PREPARE:
3902 	default:
3903 		break;
3904 	}
3905 
3906 	return NOTIFY_DONE;
3907 }
3908 #endif
3909 
rtl8152_open(struct net_device * netdev)3910 static int rtl8152_open(struct net_device *netdev)
3911 {
3912 	struct r8152 *tp = netdev_priv(netdev);
3913 	int res = 0;
3914 
3915 	res = alloc_all_mem(tp);
3916 	if (res)
3917 		goto out;
3918 
3919 	res = usb_autopm_get_interface(tp->intf);
3920 	if (res < 0)
3921 		goto out_free;
3922 
3923 	mutex_lock(&tp->control);
3924 
3925 	tp->rtl_ops.up(tp);
3926 
3927 	netif_carrier_off(netdev);
3928 	netif_start_queue(netdev);
3929 	set_bit(WORK_ENABLE, &tp->flags);
3930 
3931 	res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3932 	if (res) {
3933 		if (res == -ENODEV)
3934 			netif_device_detach(tp->netdev);
3935 		netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3936 			   res);
3937 		goto out_unlock;
3938 	}
3939 	napi_enable(&tp->napi);
3940 
3941 	mutex_unlock(&tp->control);
3942 
3943 	usb_autopm_put_interface(tp->intf);
3944 #ifdef CONFIG_PM_SLEEP
3945 	tp->pm_notifier.notifier_call = rtl_notifier;
3946 	register_pm_notifier(&tp->pm_notifier);
3947 #endif
3948 	return 0;
3949 
3950 out_unlock:
3951 	mutex_unlock(&tp->control);
3952 	usb_autopm_put_interface(tp->intf);
3953 out_free:
3954 	free_all_mem(tp);
3955 out:
3956 	return res;
3957 }
3958 
rtl8152_close(struct net_device * netdev)3959 static int rtl8152_close(struct net_device *netdev)
3960 {
3961 	struct r8152 *tp = netdev_priv(netdev);
3962 	int res = 0;
3963 
3964 #ifdef CONFIG_PM_SLEEP
3965 	unregister_pm_notifier(&tp->pm_notifier);
3966 #endif
3967 	if (!test_bit(RTL8152_UNPLUG, &tp->flags))
3968 		napi_disable(&tp->napi);
3969 	clear_bit(WORK_ENABLE, &tp->flags);
3970 	usb_kill_urb(tp->intr_urb);
3971 	cancel_delayed_work_sync(&tp->schedule);
3972 	netif_stop_queue(netdev);
3973 
3974 	res = usb_autopm_get_interface(tp->intf);
3975 	if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
3976 		rtl_drop_queued_tx(tp);
3977 		rtl_stop_rx(tp);
3978 	} else {
3979 		mutex_lock(&tp->control);
3980 
3981 		tp->rtl_ops.down(tp);
3982 
3983 		mutex_unlock(&tp->control);
3984 
3985 		usb_autopm_put_interface(tp->intf);
3986 	}
3987 
3988 	free_all_mem(tp);
3989 
3990 	return res;
3991 }
3992 
rtl_tally_reset(struct r8152 * tp)3993 static void rtl_tally_reset(struct r8152 *tp)
3994 {
3995 	u32 ocp_data;
3996 
3997 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3998 	ocp_data |= TALLY_RESET;
3999 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
4000 }
4001 
r8152b_init(struct r8152 * tp)4002 static void r8152b_init(struct r8152 *tp)
4003 {
4004 	u32 ocp_data;
4005 	u16 data;
4006 
4007 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
4008 		return;
4009 
4010 	data = r8152_mdio_read(tp, MII_BMCR);
4011 	if (data & BMCR_PDOWN) {
4012 		data &= ~BMCR_PDOWN;
4013 		r8152_mdio_write(tp, MII_BMCR, data);
4014 	}
4015 
4016 	r8152_aldps_en(tp, false);
4017 
4018 	if (tp->version == RTL_VER_01) {
4019 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4020 		ocp_data &= ~LED_MODE_MASK;
4021 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4022 	}
4023 
4024 	r8152_power_cut_en(tp, false);
4025 
4026 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4027 	ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
4028 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4029 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
4030 	ocp_data &= ~MCU_CLK_RATIO_MASK;
4031 	ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
4032 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
4033 	ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
4034 		   SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
4035 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
4036 
4037 	rtl_tally_reset(tp);
4038 
4039 	/* enable rx aggregation */
4040 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4041 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4042 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4043 }
4044 
r8153_init(struct r8152 * tp)4045 static void r8153_init(struct r8152 *tp)
4046 {
4047 	u32 ocp_data;
4048 	u16 data;
4049 	int i;
4050 
4051 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
4052 		return;
4053 
4054 	r8153_u1u2en(tp, false);
4055 
4056 	for (i = 0; i < 500; i++) {
4057 		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4058 		    AUTOLOAD_DONE)
4059 			break;
4060 
4061 		msleep(20);
4062 		if (test_bit(RTL8152_UNPLUG, &tp->flags))
4063 			break;
4064 	}
4065 
4066 	data = r8153_phy_status(tp, 0);
4067 
4068 	if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
4069 	    tp->version == RTL_VER_05)
4070 		ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
4071 
4072 	data = r8152_mdio_read(tp, MII_BMCR);
4073 	if (data & BMCR_PDOWN) {
4074 		data &= ~BMCR_PDOWN;
4075 		r8152_mdio_write(tp, MII_BMCR, data);
4076 	}
4077 
4078 	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4079 
4080 	r8153_u2p3en(tp, false);
4081 
4082 	if (tp->version == RTL_VER_04) {
4083 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
4084 		ocp_data &= ~pwd_dn_scale_mask;
4085 		ocp_data |= pwd_dn_scale(96);
4086 		ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
4087 
4088 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4089 		ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4090 		ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4091 	} else if (tp->version == RTL_VER_05) {
4092 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
4093 		ocp_data &= ~ECM_ALDPS;
4094 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
4095 
4096 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4097 		if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4098 			ocp_data &= ~DYNAMIC_BURST;
4099 		else
4100 			ocp_data |= DYNAMIC_BURST;
4101 		ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4102 	} else if (tp->version == RTL_VER_06) {
4103 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4104 		if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4105 			ocp_data &= ~DYNAMIC_BURST;
4106 		else
4107 			ocp_data |= DYNAMIC_BURST;
4108 		ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4109 	}
4110 
4111 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
4112 	ocp_data |= EP4_FULL_FC;
4113 	ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
4114 
4115 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
4116 	ocp_data &= ~TIMER11_EN;
4117 	ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
4118 
4119 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4120 	ocp_data &= ~LED_MODE_MASK;
4121 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4122 
4123 	ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
4124 	if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
4125 		ocp_data |= LPM_TIMER_500MS;
4126 	else
4127 		ocp_data |= LPM_TIMER_500US;
4128 	ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
4129 
4130 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
4131 	ocp_data &= ~SEN_VAL_MASK;
4132 	ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
4133 	ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
4134 
4135 	ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
4136 
4137 	r8153_power_cut_en(tp, false);
4138 	r8153_u1u2en(tp, true);
4139 	r8153_mac_clk_spd(tp, false);
4140 	usb_enable_lpm(tp->udev);
4141 
4142 	/* rx aggregation */
4143 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4144 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4145 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4146 
4147 	rtl_tally_reset(tp);
4148 
4149 	switch (tp->udev->speed) {
4150 	case USB_SPEED_SUPER:
4151 	case USB_SPEED_SUPER_PLUS:
4152 		tp->coalesce = COALESCE_SUPER;
4153 		break;
4154 	case USB_SPEED_HIGH:
4155 		tp->coalesce = COALESCE_HIGH;
4156 		break;
4157 	default:
4158 		tp->coalesce = COALESCE_SLOW;
4159 		break;
4160 	}
4161 }
4162 
r8153b_init(struct r8152 * tp)4163 static void r8153b_init(struct r8152 *tp)
4164 {
4165 	u32 ocp_data;
4166 	u16 data;
4167 	int i;
4168 
4169 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
4170 		return;
4171 
4172 	r8153b_u1u2en(tp, false);
4173 
4174 	for (i = 0; i < 500; i++) {
4175 		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4176 		    AUTOLOAD_DONE)
4177 			break;
4178 
4179 		msleep(20);
4180 		if (test_bit(RTL8152_UNPLUG, &tp->flags))
4181 			break;
4182 	}
4183 
4184 	data = r8153_phy_status(tp, 0);
4185 
4186 	data = r8152_mdio_read(tp, MII_BMCR);
4187 	if (data & BMCR_PDOWN) {
4188 		data &= ~BMCR_PDOWN;
4189 		r8152_mdio_write(tp, MII_BMCR, data);
4190 	}
4191 
4192 	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4193 
4194 	r8153_u2p3en(tp, false);
4195 
4196 	/* MSC timer = 0xfff * 8ms = 32760 ms */
4197 	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
4198 
4199 	/* U1/U2/L1 idle timer. 500 us */
4200 	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
4201 
4202 	r8153b_power_cut_en(tp, false);
4203 	r8153b_ups_en(tp, false);
4204 	r8153b_queue_wake(tp, false);
4205 	rtl_runtime_suspend_enable(tp, false);
4206 	r8153b_u1u2en(tp, true);
4207 	usb_enable_lpm(tp->udev);
4208 
4209 	/* MAC clock speed down */
4210 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
4211 	ocp_data |= MAC_CLK_SPDWN_EN;
4212 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
4213 
4214 	set_bit(GREEN_ETHERNET, &tp->flags);
4215 
4216 	/* rx aggregation */
4217 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4218 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4219 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4220 
4221 	rtl_tally_reset(tp);
4222 
4223 	tp->coalesce = 15000;	/* 15 us */
4224 }
4225 
rtl8152_pre_reset(struct usb_interface * intf)4226 static int rtl8152_pre_reset(struct usb_interface *intf)
4227 {
4228 	struct r8152 *tp = usb_get_intfdata(intf);
4229 	struct net_device *netdev;
4230 
4231 	if (!tp)
4232 		return 0;
4233 
4234 	netdev = tp->netdev;
4235 	if (!netif_running(netdev))
4236 		return 0;
4237 
4238 	netif_stop_queue(netdev);
4239 	napi_disable(&tp->napi);
4240 	clear_bit(WORK_ENABLE, &tp->flags);
4241 	usb_kill_urb(tp->intr_urb);
4242 	cancel_delayed_work_sync(&tp->schedule);
4243 	if (netif_carrier_ok(netdev)) {
4244 		mutex_lock(&tp->control);
4245 		tp->rtl_ops.disable(tp);
4246 		mutex_unlock(&tp->control);
4247 	}
4248 
4249 	return 0;
4250 }
4251 
rtl8152_post_reset(struct usb_interface * intf)4252 static int rtl8152_post_reset(struct usb_interface *intf)
4253 {
4254 	struct r8152 *tp = usb_get_intfdata(intf);
4255 	struct net_device *netdev;
4256 
4257 	if (!tp)
4258 		return 0;
4259 
4260 	netdev = tp->netdev;
4261 	if (!netif_running(netdev))
4262 		return 0;
4263 
4264 	set_bit(WORK_ENABLE, &tp->flags);
4265 	if (netif_carrier_ok(netdev)) {
4266 		mutex_lock(&tp->control);
4267 		tp->rtl_ops.enable(tp);
4268 		rtl_start_rx(tp);
4269 		rtl8152_set_rx_mode(netdev);
4270 		mutex_unlock(&tp->control);
4271 	}
4272 
4273 	napi_enable(&tp->napi);
4274 	netif_wake_queue(netdev);
4275 	usb_submit_urb(tp->intr_urb, GFP_KERNEL);
4276 
4277 	if (!list_empty(&tp->rx_done))
4278 		napi_schedule(&tp->napi);
4279 
4280 	return 0;
4281 }
4282 
delay_autosuspend(struct r8152 * tp)4283 static bool delay_autosuspend(struct r8152 *tp)
4284 {
4285 	bool sw_linking = !!netif_carrier_ok(tp->netdev);
4286 	bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
4287 
4288 	/* This means a linking change occurs and the driver doesn't detect it,
4289 	 * yet. If the driver has disabled tx/rx and hw is linking on, the
4290 	 * device wouldn't wake up by receiving any packet.
4291 	 */
4292 	if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
4293 		return true;
4294 
4295 	/* If the linking down is occurred by nway, the device may miss the
4296 	 * linking change event. And it wouldn't wake when linking on.
4297 	 */
4298 	if (!sw_linking && tp->rtl_ops.in_nway(tp))
4299 		return true;
4300 	else if (!skb_queue_empty(&tp->tx_queue))
4301 		return true;
4302 	else
4303 		return false;
4304 }
4305 
rtl8152_runtime_resume(struct r8152 * tp)4306 static int rtl8152_runtime_resume(struct r8152 *tp)
4307 {
4308 	struct net_device *netdev = tp->netdev;
4309 
4310 	if (netif_running(netdev) && netdev->flags & IFF_UP) {
4311 		struct napi_struct *napi = &tp->napi;
4312 
4313 		tp->rtl_ops.autosuspend_en(tp, false);
4314 		napi_disable(napi);
4315 		set_bit(WORK_ENABLE, &tp->flags);
4316 
4317 		if (netif_carrier_ok(netdev)) {
4318 			if (rtl8152_get_speed(tp) & LINK_STATUS) {
4319 				rtl_start_rx(tp);
4320 			} else {
4321 				netif_carrier_off(netdev);
4322 				tp->rtl_ops.disable(tp);
4323 				netif_info(tp, link, netdev, "linking down\n");
4324 			}
4325 		}
4326 
4327 		napi_enable(napi);
4328 		clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4329 		smp_mb__after_atomic();
4330 
4331 		if (!list_empty(&tp->rx_done))
4332 			napi_schedule(&tp->napi);
4333 
4334 		usb_submit_urb(tp->intr_urb, GFP_NOIO);
4335 	} else {
4336 		if (netdev->flags & IFF_UP)
4337 			tp->rtl_ops.autosuspend_en(tp, false);
4338 
4339 		clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4340 	}
4341 
4342 	return 0;
4343 }
4344 
rtl8152_system_resume(struct r8152 * tp)4345 static int rtl8152_system_resume(struct r8152 *tp)
4346 {
4347 	struct net_device *netdev = tp->netdev;
4348 
4349 	netif_device_attach(netdev);
4350 
4351 	if (netif_running(netdev) && netdev->flags & IFF_UP) {
4352 		tp->rtl_ops.up(tp);
4353 		netif_carrier_off(netdev);
4354 		set_bit(WORK_ENABLE, &tp->flags);
4355 		usb_submit_urb(tp->intr_urb, GFP_NOIO);
4356 	}
4357 
4358 	return 0;
4359 }
4360 
rtl8152_runtime_suspend(struct r8152 * tp)4361 static int rtl8152_runtime_suspend(struct r8152 *tp)
4362 {
4363 	struct net_device *netdev = tp->netdev;
4364 	int ret = 0;
4365 
4366 	set_bit(SELECTIVE_SUSPEND, &tp->flags);
4367 	smp_mb__after_atomic();
4368 
4369 	if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4370 		u32 rcr = 0;
4371 
4372 		if (netif_carrier_ok(netdev)) {
4373 			u32 ocp_data;
4374 
4375 			rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4376 			ocp_data = rcr & ~RCR_ACPT_ALL;
4377 			ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4378 			rxdy_gated_en(tp, true);
4379 			ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
4380 						 PLA_OOB_CTRL);
4381 			if (!(ocp_data & RXFIFO_EMPTY)) {
4382 				rxdy_gated_en(tp, false);
4383 				ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4384 				clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4385 				smp_mb__after_atomic();
4386 				ret = -EBUSY;
4387 				goto out1;
4388 			}
4389 		}
4390 
4391 		clear_bit(WORK_ENABLE, &tp->flags);
4392 		usb_kill_urb(tp->intr_urb);
4393 
4394 		tp->rtl_ops.autosuspend_en(tp, true);
4395 
4396 		if (netif_carrier_ok(netdev)) {
4397 			struct napi_struct *napi = &tp->napi;
4398 
4399 			napi_disable(napi);
4400 			rtl_stop_rx(tp);
4401 			rxdy_gated_en(tp, false);
4402 			ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4403 			napi_enable(napi);
4404 		}
4405 
4406 		if (delay_autosuspend(tp)) {
4407 			rtl8152_runtime_resume(tp);
4408 			ret = -EBUSY;
4409 		}
4410 	}
4411 
4412 out1:
4413 	return ret;
4414 }
4415 
rtl8152_system_suspend(struct r8152 * tp)4416 static int rtl8152_system_suspend(struct r8152 *tp)
4417 {
4418 	struct net_device *netdev = tp->netdev;
4419 	int ret = 0;
4420 
4421 	netif_device_detach(netdev);
4422 
4423 	if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4424 		struct napi_struct *napi = &tp->napi;
4425 
4426 		clear_bit(WORK_ENABLE, &tp->flags);
4427 		usb_kill_urb(tp->intr_urb);
4428 		napi_disable(napi);
4429 		cancel_delayed_work_sync(&tp->schedule);
4430 		tp->rtl_ops.down(tp);
4431 		napi_enable(napi);
4432 	}
4433 
4434 	return ret;
4435 }
4436 
rtl8152_suspend(struct usb_interface * intf,pm_message_t message)4437 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
4438 {
4439 	struct r8152 *tp = usb_get_intfdata(intf);
4440 	int ret;
4441 
4442 	mutex_lock(&tp->control);
4443 
4444 	if (PMSG_IS_AUTO(message))
4445 		ret = rtl8152_runtime_suspend(tp);
4446 	else
4447 		ret = rtl8152_system_suspend(tp);
4448 
4449 	mutex_unlock(&tp->control);
4450 
4451 	return ret;
4452 }
4453 
rtl8152_resume(struct usb_interface * intf)4454 static int rtl8152_resume(struct usb_interface *intf)
4455 {
4456 	struct r8152 *tp = usb_get_intfdata(intf);
4457 	int ret;
4458 
4459 	mutex_lock(&tp->control);
4460 
4461 	if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
4462 		ret = rtl8152_runtime_resume(tp);
4463 	else
4464 		ret = rtl8152_system_resume(tp);
4465 
4466 	mutex_unlock(&tp->control);
4467 
4468 	return ret;
4469 }
4470 
rtl8152_reset_resume(struct usb_interface * intf)4471 static int rtl8152_reset_resume(struct usb_interface *intf)
4472 {
4473 	struct r8152 *tp = usb_get_intfdata(intf);
4474 
4475 	clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4476 	tp->rtl_ops.init(tp);
4477 	queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
4478 	set_ethernet_addr(tp);
4479 	return rtl8152_resume(intf);
4480 }
4481 
rtl8152_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)4482 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4483 {
4484 	struct r8152 *tp = netdev_priv(dev);
4485 
4486 	if (usb_autopm_get_interface(tp->intf) < 0)
4487 		return;
4488 
4489 	if (!rtl_can_wakeup(tp)) {
4490 		wol->supported = 0;
4491 		wol->wolopts = 0;
4492 	} else {
4493 		mutex_lock(&tp->control);
4494 		wol->supported = WAKE_ANY;
4495 		wol->wolopts = __rtl_get_wol(tp);
4496 		mutex_unlock(&tp->control);
4497 	}
4498 
4499 	usb_autopm_put_interface(tp->intf);
4500 }
4501 
rtl8152_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)4502 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4503 {
4504 	struct r8152 *tp = netdev_priv(dev);
4505 	int ret;
4506 
4507 	if (!rtl_can_wakeup(tp))
4508 		return -EOPNOTSUPP;
4509 
4510 	if (wol->wolopts & ~WAKE_ANY)
4511 		return -EINVAL;
4512 
4513 	ret = usb_autopm_get_interface(tp->intf);
4514 	if (ret < 0)
4515 		goto out_set_wol;
4516 
4517 	mutex_lock(&tp->control);
4518 
4519 	__rtl_set_wol(tp, wol->wolopts);
4520 	tp->saved_wolopts = wol->wolopts & WAKE_ANY;
4521 
4522 	mutex_unlock(&tp->control);
4523 
4524 	usb_autopm_put_interface(tp->intf);
4525 
4526 out_set_wol:
4527 	return ret;
4528 }
4529 
rtl8152_get_msglevel(struct net_device * dev)4530 static u32 rtl8152_get_msglevel(struct net_device *dev)
4531 {
4532 	struct r8152 *tp = netdev_priv(dev);
4533 
4534 	return tp->msg_enable;
4535 }
4536 
rtl8152_set_msglevel(struct net_device * dev,u32 value)4537 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
4538 {
4539 	struct r8152 *tp = netdev_priv(dev);
4540 
4541 	tp->msg_enable = value;
4542 }
4543 
rtl8152_get_drvinfo(struct net_device * netdev,struct ethtool_drvinfo * info)4544 static void rtl8152_get_drvinfo(struct net_device *netdev,
4545 				struct ethtool_drvinfo *info)
4546 {
4547 	struct r8152 *tp = netdev_priv(netdev);
4548 
4549 	strlcpy(info->driver, MODULENAME, sizeof(info->driver));
4550 	strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
4551 	usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
4552 }
4553 
4554 static
rtl8152_get_link_ksettings(struct net_device * netdev,struct ethtool_link_ksettings * cmd)4555 int rtl8152_get_link_ksettings(struct net_device *netdev,
4556 			       struct ethtool_link_ksettings *cmd)
4557 {
4558 	struct r8152 *tp = netdev_priv(netdev);
4559 	int ret;
4560 
4561 	if (!tp->mii.mdio_read)
4562 		return -EOPNOTSUPP;
4563 
4564 	ret = usb_autopm_get_interface(tp->intf);
4565 	if (ret < 0)
4566 		goto out;
4567 
4568 	mutex_lock(&tp->control);
4569 
4570 	mii_ethtool_get_link_ksettings(&tp->mii, cmd);
4571 
4572 	mutex_unlock(&tp->control);
4573 
4574 	usb_autopm_put_interface(tp->intf);
4575 
4576 out:
4577 	return ret;
4578 }
4579 
rtl8152_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)4580 static int rtl8152_set_link_ksettings(struct net_device *dev,
4581 				      const struct ethtool_link_ksettings *cmd)
4582 {
4583 	struct r8152 *tp = netdev_priv(dev);
4584 	int ret;
4585 
4586 	ret = usb_autopm_get_interface(tp->intf);
4587 	if (ret < 0)
4588 		goto out;
4589 
4590 	mutex_lock(&tp->control);
4591 
4592 	ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
4593 				cmd->base.duplex);
4594 	if (!ret) {
4595 		tp->autoneg = cmd->base.autoneg;
4596 		tp->speed = cmd->base.speed;
4597 		tp->duplex = cmd->base.duplex;
4598 	}
4599 
4600 	mutex_unlock(&tp->control);
4601 
4602 	usb_autopm_put_interface(tp->intf);
4603 
4604 out:
4605 	return ret;
4606 }
4607 
4608 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
4609 	"tx_packets",
4610 	"rx_packets",
4611 	"tx_errors",
4612 	"rx_errors",
4613 	"rx_missed",
4614 	"align_errors",
4615 	"tx_single_collisions",
4616 	"tx_multi_collisions",
4617 	"rx_unicast",
4618 	"rx_broadcast",
4619 	"rx_multicast",
4620 	"tx_aborted",
4621 	"tx_underrun",
4622 };
4623 
rtl8152_get_sset_count(struct net_device * dev,int sset)4624 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
4625 {
4626 	switch (sset) {
4627 	case ETH_SS_STATS:
4628 		return ARRAY_SIZE(rtl8152_gstrings);
4629 	default:
4630 		return -EOPNOTSUPP;
4631 	}
4632 }
4633 
rtl8152_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)4634 static void rtl8152_get_ethtool_stats(struct net_device *dev,
4635 				      struct ethtool_stats *stats, u64 *data)
4636 {
4637 	struct r8152 *tp = netdev_priv(dev);
4638 	struct tally_counter tally;
4639 
4640 	if (usb_autopm_get_interface(tp->intf) < 0)
4641 		return;
4642 
4643 	generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
4644 
4645 	usb_autopm_put_interface(tp->intf);
4646 
4647 	data[0] = le64_to_cpu(tally.tx_packets);
4648 	data[1] = le64_to_cpu(tally.rx_packets);
4649 	data[2] = le64_to_cpu(tally.tx_errors);
4650 	data[3] = le32_to_cpu(tally.rx_errors);
4651 	data[4] = le16_to_cpu(tally.rx_missed);
4652 	data[5] = le16_to_cpu(tally.align_errors);
4653 	data[6] = le32_to_cpu(tally.tx_one_collision);
4654 	data[7] = le32_to_cpu(tally.tx_multi_collision);
4655 	data[8] = le64_to_cpu(tally.rx_unicast);
4656 	data[9] = le64_to_cpu(tally.rx_broadcast);
4657 	data[10] = le32_to_cpu(tally.rx_multicast);
4658 	data[11] = le16_to_cpu(tally.tx_aborted);
4659 	data[12] = le16_to_cpu(tally.tx_underrun);
4660 }
4661 
rtl8152_get_strings(struct net_device * dev,u32 stringset,u8 * data)4662 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4663 {
4664 	switch (stringset) {
4665 	case ETH_SS_STATS:
4666 		memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
4667 		break;
4668 	}
4669 }
4670 
r8152_get_eee(struct r8152 * tp,struct ethtool_eee * eee)4671 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4672 {
4673 	u32 ocp_data, lp, adv, supported = 0;
4674 	u16 val;
4675 
4676 	val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
4677 	supported = mmd_eee_cap_to_ethtool_sup_t(val);
4678 
4679 	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
4680 	adv = mmd_eee_adv_to_ethtool_adv_t(val);
4681 
4682 	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
4683 	lp = mmd_eee_adv_to_ethtool_adv_t(val);
4684 
4685 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4686 	ocp_data &= EEE_RX_EN | EEE_TX_EN;
4687 
4688 	eee->eee_enabled = !!ocp_data;
4689 	eee->eee_active = !!(supported & adv & lp);
4690 	eee->supported = supported;
4691 	eee->advertised = adv;
4692 	eee->lp_advertised = lp;
4693 
4694 	return 0;
4695 }
4696 
r8152_set_eee(struct r8152 * tp,struct ethtool_eee * eee)4697 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4698 {
4699 	u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4700 
4701 	r8152_eee_en(tp, eee->eee_enabled);
4702 
4703 	if (!eee->eee_enabled)
4704 		val = 0;
4705 
4706 	r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4707 
4708 	return 0;
4709 }
4710 
r8153_get_eee(struct r8152 * tp,struct ethtool_eee * eee)4711 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4712 {
4713 	u32 ocp_data, lp, adv, supported = 0;
4714 	u16 val;
4715 
4716 	val = ocp_reg_read(tp, OCP_EEE_ABLE);
4717 	supported = mmd_eee_cap_to_ethtool_sup_t(val);
4718 
4719 	val = ocp_reg_read(tp, OCP_EEE_ADV);
4720 	adv = mmd_eee_adv_to_ethtool_adv_t(val);
4721 
4722 	val = ocp_reg_read(tp, OCP_EEE_LPABLE);
4723 	lp = mmd_eee_adv_to_ethtool_adv_t(val);
4724 
4725 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4726 	ocp_data &= EEE_RX_EN | EEE_TX_EN;
4727 
4728 	eee->eee_enabled = !!ocp_data;
4729 	eee->eee_active = !!(supported & adv & lp);
4730 	eee->supported = supported;
4731 	eee->advertised = adv;
4732 	eee->lp_advertised = lp;
4733 
4734 	return 0;
4735 }
4736 
r8153_set_eee(struct r8152 * tp,struct ethtool_eee * eee)4737 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4738 {
4739 	u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4740 
4741 	r8153_eee_en(tp, eee->eee_enabled);
4742 
4743 	if (!eee->eee_enabled)
4744 		val = 0;
4745 
4746 	ocp_reg_write(tp, OCP_EEE_ADV, val);
4747 
4748 	return 0;
4749 }
4750 
r8153b_set_eee(struct r8152 * tp,struct ethtool_eee * eee)4751 static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4752 {
4753 	u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4754 
4755 	r8153b_eee_en(tp, eee->eee_enabled);
4756 
4757 	if (!eee->eee_enabled)
4758 		val = 0;
4759 
4760 	ocp_reg_write(tp, OCP_EEE_ADV, val);
4761 
4762 	return 0;
4763 }
4764 
4765 static int
rtl_ethtool_get_eee(struct net_device * net,struct ethtool_eee * edata)4766 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
4767 {
4768 	struct r8152 *tp = netdev_priv(net);
4769 	int ret;
4770 
4771 	ret = usb_autopm_get_interface(tp->intf);
4772 	if (ret < 0)
4773 		goto out;
4774 
4775 	mutex_lock(&tp->control);
4776 
4777 	ret = tp->rtl_ops.eee_get(tp, edata);
4778 
4779 	mutex_unlock(&tp->control);
4780 
4781 	usb_autopm_put_interface(tp->intf);
4782 
4783 out:
4784 	return ret;
4785 }
4786 
4787 static int
rtl_ethtool_set_eee(struct net_device * net,struct ethtool_eee * edata)4788 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
4789 {
4790 	struct r8152 *tp = netdev_priv(net);
4791 	int ret;
4792 
4793 	ret = usb_autopm_get_interface(tp->intf);
4794 	if (ret < 0)
4795 		goto out;
4796 
4797 	mutex_lock(&tp->control);
4798 
4799 	ret = tp->rtl_ops.eee_set(tp, edata);
4800 	if (!ret)
4801 		ret = mii_nway_restart(&tp->mii);
4802 
4803 	mutex_unlock(&tp->control);
4804 
4805 	usb_autopm_put_interface(tp->intf);
4806 
4807 out:
4808 	return ret;
4809 }
4810 
rtl8152_nway_reset(struct net_device * dev)4811 static int rtl8152_nway_reset(struct net_device *dev)
4812 {
4813 	struct r8152 *tp = netdev_priv(dev);
4814 	int ret;
4815 
4816 	ret = usb_autopm_get_interface(tp->intf);
4817 	if (ret < 0)
4818 		goto out;
4819 
4820 	mutex_lock(&tp->control);
4821 
4822 	ret = mii_nway_restart(&tp->mii);
4823 
4824 	mutex_unlock(&tp->control);
4825 
4826 	usb_autopm_put_interface(tp->intf);
4827 
4828 out:
4829 	return ret;
4830 }
4831 
rtl8152_get_coalesce(struct net_device * netdev,struct ethtool_coalesce * coalesce)4832 static int rtl8152_get_coalesce(struct net_device *netdev,
4833 				struct ethtool_coalesce *coalesce)
4834 {
4835 	struct r8152 *tp = netdev_priv(netdev);
4836 
4837 	switch (tp->version) {
4838 	case RTL_VER_01:
4839 	case RTL_VER_02:
4840 	case RTL_VER_07:
4841 		return -EOPNOTSUPP;
4842 	default:
4843 		break;
4844 	}
4845 
4846 	coalesce->rx_coalesce_usecs = tp->coalesce;
4847 
4848 	return 0;
4849 }
4850 
rtl8152_set_coalesce(struct net_device * netdev,struct ethtool_coalesce * coalesce)4851 static int rtl8152_set_coalesce(struct net_device *netdev,
4852 				struct ethtool_coalesce *coalesce)
4853 {
4854 	struct r8152 *tp = netdev_priv(netdev);
4855 	int ret;
4856 
4857 	switch (tp->version) {
4858 	case RTL_VER_01:
4859 	case RTL_VER_02:
4860 	case RTL_VER_07:
4861 		return -EOPNOTSUPP;
4862 	default:
4863 		break;
4864 	}
4865 
4866 	if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
4867 		return -EINVAL;
4868 
4869 	ret = usb_autopm_get_interface(tp->intf);
4870 	if (ret < 0)
4871 		return ret;
4872 
4873 	mutex_lock(&tp->control);
4874 
4875 	if (tp->coalesce != coalesce->rx_coalesce_usecs) {
4876 		tp->coalesce = coalesce->rx_coalesce_usecs;
4877 
4878 		if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
4879 			r8153_set_rx_early_timeout(tp);
4880 	}
4881 
4882 	mutex_unlock(&tp->control);
4883 
4884 	usb_autopm_put_interface(tp->intf);
4885 
4886 	return ret;
4887 }
4888 
4889 static const struct ethtool_ops ops = {
4890 	.get_drvinfo = rtl8152_get_drvinfo,
4891 	.get_link = ethtool_op_get_link,
4892 	.nway_reset = rtl8152_nway_reset,
4893 	.get_msglevel = rtl8152_get_msglevel,
4894 	.set_msglevel = rtl8152_set_msglevel,
4895 	.get_wol = rtl8152_get_wol,
4896 	.set_wol = rtl8152_set_wol,
4897 	.get_strings = rtl8152_get_strings,
4898 	.get_sset_count = rtl8152_get_sset_count,
4899 	.get_ethtool_stats = rtl8152_get_ethtool_stats,
4900 	.get_coalesce = rtl8152_get_coalesce,
4901 	.set_coalesce = rtl8152_set_coalesce,
4902 	.get_eee = rtl_ethtool_get_eee,
4903 	.set_eee = rtl_ethtool_set_eee,
4904 	.get_link_ksettings = rtl8152_get_link_ksettings,
4905 	.set_link_ksettings = rtl8152_set_link_ksettings,
4906 };
4907 
rtl8152_ioctl(struct net_device * netdev,struct ifreq * rq,int cmd)4908 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
4909 {
4910 	struct r8152 *tp = netdev_priv(netdev);
4911 	struct mii_ioctl_data *data = if_mii(rq);
4912 	int res;
4913 
4914 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
4915 		return -ENODEV;
4916 
4917 	res = usb_autopm_get_interface(tp->intf);
4918 	if (res < 0)
4919 		goto out;
4920 
4921 	switch (cmd) {
4922 	case SIOCGMIIPHY:
4923 		data->phy_id = R8152_PHY_ID; /* Internal PHY */
4924 		break;
4925 
4926 	case SIOCGMIIREG:
4927 		mutex_lock(&tp->control);
4928 		data->val_out = r8152_mdio_read(tp, data->reg_num);
4929 		mutex_unlock(&tp->control);
4930 		break;
4931 
4932 	case SIOCSMIIREG:
4933 		if (!capable(CAP_NET_ADMIN)) {
4934 			res = -EPERM;
4935 			break;
4936 		}
4937 		mutex_lock(&tp->control);
4938 		r8152_mdio_write(tp, data->reg_num, data->val_in);
4939 		mutex_unlock(&tp->control);
4940 		break;
4941 
4942 	default:
4943 		res = -EOPNOTSUPP;
4944 	}
4945 
4946 	usb_autopm_put_interface(tp->intf);
4947 
4948 out:
4949 	return res;
4950 }
4951 
rtl8152_change_mtu(struct net_device * dev,int new_mtu)4952 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
4953 {
4954 	struct r8152 *tp = netdev_priv(dev);
4955 	int ret;
4956 
4957 	switch (tp->version) {
4958 	case RTL_VER_01:
4959 	case RTL_VER_02:
4960 	case RTL_VER_07:
4961 		dev->mtu = new_mtu;
4962 		return 0;
4963 	default:
4964 		break;
4965 	}
4966 
4967 	ret = usb_autopm_get_interface(tp->intf);
4968 	if (ret < 0)
4969 		return ret;
4970 
4971 	mutex_lock(&tp->control);
4972 
4973 	dev->mtu = new_mtu;
4974 
4975 	if (netif_running(dev)) {
4976 		u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4977 
4978 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
4979 
4980 		if (netif_carrier_ok(dev))
4981 			r8153_set_rx_early_size(tp);
4982 	}
4983 
4984 	mutex_unlock(&tp->control);
4985 
4986 	usb_autopm_put_interface(tp->intf);
4987 
4988 	return ret;
4989 }
4990 
4991 static const struct net_device_ops rtl8152_netdev_ops = {
4992 	.ndo_open		= rtl8152_open,
4993 	.ndo_stop		= rtl8152_close,
4994 	.ndo_do_ioctl		= rtl8152_ioctl,
4995 	.ndo_start_xmit		= rtl8152_start_xmit,
4996 	.ndo_tx_timeout		= rtl8152_tx_timeout,
4997 	.ndo_set_features	= rtl8152_set_features,
4998 	.ndo_set_rx_mode	= rtl8152_set_rx_mode,
4999 	.ndo_set_mac_address	= rtl8152_set_mac_address,
5000 	.ndo_change_mtu		= rtl8152_change_mtu,
5001 	.ndo_validate_addr	= eth_validate_addr,
5002 	.ndo_features_check	= rtl8152_features_check,
5003 };
5004 
rtl8152_unload(struct r8152 * tp)5005 static void rtl8152_unload(struct r8152 *tp)
5006 {
5007 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
5008 		return;
5009 
5010 	if (tp->version != RTL_VER_01)
5011 		r8152_power_cut_en(tp, true);
5012 }
5013 
rtl8153_unload(struct r8152 * tp)5014 static void rtl8153_unload(struct r8152 *tp)
5015 {
5016 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
5017 		return;
5018 
5019 	r8153_power_cut_en(tp, false);
5020 }
5021 
rtl8153b_unload(struct r8152 * tp)5022 static void rtl8153b_unload(struct r8152 *tp)
5023 {
5024 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
5025 		return;
5026 
5027 	r8153b_power_cut_en(tp, false);
5028 }
5029 
rtl_ops_init(struct r8152 * tp)5030 static int rtl_ops_init(struct r8152 *tp)
5031 {
5032 	struct rtl_ops *ops = &tp->rtl_ops;
5033 	int ret = 0;
5034 
5035 	switch (tp->version) {
5036 	case RTL_VER_01:
5037 	case RTL_VER_02:
5038 	case RTL_VER_07:
5039 		ops->init		= r8152b_init;
5040 		ops->enable		= rtl8152_enable;
5041 		ops->disable		= rtl8152_disable;
5042 		ops->up			= rtl8152_up;
5043 		ops->down		= rtl8152_down;
5044 		ops->unload		= rtl8152_unload;
5045 		ops->eee_get		= r8152_get_eee;
5046 		ops->eee_set		= r8152_set_eee;
5047 		ops->in_nway		= rtl8152_in_nway;
5048 		ops->hw_phy_cfg		= r8152b_hw_phy_cfg;
5049 		ops->autosuspend_en	= rtl_runtime_suspend_enable;
5050 		break;
5051 
5052 	case RTL_VER_03:
5053 	case RTL_VER_04:
5054 	case RTL_VER_05:
5055 	case RTL_VER_06:
5056 		ops->init		= r8153_init;
5057 		ops->enable		= rtl8153_enable;
5058 		ops->disable		= rtl8153_disable;
5059 		ops->up			= rtl8153_up;
5060 		ops->down		= rtl8153_down;
5061 		ops->unload		= rtl8153_unload;
5062 		ops->eee_get		= r8153_get_eee;
5063 		ops->eee_set		= r8153_set_eee;
5064 		ops->in_nway		= rtl8153_in_nway;
5065 		ops->hw_phy_cfg		= r8153_hw_phy_cfg;
5066 		ops->autosuspend_en	= rtl8153_runtime_enable;
5067 		break;
5068 
5069 	case RTL_VER_08:
5070 	case RTL_VER_09:
5071 		ops->init		= r8153b_init;
5072 		ops->enable		= rtl8153_enable;
5073 		ops->disable		= rtl8153b_disable;
5074 		ops->up			= rtl8153b_up;
5075 		ops->down		= rtl8153b_down;
5076 		ops->unload		= rtl8153b_unload;
5077 		ops->eee_get		= r8153_get_eee;
5078 		ops->eee_set		= r8153b_set_eee;
5079 		ops->in_nway		= rtl8153_in_nway;
5080 		ops->hw_phy_cfg		= r8153b_hw_phy_cfg;
5081 		ops->autosuspend_en	= rtl8153b_runtime_enable;
5082 		break;
5083 
5084 	default:
5085 		ret = -ENODEV;
5086 		netif_err(tp, probe, tp->netdev, "Unknown Device\n");
5087 		break;
5088 	}
5089 
5090 	return ret;
5091 }
5092 
rtl_get_version(struct usb_interface * intf)5093 static u8 rtl_get_version(struct usb_interface *intf)
5094 {
5095 	struct usb_device *udev = interface_to_usbdev(intf);
5096 	u32 ocp_data = 0;
5097 	__le32 *tmp;
5098 	u8 version;
5099 	int ret;
5100 
5101 	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
5102 	if (!tmp)
5103 		return 0;
5104 
5105 	ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
5106 			      RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
5107 			      PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
5108 	if (ret > 0)
5109 		ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
5110 
5111 	kfree(tmp);
5112 
5113 	switch (ocp_data) {
5114 	case 0x4c00:
5115 		version = RTL_VER_01;
5116 		break;
5117 	case 0x4c10:
5118 		version = RTL_VER_02;
5119 		break;
5120 	case 0x5c00:
5121 		version = RTL_VER_03;
5122 		break;
5123 	case 0x5c10:
5124 		version = RTL_VER_04;
5125 		break;
5126 	case 0x5c20:
5127 		version = RTL_VER_05;
5128 		break;
5129 	case 0x5c30:
5130 		version = RTL_VER_06;
5131 		break;
5132 	case 0x4800:
5133 		version = RTL_VER_07;
5134 		break;
5135 	case 0x6000:
5136 		version = RTL_VER_08;
5137 		break;
5138 	case 0x6010:
5139 		version = RTL_VER_09;
5140 		break;
5141 	default:
5142 		version = RTL_VER_UNKNOWN;
5143 		dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
5144 		break;
5145 	}
5146 
5147 	dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
5148 
5149 	return version;
5150 }
5151 
rtl8152_probe(struct usb_interface * intf,const struct usb_device_id * id)5152 static int rtl8152_probe(struct usb_interface *intf,
5153 			 const struct usb_device_id *id)
5154 {
5155 	struct usb_device *udev = interface_to_usbdev(intf);
5156 	u8 version = rtl_get_version(intf);
5157 	struct r8152 *tp;
5158 	struct net_device *netdev;
5159 	int ret;
5160 
5161 	if (version == RTL_VER_UNKNOWN)
5162 		return -ENODEV;
5163 
5164 	if (udev->actconfig->desc.bConfigurationValue != 1) {
5165 		usb_driver_set_configuration(udev, 1);
5166 		return -ENODEV;
5167 	}
5168 
5169 	if (intf->cur_altsetting->desc.bNumEndpoints < 3)
5170 		return -ENODEV;
5171 
5172 	usb_reset_device(udev);
5173 	netdev = alloc_etherdev(sizeof(struct r8152));
5174 	if (!netdev) {
5175 		dev_err(&intf->dev, "Out of memory\n");
5176 		return -ENOMEM;
5177 	}
5178 
5179 	SET_NETDEV_DEV(netdev, &intf->dev);
5180 	tp = netdev_priv(netdev);
5181 	tp->msg_enable = 0x7FFF;
5182 
5183 	tp->udev = udev;
5184 	tp->netdev = netdev;
5185 	tp->intf = intf;
5186 	tp->version = version;
5187 
5188 	switch (version) {
5189 	case RTL_VER_01:
5190 	case RTL_VER_02:
5191 	case RTL_VER_07:
5192 		tp->mii.supports_gmii = 0;
5193 		break;
5194 	default:
5195 		tp->mii.supports_gmii = 1;
5196 		break;
5197 	}
5198 
5199 	ret = rtl_ops_init(tp);
5200 	if (ret)
5201 		goto out;
5202 
5203 	mutex_init(&tp->control);
5204 	INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
5205 	INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
5206 
5207 	netdev->netdev_ops = &rtl8152_netdev_ops;
5208 	netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5209 
5210 	netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5211 			    NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
5212 			    NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
5213 			    NETIF_F_HW_VLAN_CTAG_TX;
5214 	netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5215 			      NETIF_F_TSO | NETIF_F_FRAGLIST |
5216 			      NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
5217 			      NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
5218 	netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
5219 				NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
5220 				NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
5221 
5222 	if (tp->version == RTL_VER_01) {
5223 		netdev->features &= ~NETIF_F_RXCSUM;
5224 		netdev->hw_features &= ~NETIF_F_RXCSUM;
5225 	}
5226 
5227 	netdev->ethtool_ops = &ops;
5228 	netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
5229 
5230 	/* MTU range: 68 - 1500 or 9194 */
5231 	netdev->min_mtu = ETH_MIN_MTU;
5232 	switch (tp->version) {
5233 	case RTL_VER_01:
5234 	case RTL_VER_02:
5235 		netdev->max_mtu = ETH_DATA_LEN;
5236 		break;
5237 	default:
5238 		netdev->max_mtu = RTL8153_MAX_MTU;
5239 		break;
5240 	}
5241 
5242 	tp->mii.dev = netdev;
5243 	tp->mii.mdio_read = read_mii_word;
5244 	tp->mii.mdio_write = write_mii_word;
5245 	tp->mii.phy_id_mask = 0x3f;
5246 	tp->mii.reg_num_mask = 0x1f;
5247 	tp->mii.phy_id = R8152_PHY_ID;
5248 
5249 	tp->autoneg = AUTONEG_ENABLE;
5250 	tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
5251 	tp->duplex = DUPLEX_FULL;
5252 
5253 	intf->needs_remote_wakeup = 1;
5254 
5255 	if (!rtl_can_wakeup(tp))
5256 		__rtl_set_wol(tp, 0);
5257 	else
5258 		tp->saved_wolopts = __rtl_get_wol(tp);
5259 
5260 	tp->rtl_ops.init(tp);
5261 	queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5262 	set_ethernet_addr(tp);
5263 
5264 	usb_set_intfdata(intf, tp);
5265 	netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
5266 
5267 	ret = register_netdev(netdev);
5268 	if (ret != 0) {
5269 		netif_err(tp, probe, netdev, "couldn't register the device\n");
5270 		goto out1;
5271 	}
5272 
5273 	if (tp->saved_wolopts)
5274 		device_set_wakeup_enable(&udev->dev, true);
5275 	else
5276 		device_set_wakeup_enable(&udev->dev, false);
5277 
5278 	netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
5279 
5280 	return 0;
5281 
5282 out1:
5283 	netif_napi_del(&tp->napi);
5284 	usb_set_intfdata(intf, NULL);
5285 out:
5286 	free_netdev(netdev);
5287 	return ret;
5288 }
5289 
rtl8152_disconnect(struct usb_interface * intf)5290 static void rtl8152_disconnect(struct usb_interface *intf)
5291 {
5292 	struct r8152 *tp = usb_get_intfdata(intf);
5293 
5294 	usb_set_intfdata(intf, NULL);
5295 	if (tp) {
5296 		struct usb_device *udev = tp->udev;
5297 
5298 		if (udev->state == USB_STATE_NOTATTACHED)
5299 			set_bit(RTL8152_UNPLUG, &tp->flags);
5300 
5301 		netif_napi_del(&tp->napi);
5302 		unregister_netdev(tp->netdev);
5303 		cancel_delayed_work_sync(&tp->hw_phy_work);
5304 		tp->rtl_ops.unload(tp);
5305 		free_netdev(tp->netdev);
5306 	}
5307 }
5308 
5309 #define REALTEK_USB_DEVICE(vend, prod)	\
5310 	.match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
5311 		       USB_DEVICE_ID_MATCH_INT_CLASS, \
5312 	.idVendor = (vend), \
5313 	.idProduct = (prod), \
5314 	.bInterfaceClass = USB_CLASS_VENDOR_SPEC \
5315 }, \
5316 { \
5317 	.match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
5318 		       USB_DEVICE_ID_MATCH_DEVICE, \
5319 	.idVendor = (vend), \
5320 	.idProduct = (prod), \
5321 	.bInterfaceClass = USB_CLASS_COMM, \
5322 	.bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
5323 	.bInterfaceProtocol = USB_CDC_PROTO_NONE
5324 
5325 /* table of devices that work with this driver */
5326 static const struct usb_device_id rtl8152_table[] = {
5327 	{REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
5328 	{REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
5329 	{REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
5330 	{REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
5331 	{REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
5332 	{REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
5333 	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x304f)},
5334 	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3062)},
5335 	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3069)},
5336 	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7205)},
5337 	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x720c)},
5338 	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7214)},
5339 	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0xa387)},
5340 	{REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
5341 	{REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff)},
5342 	{REALTEK_USB_DEVICE(VENDOR_ID_TPLINK,  0x0601)},
5343 	{}
5344 };
5345 
5346 MODULE_DEVICE_TABLE(usb, rtl8152_table);
5347 
5348 static struct usb_driver rtl8152_driver = {
5349 	.name =		MODULENAME,
5350 	.id_table =	rtl8152_table,
5351 	.probe =	rtl8152_probe,
5352 	.disconnect =	rtl8152_disconnect,
5353 	.suspend =	rtl8152_suspend,
5354 	.resume =	rtl8152_resume,
5355 	.reset_resume =	rtl8152_reset_resume,
5356 	.pre_reset =	rtl8152_pre_reset,
5357 	.post_reset =	rtl8152_post_reset,
5358 	.supports_autosuspend = 1,
5359 	.disable_hub_initiated_lpm = 1,
5360 };
5361 
5362 module_usb_driver(rtl8152_driver);
5363 
5364 MODULE_AUTHOR(DRIVER_AUTHOR);
5365 MODULE_DESCRIPTION(DRIVER_DESC);
5366 MODULE_LICENSE("GPL");
5367 MODULE_VERSION(DRIVER_VERSION);
5368