1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * USA
25 *
26 * The full GNU General Public License is included in this distribution
27 * in the file called COPYING.
28 *
29 * Contact Information:
30 * Intel Linux Wireless <linuxwifi@intel.com>
31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32 *
33 * BSD LICENSE
34 *
35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
37 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
38 * All rights reserved.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 *
44 * * Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * * Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
49 * distribution.
50 * * Neither the name Intel Corporation nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific prior written permission.
53 *
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 *
66 *****************************************************************************/
67 #include <linux/pci.h>
68 #include <linux/pci-aspm.h>
69 #include <linux/interrupt.h>
70 #include <linux/debugfs.h>
71 #include <linux/sched.h>
72 #include <linux/bitops.h>
73 #include <linux/gfp.h>
74 #include <linux/vmalloc.h>
75 #include <linux/pm_runtime.h>
76
77 #include "iwl-drv.h"
78 #include "iwl-trans.h"
79 #include "iwl-csr.h"
80 #include "iwl-prph.h"
81 #include "iwl-scd.h"
82 #include "iwl-agn-hw.h"
83 #include "fw/error-dump.h"
84 #include "internal.h"
85 #include "iwl-fh.h"
86
87 /* extended range in FW SRAM */
88 #define IWL_FW_MEM_EXTENDED_START 0x40000
89 #define IWL_FW_MEM_EXTENDED_END 0x57FFF
90
iwl_pcie_free_fw_monitor(struct iwl_trans * trans)91 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
92 {
93 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
94
95 if (!trans_pcie->fw_mon_page)
96 return;
97
98 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
99 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
100 __free_pages(trans_pcie->fw_mon_page,
101 get_order(trans_pcie->fw_mon_size));
102 trans_pcie->fw_mon_page = NULL;
103 trans_pcie->fw_mon_phys = 0;
104 trans_pcie->fw_mon_size = 0;
105 }
106
iwl_pcie_alloc_fw_monitor(struct iwl_trans * trans,u8 max_power)107 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
108 {
109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
110 struct page *page = NULL;
111 dma_addr_t phys;
112 u32 size = 0;
113 u8 power;
114
115 if (!max_power) {
116 /* default max_power is maximum */
117 max_power = 26;
118 } else {
119 max_power += 11;
120 }
121
122 if (WARN(max_power > 26,
123 "External buffer size for monitor is too big %d, check the FW TLV\n",
124 max_power))
125 return;
126
127 if (trans_pcie->fw_mon_page) {
128 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
129 trans_pcie->fw_mon_size,
130 DMA_FROM_DEVICE);
131 return;
132 }
133
134 phys = 0;
135 for (power = max_power; power >= 11; power--) {
136 int order;
137
138 size = BIT(power);
139 order = get_order(size);
140 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
141 order);
142 if (!page)
143 continue;
144
145 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
146 DMA_FROM_DEVICE);
147 if (dma_mapping_error(trans->dev, phys)) {
148 __free_pages(page, order);
149 page = NULL;
150 continue;
151 }
152 IWL_INFO(trans,
153 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
154 size, order);
155 break;
156 }
157
158 if (WARN_ON_ONCE(!page))
159 return;
160
161 if (power != max_power)
162 IWL_ERR(trans,
163 "Sorry - debug buffer is only %luK while you requested %luK\n",
164 (unsigned long)BIT(power - 10),
165 (unsigned long)BIT(max_power - 10));
166
167 trans_pcie->fw_mon_page = page;
168 trans_pcie->fw_mon_phys = phys;
169 trans_pcie->fw_mon_size = size;
170 }
171
iwl_trans_pcie_read_shr(struct iwl_trans * trans,u32 reg)172 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
173 {
174 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
175 ((reg & 0x0000ffff) | (2 << 28)));
176 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
177 }
178
iwl_trans_pcie_write_shr(struct iwl_trans * trans,u32 reg,u32 val)179 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
180 {
181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
182 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
183 ((reg & 0x0000ffff) | (3 << 28)));
184 }
185
iwl_pcie_set_pwr(struct iwl_trans * trans,bool vaux)186 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
187 {
188 if (trans->cfg->apmg_not_supported)
189 return;
190
191 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
192 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
193 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
194 ~APMG_PS_CTRL_MSK_PWR_SRC);
195 else
196 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
197 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
198 ~APMG_PS_CTRL_MSK_PWR_SRC);
199 }
200
201 /* PCI registers */
202 #define PCI_CFG_RETRY_TIMEOUT 0x041
203
iwl_pcie_apm_config(struct iwl_trans * trans)204 void iwl_pcie_apm_config(struct iwl_trans *trans)
205 {
206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
207 u16 lctl;
208 u16 cap;
209
210 /*
211 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
212 * Check if BIOS (or OS) enabled L1-ASPM on this device.
213 * If so (likely), disable L0S, so device moves directly L0->L1;
214 * costs negligible amount of power savings.
215 * If not (unlikely), enable L0S, so there is at least some
216 * power savings, even without L1.
217 */
218 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
219 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
220 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
221 else
222 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
223 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
224
225 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
226 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
227 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
228 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
229 trans->ltr_enabled ? "En" : "Dis");
230 }
231
232 /*
233 * Start up NIC's basic functionality after it has been reset
234 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
235 * NOTE: This does not load uCode nor start the embedded processor
236 */
iwl_pcie_apm_init(struct iwl_trans * trans)237 static int iwl_pcie_apm_init(struct iwl_trans *trans)
238 {
239 int ret;
240
241 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
242
243 /*
244 * Use "set_bit" below rather than "write", to preserve any hardware
245 * bits already set by default after reset.
246 */
247
248 /* Disable L0S exit timer (platform NMI Work/Around) */
249 if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000)
250 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
251 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
252
253 /*
254 * Disable L0s without affecting L1;
255 * don't wait for ICH L0s (ICH bug W/A)
256 */
257 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
258 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
259
260 /* Set FH wait threshold to maximum (HW error during stress W/A) */
261 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
262
263 /*
264 * Enable HAP INTA (interrupt from management bus) to
265 * wake device's PCI Express link L1a -> L0s
266 */
267 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
268 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
269
270 iwl_pcie_apm_config(trans);
271
272 /* Configure analog phase-lock-loop before activating to D0A */
273 if (trans->cfg->base_params->pll_cfg)
274 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
275
276 /*
277 * Set "initialization complete" bit to move adapter from
278 * D0U* --> D0A* (powered-up active) state.
279 */
280 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
281
282 /*
283 * Wait for clock stabilization; once stabilized, access to
284 * device-internal resources is supported, e.g. iwl_write_prph()
285 * and accesses to uCode SRAM.
286 */
287 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
289 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
290 if (ret < 0) {
291 IWL_ERR(trans, "Failed to init the card\n");
292 return ret;
293 }
294
295 if (trans->cfg->host_interrupt_operation_mode) {
296 /*
297 * This is a bit of an abuse - This is needed for 7260 / 3160
298 * only check host_interrupt_operation_mode even if this is
299 * not related to host_interrupt_operation_mode.
300 *
301 * Enable the oscillator to count wake up time for L1 exit. This
302 * consumes slightly more power (100uA) - but allows to be sure
303 * that we wake up from L1 on time.
304 *
305 * This looks weird: read twice the same register, discard the
306 * value, set a bit, and yet again, read that same register
307 * just to discard the value. But that's the way the hardware
308 * seems to like it.
309 */
310 iwl_read_prph(trans, OSC_CLK);
311 iwl_read_prph(trans, OSC_CLK);
312 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
313 iwl_read_prph(trans, OSC_CLK);
314 iwl_read_prph(trans, OSC_CLK);
315 }
316
317 /*
318 * Enable DMA clock and wait for it to stabilize.
319 *
320 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
321 * bits do not disable clocks. This preserves any hardware
322 * bits already set by default in "CLK_CTRL_REG" after reset.
323 */
324 if (!trans->cfg->apmg_not_supported) {
325 iwl_write_prph(trans, APMG_CLK_EN_REG,
326 APMG_CLK_VAL_DMA_CLK_RQT);
327 udelay(20);
328
329 /* Disable L1-Active */
330 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
331 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
332
333 /* Clear the interrupt in APMG if the NIC is in RFKILL */
334 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
335 APMG_RTC_INT_STT_RFKILL);
336 }
337
338 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
339
340 return 0;
341 }
342
343 /*
344 * Enable LP XTAL to avoid HW bug where device may consume much power if
345 * FW is not loaded after device reset. LP XTAL is disabled by default
346 * after device HW reset. Do it only if XTAL is fed by internal source.
347 * Configure device's "persistence" mode to avoid resetting XTAL again when
348 * SHRD_HW_RST occurs in S3.
349 */
iwl_pcie_apm_lp_xtal_enable(struct iwl_trans * trans)350 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
351 {
352 int ret;
353 u32 apmg_gp1_reg;
354 u32 apmg_xtal_cfg_reg;
355 u32 dl_cfg_reg;
356
357 /* Force XTAL ON */
358 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
360
361 iwl_pcie_sw_reset(trans);
362
363 /*
364 * Set "initialization complete" bit to move adapter from
365 * D0U* --> D0A* (powered-up active) state.
366 */
367 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
368
369 /*
370 * Wait for clock stabilization; once stabilized, access to
371 * device-internal resources is possible.
372 */
373 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
374 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
375 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
376 25000);
377 if (WARN_ON(ret < 0)) {
378 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
379 /* Release XTAL ON request */
380 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
381 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
382 return;
383 }
384
385 /*
386 * Clear "disable persistence" to avoid LP XTAL resetting when
387 * SHRD_HW_RST is applied in S3.
388 */
389 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
390 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
391
392 /*
393 * Force APMG XTAL to be active to prevent its disabling by HW
394 * caused by APMG idle state.
395 */
396 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
397 SHR_APMG_XTAL_CFG_REG);
398 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
399 apmg_xtal_cfg_reg |
400 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
401
402 iwl_pcie_sw_reset(trans);
403
404 /* Enable LP XTAL by indirect access through CSR */
405 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
406 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
407 SHR_APMG_GP1_WF_XTAL_LP_EN |
408 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
409
410 /* Clear delay line clock power up */
411 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
412 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
413 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
414
415 /*
416 * Enable persistence mode to avoid LP XTAL resetting when
417 * SHRD_HW_RST is applied in S3.
418 */
419 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
420 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
421
422 /*
423 * Clear "initialization complete" bit to move adapter from
424 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
425 */
426 iwl_clear_bit(trans, CSR_GP_CNTRL,
427 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
428
429 /* Activates XTAL resources monitor */
430 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
431 CSR_MONITOR_XTAL_RESOURCES);
432
433 /* Release XTAL ON request */
434 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
435 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
436 udelay(10);
437
438 /* Release APMG XTAL */
439 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
440 apmg_xtal_cfg_reg &
441 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
442 }
443
iwl_pcie_apm_stop_master(struct iwl_trans * trans)444 void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
445 {
446 int ret;
447
448 /* stop device's busmaster DMA activity */
449 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
450
451 ret = iwl_poll_bit(trans, CSR_RESET,
452 CSR_RESET_REG_FLAG_MASTER_DISABLED,
453 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
454 if (ret < 0)
455 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
456
457 IWL_DEBUG_INFO(trans, "stop master\n");
458 }
459
iwl_pcie_apm_stop(struct iwl_trans * trans,bool op_mode_leave)460 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
461 {
462 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
463
464 if (op_mode_leave) {
465 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
466 iwl_pcie_apm_init(trans);
467
468 /* inform ME that we are leaving */
469 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
470 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
471 APMG_PCIDEV_STT_VAL_WAKE_ME);
472 else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
473 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
474 CSR_RESET_LINK_PWR_MGMT_DISABLED);
475 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
476 CSR_HW_IF_CONFIG_REG_PREPARE |
477 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
478 mdelay(1);
479 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
480 CSR_RESET_LINK_PWR_MGMT_DISABLED);
481 }
482 mdelay(5);
483 }
484
485 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
486
487 /* Stop device's DMA activity */
488 iwl_pcie_apm_stop_master(trans);
489
490 if (trans->cfg->lp_xtal_workaround) {
491 iwl_pcie_apm_lp_xtal_enable(trans);
492 return;
493 }
494
495 iwl_pcie_sw_reset(trans);
496
497 /*
498 * Clear "initialization complete" bit to move adapter from
499 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
500 */
501 iwl_clear_bit(trans, CSR_GP_CNTRL,
502 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
503 }
504
iwl_pcie_nic_init(struct iwl_trans * trans)505 static int iwl_pcie_nic_init(struct iwl_trans *trans)
506 {
507 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
508 int ret;
509
510 /* nic_init */
511 spin_lock(&trans_pcie->irq_lock);
512 ret = iwl_pcie_apm_init(trans);
513 spin_unlock(&trans_pcie->irq_lock);
514
515 if (ret)
516 return ret;
517
518 iwl_pcie_set_pwr(trans, false);
519
520 iwl_op_mode_nic_config(trans->op_mode);
521
522 /* Allocate the RX queue, or reset if it is already allocated */
523 iwl_pcie_rx_init(trans);
524
525 /* Allocate or reset and init all Tx and Command queues */
526 if (iwl_pcie_tx_init(trans))
527 return -ENOMEM;
528
529 if (trans->cfg->base_params->shadow_reg_enable) {
530 /* enable shadow regs in HW */
531 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
532 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
533 }
534
535 return 0;
536 }
537
538 #define HW_READY_TIMEOUT (50)
539
540 /* Note: returns poll_bit return value, which is >= 0 if success */
iwl_pcie_set_hw_ready(struct iwl_trans * trans)541 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
542 {
543 int ret;
544
545 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
546 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
547
548 /* See if we got it */
549 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
550 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
551 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
552 HW_READY_TIMEOUT);
553
554 if (ret >= 0)
555 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
556
557 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
558 return ret;
559 }
560
561 /* Note: returns standard 0/-ERROR code */
iwl_pcie_prepare_card_hw(struct iwl_trans * trans)562 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
563 {
564 int ret;
565 int t = 0;
566 int iter;
567
568 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
569
570 ret = iwl_pcie_set_hw_ready(trans);
571 /* If the card is ready, exit 0 */
572 if (ret >= 0)
573 return 0;
574
575 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
576 CSR_RESET_LINK_PWR_MGMT_DISABLED);
577 usleep_range(1000, 2000);
578
579 for (iter = 0; iter < 10; iter++) {
580 /* If HW is not ready, prepare the conditions to check again */
581 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
582 CSR_HW_IF_CONFIG_REG_PREPARE);
583
584 do {
585 ret = iwl_pcie_set_hw_ready(trans);
586 if (ret >= 0)
587 return 0;
588
589 usleep_range(200, 1000);
590 t += 200;
591 } while (t < 150000);
592 msleep(25);
593 }
594
595 IWL_ERR(trans, "Couldn't prepare the card\n");
596
597 return ret;
598 }
599
600 /*
601 * ucode
602 */
iwl_pcie_load_firmware_chunk_fh(struct iwl_trans * trans,u32 dst_addr,dma_addr_t phy_addr,u32 byte_cnt)603 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
604 u32 dst_addr, dma_addr_t phy_addr,
605 u32 byte_cnt)
606 {
607 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
608 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
609
610 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
611 dst_addr);
612
613 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
614 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
615
616 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
617 (iwl_get_dma_hi_addr(phy_addr)
618 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
619
620 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
621 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
622 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
623 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
624
625 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
626 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
627 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
628 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
629 }
630
iwl_pcie_load_firmware_chunk(struct iwl_trans * trans,u32 dst_addr,dma_addr_t phy_addr,u32 byte_cnt)631 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
632 u32 dst_addr, dma_addr_t phy_addr,
633 u32 byte_cnt)
634 {
635 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
636 unsigned long flags;
637 int ret;
638
639 trans_pcie->ucode_write_complete = false;
640
641 if (!iwl_trans_grab_nic_access(trans, &flags))
642 return -EIO;
643
644 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
645 byte_cnt);
646 iwl_trans_release_nic_access(trans, &flags);
647
648 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
649 trans_pcie->ucode_write_complete, 5 * HZ);
650 if (!ret) {
651 IWL_ERR(trans, "Failed to load firmware chunk!\n");
652 return -ETIMEDOUT;
653 }
654
655 return 0;
656 }
657
iwl_pcie_load_section(struct iwl_trans * trans,u8 section_num,const struct fw_desc * section)658 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
659 const struct fw_desc *section)
660 {
661 u8 *v_addr;
662 dma_addr_t p_addr;
663 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
664 int ret = 0;
665
666 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
667 section_num);
668
669 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
670 GFP_KERNEL | __GFP_NOWARN);
671 if (!v_addr) {
672 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
673 chunk_sz = PAGE_SIZE;
674 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
675 &p_addr, GFP_KERNEL);
676 if (!v_addr)
677 return -ENOMEM;
678 }
679
680 for (offset = 0; offset < section->len; offset += chunk_sz) {
681 u32 copy_size, dst_addr;
682 bool extended_addr = false;
683
684 copy_size = min_t(u32, chunk_sz, section->len - offset);
685 dst_addr = section->offset + offset;
686
687 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
688 dst_addr <= IWL_FW_MEM_EXTENDED_END)
689 extended_addr = true;
690
691 if (extended_addr)
692 iwl_set_bits_prph(trans, LMPM_CHICK,
693 LMPM_CHICK_EXTENDED_ADDR_SPACE);
694
695 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
696 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
697 copy_size);
698
699 if (extended_addr)
700 iwl_clear_bits_prph(trans, LMPM_CHICK,
701 LMPM_CHICK_EXTENDED_ADDR_SPACE);
702
703 if (ret) {
704 IWL_ERR(trans,
705 "Could not load the [%d] uCode section\n",
706 section_num);
707 break;
708 }
709 }
710
711 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
712 return ret;
713 }
714
iwl_pcie_load_cpu_sections_8000(struct iwl_trans * trans,const struct fw_img * image,int cpu,int * first_ucode_section)715 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
716 const struct fw_img *image,
717 int cpu,
718 int *first_ucode_section)
719 {
720 int shift_param;
721 int i, ret = 0, sec_num = 0x1;
722 u32 val, last_read_idx = 0;
723
724 if (cpu == 1) {
725 shift_param = 0;
726 *first_ucode_section = 0;
727 } else {
728 shift_param = 16;
729 (*first_ucode_section)++;
730 }
731
732 for (i = *first_ucode_section; i < image->num_sec; i++) {
733 last_read_idx = i;
734
735 /*
736 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
737 * CPU1 to CPU2.
738 * PAGING_SEPARATOR_SECTION delimiter - separate between
739 * CPU2 non paged to CPU2 paging sec.
740 */
741 if (!image->sec[i].data ||
742 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
743 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
744 IWL_DEBUG_FW(trans,
745 "Break since Data not valid or Empty section, sec = %d\n",
746 i);
747 break;
748 }
749
750 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
751 if (ret)
752 return ret;
753
754 /* Notify ucode of loaded section number and status */
755 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
756 val = val | (sec_num << shift_param);
757 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
758
759 sec_num = (sec_num << 1) | 0x1;
760 }
761
762 *first_ucode_section = last_read_idx;
763
764 iwl_enable_interrupts(trans);
765
766 if (trans->cfg->use_tfh) {
767 if (cpu == 1)
768 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
769 0xFFFF);
770 else
771 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
772 0xFFFFFFFF);
773 } else {
774 if (cpu == 1)
775 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
776 0xFFFF);
777 else
778 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
779 0xFFFFFFFF);
780 }
781
782 return 0;
783 }
784
iwl_pcie_load_cpu_sections(struct iwl_trans * trans,const struct fw_img * image,int cpu,int * first_ucode_section)785 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
786 const struct fw_img *image,
787 int cpu,
788 int *first_ucode_section)
789 {
790 int i, ret = 0;
791 u32 last_read_idx = 0;
792
793 if (cpu == 1)
794 *first_ucode_section = 0;
795 else
796 (*first_ucode_section)++;
797
798 for (i = *first_ucode_section; i < image->num_sec; i++) {
799 last_read_idx = i;
800
801 /*
802 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
803 * CPU1 to CPU2.
804 * PAGING_SEPARATOR_SECTION delimiter - separate between
805 * CPU2 non paged to CPU2 paging sec.
806 */
807 if (!image->sec[i].data ||
808 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
809 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
810 IWL_DEBUG_FW(trans,
811 "Break since Data not valid or Empty section, sec = %d\n",
812 i);
813 break;
814 }
815
816 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
817 if (ret)
818 return ret;
819 }
820
821 *first_ucode_section = last_read_idx;
822
823 return 0;
824 }
825
iwl_pcie_apply_destination(struct iwl_trans * trans)826 void iwl_pcie_apply_destination(struct iwl_trans *trans)
827 {
828 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
829 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
830 int i;
831
832 if (dest->version)
833 IWL_ERR(trans,
834 "DBG DEST version is %d - expect issues\n",
835 dest->version);
836
837 IWL_INFO(trans, "Applying debug destination %s\n",
838 get_fw_dbg_mode_string(dest->monitor_mode));
839
840 if (dest->monitor_mode == EXTERNAL_MODE)
841 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
842 else
843 IWL_WARN(trans, "PCI should have external buffer debug\n");
844
845 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
846 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
847 u32 val = le32_to_cpu(dest->reg_ops[i].val);
848
849 switch (dest->reg_ops[i].op) {
850 case CSR_ASSIGN:
851 iwl_write32(trans, addr, val);
852 break;
853 case CSR_SETBIT:
854 iwl_set_bit(trans, addr, BIT(val));
855 break;
856 case CSR_CLEARBIT:
857 iwl_clear_bit(trans, addr, BIT(val));
858 break;
859 case PRPH_ASSIGN:
860 iwl_write_prph(trans, addr, val);
861 break;
862 case PRPH_SETBIT:
863 iwl_set_bits_prph(trans, addr, BIT(val));
864 break;
865 case PRPH_CLEARBIT:
866 iwl_clear_bits_prph(trans, addr, BIT(val));
867 break;
868 case PRPH_BLOCKBIT:
869 if (iwl_read_prph(trans, addr) & BIT(val)) {
870 IWL_ERR(trans,
871 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
872 val, addr);
873 goto monitor;
874 }
875 break;
876 default:
877 IWL_ERR(trans, "FW debug - unknown OP %d\n",
878 dest->reg_ops[i].op);
879 break;
880 }
881 }
882
883 monitor:
884 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
885 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
886 trans_pcie->fw_mon_phys >> dest->base_shift);
887 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
888 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
889 (trans_pcie->fw_mon_phys +
890 trans_pcie->fw_mon_size - 256) >>
891 dest->end_shift);
892 else
893 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
894 (trans_pcie->fw_mon_phys +
895 trans_pcie->fw_mon_size) >>
896 dest->end_shift);
897 }
898 }
899
iwl_pcie_load_given_ucode(struct iwl_trans * trans,const struct fw_img * image)900 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
901 const struct fw_img *image)
902 {
903 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
904 int ret = 0;
905 int first_ucode_section;
906
907 IWL_DEBUG_FW(trans, "working with %s CPU\n",
908 image->is_dual_cpus ? "Dual" : "Single");
909
910 /* load to FW the binary non secured sections of CPU1 */
911 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
912 if (ret)
913 return ret;
914
915 if (image->is_dual_cpus) {
916 /* set CPU2 header address */
917 iwl_write_prph(trans,
918 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
919 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
920
921 /* load to FW the binary sections of CPU2 */
922 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
923 &first_ucode_section);
924 if (ret)
925 return ret;
926 }
927
928 /* supported for 7000 only for the moment */
929 if (iwlwifi_mod_params.fw_monitor &&
930 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
931 iwl_pcie_alloc_fw_monitor(trans, 0);
932
933 if (trans_pcie->fw_mon_size) {
934 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
935 trans_pcie->fw_mon_phys >> 4);
936 iwl_write_prph(trans, MON_BUFF_END_ADDR,
937 (trans_pcie->fw_mon_phys +
938 trans_pcie->fw_mon_size) >> 4);
939 }
940 } else if (trans->dbg_dest_tlv) {
941 iwl_pcie_apply_destination(trans);
942 }
943
944 iwl_enable_interrupts(trans);
945
946 /* release CPU reset */
947 iwl_write32(trans, CSR_RESET, 0);
948
949 return 0;
950 }
951
iwl_pcie_load_given_ucode_8000(struct iwl_trans * trans,const struct fw_img * image)952 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
953 const struct fw_img *image)
954 {
955 int ret = 0;
956 int first_ucode_section;
957
958 IWL_DEBUG_FW(trans, "working with %s CPU\n",
959 image->is_dual_cpus ? "Dual" : "Single");
960
961 if (trans->dbg_dest_tlv)
962 iwl_pcie_apply_destination(trans);
963
964 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
965 iwl_read_prph(trans, WFPM_GP2));
966
967 /*
968 * Set default value. On resume reading the values that were
969 * zeored can provide debug data on the resume flow.
970 * This is for debugging only and has no functional impact.
971 */
972 iwl_write_prph(trans, WFPM_GP2, 0x01010101);
973
974 /* configure the ucode to be ready to get the secured image */
975 /* release CPU reset */
976 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
977
978 /* load to FW the binary Secured sections of CPU1 */
979 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
980 &first_ucode_section);
981 if (ret)
982 return ret;
983
984 /* load to FW the binary sections of CPU2 */
985 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
986 &first_ucode_section);
987 }
988
iwl_pcie_check_hw_rf_kill(struct iwl_trans * trans)989 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
990 {
991 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
992 bool hw_rfkill = iwl_is_rfkill_set(trans);
993 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
994 bool report;
995
996 if (hw_rfkill) {
997 set_bit(STATUS_RFKILL_HW, &trans->status);
998 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
999 } else {
1000 clear_bit(STATUS_RFKILL_HW, &trans->status);
1001 if (trans_pcie->opmode_down)
1002 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1003 }
1004
1005 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1006
1007 if (prev != report)
1008 iwl_trans_pcie_rf_kill(trans, report);
1009
1010 return hw_rfkill;
1011 }
1012
1013 struct iwl_causes_list {
1014 u32 cause_num;
1015 u32 mask_reg;
1016 u8 addr;
1017 };
1018
1019 static struct iwl_causes_list causes_list[] = {
1020 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1021 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1022 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1023 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1024 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1025 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11},
1026 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1027 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1028 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1029 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29},
1030 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1031 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1032 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1033 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1034 };
1035
iwl_pcie_map_non_rx_causes(struct iwl_trans * trans)1036 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1037 {
1038 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1039 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1040 int i;
1041
1042 /*
1043 * Access all non RX causes and map them to the default irq.
1044 * In case we are missing at least one interrupt vector,
1045 * the first interrupt vector will serve non-RX and FBQ causes.
1046 */
1047 for (i = 0; i < ARRAY_SIZE(causes_list); i++) {
1048 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val);
1049 iwl_clear_bit(trans, causes_list[i].mask_reg,
1050 causes_list[i].cause_num);
1051 }
1052 }
1053
iwl_pcie_map_rx_causes(struct iwl_trans * trans)1054 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1055 {
1056 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1057 u32 offset =
1058 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1059 u32 val, idx;
1060
1061 /*
1062 * The first RX queue - fallback queue, which is designated for
1063 * management frame, command responses etc, is always mapped to the
1064 * first interrupt vector. The other RX queues are mapped to
1065 * the other (N - 2) interrupt vectors.
1066 */
1067 val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1068 for (idx = 1; idx < trans->num_rx_queues; idx++) {
1069 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1070 MSIX_FH_INT_CAUSES_Q(idx - offset));
1071 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1072 }
1073 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1074
1075 val = MSIX_FH_INT_CAUSES_Q(0);
1076 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1077 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1078 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1079
1080 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1081 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1082 }
1083
iwl_pcie_conf_msix_hw(struct iwl_trans_pcie * trans_pcie)1084 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
1085 {
1086 struct iwl_trans *trans = trans_pcie->trans;
1087
1088 if (!trans_pcie->msix_enabled) {
1089 if (trans->cfg->mq_rx_supported &&
1090 test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1091 iwl_write_prph(trans, UREG_CHICK,
1092 UREG_CHICK_MSI_ENABLE);
1093 return;
1094 }
1095 /*
1096 * The IVAR table needs to be configured again after reset,
1097 * but if the device is disabled, we can't write to
1098 * prph.
1099 */
1100 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1101 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1102
1103 /*
1104 * Each cause from the causes list above and the RX causes is
1105 * represented as a byte in the IVAR table. The first nibble
1106 * represents the bound interrupt vector of the cause, the second
1107 * represents no auto clear for this cause. This will be set if its
1108 * interrupt vector is bound to serve other causes.
1109 */
1110 iwl_pcie_map_rx_causes(trans);
1111
1112 iwl_pcie_map_non_rx_causes(trans);
1113 }
1114
iwl_pcie_init_msix(struct iwl_trans_pcie * trans_pcie)1115 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1116 {
1117 struct iwl_trans *trans = trans_pcie->trans;
1118
1119 iwl_pcie_conf_msix_hw(trans_pcie);
1120
1121 if (!trans_pcie->msix_enabled)
1122 return;
1123
1124 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1125 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1126 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1127 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1128 }
1129
_iwl_trans_pcie_stop_device(struct iwl_trans * trans,bool low_power)1130 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1131 {
1132 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1133
1134 lockdep_assert_held(&trans_pcie->mutex);
1135
1136 if (trans_pcie->is_down)
1137 return;
1138
1139 trans_pcie->is_down = true;
1140
1141 /* Stop dbgc before stopping device */
1142 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1143 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
1144 } else {
1145 iwl_write_prph(trans, DBGC_IN_SAMPLE, 0);
1146 udelay(100);
1147 iwl_write_prph(trans, DBGC_OUT_CTRL, 0);
1148 }
1149
1150 /* tell the device to stop sending interrupts */
1151 iwl_disable_interrupts(trans);
1152
1153 /* device going down, Stop using ICT table */
1154 iwl_pcie_disable_ict(trans);
1155
1156 /*
1157 * If a HW restart happens during firmware loading,
1158 * then the firmware loading might call this function
1159 * and later it might be called again due to the
1160 * restart. So don't process again if the device is
1161 * already dead.
1162 */
1163 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1164 IWL_DEBUG_INFO(trans,
1165 "DEVICE_ENABLED bit was set and is now cleared\n");
1166 iwl_pcie_tx_stop(trans);
1167 iwl_pcie_rx_stop(trans);
1168
1169 /* Power-down device's busmaster DMA clocks */
1170 if (!trans->cfg->apmg_not_supported) {
1171 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1172 APMG_CLK_VAL_DMA_CLK_RQT);
1173 udelay(5);
1174 }
1175 }
1176
1177 /* Make sure (redundant) we've released our request to stay awake */
1178 iwl_clear_bit(trans, CSR_GP_CNTRL,
1179 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1180
1181 /* Stop the device, and put it in low power state */
1182 iwl_pcie_apm_stop(trans, false);
1183
1184 iwl_pcie_sw_reset(trans);
1185
1186 /*
1187 * Upon stop, the IVAR table gets erased, so msi-x won't
1188 * work. This causes a bug in RF-KILL flows, since the interrupt
1189 * that enables radio won't fire on the correct irq, and the
1190 * driver won't be able to handle the interrupt.
1191 * Configure the IVAR table again after reset.
1192 */
1193 iwl_pcie_conf_msix_hw(trans_pcie);
1194
1195 /*
1196 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1197 * This is a bug in certain verions of the hardware.
1198 * Certain devices also keep sending HW RF kill interrupt all
1199 * the time, unless the interrupt is ACKed even if the interrupt
1200 * should be masked. Re-ACK all the interrupts here.
1201 */
1202 iwl_disable_interrupts(trans);
1203
1204 /* clear all status bits */
1205 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1206 clear_bit(STATUS_INT_ENABLED, &trans->status);
1207 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1208
1209 /*
1210 * Even if we stop the HW, we still want the RF kill
1211 * interrupt
1212 */
1213 iwl_enable_rfkill_int(trans);
1214
1215 /* re-take ownership to prevent other users from stealing the device */
1216 iwl_pcie_prepare_card_hw(trans);
1217 }
1218
iwl_pcie_synchronize_irqs(struct iwl_trans * trans)1219 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1220 {
1221 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1222
1223 if (trans_pcie->msix_enabled) {
1224 int i;
1225
1226 for (i = 0; i < trans_pcie->alloc_vecs; i++)
1227 synchronize_irq(trans_pcie->msix_entries[i].vector);
1228 } else {
1229 synchronize_irq(trans_pcie->pci_dev->irq);
1230 }
1231 }
1232
iwl_trans_pcie_start_fw(struct iwl_trans * trans,const struct fw_img * fw,bool run_in_rfkill)1233 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1234 const struct fw_img *fw, bool run_in_rfkill)
1235 {
1236 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1237 bool hw_rfkill;
1238 int ret;
1239
1240 /* This may fail if AMT took ownership of the device */
1241 if (iwl_pcie_prepare_card_hw(trans)) {
1242 IWL_WARN(trans, "Exit HW not ready\n");
1243 ret = -EIO;
1244 goto out;
1245 }
1246
1247 iwl_enable_rfkill_int(trans);
1248
1249 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1250
1251 /*
1252 * We enabled the RF-Kill interrupt and the handler may very
1253 * well be running. Disable the interrupts to make sure no other
1254 * interrupt can be fired.
1255 */
1256 iwl_disable_interrupts(trans);
1257
1258 /* Make sure it finished running */
1259 iwl_pcie_synchronize_irqs(trans);
1260
1261 mutex_lock(&trans_pcie->mutex);
1262
1263 /* If platform's RF_KILL switch is NOT set to KILL */
1264 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1265 if (hw_rfkill && !run_in_rfkill) {
1266 ret = -ERFKILL;
1267 goto out;
1268 }
1269
1270 /* Someone called stop_device, don't try to start_fw */
1271 if (trans_pcie->is_down) {
1272 IWL_WARN(trans,
1273 "Can't start_fw since the HW hasn't been started\n");
1274 ret = -EIO;
1275 goto out;
1276 }
1277
1278 /* make sure rfkill handshake bits are cleared */
1279 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1280 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1281 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1282
1283 /* clear (again), then enable host interrupts */
1284 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1285
1286 ret = iwl_pcie_nic_init(trans);
1287 if (ret) {
1288 IWL_ERR(trans, "Unable to init nic\n");
1289 goto out;
1290 }
1291
1292 /*
1293 * Now, we load the firmware and don't want to be interrupted, even
1294 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1295 * FH_TX interrupt which is needed to load the firmware). If the
1296 * RF-Kill switch is toggled, we will find out after having loaded
1297 * the firmware and return the proper value to the caller.
1298 */
1299 iwl_enable_fw_load_int(trans);
1300
1301 /* really make sure rfkill handshake bits are cleared */
1302 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1303 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1304
1305 /* Load the given image to the HW */
1306 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1307 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1308 else
1309 ret = iwl_pcie_load_given_ucode(trans, fw);
1310
1311 /* re-check RF-Kill state since we may have missed the interrupt */
1312 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1313 if (hw_rfkill && !run_in_rfkill)
1314 ret = -ERFKILL;
1315
1316 out:
1317 mutex_unlock(&trans_pcie->mutex);
1318 return ret;
1319 }
1320
iwl_trans_pcie_fw_alive(struct iwl_trans * trans,u32 scd_addr)1321 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1322 {
1323 iwl_pcie_reset_ict(trans);
1324 iwl_pcie_tx_start(trans, scd_addr);
1325 }
1326
iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans * trans,bool was_in_rfkill)1327 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1328 bool was_in_rfkill)
1329 {
1330 bool hw_rfkill;
1331
1332 /*
1333 * Check again since the RF kill state may have changed while
1334 * all the interrupts were disabled, in this case we couldn't
1335 * receive the RF kill interrupt and update the state in the
1336 * op_mode.
1337 * Don't call the op_mode if the rkfill state hasn't changed.
1338 * This allows the op_mode to call stop_device from the rfkill
1339 * notification without endless recursion. Under very rare
1340 * circumstances, we might have a small recursion if the rfkill
1341 * state changed exactly now while we were called from stop_device.
1342 * This is very unlikely but can happen and is supported.
1343 */
1344 hw_rfkill = iwl_is_rfkill_set(trans);
1345 if (hw_rfkill) {
1346 set_bit(STATUS_RFKILL_HW, &trans->status);
1347 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1348 } else {
1349 clear_bit(STATUS_RFKILL_HW, &trans->status);
1350 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1351 }
1352 if (hw_rfkill != was_in_rfkill)
1353 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1354 }
1355
iwl_trans_pcie_stop_device(struct iwl_trans * trans,bool low_power)1356 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1357 {
1358 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1359 bool was_in_rfkill;
1360
1361 mutex_lock(&trans_pcie->mutex);
1362 trans_pcie->opmode_down = true;
1363 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1364 _iwl_trans_pcie_stop_device(trans, low_power);
1365 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
1366 mutex_unlock(&trans_pcie->mutex);
1367 }
1368
iwl_trans_pcie_rf_kill(struct iwl_trans * trans,bool state)1369 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1370 {
1371 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1372 IWL_TRANS_GET_PCIE_TRANS(trans);
1373
1374 lockdep_assert_held(&trans_pcie->mutex);
1375
1376 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1377 state ? "disabled" : "enabled");
1378 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1379 if (trans->cfg->gen2)
1380 _iwl_trans_pcie_gen2_stop_device(trans, true);
1381 else
1382 _iwl_trans_pcie_stop_device(trans, true);
1383 }
1384 }
1385
iwl_trans_pcie_d3_suspend(struct iwl_trans * trans,bool test,bool reset)1386 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1387 bool reset)
1388 {
1389 if (!reset) {
1390 /* Enable persistence mode to avoid reset */
1391 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1392 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1393 }
1394
1395 iwl_disable_interrupts(trans);
1396
1397 /*
1398 * in testing mode, the host stays awake and the
1399 * hardware won't be reset (not even partially)
1400 */
1401 if (test)
1402 return;
1403
1404 iwl_pcie_disable_ict(trans);
1405
1406 iwl_pcie_synchronize_irqs(trans);
1407
1408 iwl_clear_bit(trans, CSR_GP_CNTRL,
1409 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1410 iwl_clear_bit(trans, CSR_GP_CNTRL,
1411 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1412
1413 iwl_pcie_enable_rx_wake(trans, false);
1414
1415 if (reset) {
1416 /*
1417 * reset TX queues -- some of their registers reset during S3
1418 * so if we don't reset everything here the D3 image would try
1419 * to execute some invalid memory upon resume
1420 */
1421 iwl_trans_pcie_tx_reset(trans);
1422 }
1423
1424 iwl_pcie_set_pwr(trans, true);
1425 }
1426
iwl_trans_pcie_d3_resume(struct iwl_trans * trans,enum iwl_d3_status * status,bool test,bool reset)1427 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1428 enum iwl_d3_status *status,
1429 bool test, bool reset)
1430 {
1431 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1432 u32 val;
1433 int ret;
1434
1435 if (test) {
1436 iwl_enable_interrupts(trans);
1437 *status = IWL_D3_STATUS_ALIVE;
1438 return 0;
1439 }
1440
1441 iwl_pcie_enable_rx_wake(trans, true);
1442
1443 /*
1444 * Reconfigure IVAR table in case of MSIX or reset ict table in
1445 * MSI mode since HW reset erased it.
1446 * Also enables interrupts - none will happen as
1447 * the device doesn't know we're waking it up, only when
1448 * the opmode actually tells it after this call.
1449 */
1450 iwl_pcie_conf_msix_hw(trans_pcie);
1451 if (!trans_pcie->msix_enabled)
1452 iwl_pcie_reset_ict(trans);
1453 iwl_enable_interrupts(trans);
1454
1455 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1456 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1457
1458 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1459 udelay(2);
1460
1461 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1462 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1463 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1464 25000);
1465 if (ret < 0) {
1466 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1467 return ret;
1468 }
1469
1470 iwl_pcie_set_pwr(trans, false);
1471
1472 if (!reset) {
1473 iwl_clear_bit(trans, CSR_GP_CNTRL,
1474 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1475 } else {
1476 iwl_trans_pcie_tx_reset(trans);
1477
1478 ret = iwl_pcie_rx_init(trans);
1479 if (ret) {
1480 IWL_ERR(trans,
1481 "Failed to resume the device (RX reset)\n");
1482 return ret;
1483 }
1484 }
1485
1486 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1487 iwl_read_prph(trans, WFPM_GP2));
1488
1489 val = iwl_read32(trans, CSR_RESET);
1490 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1491 *status = IWL_D3_STATUS_RESET;
1492 else
1493 *status = IWL_D3_STATUS_ALIVE;
1494
1495 return 0;
1496 }
1497
iwl_pcie_set_interrupt_capa(struct pci_dev * pdev,struct iwl_trans * trans)1498 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1499 struct iwl_trans *trans)
1500 {
1501 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1502 int max_irqs, num_irqs, i, ret;
1503 u16 pci_cmd;
1504
1505 if (!trans->cfg->mq_rx_supported)
1506 goto enable_msi;
1507
1508 max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES);
1509 for (i = 0; i < max_irqs; i++)
1510 trans_pcie->msix_entries[i].entry = i;
1511
1512 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1513 MSIX_MIN_INTERRUPT_VECTORS,
1514 max_irqs);
1515 if (num_irqs < 0) {
1516 IWL_DEBUG_INFO(trans,
1517 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1518 num_irqs);
1519 goto enable_msi;
1520 }
1521 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
1522
1523 IWL_DEBUG_INFO(trans,
1524 "MSI-X enabled. %d interrupt vectors were allocated\n",
1525 num_irqs);
1526
1527 /*
1528 * In case the OS provides fewer interrupts than requested, different
1529 * causes will share the same interrupt vector as follows:
1530 * One interrupt less: non rx causes shared with FBQ.
1531 * Two interrupts less: non rx causes shared with FBQ and RSS.
1532 * More than two interrupts: we will use fewer RSS queues.
1533 */
1534 if (num_irqs <= max_irqs - 2) {
1535 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1536 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1537 IWL_SHARED_IRQ_FIRST_RSS;
1538 } else if (num_irqs == max_irqs - 1) {
1539 trans_pcie->trans->num_rx_queues = num_irqs;
1540 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1541 } else {
1542 trans_pcie->trans->num_rx_queues = num_irqs - 1;
1543 }
1544 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
1545
1546 trans_pcie->alloc_vecs = num_irqs;
1547 trans_pcie->msix_enabled = true;
1548 return;
1549
1550 enable_msi:
1551 ret = pci_enable_msi(pdev);
1552 if (ret) {
1553 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1554 /* enable rfkill interrupt: hw bug w/a */
1555 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1556 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1557 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1558 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1559 }
1560 }
1561 }
1562
iwl_pcie_irq_set_affinity(struct iwl_trans * trans)1563 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1564 {
1565 int iter_rx_q, i, ret, cpu, offset;
1566 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1567
1568 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1569 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1570 offset = 1 + i;
1571 for (; i < iter_rx_q ; i++) {
1572 /*
1573 * Get the cpu prior to the place to search
1574 * (i.e. return will be > i - 1).
1575 */
1576 cpu = cpumask_next(i - offset, cpu_online_mask);
1577 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1578 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1579 &trans_pcie->affinity_mask[i]);
1580 if (ret)
1581 IWL_ERR(trans_pcie->trans,
1582 "Failed to set affinity mask for IRQ %d\n",
1583 i);
1584 }
1585 }
1586
queue_name(struct device * dev,struct iwl_trans_pcie * trans_p,int i)1587 static const char *queue_name(struct device *dev,
1588 struct iwl_trans_pcie *trans_p, int i)
1589 {
1590 if (trans_p->shared_vec_mask) {
1591 int vec = trans_p->shared_vec_mask &
1592 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1593
1594 if (i == 0)
1595 return DRV_NAME ": shared IRQ";
1596
1597 return devm_kasprintf(dev, GFP_KERNEL,
1598 DRV_NAME ": queue %d", i + vec);
1599 }
1600 if (i == 0)
1601 return DRV_NAME ": default queue";
1602
1603 if (i == trans_p->alloc_vecs - 1)
1604 return DRV_NAME ": exception";
1605
1606 return devm_kasprintf(dev, GFP_KERNEL,
1607 DRV_NAME ": queue %d", i);
1608 }
1609
iwl_pcie_init_msix_handler(struct pci_dev * pdev,struct iwl_trans_pcie * trans_pcie)1610 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1611 struct iwl_trans_pcie *trans_pcie)
1612 {
1613 int i;
1614
1615 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1616 int ret;
1617 struct msix_entry *msix_entry;
1618 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1619
1620 if (!qname)
1621 return -ENOMEM;
1622
1623 msix_entry = &trans_pcie->msix_entries[i];
1624 ret = devm_request_threaded_irq(&pdev->dev,
1625 msix_entry->vector,
1626 iwl_pcie_msix_isr,
1627 (i == trans_pcie->def_irq) ?
1628 iwl_pcie_irq_msix_handler :
1629 iwl_pcie_irq_rx_msix_handler,
1630 IRQF_SHARED,
1631 qname,
1632 msix_entry);
1633 if (ret) {
1634 IWL_ERR(trans_pcie->trans,
1635 "Error allocating IRQ %d\n", i);
1636
1637 return ret;
1638 }
1639 }
1640 iwl_pcie_irq_set_affinity(trans_pcie->trans);
1641
1642 return 0;
1643 }
1644
_iwl_trans_pcie_start_hw(struct iwl_trans * trans,bool low_power)1645 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1646 {
1647 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1648 int err;
1649
1650 lockdep_assert_held(&trans_pcie->mutex);
1651
1652 err = iwl_pcie_prepare_card_hw(trans);
1653 if (err) {
1654 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1655 return err;
1656 }
1657
1658 iwl_pcie_sw_reset(trans);
1659
1660 err = iwl_pcie_apm_init(trans);
1661 if (err)
1662 return err;
1663
1664 iwl_pcie_init_msix(trans_pcie);
1665
1666 /* From now on, the op_mode will be kept updated about RF kill state */
1667 iwl_enable_rfkill_int(trans);
1668
1669 trans_pcie->opmode_down = false;
1670
1671 /* Set is_down to false here so that...*/
1672 trans_pcie->is_down = false;
1673
1674 /* ...rfkill can call stop_device and set it false if needed */
1675 iwl_pcie_check_hw_rf_kill(trans);
1676
1677 /* Make sure we sync here, because we'll need full access later */
1678 if (low_power)
1679 pm_runtime_resume(trans->dev);
1680
1681 return 0;
1682 }
1683
iwl_trans_pcie_start_hw(struct iwl_trans * trans,bool low_power)1684 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1685 {
1686 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1687 int ret;
1688
1689 mutex_lock(&trans_pcie->mutex);
1690 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1691 mutex_unlock(&trans_pcie->mutex);
1692
1693 return ret;
1694 }
1695
iwl_trans_pcie_op_mode_leave(struct iwl_trans * trans)1696 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1697 {
1698 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1699
1700 mutex_lock(&trans_pcie->mutex);
1701
1702 /* disable interrupts - don't enable HW RF kill interrupt */
1703 iwl_disable_interrupts(trans);
1704
1705 iwl_pcie_apm_stop(trans, true);
1706
1707 iwl_disable_interrupts(trans);
1708
1709 iwl_pcie_disable_ict(trans);
1710
1711 mutex_unlock(&trans_pcie->mutex);
1712
1713 iwl_pcie_synchronize_irqs(trans);
1714 }
1715
iwl_trans_pcie_write8(struct iwl_trans * trans,u32 ofs,u8 val)1716 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1717 {
1718 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1719 }
1720
iwl_trans_pcie_write32(struct iwl_trans * trans,u32 ofs,u32 val)1721 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1722 {
1723 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1724 }
1725
iwl_trans_pcie_read32(struct iwl_trans * trans,u32 ofs)1726 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1727 {
1728 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1729 }
1730
iwl_trans_pcie_read_prph(struct iwl_trans * trans,u32 reg)1731 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1732 {
1733 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1734 ((reg & 0x000FFFFF) | (3 << 24)));
1735 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1736 }
1737
iwl_trans_pcie_write_prph(struct iwl_trans * trans,u32 addr,u32 val)1738 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1739 u32 val)
1740 {
1741 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1742 ((addr & 0x000FFFFF) | (3 << 24)));
1743 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1744 }
1745
iwl_trans_pcie_configure(struct iwl_trans * trans,const struct iwl_trans_config * trans_cfg)1746 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1747 const struct iwl_trans_config *trans_cfg)
1748 {
1749 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1750
1751 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1752 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1753 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1754 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1755 trans_pcie->n_no_reclaim_cmds = 0;
1756 else
1757 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1758 if (trans_pcie->n_no_reclaim_cmds)
1759 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1760 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1761
1762 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1763 trans_pcie->rx_page_order =
1764 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1765
1766 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1767 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1768 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1769
1770 trans_pcie->page_offs = trans_cfg->cb_data_offs;
1771 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1772
1773 trans->command_groups = trans_cfg->command_groups;
1774 trans->command_groups_size = trans_cfg->command_groups_size;
1775
1776 /* Initialize NAPI here - it should be before registering to mac80211
1777 * in the opmode but after the HW struct is allocated.
1778 * As this function may be called again in some corner cases don't
1779 * do anything if NAPI was already initialized.
1780 */
1781 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1782 init_dummy_netdev(&trans_pcie->napi_dev);
1783 }
1784
iwl_trans_pcie_free(struct iwl_trans * trans)1785 void iwl_trans_pcie_free(struct iwl_trans *trans)
1786 {
1787 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1788 int i;
1789
1790 iwl_pcie_synchronize_irqs(trans);
1791
1792 if (trans->cfg->gen2)
1793 iwl_pcie_gen2_tx_free(trans);
1794 else
1795 iwl_pcie_tx_free(trans);
1796 iwl_pcie_rx_free(trans);
1797
1798 if (trans_pcie->rba.alloc_wq) {
1799 destroy_workqueue(trans_pcie->rba.alloc_wq);
1800 trans_pcie->rba.alloc_wq = NULL;
1801 }
1802
1803 if (trans_pcie->msix_enabled) {
1804 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1805 irq_set_affinity_hint(
1806 trans_pcie->msix_entries[i].vector,
1807 NULL);
1808 }
1809
1810 trans_pcie->msix_enabled = false;
1811 } else {
1812 iwl_pcie_free_ict(trans);
1813 }
1814
1815 iwl_pcie_free_fw_monitor(trans);
1816
1817 for_each_possible_cpu(i) {
1818 struct iwl_tso_hdr_page *p =
1819 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1820
1821 if (p->page)
1822 __free_page(p->page);
1823 }
1824
1825 free_percpu(trans_pcie->tso_hdr_page);
1826 mutex_destroy(&trans_pcie->mutex);
1827 iwl_trans_free(trans);
1828 }
1829
iwl_trans_pcie_set_pmi(struct iwl_trans * trans,bool state)1830 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1831 {
1832 if (state)
1833 set_bit(STATUS_TPOWER_PMI, &trans->status);
1834 else
1835 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1836 }
1837
iwl_trans_pcie_grab_nic_access(struct iwl_trans * trans,unsigned long * flags)1838 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1839 unsigned long *flags)
1840 {
1841 int ret;
1842 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1843
1844 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1845
1846 if (trans_pcie->cmd_hold_nic_awake)
1847 goto out;
1848
1849 /* this bit wakes up the NIC */
1850 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1851 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1852 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1853 udelay(2);
1854
1855 /*
1856 * These bits say the device is running, and should keep running for
1857 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1858 * but they do not indicate that embedded SRAM is restored yet;
1859 * HW with volatile SRAM must save/restore contents to/from
1860 * host DRAM when sleeping/waking for power-saving.
1861 * Each direction takes approximately 1/4 millisecond; with this
1862 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1863 * series of register accesses are expected (e.g. reading Event Log),
1864 * to keep device from sleeping.
1865 *
1866 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1867 * SRAM is okay/restored. We don't check that here because this call
1868 * is just for hardware register access; but GP1 MAC_SLEEP
1869 * check is a good idea before accessing the SRAM of HW with
1870 * volatile SRAM (e.g. reading Event Log).
1871 *
1872 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1873 * and do not save/restore SRAM when power cycling.
1874 */
1875 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1876 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1877 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1878 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1879 if (unlikely(ret < 0)) {
1880 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1881 WARN_ONCE(1,
1882 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1883 iwl_read32(trans, CSR_GP_CNTRL));
1884 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1885 return false;
1886 }
1887
1888 out:
1889 /*
1890 * Fool sparse by faking we release the lock - sparse will
1891 * track nic_access anyway.
1892 */
1893 __release(&trans_pcie->reg_lock);
1894 return true;
1895 }
1896
iwl_trans_pcie_release_nic_access(struct iwl_trans * trans,unsigned long * flags)1897 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1898 unsigned long *flags)
1899 {
1900 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1901
1902 lockdep_assert_held(&trans_pcie->reg_lock);
1903
1904 /*
1905 * Fool sparse by faking we acquiring the lock - sparse will
1906 * track nic_access anyway.
1907 */
1908 __acquire(&trans_pcie->reg_lock);
1909
1910 if (trans_pcie->cmd_hold_nic_awake)
1911 goto out;
1912
1913 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1914 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1915 /*
1916 * Above we read the CSR_GP_CNTRL register, which will flush
1917 * any previous writes, but we need the write that clears the
1918 * MAC_ACCESS_REQ bit to be performed before any other writes
1919 * scheduled on different CPUs (after we drop reg_lock).
1920 */
1921 mmiowb();
1922 out:
1923 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1924 }
1925
iwl_trans_pcie_read_mem(struct iwl_trans * trans,u32 addr,void * buf,int dwords)1926 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1927 void *buf, int dwords)
1928 {
1929 unsigned long flags;
1930 int offs, ret = 0;
1931 u32 *vals = buf;
1932
1933 if (iwl_trans_grab_nic_access(trans, &flags)) {
1934 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1935 for (offs = 0; offs < dwords; offs++)
1936 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1937 iwl_trans_release_nic_access(trans, &flags);
1938 } else {
1939 ret = -EBUSY;
1940 }
1941 return ret;
1942 }
1943
iwl_trans_pcie_write_mem(struct iwl_trans * trans,u32 addr,const void * buf,int dwords)1944 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1945 const void *buf, int dwords)
1946 {
1947 unsigned long flags;
1948 int offs, ret = 0;
1949 const u32 *vals = buf;
1950
1951 if (iwl_trans_grab_nic_access(trans, &flags)) {
1952 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1953 for (offs = 0; offs < dwords; offs++)
1954 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1955 vals ? vals[offs] : 0);
1956 iwl_trans_release_nic_access(trans, &flags);
1957 } else {
1958 ret = -EBUSY;
1959 }
1960 return ret;
1961 }
1962
iwl_trans_pcie_freeze_txq_timer(struct iwl_trans * trans,unsigned long txqs,bool freeze)1963 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1964 unsigned long txqs,
1965 bool freeze)
1966 {
1967 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1968 int queue;
1969
1970 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1971 struct iwl_txq *txq = trans_pcie->txq[queue];
1972 unsigned long now;
1973
1974 spin_lock_bh(&txq->lock);
1975
1976 now = jiffies;
1977
1978 if (txq->frozen == freeze)
1979 goto next_queue;
1980
1981 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1982 freeze ? "Freezing" : "Waking", queue);
1983
1984 txq->frozen = freeze;
1985
1986 if (txq->read_ptr == txq->write_ptr)
1987 goto next_queue;
1988
1989 if (freeze) {
1990 if (unlikely(time_after(now,
1991 txq->stuck_timer.expires))) {
1992 /*
1993 * The timer should have fired, maybe it is
1994 * spinning right now on the lock.
1995 */
1996 goto next_queue;
1997 }
1998 /* remember how long until the timer fires */
1999 txq->frozen_expiry_remainder =
2000 txq->stuck_timer.expires - now;
2001 del_timer(&txq->stuck_timer);
2002 goto next_queue;
2003 }
2004
2005 /*
2006 * Wake a non-empty queue -> arm timer with the
2007 * remainder before it froze
2008 */
2009 mod_timer(&txq->stuck_timer,
2010 now + txq->frozen_expiry_remainder);
2011
2012 next_queue:
2013 spin_unlock_bh(&txq->lock);
2014 }
2015 }
2016
iwl_trans_pcie_block_txq_ptrs(struct iwl_trans * trans,bool block)2017 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2018 {
2019 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2020 int i;
2021
2022 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
2023 struct iwl_txq *txq = trans_pcie->txq[i];
2024
2025 if (i == trans_pcie->cmd_queue)
2026 continue;
2027
2028 spin_lock_bh(&txq->lock);
2029
2030 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2031 txq->block--;
2032 if (!txq->block) {
2033 iwl_write32(trans, HBUS_TARG_WRPTR,
2034 txq->write_ptr | (i << 8));
2035 }
2036 } else if (block) {
2037 txq->block++;
2038 }
2039
2040 spin_unlock_bh(&txq->lock);
2041 }
2042 }
2043
2044 #define IWL_FLUSH_WAIT_MS 2000
2045
iwl_trans_pcie_log_scd_error(struct iwl_trans * trans,struct iwl_txq * txq)2046 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2047 {
2048 u32 txq_id = txq->id;
2049 u32 status;
2050 bool active;
2051 u8 fifo;
2052
2053 if (trans->cfg->use_tfh) {
2054 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2055 txq->read_ptr, txq->write_ptr);
2056 /* TODO: access new SCD registers and dump them */
2057 return;
2058 }
2059
2060 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2061 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2062 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2063
2064 IWL_ERR(trans,
2065 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2066 txq_id, active ? "" : "in", fifo,
2067 jiffies_to_msecs(txq->wd_timeout),
2068 txq->read_ptr, txq->write_ptr,
2069 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
2070 (TFD_QUEUE_SIZE_MAX - 1),
2071 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
2072 (TFD_QUEUE_SIZE_MAX - 1),
2073 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
2074 }
2075
iwl_trans_pcie_wait_txq_empty(struct iwl_trans * trans,int txq_idx)2076 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
2077 {
2078 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2079 struct iwl_txq *txq;
2080 unsigned long now = jiffies;
2081 u8 wr_ptr;
2082
2083 if (!test_bit(txq_idx, trans_pcie->queue_used))
2084 return -EINVAL;
2085
2086 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2087 txq = trans_pcie->txq[txq_idx];
2088 wr_ptr = ACCESS_ONCE(txq->write_ptr);
2089
2090 while (txq->read_ptr != ACCESS_ONCE(txq->write_ptr) &&
2091 !time_after(jiffies,
2092 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2093 u8 write_ptr = ACCESS_ONCE(txq->write_ptr);
2094
2095 if (WARN_ONCE(wr_ptr != write_ptr,
2096 "WR pointer moved while flushing %d -> %d\n",
2097 wr_ptr, write_ptr))
2098 return -ETIMEDOUT;
2099 usleep_range(1000, 2000);
2100 }
2101
2102 if (txq->read_ptr != txq->write_ptr) {
2103 IWL_ERR(trans,
2104 "fail to flush all tx fifo queues Q %d\n", txq_idx);
2105 iwl_trans_pcie_log_scd_error(trans, txq);
2106 return -ETIMEDOUT;
2107 }
2108
2109 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2110
2111 return 0;
2112 }
2113
iwl_trans_pcie_wait_txqs_empty(struct iwl_trans * trans,u32 txq_bm)2114 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2115 {
2116 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2117 int cnt;
2118 int ret = 0;
2119
2120 /* waiting for all the tx frames complete might take a while */
2121 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2122
2123 if (cnt == trans_pcie->cmd_queue)
2124 continue;
2125 if (!test_bit(cnt, trans_pcie->queue_used))
2126 continue;
2127 if (!(BIT(cnt) & txq_bm))
2128 continue;
2129
2130 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2131 if (ret)
2132 break;
2133 }
2134
2135 return ret;
2136 }
2137
iwl_trans_pcie_set_bits_mask(struct iwl_trans * trans,u32 reg,u32 mask,u32 value)2138 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2139 u32 mask, u32 value)
2140 {
2141 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2142 unsigned long flags;
2143
2144 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
2145 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2146 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
2147 }
2148
iwl_trans_pcie_ref(struct iwl_trans * trans)2149 static void iwl_trans_pcie_ref(struct iwl_trans *trans)
2150 {
2151 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2152
2153 if (iwlwifi_mod_params.d0i3_disable)
2154 return;
2155
2156 pm_runtime_get(&trans_pcie->pci_dev->dev);
2157
2158 #ifdef CONFIG_PM
2159 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2160 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2161 #endif /* CONFIG_PM */
2162 }
2163
iwl_trans_pcie_unref(struct iwl_trans * trans)2164 static void iwl_trans_pcie_unref(struct iwl_trans *trans)
2165 {
2166 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2167
2168 if (iwlwifi_mod_params.d0i3_disable)
2169 return;
2170
2171 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2172 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
2173
2174 #ifdef CONFIG_PM
2175 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2176 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2177 #endif /* CONFIG_PM */
2178 }
2179
get_csr_string(int cmd)2180 static const char *get_csr_string(int cmd)
2181 {
2182 #define IWL_CMD(x) case x: return #x
2183 switch (cmd) {
2184 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2185 IWL_CMD(CSR_INT_COALESCING);
2186 IWL_CMD(CSR_INT);
2187 IWL_CMD(CSR_INT_MASK);
2188 IWL_CMD(CSR_FH_INT_STATUS);
2189 IWL_CMD(CSR_GPIO_IN);
2190 IWL_CMD(CSR_RESET);
2191 IWL_CMD(CSR_GP_CNTRL);
2192 IWL_CMD(CSR_HW_REV);
2193 IWL_CMD(CSR_EEPROM_REG);
2194 IWL_CMD(CSR_EEPROM_GP);
2195 IWL_CMD(CSR_OTP_GP_REG);
2196 IWL_CMD(CSR_GIO_REG);
2197 IWL_CMD(CSR_GP_UCODE_REG);
2198 IWL_CMD(CSR_GP_DRIVER_REG);
2199 IWL_CMD(CSR_UCODE_DRV_GP1);
2200 IWL_CMD(CSR_UCODE_DRV_GP2);
2201 IWL_CMD(CSR_LED_REG);
2202 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2203 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2204 IWL_CMD(CSR_ANA_PLL_CFG);
2205 IWL_CMD(CSR_HW_REV_WA_REG);
2206 IWL_CMD(CSR_MONITOR_STATUS_REG);
2207 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2208 default:
2209 return "UNKNOWN";
2210 }
2211 #undef IWL_CMD
2212 }
2213
iwl_pcie_dump_csr(struct iwl_trans * trans)2214 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2215 {
2216 int i;
2217 static const u32 csr_tbl[] = {
2218 CSR_HW_IF_CONFIG_REG,
2219 CSR_INT_COALESCING,
2220 CSR_INT,
2221 CSR_INT_MASK,
2222 CSR_FH_INT_STATUS,
2223 CSR_GPIO_IN,
2224 CSR_RESET,
2225 CSR_GP_CNTRL,
2226 CSR_HW_REV,
2227 CSR_EEPROM_REG,
2228 CSR_EEPROM_GP,
2229 CSR_OTP_GP_REG,
2230 CSR_GIO_REG,
2231 CSR_GP_UCODE_REG,
2232 CSR_GP_DRIVER_REG,
2233 CSR_UCODE_DRV_GP1,
2234 CSR_UCODE_DRV_GP2,
2235 CSR_LED_REG,
2236 CSR_DRAM_INT_TBL_REG,
2237 CSR_GIO_CHICKEN_BITS,
2238 CSR_ANA_PLL_CFG,
2239 CSR_MONITOR_STATUS_REG,
2240 CSR_HW_REV_WA_REG,
2241 CSR_DBG_HPET_MEM_REG
2242 };
2243 IWL_ERR(trans, "CSR values:\n");
2244 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2245 "CSR_INT_PERIODIC_REG)\n");
2246 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2247 IWL_ERR(trans, " %25s: 0X%08x\n",
2248 get_csr_string(csr_tbl[i]),
2249 iwl_read32(trans, csr_tbl[i]));
2250 }
2251 }
2252
2253 #ifdef CONFIG_IWLWIFI_DEBUGFS
2254 /* create and remove of files */
2255 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
2256 if (!debugfs_create_file(#name, mode, parent, trans, \
2257 &iwl_dbgfs_##name##_ops)) \
2258 goto err; \
2259 } while (0)
2260
2261 /* file operation */
2262 #define DEBUGFS_READ_FILE_OPS(name) \
2263 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2264 .read = iwl_dbgfs_##name##_read, \
2265 .open = simple_open, \
2266 .llseek = generic_file_llseek, \
2267 };
2268
2269 #define DEBUGFS_WRITE_FILE_OPS(name) \
2270 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2271 .write = iwl_dbgfs_##name##_write, \
2272 .open = simple_open, \
2273 .llseek = generic_file_llseek, \
2274 };
2275
2276 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
2277 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2278 .write = iwl_dbgfs_##name##_write, \
2279 .read = iwl_dbgfs_##name##_read, \
2280 .open = simple_open, \
2281 .llseek = generic_file_llseek, \
2282 };
2283
iwl_dbgfs_tx_queue_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)2284 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
2285 char __user *user_buf,
2286 size_t count, loff_t *ppos)
2287 {
2288 struct iwl_trans *trans = file->private_data;
2289 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2290 struct iwl_txq *txq;
2291 char *buf;
2292 int pos = 0;
2293 int cnt;
2294 int ret;
2295 size_t bufsz;
2296
2297 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
2298
2299 if (!trans_pcie->txq_memory)
2300 return -EAGAIN;
2301
2302 buf = kzalloc(bufsz, GFP_KERNEL);
2303 if (!buf)
2304 return -ENOMEM;
2305
2306 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2307 txq = trans_pcie->txq[cnt];
2308 pos += scnprintf(buf + pos, bufsz - pos,
2309 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2310 cnt, txq->read_ptr, txq->write_ptr,
2311 !!test_bit(cnt, trans_pcie->queue_used),
2312 !!test_bit(cnt, trans_pcie->queue_stopped),
2313 txq->need_update, txq->frozen,
2314 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
2315 }
2316 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2317 kfree(buf);
2318 return ret;
2319 }
2320
iwl_dbgfs_rx_queue_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)2321 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2322 char __user *user_buf,
2323 size_t count, loff_t *ppos)
2324 {
2325 struct iwl_trans *trans = file->private_data;
2326 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2327 char *buf;
2328 int pos = 0, i, ret;
2329 size_t bufsz = sizeof(buf);
2330
2331 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2332
2333 if (!trans_pcie->rxq)
2334 return -EAGAIN;
2335
2336 buf = kzalloc(bufsz, GFP_KERNEL);
2337 if (!buf)
2338 return -ENOMEM;
2339
2340 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2341 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2342
2343 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2344 i);
2345 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2346 rxq->read);
2347 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2348 rxq->write);
2349 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2350 rxq->write_actual);
2351 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2352 rxq->need_update);
2353 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2354 rxq->free_count);
2355 if (rxq->rb_stts) {
2356 pos += scnprintf(buf + pos, bufsz - pos,
2357 "\tclosed_rb_num: %u\n",
2358 le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2359 0x0FFF);
2360 } else {
2361 pos += scnprintf(buf + pos, bufsz - pos,
2362 "\tclosed_rb_num: Not Allocated\n");
2363 }
2364 }
2365 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2366 kfree(buf);
2367
2368 return ret;
2369 }
2370
iwl_dbgfs_interrupt_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)2371 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2372 char __user *user_buf,
2373 size_t count, loff_t *ppos)
2374 {
2375 struct iwl_trans *trans = file->private_data;
2376 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2377 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2378
2379 int pos = 0;
2380 char *buf;
2381 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2382 ssize_t ret;
2383
2384 buf = kzalloc(bufsz, GFP_KERNEL);
2385 if (!buf)
2386 return -ENOMEM;
2387
2388 pos += scnprintf(buf + pos, bufsz - pos,
2389 "Interrupt Statistics Report:\n");
2390
2391 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2392 isr_stats->hw);
2393 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2394 isr_stats->sw);
2395 if (isr_stats->sw || isr_stats->hw) {
2396 pos += scnprintf(buf + pos, bufsz - pos,
2397 "\tLast Restarting Code: 0x%X\n",
2398 isr_stats->err_code);
2399 }
2400 #ifdef CONFIG_IWLWIFI_DEBUG
2401 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2402 isr_stats->sch);
2403 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2404 isr_stats->alive);
2405 #endif
2406 pos += scnprintf(buf + pos, bufsz - pos,
2407 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2408
2409 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2410 isr_stats->ctkill);
2411
2412 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2413 isr_stats->wakeup);
2414
2415 pos += scnprintf(buf + pos, bufsz - pos,
2416 "Rx command responses:\t\t %u\n", isr_stats->rx);
2417
2418 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2419 isr_stats->tx);
2420
2421 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2422 isr_stats->unhandled);
2423
2424 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2425 kfree(buf);
2426 return ret;
2427 }
2428
iwl_dbgfs_interrupt_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)2429 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2430 const char __user *user_buf,
2431 size_t count, loff_t *ppos)
2432 {
2433 struct iwl_trans *trans = file->private_data;
2434 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2435 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2436 u32 reset_flag;
2437 int ret;
2438
2439 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2440 if (ret)
2441 return ret;
2442 if (reset_flag == 0)
2443 memset(isr_stats, 0, sizeof(*isr_stats));
2444
2445 return count;
2446 }
2447
iwl_dbgfs_csr_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)2448 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2449 const char __user *user_buf,
2450 size_t count, loff_t *ppos)
2451 {
2452 struct iwl_trans *trans = file->private_data;
2453
2454 iwl_pcie_dump_csr(trans);
2455
2456 return count;
2457 }
2458
iwl_dbgfs_fh_reg_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)2459 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2460 char __user *user_buf,
2461 size_t count, loff_t *ppos)
2462 {
2463 struct iwl_trans *trans = file->private_data;
2464 char *buf = NULL;
2465 ssize_t ret;
2466
2467 ret = iwl_dump_fh(trans, &buf);
2468 if (ret < 0)
2469 return ret;
2470 if (!buf)
2471 return -EINVAL;
2472 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2473 kfree(buf);
2474 return ret;
2475 }
2476
iwl_dbgfs_rfkill_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)2477 static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2478 char __user *user_buf,
2479 size_t count, loff_t *ppos)
2480 {
2481 struct iwl_trans *trans = file->private_data;
2482 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2483 char buf[100];
2484 int pos;
2485
2486 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2487 trans_pcie->debug_rfkill,
2488 !(iwl_read32(trans, CSR_GP_CNTRL) &
2489 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2490
2491 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2492 }
2493
iwl_dbgfs_rfkill_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)2494 static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2495 const char __user *user_buf,
2496 size_t count, loff_t *ppos)
2497 {
2498 struct iwl_trans *trans = file->private_data;
2499 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2500 bool old = trans_pcie->debug_rfkill;
2501 int ret;
2502
2503 ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill);
2504 if (ret)
2505 return ret;
2506 if (old == trans_pcie->debug_rfkill)
2507 return count;
2508 IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2509 old, trans_pcie->debug_rfkill);
2510 iwl_pcie_handle_rfkill_irq(trans);
2511
2512 return count;
2513 }
2514
2515 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2516 DEBUGFS_READ_FILE_OPS(fh_reg);
2517 DEBUGFS_READ_FILE_OPS(rx_queue);
2518 DEBUGFS_READ_FILE_OPS(tx_queue);
2519 DEBUGFS_WRITE_FILE_OPS(csr);
2520 DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
2521
2522 /* Create the debugfs files and directories */
iwl_trans_pcie_dbgfs_register(struct iwl_trans * trans)2523 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2524 {
2525 struct dentry *dir = trans->dbgfs_dir;
2526
2527 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2528 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2529 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2530 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2531 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2532 DEBUGFS_ADD_FILE(rfkill, dir, S_IWUSR | S_IRUSR);
2533 return 0;
2534
2535 err:
2536 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2537 return -ENOMEM;
2538 }
2539 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2540
iwl_trans_pcie_get_cmdlen(struct iwl_trans * trans,void * tfd)2541 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
2542 {
2543 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2544 u32 cmdlen = 0;
2545 int i;
2546
2547 for (i = 0; i < trans_pcie->max_tbs; i++)
2548 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
2549
2550 return cmdlen;
2551 }
2552
iwl_trans_pcie_dump_rbs(struct iwl_trans * trans,struct iwl_fw_error_dump_data ** data,int allocated_rb_nums)2553 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2554 struct iwl_fw_error_dump_data **data,
2555 int allocated_rb_nums)
2556 {
2557 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2558 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2559 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2560 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2561 u32 i, r, j, rb_len = 0;
2562
2563 spin_lock(&rxq->lock);
2564
2565 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2566
2567 for (i = rxq->read, j = 0;
2568 i != r && j < allocated_rb_nums;
2569 i = (i + 1) & RX_QUEUE_MASK, j++) {
2570 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2571 struct iwl_fw_error_dump_rb *rb;
2572
2573 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2574 DMA_FROM_DEVICE);
2575
2576 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2577
2578 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2579 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2580 rb = (void *)(*data)->data;
2581 rb->index = cpu_to_le32(i);
2582 memcpy(rb->data, page_address(rxb->page), max_len);
2583 /* remap the page for the free benefit */
2584 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2585 max_len,
2586 DMA_FROM_DEVICE);
2587
2588 *data = iwl_fw_error_next_data(*data);
2589 }
2590
2591 spin_unlock(&rxq->lock);
2592
2593 return rb_len;
2594 }
2595 #define IWL_CSR_TO_DUMP (0x250)
2596
iwl_trans_pcie_dump_csr(struct iwl_trans * trans,struct iwl_fw_error_dump_data ** data)2597 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2598 struct iwl_fw_error_dump_data **data)
2599 {
2600 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2601 __le32 *val;
2602 int i;
2603
2604 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2605 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2606 val = (void *)(*data)->data;
2607
2608 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2609 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2610
2611 *data = iwl_fw_error_next_data(*data);
2612
2613 return csr_len;
2614 }
2615
iwl_trans_pcie_fh_regs_dump(struct iwl_trans * trans,struct iwl_fw_error_dump_data ** data)2616 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2617 struct iwl_fw_error_dump_data **data)
2618 {
2619 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2620 unsigned long flags;
2621 __le32 *val;
2622 int i;
2623
2624 if (!iwl_trans_grab_nic_access(trans, &flags))
2625 return 0;
2626
2627 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2628 (*data)->len = cpu_to_le32(fh_regs_len);
2629 val = (void *)(*data)->data;
2630
2631 if (!trans->cfg->gen2)
2632 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
2633 i += sizeof(u32))
2634 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2635 else
2636 for (i = FH_MEM_LOWER_BOUND_GEN2; i < FH_MEM_UPPER_BOUND_GEN2;
2637 i += sizeof(u32))
2638 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2639 i));
2640
2641 iwl_trans_release_nic_access(trans, &flags);
2642
2643 *data = iwl_fw_error_next_data(*data);
2644
2645 return sizeof(**data) + fh_regs_len;
2646 }
2647
2648 static u32
iwl_trans_pci_dump_marbh_monitor(struct iwl_trans * trans,struct iwl_fw_error_dump_fw_mon * fw_mon_data,u32 monitor_len)2649 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2650 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2651 u32 monitor_len)
2652 {
2653 u32 buf_size_in_dwords = (monitor_len >> 2);
2654 u32 *buffer = (u32 *)fw_mon_data->data;
2655 unsigned long flags;
2656 u32 i;
2657
2658 if (!iwl_trans_grab_nic_access(trans, &flags))
2659 return 0;
2660
2661 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2662 for (i = 0; i < buf_size_in_dwords; i++)
2663 buffer[i] = iwl_read_prph_no_grab(trans,
2664 MON_DMARB_RD_DATA_ADDR);
2665 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2666
2667 iwl_trans_release_nic_access(trans, &flags);
2668
2669 return monitor_len;
2670 }
2671
2672 static u32
iwl_trans_pcie_dump_monitor(struct iwl_trans * trans,struct iwl_fw_error_dump_data ** data,u32 monitor_len)2673 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2674 struct iwl_fw_error_dump_data **data,
2675 u32 monitor_len)
2676 {
2677 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2678 u32 len = 0;
2679
2680 if ((trans_pcie->fw_mon_page &&
2681 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2682 trans->dbg_dest_tlv) {
2683 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2684 u32 base, write_ptr, wrap_cnt;
2685
2686 /* If there was a dest TLV - use the values from there */
2687 if (trans->dbg_dest_tlv) {
2688 write_ptr =
2689 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2690 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2691 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2692 } else {
2693 base = MON_BUFF_BASE_ADDR;
2694 write_ptr = MON_BUFF_WRPTR;
2695 wrap_cnt = MON_BUFF_CYCLE_CNT;
2696 }
2697
2698 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2699 fw_mon_data = (void *)(*data)->data;
2700 fw_mon_data->fw_mon_wr_ptr =
2701 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2702 fw_mon_data->fw_mon_cycle_cnt =
2703 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2704 fw_mon_data->fw_mon_base_ptr =
2705 cpu_to_le32(iwl_read_prph(trans, base));
2706
2707 len += sizeof(**data) + sizeof(*fw_mon_data);
2708 if (trans_pcie->fw_mon_page) {
2709 /*
2710 * The firmware is now asserted, it won't write anything
2711 * to the buffer. CPU can take ownership to fetch the
2712 * data. The buffer will be handed back to the device
2713 * before the firmware will be restarted.
2714 */
2715 dma_sync_single_for_cpu(trans->dev,
2716 trans_pcie->fw_mon_phys,
2717 trans_pcie->fw_mon_size,
2718 DMA_FROM_DEVICE);
2719 memcpy(fw_mon_data->data,
2720 page_address(trans_pcie->fw_mon_page),
2721 trans_pcie->fw_mon_size);
2722
2723 monitor_len = trans_pcie->fw_mon_size;
2724 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2725 /*
2726 * Update pointers to reflect actual values after
2727 * shifting
2728 */
2729 base = iwl_read_prph(trans, base) <<
2730 trans->dbg_dest_tlv->base_shift;
2731 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2732 monitor_len / sizeof(u32));
2733 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2734 monitor_len =
2735 iwl_trans_pci_dump_marbh_monitor(trans,
2736 fw_mon_data,
2737 monitor_len);
2738 } else {
2739 /* Didn't match anything - output no monitor data */
2740 monitor_len = 0;
2741 }
2742
2743 len += monitor_len;
2744 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2745 }
2746
2747 return len;
2748 }
2749
2750 static struct iwl_trans_dump_data
iwl_trans_pcie_dump_data(struct iwl_trans * trans,const struct iwl_fw_dbg_trigger_tlv * trigger)2751 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
2752 const struct iwl_fw_dbg_trigger_tlv *trigger)
2753 {
2754 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2755 struct iwl_fw_error_dump_data *data;
2756 struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
2757 struct iwl_fw_error_dump_txcmd *txcmd;
2758 struct iwl_trans_dump_data *dump_data;
2759 u32 len, num_rbs;
2760 u32 monitor_len;
2761 int i, ptr;
2762 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2763 !trans->cfg->mq_rx_supported;
2764
2765 /* transport dump header */
2766 len = sizeof(*dump_data);
2767
2768 /* host commands */
2769 len += sizeof(*data) +
2770 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2771
2772 /* FW monitor */
2773 if (trans_pcie->fw_mon_page) {
2774 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2775 trans_pcie->fw_mon_size;
2776 monitor_len = trans_pcie->fw_mon_size;
2777 } else if (trans->dbg_dest_tlv) {
2778 u32 base, end;
2779
2780 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2781 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2782
2783 base = iwl_read_prph(trans, base) <<
2784 trans->dbg_dest_tlv->base_shift;
2785 end = iwl_read_prph(trans, end) <<
2786 trans->dbg_dest_tlv->end_shift;
2787
2788 /* Make "end" point to the actual end */
2789 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000 ||
2790 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2791 end += (1 << trans->dbg_dest_tlv->end_shift);
2792 monitor_len = end - base;
2793 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2794 monitor_len;
2795 } else {
2796 monitor_len = 0;
2797 }
2798
2799 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2800 dump_data = vzalloc(len);
2801 if (!dump_data)
2802 return NULL;
2803
2804 data = (void *)dump_data->data;
2805 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2806 dump_data->len = len;
2807
2808 return dump_data;
2809 }
2810
2811 /* CSR registers */
2812 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2813
2814 /* FH registers */
2815 if (trans->cfg->gen2)
2816 len += sizeof(*data) +
2817 (FH_MEM_UPPER_BOUND_GEN2 - FH_MEM_LOWER_BOUND_GEN2);
2818 else
2819 len += sizeof(*data) +
2820 (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2821
2822 if (dump_rbs) {
2823 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2824 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2825 /* RBs */
2826 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num))
2827 & 0x0FFF;
2828 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
2829 len += num_rbs * (sizeof(*data) +
2830 sizeof(struct iwl_fw_error_dump_rb) +
2831 (PAGE_SIZE << trans_pcie->rx_page_order));
2832 }
2833
2834 /* Paged memory for gen2 HW */
2835 if (trans->cfg->gen2)
2836 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++)
2837 len += sizeof(*data) +
2838 sizeof(struct iwl_fw_error_dump_paging) +
2839 trans_pcie->init_dram.paging[i].size;
2840
2841 dump_data = vzalloc(len);
2842 if (!dump_data)
2843 return NULL;
2844
2845 len = 0;
2846 data = (void *)dump_data->data;
2847 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2848 txcmd = (void *)data->data;
2849 spin_lock_bh(&cmdq->lock);
2850 ptr = cmdq->write_ptr;
2851 for (i = 0; i < cmdq->n_window; i++) {
2852 u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr);
2853 u32 caplen, cmdlen;
2854
2855 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds +
2856 trans_pcie->tfd_size * ptr);
2857 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2858
2859 if (cmdlen) {
2860 len += sizeof(*txcmd) + caplen;
2861 txcmd->cmdlen = cpu_to_le32(cmdlen);
2862 txcmd->caplen = cpu_to_le32(caplen);
2863 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2864 txcmd = (void *)((u8 *)txcmd->data + caplen);
2865 }
2866
2867 ptr = iwl_queue_dec_wrap(ptr);
2868 }
2869 spin_unlock_bh(&cmdq->lock);
2870
2871 data->len = cpu_to_le32(len);
2872 len += sizeof(*data);
2873 data = iwl_fw_error_next_data(data);
2874
2875 len += iwl_trans_pcie_dump_csr(trans, &data);
2876 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2877 if (dump_rbs)
2878 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
2879
2880 /* Paged memory for gen2 HW */
2881 if (trans->cfg->gen2) {
2882 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) {
2883 struct iwl_fw_error_dump_paging *paging;
2884 dma_addr_t addr =
2885 trans_pcie->init_dram.paging[i].physical;
2886 u32 page_len = trans_pcie->init_dram.paging[i].size;
2887
2888 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
2889 data->len = cpu_to_le32(sizeof(*paging) + page_len);
2890 paging = (void *)data->data;
2891 paging->index = cpu_to_le32(i);
2892 dma_sync_single_for_cpu(trans->dev, addr, page_len,
2893 DMA_BIDIRECTIONAL);
2894 memcpy(paging->data,
2895 trans_pcie->init_dram.paging[i].block, page_len);
2896 data = iwl_fw_error_next_data(data);
2897
2898 len += sizeof(*data) + sizeof(*paging) + page_len;
2899 }
2900 }
2901
2902 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2903
2904 dump_data->len = len;
2905
2906 return dump_data;
2907 }
2908
2909 #ifdef CONFIG_PM_SLEEP
iwl_trans_pcie_suspend(struct iwl_trans * trans)2910 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
2911 {
2912 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
2913 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
2914 return iwl_pci_fw_enter_d0i3(trans);
2915
2916 return 0;
2917 }
2918
iwl_trans_pcie_resume(struct iwl_trans * trans)2919 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
2920 {
2921 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
2922 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
2923 iwl_pci_fw_exit_d0i3(trans);
2924 }
2925 #endif /* CONFIG_PM_SLEEP */
2926
2927 #define IWL_TRANS_COMMON_OPS \
2928 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \
2929 .write8 = iwl_trans_pcie_write8, \
2930 .write32 = iwl_trans_pcie_write32, \
2931 .read32 = iwl_trans_pcie_read32, \
2932 .read_prph = iwl_trans_pcie_read_prph, \
2933 .write_prph = iwl_trans_pcie_write_prph, \
2934 .read_mem = iwl_trans_pcie_read_mem, \
2935 .write_mem = iwl_trans_pcie_write_mem, \
2936 .configure = iwl_trans_pcie_configure, \
2937 .set_pmi = iwl_trans_pcie_set_pmi, \
2938 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \
2939 .release_nic_access = iwl_trans_pcie_release_nic_access, \
2940 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \
2941 .ref = iwl_trans_pcie_ref, \
2942 .unref = iwl_trans_pcie_unref, \
2943 .dump_data = iwl_trans_pcie_dump_data, \
2944 .d3_suspend = iwl_trans_pcie_d3_suspend, \
2945 .d3_resume = iwl_trans_pcie_d3_resume
2946
2947 #ifdef CONFIG_PM_SLEEP
2948 #define IWL_TRANS_PM_OPS \
2949 .suspend = iwl_trans_pcie_suspend, \
2950 .resume = iwl_trans_pcie_resume,
2951 #else
2952 #define IWL_TRANS_PM_OPS
2953 #endif /* CONFIG_PM_SLEEP */
2954
2955 static const struct iwl_trans_ops trans_ops_pcie = {
2956 IWL_TRANS_COMMON_OPS,
2957 IWL_TRANS_PM_OPS
2958 .start_hw = iwl_trans_pcie_start_hw,
2959 .fw_alive = iwl_trans_pcie_fw_alive,
2960 .start_fw = iwl_trans_pcie_start_fw,
2961 .stop_device = iwl_trans_pcie_stop_device,
2962
2963 .send_cmd = iwl_trans_pcie_send_hcmd,
2964
2965 .tx = iwl_trans_pcie_tx,
2966 .reclaim = iwl_trans_pcie_reclaim,
2967
2968 .txq_disable = iwl_trans_pcie_txq_disable,
2969 .txq_enable = iwl_trans_pcie_txq_enable,
2970
2971 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
2972
2973 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
2974
2975 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2976 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
2977 };
2978
2979 static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
2980 IWL_TRANS_COMMON_OPS,
2981 IWL_TRANS_PM_OPS
2982 .start_hw = iwl_trans_pcie_start_hw,
2983 .fw_alive = iwl_trans_pcie_gen2_fw_alive,
2984 .start_fw = iwl_trans_pcie_gen2_start_fw,
2985 .stop_device = iwl_trans_pcie_gen2_stop_device,
2986
2987 .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
2988
2989 .tx = iwl_trans_pcie_gen2_tx,
2990 .reclaim = iwl_trans_pcie_reclaim,
2991
2992 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
2993 .txq_free = iwl_trans_pcie_dyn_txq_free,
2994 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
2995 };
2996
iwl_trans_pcie_alloc(struct pci_dev * pdev,const struct pci_device_id * ent,const struct iwl_cfg * cfg)2997 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2998 const struct pci_device_id *ent,
2999 const struct iwl_cfg *cfg)
3000 {
3001 struct iwl_trans_pcie *trans_pcie;
3002 struct iwl_trans *trans;
3003 int ret, addr_size;
3004
3005 ret = pcim_enable_device(pdev);
3006 if (ret)
3007 return ERR_PTR(ret);
3008
3009 if (cfg->gen2)
3010 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3011 &pdev->dev, cfg, &trans_ops_pcie_gen2);
3012 else
3013 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3014 &pdev->dev, cfg, &trans_ops_pcie);
3015 if (!trans)
3016 return ERR_PTR(-ENOMEM);
3017
3018 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3019
3020 trans_pcie->trans = trans;
3021 trans_pcie->opmode_down = true;
3022 spin_lock_init(&trans_pcie->irq_lock);
3023 spin_lock_init(&trans_pcie->reg_lock);
3024 mutex_init(&trans_pcie->mutex);
3025 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
3026
3027 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3028 WQ_HIGHPRI | WQ_UNBOUND, 1);
3029 if (!trans_pcie->rba.alloc_wq) {
3030 ret = -ENOMEM;
3031 goto out_free_trans;
3032 }
3033 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3034
3035 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
3036 if (!trans_pcie->tso_hdr_page) {
3037 ret = -ENOMEM;
3038 goto out_no_pci;
3039 }
3040
3041
3042 if (!cfg->base_params->pcie_l1_allowed) {
3043 /*
3044 * W/A - seems to solve weird behavior. We need to remove this
3045 * if we don't want to stay in L1 all the time. This wastes a
3046 * lot of power.
3047 */
3048 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3049 PCIE_LINK_STATE_L1 |
3050 PCIE_LINK_STATE_CLKPM);
3051 }
3052
3053 if (cfg->use_tfh) {
3054 addr_size = 64;
3055 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
3056 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
3057 } else {
3058 addr_size = 36;
3059 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
3060 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
3061 }
3062 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
3063
3064 pci_set_master(pdev);
3065
3066 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
3067 if (!ret)
3068 ret = pci_set_consistent_dma_mask(pdev,
3069 DMA_BIT_MASK(addr_size));
3070 if (ret) {
3071 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3072 if (!ret)
3073 ret = pci_set_consistent_dma_mask(pdev,
3074 DMA_BIT_MASK(32));
3075 /* both attempts failed: */
3076 if (ret) {
3077 dev_err(&pdev->dev, "No suitable DMA available\n");
3078 goto out_no_pci;
3079 }
3080 }
3081
3082 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
3083 if (ret) {
3084 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3085 goto out_no_pci;
3086 }
3087
3088 trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
3089 if (!trans_pcie->hw_base) {
3090 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
3091 ret = -ENODEV;
3092 goto out_no_pci;
3093 }
3094
3095 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3096 * PCI Tx retries from interfering with C3 CPU state */
3097 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3098
3099 trans_pcie->pci_dev = pdev;
3100 iwl_disable_interrupts(trans);
3101
3102 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
3103 /*
3104 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3105 * changed, and now the revision step also includes bit 0-1 (no more
3106 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3107 * in the old format.
3108 */
3109 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
3110 unsigned long flags;
3111
3112 trans->hw_rev = (trans->hw_rev & 0xfff0) |
3113 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
3114
3115 ret = iwl_pcie_prepare_card_hw(trans);
3116 if (ret) {
3117 IWL_WARN(trans, "Exit HW not ready\n");
3118 goto out_no_pci;
3119 }
3120
3121 /*
3122 * in-order to recognize C step driver should read chip version
3123 * id located at the AUX bus MISC address space.
3124 */
3125 iwl_set_bit(trans, CSR_GP_CNTRL,
3126 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
3127 udelay(2);
3128
3129 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
3130 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3131 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3132 25000);
3133 if (ret < 0) {
3134 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
3135 goto out_no_pci;
3136 }
3137
3138 if (iwl_trans_grab_nic_access(trans, &flags)) {
3139 u32 hw_step;
3140
3141 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
3142 hw_step |= ENABLE_WFPM;
3143 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
3144 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
3145 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
3146 if (hw_step == 0x3)
3147 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
3148 (SILICON_C_STEP << 2);
3149 iwl_trans_release_nic_access(trans, &flags);
3150 }
3151 }
3152
3153 /*
3154 * 9000-series integrated A-step has a problem with suspend/resume
3155 * and sometimes even causes the whole platform to get stuck. This
3156 * workaround makes the hardware not go into the problematic state.
3157 */
3158 if (trans->cfg->integrated &&
3159 trans->cfg->device_family == IWL_DEVICE_FAMILY_9000 &&
3160 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_A_STEP)
3161 iwl_set_bit(trans, CSR_HOST_CHICKEN,
3162 CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME);
3163
3164 #if IS_ENABLED(CONFIG_IWLMVM)
3165 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
3166 if (trans->hw_rf_id == CSR_HW_RF_ID_TYPE_HR) {
3167 u32 hw_status;
3168
3169 hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS);
3170 if (hw_status & UMAG_GEN_HW_IS_FPGA)
3171 trans->cfg = &iwla000_2ax_cfg_qnj_hr_f0;
3172 else
3173 trans->cfg = &iwla000_2ac_cfg_hr;
3174 }
3175 #endif
3176
3177 iwl_pcie_set_interrupt_capa(pdev, trans);
3178 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
3179 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3180 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
3181
3182 /* Initialize the wait queue for commands */
3183 init_waitqueue_head(&trans_pcie->wait_command_queue);
3184
3185 init_waitqueue_head(&trans_pcie->d0i3_waitq);
3186
3187 if (trans_pcie->msix_enabled) {
3188 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3189 if (ret)
3190 goto out_no_pci;
3191 } else {
3192 ret = iwl_pcie_alloc_ict(trans);
3193 if (ret)
3194 goto out_no_pci;
3195
3196 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3197 iwl_pcie_isr,
3198 iwl_pcie_irq_handler,
3199 IRQF_SHARED, DRV_NAME, trans);
3200 if (ret) {
3201 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3202 goto out_free_ict;
3203 }
3204 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3205 }
3206
3207 #ifdef CONFIG_IWLWIFI_PCIE_RTPM
3208 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
3209 #else
3210 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
3211 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3212
3213 return trans;
3214
3215 out_free_ict:
3216 iwl_pcie_free_ict(trans);
3217 out_no_pci:
3218 free_percpu(trans_pcie->tso_hdr_page);
3219 destroy_workqueue(trans_pcie->rba.alloc_wq);
3220 out_free_trans:
3221 iwl_trans_free(trans);
3222 return ERR_PTR(ret);
3223 }
3224