1 /*
2 * PCIe host controller driver for Texas Instruments Keystone SoCs
3 *
4 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
5 * http://www.ti.com
6 *
7 * Author: Murali Karicheri <m-karicheri2@ti.com>
8 * Implementation based on pci-exynos.c and pcie-designware.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/irqchip/chained_irq.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/irqdomain.h>
20 #include <linux/init.h>
21 #include <linux/msi.h>
22 #include <linux/of_irq.h>
23 #include <linux/of.h>
24 #include <linux/of_pci.h>
25 #include <linux/platform_device.h>
26 #include <linux/phy/phy.h>
27 #include <linux/resource.h>
28 #include <linux/signal.h>
29
30 #include "pcie-designware.h"
31 #include "pci-keystone.h"
32
33 #define DRIVER_NAME "keystone-pcie"
34
35 /* DEV_STAT_CTRL */
36 #define PCIE_CAP_BASE 0x70
37
38 /* PCIE controller device IDs */
39 #define PCIE_RC_K2HK 0xb008
40 #define PCIE_RC_K2E 0xb009
41 #define PCIE_RC_K2L 0xb00a
42 #define PCIE_RC_K2G 0xb00b
43
44 #define to_keystone_pcie(x) dev_get_drvdata((x)->dev)
45
quirk_limit_mrrs(struct pci_dev * dev)46 static void quirk_limit_mrrs(struct pci_dev *dev)
47 {
48 struct pci_bus *bus = dev->bus;
49 struct pci_dev *bridge = bus->self;
50 static const struct pci_device_id rc_pci_devids[] = {
51 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK),
52 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
53 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E),
54 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
55 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L),
56 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
57 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2G),
58 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
59 { 0, },
60 };
61
62 if (pci_is_root_bus(bus))
63 return;
64
65 /* look for the host bridge */
66 while (!pci_is_root_bus(bus)) {
67 bridge = bus->self;
68 bus = bus->parent;
69 }
70
71 if (bridge) {
72 /*
73 * Keystone PCI controller has a h/w limitation of
74 * 256 bytes maximum read request size. It can't handle
75 * anything higher than this. So force this limit on
76 * all downstream devices.
77 */
78 if (pci_match_id(rc_pci_devids, bridge)) {
79 if (pcie_get_readrq(dev) > 256) {
80 dev_info(&dev->dev, "limiting MRRS to 256\n");
81 pcie_set_readrq(dev, 256);
82 }
83 }
84 }
85 }
86 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs);
87
ks_pcie_establish_link(struct keystone_pcie * ks_pcie)88 static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
89 {
90 struct dw_pcie *pci = ks_pcie->pci;
91 struct pcie_port *pp = &pci->pp;
92 struct device *dev = pci->dev;
93 unsigned int retries;
94
95 dw_pcie_setup_rc(pp);
96
97 if (dw_pcie_link_up(pci)) {
98 dev_err(dev, "Link already up\n");
99 return 0;
100 }
101
102 /* check if the link is up or not */
103 for (retries = 0; retries < 5; retries++) {
104 ks_dw_pcie_initiate_link_train(ks_pcie);
105 if (!dw_pcie_wait_for_link(pci))
106 return 0;
107 }
108
109 dev_err(dev, "phy link never came up\n");
110 return -ETIMEDOUT;
111 }
112
ks_pcie_msi_irq_handler(struct irq_desc * desc)113 static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
114 {
115 unsigned int irq = irq_desc_get_irq(desc);
116 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
117 u32 offset = irq - ks_pcie->msi_host_irqs[0];
118 struct dw_pcie *pci = ks_pcie->pci;
119 struct device *dev = pci->dev;
120 struct irq_chip *chip = irq_desc_get_chip(desc);
121
122 dev_dbg(dev, "%s, irq %d\n", __func__, irq);
123
124 /*
125 * The chained irq handler installation would have replaced normal
126 * interrupt driver handler so we need to take care of mask/unmask and
127 * ack operation.
128 */
129 chained_irq_enter(chip, desc);
130 ks_dw_pcie_handle_msi_irq(ks_pcie, offset);
131 chained_irq_exit(chip, desc);
132 }
133
134 /**
135 * ks_pcie_legacy_irq_handler() - Handle legacy interrupt
136 * @irq: IRQ line for legacy interrupts
137 * @desc: Pointer to irq descriptor
138 *
139 * Traverse through pending legacy interrupts and invoke handler for each. Also
140 * takes care of interrupt controller level mask/ack operation.
141 */
ks_pcie_legacy_irq_handler(struct irq_desc * desc)142 static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
143 {
144 unsigned int irq = irq_desc_get_irq(desc);
145 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
146 struct dw_pcie *pci = ks_pcie->pci;
147 struct device *dev = pci->dev;
148 u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
149 struct irq_chip *chip = irq_desc_get_chip(desc);
150
151 dev_dbg(dev, ": Handling legacy irq %d\n", irq);
152
153 /*
154 * The chained irq handler installation would have replaced normal
155 * interrupt driver handler so we need to take care of mask/unmask and
156 * ack operation.
157 */
158 chained_irq_enter(chip, desc);
159 ks_dw_pcie_handle_legacy_irq(ks_pcie, irq_offset);
160 chained_irq_exit(chip, desc);
161 }
162
ks_pcie_get_irq_controller_info(struct keystone_pcie * ks_pcie,char * controller,int * num_irqs)163 static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
164 char *controller, int *num_irqs)
165 {
166 int temp, max_host_irqs, legacy = 1, *host_irqs;
167 struct device *dev = ks_pcie->pci->dev;
168 struct device_node *np_pcie = dev->of_node, **np_temp;
169
170 if (!strcmp(controller, "msi-interrupt-controller"))
171 legacy = 0;
172
173 if (legacy) {
174 np_temp = &ks_pcie->legacy_intc_np;
175 max_host_irqs = PCI_NUM_INTX;
176 host_irqs = &ks_pcie->legacy_host_irqs[0];
177 } else {
178 np_temp = &ks_pcie->msi_intc_np;
179 max_host_irqs = MAX_MSI_HOST_IRQS;
180 host_irqs = &ks_pcie->msi_host_irqs[0];
181 }
182
183 /* interrupt controller is in a child node */
184 *np_temp = of_get_child_by_name(np_pcie, controller);
185 if (!(*np_temp)) {
186 dev_err(dev, "Node for %s is absent\n", controller);
187 return -EINVAL;
188 }
189
190 temp = of_irq_count(*np_temp);
191 if (!temp) {
192 dev_err(dev, "No IRQ entries in %s\n", controller);
193 of_node_put(*np_temp);
194 return -EINVAL;
195 }
196
197 if (temp > max_host_irqs)
198 dev_warn(dev, "Too many %s interrupts defined %u\n",
199 (legacy ? "legacy" : "MSI"), temp);
200
201 /*
202 * support upto max_host_irqs. In dt from index 0 to 3 (legacy) or 0 to
203 * 7 (MSI)
204 */
205 for (temp = 0; temp < max_host_irqs; temp++) {
206 host_irqs[temp] = irq_of_parse_and_map(*np_temp, temp);
207 if (!host_irqs[temp])
208 break;
209 }
210
211 of_node_put(*np_temp);
212
213 if (temp) {
214 *num_irqs = temp;
215 return 0;
216 }
217
218 return -EINVAL;
219 }
220
ks_pcie_setup_interrupts(struct keystone_pcie * ks_pcie)221 static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
222 {
223 int i;
224
225 /* Legacy IRQ */
226 for (i = 0; i < ks_pcie->num_legacy_host_irqs; i++) {
227 irq_set_chained_handler_and_data(ks_pcie->legacy_host_irqs[i],
228 ks_pcie_legacy_irq_handler,
229 ks_pcie);
230 }
231 ks_dw_pcie_enable_legacy_irqs(ks_pcie);
232
233 /* MSI IRQ */
234 if (IS_ENABLED(CONFIG_PCI_MSI)) {
235 for (i = 0; i < ks_pcie->num_msi_host_irqs; i++) {
236 irq_set_chained_handler_and_data(ks_pcie->msi_host_irqs[i],
237 ks_pcie_msi_irq_handler,
238 ks_pcie);
239 }
240 }
241
242 if (ks_pcie->error_irq > 0)
243 ks_dw_pcie_enable_error_irq(ks_pcie);
244 }
245
246 #ifdef CONFIG_ARM
247 /*
248 * When a PCI device does not exist during config cycles, keystone host gets a
249 * bus error instead of returning 0xffffffff. This handler always returns 0
250 * for this kind of faults.
251 */
keystone_pcie_fault(unsigned long addr,unsigned int fsr,struct pt_regs * regs)252 static int keystone_pcie_fault(unsigned long addr, unsigned int fsr,
253 struct pt_regs *regs)
254 {
255 unsigned long instr = *(unsigned long *) instruction_pointer(regs);
256
257 if ((instr & 0x0e100090) == 0x00100090) {
258 int reg = (instr >> 12) & 15;
259
260 regs->uregs[reg] = -1;
261 regs->ARM_pc += 4;
262 }
263
264 return 0;
265 }
266 #endif
267
ks_pcie_host_init(struct pcie_port * pp)268 static int __init ks_pcie_host_init(struct pcie_port *pp)
269 {
270 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
271 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
272 u32 val;
273
274 ks_pcie_establish_link(ks_pcie);
275 ks_dw_pcie_setup_rc_app_regs(ks_pcie);
276 ks_pcie_setup_interrupts(ks_pcie);
277 writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
278 pci->dbi_base + PCI_IO_BASE);
279
280 /* update the Vendor ID */
281 writew(ks_pcie->device_id, pci->dbi_base + PCI_DEVICE_ID);
282
283 /* update the DEV_STAT_CTRL to publish right mrrs */
284 val = readl(pci->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
285 val &= ~PCI_EXP_DEVCTL_READRQ;
286 /* set the mrrs to 256 bytes */
287 val |= BIT(12);
288 writel(val, pci->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
289
290 #ifdef CONFIG_ARM
291 /*
292 * PCIe access errors that result into OCP errors are caught by ARM as
293 * "External aborts"
294 */
295 hook_fault_code(17, keystone_pcie_fault, SIGBUS, 0,
296 "Asynchronous external abort");
297 #endif
298
299 return 0;
300 }
301
302 static const struct dw_pcie_host_ops keystone_pcie_host_ops = {
303 .rd_other_conf = ks_dw_pcie_rd_other_conf,
304 .wr_other_conf = ks_dw_pcie_wr_other_conf,
305 .host_init = ks_pcie_host_init,
306 .msi_set_irq = ks_dw_pcie_msi_set_irq,
307 .msi_clear_irq = ks_dw_pcie_msi_clear_irq,
308 .get_msi_addr = ks_dw_pcie_get_msi_addr,
309 .msi_host_init = ks_dw_pcie_msi_host_init,
310 .scan_bus = ks_dw_pcie_v3_65_scan_bus,
311 };
312
pcie_err_irq_handler(int irq,void * priv)313 static irqreturn_t pcie_err_irq_handler(int irq, void *priv)
314 {
315 struct keystone_pcie *ks_pcie = priv;
316
317 return ks_dw_pcie_handle_error_irq(ks_pcie);
318 }
319
ks_add_pcie_port(struct keystone_pcie * ks_pcie,struct platform_device * pdev)320 static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
321 struct platform_device *pdev)
322 {
323 struct dw_pcie *pci = ks_pcie->pci;
324 struct pcie_port *pp = &pci->pp;
325 struct device *dev = &pdev->dev;
326 int ret;
327
328 ret = ks_pcie_get_irq_controller_info(ks_pcie,
329 "legacy-interrupt-controller",
330 &ks_pcie->num_legacy_host_irqs);
331 if (ret)
332 return ret;
333
334 if (IS_ENABLED(CONFIG_PCI_MSI)) {
335 ret = ks_pcie_get_irq_controller_info(ks_pcie,
336 "msi-interrupt-controller",
337 &ks_pcie->num_msi_host_irqs);
338 if (ret)
339 return ret;
340 }
341
342 /*
343 * Index 0 is the platform interrupt for error interrupt
344 * from RC. This is optional.
345 */
346 ks_pcie->error_irq = irq_of_parse_and_map(ks_pcie->np, 0);
347 if (ks_pcie->error_irq <= 0)
348 dev_info(dev, "no error IRQ defined\n");
349 else {
350 ret = request_irq(ks_pcie->error_irq, pcie_err_irq_handler,
351 IRQF_SHARED, "pcie-error-irq", ks_pcie);
352 if (ret < 0) {
353 dev_err(dev, "failed to request error IRQ %d\n",
354 ks_pcie->error_irq);
355 return ret;
356 }
357 }
358
359 pp->root_bus_nr = -1;
360 pp->ops = &keystone_pcie_host_ops;
361 ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np);
362 if (ret) {
363 dev_err(dev, "failed to initialize host\n");
364 return ret;
365 }
366
367 return 0;
368 }
369
370 static const struct of_device_id ks_pcie_of_match[] = {
371 {
372 .type = "pci",
373 .compatible = "ti,keystone-pcie",
374 },
375 { },
376 };
377
378 static const struct dw_pcie_ops dw_pcie_ops = {
379 .link_up = ks_dw_pcie_link_up,
380 };
381
ks_pcie_remove(struct platform_device * pdev)382 static int __exit ks_pcie_remove(struct platform_device *pdev)
383 {
384 struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
385
386 clk_disable_unprepare(ks_pcie->clk);
387
388 return 0;
389 }
390
ks_pcie_probe(struct platform_device * pdev)391 static int __init ks_pcie_probe(struct platform_device *pdev)
392 {
393 struct device *dev = &pdev->dev;
394 struct dw_pcie *pci;
395 struct keystone_pcie *ks_pcie;
396 struct resource *res;
397 void __iomem *reg_p;
398 struct phy *phy;
399 int ret;
400
401 ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL);
402 if (!ks_pcie)
403 return -ENOMEM;
404
405 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
406 if (!pci)
407 return -ENOMEM;
408
409 pci->dev = dev;
410 pci->ops = &dw_pcie_ops;
411
412 ks_pcie->pci = pci;
413
414 /* initialize SerDes Phy if present */
415 phy = devm_phy_get(dev, "pcie-phy");
416 if (PTR_ERR_OR_ZERO(phy) == -EPROBE_DEFER)
417 return PTR_ERR(phy);
418
419 if (!IS_ERR_OR_NULL(phy)) {
420 ret = phy_init(phy);
421 if (ret < 0)
422 return ret;
423 }
424
425 /* index 2 is to read PCI DEVICE_ID */
426 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
427 reg_p = devm_ioremap_resource(dev, res);
428 if (IS_ERR(reg_p))
429 return PTR_ERR(reg_p);
430 ks_pcie->device_id = readl(reg_p) >> 16;
431 devm_iounmap(dev, reg_p);
432 devm_release_mem_region(dev, res->start, resource_size(res));
433
434 ks_pcie->np = dev->of_node;
435 platform_set_drvdata(pdev, ks_pcie);
436 ks_pcie->clk = devm_clk_get(dev, "pcie");
437 if (IS_ERR(ks_pcie->clk)) {
438 dev_err(dev, "Failed to get pcie rc clock\n");
439 return PTR_ERR(ks_pcie->clk);
440 }
441 ret = clk_prepare_enable(ks_pcie->clk);
442 if (ret)
443 return ret;
444
445 platform_set_drvdata(pdev, ks_pcie);
446
447 ret = ks_add_pcie_port(ks_pcie, pdev);
448 if (ret < 0)
449 goto fail_clk;
450
451 return 0;
452 fail_clk:
453 clk_disable_unprepare(ks_pcie->clk);
454
455 return ret;
456 }
457
458 static struct platform_driver ks_pcie_driver __refdata = {
459 .probe = ks_pcie_probe,
460 .remove = __exit_p(ks_pcie_remove),
461 .driver = {
462 .name = "keystone-pcie",
463 .of_match_table = of_match_ptr(ks_pcie_of_match),
464 },
465 };
466 builtin_platform_driver(ks_pcie_driver);
467