1 /*
2 * pci-rcar-gen2: internal PCI bus support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Cogent Embedded, Inc.
6 *
7 * Author: Valentine Barshak <valentine.barshak@cogentembedded.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/delay.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/kernel.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21 #include <linux/pci.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/sizes.h>
25 #include <linux/slab.h>
26
27 /* AHB-PCI Bridge PCI communication registers */
28 #define RCAR_AHBPCI_PCICOM_OFFSET 0x800
29
30 #define RCAR_PCIAHB_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
31 #define RCAR_PCIAHB_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
32 #define RCAR_PCIAHB_PREFETCH0 0x0
33 #define RCAR_PCIAHB_PREFETCH4 0x1
34 #define RCAR_PCIAHB_PREFETCH8 0x2
35 #define RCAR_PCIAHB_PREFETCH16 0x3
36
37 #define RCAR_AHBPCI_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
38 #define RCAR_AHBPCI_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
39 #define RCAR_AHBPCI_WIN_CTR_MEM (3 << 1)
40 #define RCAR_AHBPCI_WIN_CTR_CFG (5 << 1)
41 #define RCAR_AHBPCI_WIN1_HOST (1 << 30)
42 #define RCAR_AHBPCI_WIN1_DEVICE (1 << 31)
43
44 #define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
45 #define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
46 #define RCAR_PCI_INT_SIGTABORT (1 << 0)
47 #define RCAR_PCI_INT_SIGRETABORT (1 << 1)
48 #define RCAR_PCI_INT_REMABORT (1 << 2)
49 #define RCAR_PCI_INT_PERR (1 << 3)
50 #define RCAR_PCI_INT_SIGSERR (1 << 4)
51 #define RCAR_PCI_INT_RESERR (1 << 5)
52 #define RCAR_PCI_INT_WIN1ERR (1 << 12)
53 #define RCAR_PCI_INT_WIN2ERR (1 << 13)
54 #define RCAR_PCI_INT_A (1 << 16)
55 #define RCAR_PCI_INT_B (1 << 17)
56 #define RCAR_PCI_INT_PME (1 << 19)
57 #define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT | \
58 RCAR_PCI_INT_SIGRETABORT | \
59 RCAR_PCI_INT_SIGRETABORT | \
60 RCAR_PCI_INT_REMABORT | \
61 RCAR_PCI_INT_PERR | \
62 RCAR_PCI_INT_SIGSERR | \
63 RCAR_PCI_INT_RESERR | \
64 RCAR_PCI_INT_WIN1ERR | \
65 RCAR_PCI_INT_WIN2ERR)
66
67 #define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
68 #define RCAR_AHB_BUS_MMODE_HTRANS (1 << 0)
69 #define RCAR_AHB_BUS_MMODE_BYTE_BURST (1 << 1)
70 #define RCAR_AHB_BUS_MMODE_WR_INCR (1 << 2)
71 #define RCAR_AHB_BUS_MMODE_HBUS_REQ (1 << 7)
72 #define RCAR_AHB_BUS_SMODE_READYCTR (1 << 17)
73 #define RCAR_AHB_BUS_MODE (RCAR_AHB_BUS_MMODE_HTRANS | \
74 RCAR_AHB_BUS_MMODE_BYTE_BURST | \
75 RCAR_AHB_BUS_MMODE_WR_INCR | \
76 RCAR_AHB_BUS_MMODE_HBUS_REQ | \
77 RCAR_AHB_BUS_SMODE_READYCTR)
78
79 #define RCAR_USBCTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
80 #define RCAR_USBCTR_USBH_RST (1 << 0)
81 #define RCAR_USBCTR_PCICLK_MASK (1 << 1)
82 #define RCAR_USBCTR_PLL_RST (1 << 2)
83 #define RCAR_USBCTR_DIRPD (1 << 8)
84 #define RCAR_USBCTR_PCIAHB_WIN2_EN (1 << 9)
85 #define RCAR_USBCTR_PCIAHB_WIN1_256M (0 << 10)
86 #define RCAR_USBCTR_PCIAHB_WIN1_512M (1 << 10)
87 #define RCAR_USBCTR_PCIAHB_WIN1_1G (2 << 10)
88 #define RCAR_USBCTR_PCIAHB_WIN1_2G (3 << 10)
89 #define RCAR_USBCTR_PCIAHB_WIN1_MASK (3 << 10)
90
91 #define RCAR_PCI_ARBITER_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
92 #define RCAR_PCI_ARBITER_PCIREQ0 (1 << 0)
93 #define RCAR_PCI_ARBITER_PCIREQ1 (1 << 1)
94 #define RCAR_PCI_ARBITER_PCIBP_MODE (1 << 12)
95
96 #define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
97
98 struct rcar_pci_priv {
99 struct device *dev;
100 void __iomem *reg;
101 struct resource mem_res;
102 struct resource *cfg_res;
103 unsigned busnr;
104 int irq;
105 unsigned long window_size;
106 unsigned long window_addr;
107 unsigned long window_pci;
108 };
109
110 /* PCI configuration space operations */
rcar_pci_cfg_base(struct pci_bus * bus,unsigned int devfn,int where)111 static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn,
112 int where)
113 {
114 struct pci_sys_data *sys = bus->sysdata;
115 struct rcar_pci_priv *priv = sys->private_data;
116 int slot, val;
117
118 if (sys->busnr != bus->number || PCI_FUNC(devfn))
119 return NULL;
120
121 /* Only one EHCI/OHCI device built-in */
122 slot = PCI_SLOT(devfn);
123 if (slot > 2)
124 return NULL;
125
126 /* bridge logic only has registers to 0x40 */
127 if (slot == 0x0 && where >= 0x40)
128 return NULL;
129
130 val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG :
131 RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG;
132
133 iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG);
134 return priv->reg + (slot >> 1) * 0x100 + where;
135 }
136
137 /* PCI interrupt mapping */
rcar_pci_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)138 static int rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
139 {
140 struct pci_sys_data *sys = dev->bus->sysdata;
141 struct rcar_pci_priv *priv = sys->private_data;
142 int irq;
143
144 irq = of_irq_parse_and_map_pci(dev, slot, pin);
145 if (!irq)
146 irq = priv->irq;
147
148 return irq;
149 }
150
151 #ifdef CONFIG_PCI_DEBUG
152 /* if debug enabled, then attach an error handler irq to the bridge */
153
rcar_pci_err_irq(int irq,void * pw)154 static irqreturn_t rcar_pci_err_irq(int irq, void *pw)
155 {
156 struct rcar_pci_priv *priv = pw;
157 struct device *dev = priv->dev;
158 u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG);
159
160 if (status & RCAR_PCI_INT_ALLERRORS) {
161 dev_err(dev, "error irq: status %08x\n", status);
162
163 /* clear the error(s) */
164 iowrite32(status & RCAR_PCI_INT_ALLERRORS,
165 priv->reg + RCAR_PCI_INT_STATUS_REG);
166 return IRQ_HANDLED;
167 }
168
169 return IRQ_NONE;
170 }
171
rcar_pci_setup_errirq(struct rcar_pci_priv * priv)172 static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv)
173 {
174 struct device *dev = priv->dev;
175 int ret;
176 u32 val;
177
178 ret = devm_request_irq(dev, priv->irq, rcar_pci_err_irq,
179 IRQF_SHARED, "error irq", priv);
180 if (ret) {
181 dev_err(dev, "cannot claim IRQ for error handling\n");
182 return;
183 }
184
185 val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG);
186 val |= RCAR_PCI_INT_ALLERRORS;
187 iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG);
188 }
189 #else
rcar_pci_setup_errirq(struct rcar_pci_priv * priv)190 static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { }
191 #endif
192
193 /* PCI host controller setup */
rcar_pci_setup(int nr,struct pci_sys_data * sys)194 static int rcar_pci_setup(int nr, struct pci_sys_data *sys)
195 {
196 struct rcar_pci_priv *priv = sys->private_data;
197 struct device *dev = priv->dev;
198 void __iomem *reg = priv->reg;
199 u32 val;
200 int ret;
201
202 pm_runtime_enable(dev);
203 pm_runtime_get_sync(dev);
204
205 val = ioread32(reg + RCAR_PCI_UNIT_REV_REG);
206 dev_info(dev, "PCI: bus%u revision %x\n", sys->busnr, val);
207
208 /* Disable Direct Power Down State and assert reset */
209 val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD;
210 val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST;
211 iowrite32(val, reg + RCAR_USBCTR_REG);
212 udelay(4);
213
214 /* De-assert reset and reset PCIAHB window1 size */
215 val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK |
216 RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST);
217
218 /* Setup PCIAHB window1 size */
219 switch (priv->window_size) {
220 case SZ_2G:
221 val |= RCAR_USBCTR_PCIAHB_WIN1_2G;
222 break;
223 case SZ_1G:
224 val |= RCAR_USBCTR_PCIAHB_WIN1_1G;
225 break;
226 case SZ_512M:
227 val |= RCAR_USBCTR_PCIAHB_WIN1_512M;
228 break;
229 default:
230 pr_warn("unknown window size %ld - defaulting to 256M\n",
231 priv->window_size);
232 priv->window_size = SZ_256M;
233 /* fall-through */
234 case SZ_256M:
235 val |= RCAR_USBCTR_PCIAHB_WIN1_256M;
236 break;
237 }
238 iowrite32(val, reg + RCAR_USBCTR_REG);
239
240 /* Configure AHB master and slave modes */
241 iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);
242
243 /* Configure PCI arbiter */
244 val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG);
245 val |= RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
246 RCAR_PCI_ARBITER_PCIBP_MODE;
247 iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
248
249 /* PCI-AHB mapping */
250 iowrite32(priv->window_addr | RCAR_PCIAHB_PREFETCH16,
251 reg + RCAR_PCIAHB_WIN1_CTR_REG);
252
253 /* AHB-PCI mapping: OHCI/EHCI registers */
254 val = priv->mem_res.start | RCAR_AHBPCI_WIN_CTR_MEM;
255 iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG);
256
257 /* Enable AHB-PCI bridge PCI configuration access */
258 iowrite32(RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG,
259 reg + RCAR_AHBPCI_WIN1_CTR_REG);
260 /* Set PCI-AHB Window1 address */
261 iowrite32(priv->window_pci | PCI_BASE_ADDRESS_MEM_PREFETCH,
262 reg + PCI_BASE_ADDRESS_1);
263 /* Set AHB-PCI bridge PCI communication area address */
264 val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET;
265 iowrite32(val, reg + PCI_BASE_ADDRESS_0);
266
267 val = ioread32(reg + PCI_COMMAND);
268 val |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
269 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
270 iowrite32(val, reg + PCI_COMMAND);
271
272 /* Enable PCI interrupts */
273 iowrite32(RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME,
274 reg + RCAR_PCI_INT_ENABLE_REG);
275
276 if (priv->irq > 0)
277 rcar_pci_setup_errirq(priv);
278
279 /* Add PCI resources */
280 pci_add_resource(&sys->resources, &priv->mem_res);
281 ret = devm_request_pci_bus_resources(dev, &sys->resources);
282 if (ret < 0)
283 return ret;
284
285 /* Setup bus number based on platform device id / of bus-range */
286 sys->busnr = priv->busnr;
287 return 1;
288 }
289
290 static struct pci_ops rcar_pci_ops = {
291 .map_bus = rcar_pci_cfg_base,
292 .read = pci_generic_config_read,
293 .write = pci_generic_config_write,
294 };
295
pci_dma_range_parser_init(struct of_pci_range_parser * parser,struct device_node * node)296 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
297 struct device_node *node)
298 {
299 const int na = 3, ns = 2;
300 int rlen;
301
302 parser->node = node;
303 parser->pna = of_n_addr_cells(node);
304 parser->np = parser->pna + na + ns;
305
306 parser->range = of_get_property(node, "dma-ranges", &rlen);
307 if (!parser->range)
308 return -ENOENT;
309
310 parser->end = parser->range + rlen / sizeof(__be32);
311 return 0;
312 }
313
rcar_pci_parse_map_dma_ranges(struct rcar_pci_priv * pci,struct device_node * np)314 static int rcar_pci_parse_map_dma_ranges(struct rcar_pci_priv *pci,
315 struct device_node *np)
316 {
317 struct device *dev = pci->dev;
318 struct of_pci_range range;
319 struct of_pci_range_parser parser;
320 int index = 0;
321
322 /* Failure to parse is ok as we fall back to defaults */
323 if (pci_dma_range_parser_init(&parser, np))
324 return 0;
325
326 /* Get the dma-ranges from DT */
327 for_each_of_pci_range(&parser, &range) {
328 /* Hardware only allows one inbound 32-bit range */
329 if (index)
330 return -EINVAL;
331
332 pci->window_addr = (unsigned long)range.cpu_addr;
333 pci->window_pci = (unsigned long)range.pci_addr;
334 pci->window_size = (unsigned long)range.size;
335
336 /* Catch HW limitations */
337 if (!(range.flags & IORESOURCE_PREFETCH)) {
338 dev_err(dev, "window must be prefetchable\n");
339 return -EINVAL;
340 }
341 if (pci->window_addr) {
342 u32 lowaddr = 1 << (ffs(pci->window_addr) - 1);
343
344 if (lowaddr < pci->window_size) {
345 dev_err(dev, "invalid window size/addr\n");
346 return -EINVAL;
347 }
348 }
349 index++;
350 }
351
352 return 0;
353 }
354
rcar_pci_probe(struct platform_device * pdev)355 static int rcar_pci_probe(struct platform_device *pdev)
356 {
357 struct device *dev = &pdev->dev;
358 struct resource *cfg_res, *mem_res;
359 struct rcar_pci_priv *priv;
360 void __iomem *reg;
361 struct hw_pci hw;
362 void *hw_private[1];
363
364 cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
365 reg = devm_ioremap_resource(dev, cfg_res);
366 if (IS_ERR(reg))
367 return PTR_ERR(reg);
368
369 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
370 if (!mem_res || !mem_res->start)
371 return -ENODEV;
372
373 if (mem_res->start & 0xFFFF)
374 return -EINVAL;
375
376 priv = devm_kzalloc(dev, sizeof(struct rcar_pci_priv), GFP_KERNEL);
377 if (!priv)
378 return -ENOMEM;
379
380 priv->mem_res = *mem_res;
381 priv->cfg_res = cfg_res;
382
383 priv->irq = platform_get_irq(pdev, 0);
384 priv->reg = reg;
385 priv->dev = dev;
386
387 if (priv->irq < 0) {
388 dev_err(dev, "no valid irq found\n");
389 return priv->irq;
390 }
391
392 /* default window addr and size if not specified in DT */
393 priv->window_addr = 0x40000000;
394 priv->window_pci = 0x40000000;
395 priv->window_size = SZ_1G;
396
397 if (dev->of_node) {
398 struct resource busnr;
399 int ret;
400
401 ret = of_pci_parse_bus_range(dev->of_node, &busnr);
402 if (ret < 0) {
403 dev_err(dev, "failed to parse bus-range\n");
404 return ret;
405 }
406
407 priv->busnr = busnr.start;
408 if (busnr.end != busnr.start)
409 dev_warn(dev, "only one bus number supported\n");
410
411 ret = rcar_pci_parse_map_dma_ranges(priv, dev->of_node);
412 if (ret < 0) {
413 dev_err(dev, "failed to parse dma-range\n");
414 return ret;
415 }
416 } else {
417 priv->busnr = pdev->id;
418 }
419
420 hw_private[0] = priv;
421 memset(&hw, 0, sizeof(hw));
422 hw.nr_controllers = ARRAY_SIZE(hw_private);
423 hw.io_optional = 1;
424 hw.private_data = hw_private;
425 hw.map_irq = rcar_pci_map_irq;
426 hw.ops = &rcar_pci_ops;
427 hw.setup = rcar_pci_setup;
428 pci_common_init_dev(dev, &hw);
429 return 0;
430 }
431
432 static const struct of_device_id rcar_pci_of_match[] = {
433 { .compatible = "renesas,pci-r8a7790", },
434 { .compatible = "renesas,pci-r8a7791", },
435 { .compatible = "renesas,pci-r8a7794", },
436 { .compatible = "renesas,pci-rcar-gen2", },
437 { },
438 };
439
440 static struct platform_driver rcar_pci_driver = {
441 .driver = {
442 .name = "pci-rcar-gen2",
443 .suppress_bind_attrs = true,
444 .of_match_table = rcar_pci_of_match,
445 },
446 .probe = rcar_pci_probe,
447 };
448 builtin_platform_driver(rcar_pci_driver);
449