1 /*
2 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
3 *
4 * Author: Ley Foon Tan <lftan@altera.com>
5 * Description: Altera PCIe host controller driver
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/irqchip/chained_irq.h>
23 #include <linux/init.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_pci.h>
27 #include <linux/pci.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
30
31 #define RP_TX_REG0 0x2000
32 #define RP_TX_REG1 0x2004
33 #define RP_TX_CNTRL 0x2008
34 #define RP_TX_EOP 0x2
35 #define RP_TX_SOP 0x1
36 #define RP_RXCPL_STATUS 0x2010
37 #define RP_RXCPL_EOP 0x2
38 #define RP_RXCPL_SOP 0x1
39 #define RP_RXCPL_REG0 0x2014
40 #define RP_RXCPL_REG1 0x2018
41 #define P2A_INT_STATUS 0x3060
42 #define P2A_INT_STS_ALL 0xf
43 #define P2A_INT_ENABLE 0x3070
44 #define P2A_INT_ENA_ALL 0xf
45 #define RP_LTSSM 0x3c64
46 #define RP_LTSSM_MASK 0x1f
47 #define LTSSM_L0 0xf
48
49 #define PCIE_CAP_OFFSET 0x80
50 /* TLP configuration type 0 and 1 */
51 #define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */
52 #define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */
53 #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
54 #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
55 #define TLP_PAYLOAD_SIZE 0x01
56 #define TLP_READ_TAG 0x1d
57 #define TLP_WRITE_TAG 0x10
58 #define RP_DEVFN 0
59 #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
60 #define TLP_CFGRD_DW0(pcie, bus) \
61 ((((bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 \
62 : TLP_FMTTYPE_CFGRD1) << 24) | \
63 TLP_PAYLOAD_SIZE)
64 #define TLP_CFGWR_DW0(pcie, bus) \
65 ((((bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0 \
66 : TLP_FMTTYPE_CFGWR1) << 24) | \
67 TLP_PAYLOAD_SIZE)
68 #define TLP_CFG_DW1(pcie, tag, be) \
69 (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
70 #define TLP_CFG_DW2(bus, devfn, offset) \
71 (((bus) << 24) | ((devfn) << 16) | (offset))
72 #define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
73 #define TLP_HDR_SIZE 3
74 #define TLP_LOOP 500
75
76 #define LINK_UP_TIMEOUT HZ
77 #define LINK_RETRAIN_TIMEOUT HZ
78
79 #define DWORD_MASK 3
80
81 struct altera_pcie {
82 struct platform_device *pdev;
83 void __iomem *cra_base; /* DT Cra */
84 int irq;
85 u8 root_bus_nr;
86 struct irq_domain *irq_domain;
87 struct resource bus_range;
88 struct list_head resources;
89 };
90
91 struct tlp_rp_regpair_t {
92 u32 ctrl;
93 u32 reg0;
94 u32 reg1;
95 };
96
cra_writel(struct altera_pcie * pcie,const u32 value,const u32 reg)97 static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
98 const u32 reg)
99 {
100 writel_relaxed(value, pcie->cra_base + reg);
101 }
102
cra_readl(struct altera_pcie * pcie,const u32 reg)103 static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
104 {
105 return readl_relaxed(pcie->cra_base + reg);
106 }
107
altera_pcie_link_is_up(struct altera_pcie * pcie)108 static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
109 {
110 return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
111 }
112
113 /*
114 * Altera PCIe port uses BAR0 of RC's configuration space as the translation
115 * from PCI bus to native BUS. Entire DDR region is mapped into PCIe space
116 * using these registers, so it can be reached by DMA from EP devices.
117 * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
118 * from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge
119 * should be hidden during enumeration to avoid the sizing and resource
120 * allocation by PCIe core.
121 */
altera_pcie_hide_rc_bar(struct pci_bus * bus,unsigned int devfn,int offset)122 static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn,
123 int offset)
124 {
125 if (pci_is_root_bus(bus) && (devfn == 0) &&
126 (offset == PCI_BASE_ADDRESS_0))
127 return true;
128
129 return false;
130 }
131
tlp_write_tx(struct altera_pcie * pcie,struct tlp_rp_regpair_t * tlp_rp_regdata)132 static void tlp_write_tx(struct altera_pcie *pcie,
133 struct tlp_rp_regpair_t *tlp_rp_regdata)
134 {
135 cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
136 cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
137 cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
138 }
139
altera_pcie_valid_device(struct altera_pcie * pcie,struct pci_bus * bus,int dev)140 static bool altera_pcie_valid_device(struct altera_pcie *pcie,
141 struct pci_bus *bus, int dev)
142 {
143 /* If there is no link, then there is no device */
144 if (bus->number != pcie->root_bus_nr) {
145 if (!altera_pcie_link_is_up(pcie))
146 return false;
147 }
148
149 /* access only one slot on each root port */
150 if (bus->number == pcie->root_bus_nr && dev > 0)
151 return false;
152
153 return true;
154 }
155
tlp_read_packet(struct altera_pcie * pcie,u32 * value)156 static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
157 {
158 int i;
159 bool sop = 0;
160 u32 ctrl;
161 u32 reg0, reg1;
162 u32 comp_status = 1;
163
164 /*
165 * Minimum 2 loops to read TLP headers and 1 loop to read data
166 * payload.
167 */
168 for (i = 0; i < TLP_LOOP; i++) {
169 ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
170 if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {
171 reg0 = cra_readl(pcie, RP_RXCPL_REG0);
172 reg1 = cra_readl(pcie, RP_RXCPL_REG1);
173
174 if (ctrl & RP_RXCPL_SOP) {
175 sop = true;
176 comp_status = TLP_COMP_STATUS(reg1);
177 }
178
179 if (ctrl & RP_RXCPL_EOP) {
180 if (comp_status)
181 return PCIBIOS_DEVICE_NOT_FOUND;
182
183 if (value)
184 *value = reg0;
185
186 return PCIBIOS_SUCCESSFUL;
187 }
188 }
189 udelay(5);
190 }
191
192 return PCIBIOS_DEVICE_NOT_FOUND;
193 }
194
tlp_write_packet(struct altera_pcie * pcie,u32 * headers,u32 data,bool align)195 static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
196 u32 data, bool align)
197 {
198 struct tlp_rp_regpair_t tlp_rp_regdata;
199
200 tlp_rp_regdata.reg0 = headers[0];
201 tlp_rp_regdata.reg1 = headers[1];
202 tlp_rp_regdata.ctrl = RP_TX_SOP;
203 tlp_write_tx(pcie, &tlp_rp_regdata);
204
205 if (align) {
206 tlp_rp_regdata.reg0 = headers[2];
207 tlp_rp_regdata.reg1 = 0;
208 tlp_rp_regdata.ctrl = 0;
209 tlp_write_tx(pcie, &tlp_rp_regdata);
210
211 tlp_rp_regdata.reg0 = data;
212 tlp_rp_regdata.reg1 = 0;
213 } else {
214 tlp_rp_regdata.reg0 = headers[2];
215 tlp_rp_regdata.reg1 = data;
216 }
217
218 tlp_rp_regdata.ctrl = RP_TX_EOP;
219 tlp_write_tx(pcie, &tlp_rp_regdata);
220 }
221
tlp_cfg_dword_read(struct altera_pcie * pcie,u8 bus,u32 devfn,int where,u8 byte_en,u32 * value)222 static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
223 int where, u8 byte_en, u32 *value)
224 {
225 u32 headers[TLP_HDR_SIZE];
226
227 headers[0] = TLP_CFGRD_DW0(pcie, bus);
228 headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
229 headers[2] = TLP_CFG_DW2(bus, devfn, where);
230
231 tlp_write_packet(pcie, headers, 0, false);
232
233 return tlp_read_packet(pcie, value);
234 }
235
tlp_cfg_dword_write(struct altera_pcie * pcie,u8 bus,u32 devfn,int where,u8 byte_en,u32 value)236 static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
237 int where, u8 byte_en, u32 value)
238 {
239 u32 headers[TLP_HDR_SIZE];
240 int ret;
241
242 headers[0] = TLP_CFGWR_DW0(pcie, bus);
243 headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en);
244 headers[2] = TLP_CFG_DW2(bus, devfn, where);
245
246 /* check alignment to Qword */
247 if ((where & 0x7) == 0)
248 tlp_write_packet(pcie, headers, value, true);
249 else
250 tlp_write_packet(pcie, headers, value, false);
251
252 ret = tlp_read_packet(pcie, NULL);
253 if (ret != PCIBIOS_SUCCESSFUL)
254 return ret;
255
256 /*
257 * Monitor changes to PCI_PRIMARY_BUS register on root port
258 * and update local copy of root bus number accordingly.
259 */
260 if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
261 pcie->root_bus_nr = (u8)(value);
262
263 return PCIBIOS_SUCCESSFUL;
264 }
265
_altera_pcie_cfg_read(struct altera_pcie * pcie,u8 busno,unsigned int devfn,int where,int size,u32 * value)266 static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,
267 unsigned int devfn, int where, int size,
268 u32 *value)
269 {
270 int ret;
271 u32 data;
272 u8 byte_en;
273
274 switch (size) {
275 case 1:
276 byte_en = 1 << (where & 3);
277 break;
278 case 2:
279 byte_en = 3 << (where & 3);
280 break;
281 default:
282 byte_en = 0xf;
283 break;
284 }
285
286 ret = tlp_cfg_dword_read(pcie, busno, devfn,
287 (where & ~DWORD_MASK), byte_en, &data);
288 if (ret != PCIBIOS_SUCCESSFUL)
289 return ret;
290
291 switch (size) {
292 case 1:
293 *value = (data >> (8 * (where & 0x3))) & 0xff;
294 break;
295 case 2:
296 *value = (data >> (8 * (where & 0x2))) & 0xffff;
297 break;
298 default:
299 *value = data;
300 break;
301 }
302
303 return PCIBIOS_SUCCESSFUL;
304 }
305
_altera_pcie_cfg_write(struct altera_pcie * pcie,u8 busno,unsigned int devfn,int where,int size,u32 value)306 static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno,
307 unsigned int devfn, int where, int size,
308 u32 value)
309 {
310 u32 data32;
311 u32 shift = 8 * (where & 3);
312 u8 byte_en;
313
314 switch (size) {
315 case 1:
316 data32 = (value & 0xff) << shift;
317 byte_en = 1 << (where & 3);
318 break;
319 case 2:
320 data32 = (value & 0xffff) << shift;
321 byte_en = 3 << (where & 3);
322 break;
323 default:
324 data32 = value;
325 byte_en = 0xf;
326 break;
327 }
328
329 return tlp_cfg_dword_write(pcie, busno, devfn, (where & ~DWORD_MASK),
330 byte_en, data32);
331 }
332
altera_pcie_cfg_read(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * value)333 static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
334 int where, int size, u32 *value)
335 {
336 struct altera_pcie *pcie = bus->sysdata;
337
338 if (altera_pcie_hide_rc_bar(bus, devfn, where))
339 return PCIBIOS_BAD_REGISTER_NUMBER;
340
341 if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn))) {
342 *value = 0xffffffff;
343 return PCIBIOS_DEVICE_NOT_FOUND;
344 }
345
346 return _altera_pcie_cfg_read(pcie, bus->number, devfn, where, size,
347 value);
348 }
349
altera_pcie_cfg_write(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 value)350 static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
351 int where, int size, u32 value)
352 {
353 struct altera_pcie *pcie = bus->sysdata;
354
355 if (altera_pcie_hide_rc_bar(bus, devfn, where))
356 return PCIBIOS_BAD_REGISTER_NUMBER;
357
358 if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))
359 return PCIBIOS_DEVICE_NOT_FOUND;
360
361 return _altera_pcie_cfg_write(pcie, bus->number, devfn, where, size,
362 value);
363 }
364
365 static struct pci_ops altera_pcie_ops = {
366 .read = altera_pcie_cfg_read,
367 .write = altera_pcie_cfg_write,
368 };
369
altera_read_cap_word(struct altera_pcie * pcie,u8 busno,unsigned int devfn,int offset,u16 * value)370 static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno,
371 unsigned int devfn, int offset, u16 *value)
372 {
373 u32 data;
374 int ret;
375
376 ret = _altera_pcie_cfg_read(pcie, busno, devfn,
377 PCIE_CAP_OFFSET + offset, sizeof(*value),
378 &data);
379 *value = data;
380 return ret;
381 }
382
altera_write_cap_word(struct altera_pcie * pcie,u8 busno,unsigned int devfn,int offset,u16 value)383 static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno,
384 unsigned int devfn, int offset, u16 value)
385 {
386 return _altera_pcie_cfg_write(pcie, busno, devfn,
387 PCIE_CAP_OFFSET + offset, sizeof(value),
388 value);
389 }
390
altera_wait_link_retrain(struct altera_pcie * pcie)391 static void altera_wait_link_retrain(struct altera_pcie *pcie)
392 {
393 struct device *dev = &pcie->pdev->dev;
394 u16 reg16;
395 unsigned long start_jiffies;
396
397 /* Wait for link training end. */
398 start_jiffies = jiffies;
399 for (;;) {
400 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
401 PCI_EXP_LNKSTA, ®16);
402 if (!(reg16 & PCI_EXP_LNKSTA_LT))
403 break;
404
405 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
406 dev_err(dev, "link retrain timeout\n");
407 break;
408 }
409 udelay(100);
410 }
411
412 /* Wait for link is up */
413 start_jiffies = jiffies;
414 for (;;) {
415 if (altera_pcie_link_is_up(pcie))
416 break;
417
418 if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
419 dev_err(dev, "link up timeout\n");
420 break;
421 }
422 udelay(100);
423 }
424 }
425
altera_pcie_retrain(struct altera_pcie * pcie)426 static void altera_pcie_retrain(struct altera_pcie *pcie)
427 {
428 u16 linkcap, linkstat, linkctl;
429
430 if (!altera_pcie_link_is_up(pcie))
431 return;
432
433 /*
434 * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
435 * current speed is 2.5 GB/s.
436 */
437 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKCAP,
438 &linkcap);
439 if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
440 return;
441
442 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKSTA,
443 &linkstat);
444 if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
445 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
446 PCI_EXP_LNKCTL, &linkctl);
447 linkctl |= PCI_EXP_LNKCTL_RL;
448 altera_write_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
449 PCI_EXP_LNKCTL, linkctl);
450
451 altera_wait_link_retrain(pcie);
452 }
453 }
454
altera_pcie_intx_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)455 static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
456 irq_hw_number_t hwirq)
457 {
458 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
459 irq_set_chip_data(irq, domain->host_data);
460 return 0;
461 }
462
463 static const struct irq_domain_ops intx_domain_ops = {
464 .map = altera_pcie_intx_map,
465 .xlate = pci_irqd_intx_xlate,
466 };
467
altera_pcie_isr(struct irq_desc * desc)468 static void altera_pcie_isr(struct irq_desc *desc)
469 {
470 struct irq_chip *chip = irq_desc_get_chip(desc);
471 struct altera_pcie *pcie;
472 struct device *dev;
473 unsigned long status;
474 u32 bit;
475 u32 virq;
476
477 chained_irq_enter(chip, desc);
478 pcie = irq_desc_get_handler_data(desc);
479 dev = &pcie->pdev->dev;
480
481 while ((status = cra_readl(pcie, P2A_INT_STATUS)
482 & P2A_INT_STS_ALL) != 0) {
483 for_each_set_bit(bit, &status, PCI_NUM_INTX) {
484 /* clear interrupts */
485 cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
486
487 virq = irq_find_mapping(pcie->irq_domain, bit);
488 if (virq)
489 generic_handle_irq(virq);
490 else
491 dev_err(dev, "unexpected IRQ, INT%d\n", bit);
492 }
493 }
494
495 chained_irq_exit(chip, desc);
496 }
497
altera_pcie_parse_request_of_pci_ranges(struct altera_pcie * pcie)498 static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie)
499 {
500 int err, res_valid = 0;
501 struct device *dev = &pcie->pdev->dev;
502 struct device_node *np = dev->of_node;
503 struct resource_entry *win;
504
505 err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources,
506 NULL);
507 if (err)
508 return err;
509
510 err = devm_request_pci_bus_resources(dev, &pcie->resources);
511 if (err)
512 goto out_release_res;
513
514 resource_list_for_each_entry(win, &pcie->resources) {
515 struct resource *res = win->res;
516
517 if (resource_type(res) == IORESOURCE_MEM)
518 res_valid |= !(res->flags & IORESOURCE_PREFETCH);
519 }
520
521 if (res_valid)
522 return 0;
523
524 dev_err(dev, "non-prefetchable memory resource required\n");
525 err = -EINVAL;
526
527 out_release_res:
528 pci_free_resource_list(&pcie->resources);
529 return err;
530 }
531
altera_pcie_init_irq_domain(struct altera_pcie * pcie)532 static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
533 {
534 struct device *dev = &pcie->pdev->dev;
535 struct device_node *node = dev->of_node;
536
537 /* Setup INTx */
538 pcie->irq_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
539 &intx_domain_ops, pcie);
540 if (!pcie->irq_domain) {
541 dev_err(dev, "Failed to get a INTx IRQ domain\n");
542 return -ENOMEM;
543 }
544
545 return 0;
546 }
547
altera_pcie_parse_dt(struct altera_pcie * pcie)548 static int altera_pcie_parse_dt(struct altera_pcie *pcie)
549 {
550 struct device *dev = &pcie->pdev->dev;
551 struct platform_device *pdev = pcie->pdev;
552 struct resource *cra;
553
554 cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
555 pcie->cra_base = devm_ioremap_resource(dev, cra);
556 if (IS_ERR(pcie->cra_base))
557 return PTR_ERR(pcie->cra_base);
558
559 /* setup IRQ */
560 pcie->irq = platform_get_irq(pdev, 0);
561 if (pcie->irq < 0) {
562 dev_err(dev, "failed to get IRQ: %d\n", pcie->irq);
563 return pcie->irq;
564 }
565
566 irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);
567 return 0;
568 }
569
altera_pcie_host_init(struct altera_pcie * pcie)570 static void altera_pcie_host_init(struct altera_pcie *pcie)
571 {
572 altera_pcie_retrain(pcie);
573 }
574
altera_pcie_probe(struct platform_device * pdev)575 static int altera_pcie_probe(struct platform_device *pdev)
576 {
577 struct device *dev = &pdev->dev;
578 struct altera_pcie *pcie;
579 struct pci_bus *bus;
580 struct pci_bus *child;
581 struct pci_host_bridge *bridge;
582 int ret;
583
584 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
585 if (!bridge)
586 return -ENOMEM;
587
588 pcie = pci_host_bridge_priv(bridge);
589 pcie->pdev = pdev;
590
591 ret = altera_pcie_parse_dt(pcie);
592 if (ret) {
593 dev_err(dev, "Parsing DT failed\n");
594 return ret;
595 }
596
597 INIT_LIST_HEAD(&pcie->resources);
598
599 ret = altera_pcie_parse_request_of_pci_ranges(pcie);
600 if (ret) {
601 dev_err(dev, "Failed add resources\n");
602 return ret;
603 }
604
605 ret = altera_pcie_init_irq_domain(pcie);
606 if (ret) {
607 dev_err(dev, "Failed creating IRQ Domain\n");
608 return ret;
609 }
610
611 /* clear all interrupts */
612 cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
613 /* enable all interrupts */
614 cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
615 altera_pcie_host_init(pcie);
616
617 list_splice_init(&pcie->resources, &bridge->windows);
618 bridge->dev.parent = dev;
619 bridge->sysdata = pcie;
620 bridge->busnr = pcie->root_bus_nr;
621 bridge->ops = &altera_pcie_ops;
622 bridge->map_irq = of_irq_parse_and_map_pci;
623 bridge->swizzle_irq = pci_common_swizzle;
624
625 ret = pci_scan_root_bus_bridge(bridge);
626 if (ret < 0)
627 return ret;
628
629 bus = bridge->bus;
630
631 pci_assign_unassigned_bus_resources(bus);
632
633 /* Configure PCI Express setting. */
634 list_for_each_entry(child, &bus->children, node)
635 pcie_bus_configure_settings(child);
636
637 pci_bus_add_devices(bus);
638 return ret;
639 }
640
641 static const struct of_device_id altera_pcie_of_match[] = {
642 { .compatible = "altr,pcie-root-port-1.0", },
643 {},
644 };
645
646 static struct platform_driver altera_pcie_driver = {
647 .probe = altera_pcie_probe,
648 .driver = {
649 .name = "altera-pcie",
650 .of_match_table = altera_pcie_of_match,
651 .suppress_bind_attrs = true,
652 },
653 };
654
655 builtin_platform_driver(altera_pcie_driver);
656