1 /*
2 * Allwinner sun4i USB phy driver
3 *
4 * Copyright (C) 2014-2015 Hans de Goede <hdegoede@redhat.com>
5 *
6 * Based on code from
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 *
9 * Modelled after: Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
10 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
11 * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 */
23
24 #include <linux/clk.h>
25 #include <linux/delay.h>
26 #include <linux/err.h>
27 #include <linux/extcon.h>
28 #include <linux/io.h>
29 #include <linux/interrupt.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/mutex.h>
33 #include <linux/of.h>
34 #include <linux/of_address.h>
35 #include <linux/of_device.h>
36 #include <linux/of_gpio.h>
37 #include <linux/phy/phy.h>
38 #include <linux/phy/phy-sun4i-usb.h>
39 #include <linux/platform_device.h>
40 #include <linux/power_supply.h>
41 #include <linux/regulator/consumer.h>
42 #include <linux/reset.h>
43 #include <linux/spinlock.h>
44 #include <linux/usb/of.h>
45 #include <linux/workqueue.h>
46
47 #define REG_ISCR 0x00
48 #define REG_PHYCTL_A10 0x04
49 #define REG_PHYBIST 0x08
50 #define REG_PHYTUNE 0x0c
51 #define REG_PHYCTL_A33 0x10
52 #define REG_PHY_OTGCTL 0x20
53
54 #define REG_PMU_UNK1 0x10
55
56 #define PHYCTL_DATA BIT(7)
57
58 #define OTGCTL_ROUTE_MUSB BIT(0)
59
60 #define SUNXI_AHB_ICHR8_EN BIT(10)
61 #define SUNXI_AHB_INCR4_BURST_EN BIT(9)
62 #define SUNXI_AHB_INCRX_ALIGN_EN BIT(8)
63 #define SUNXI_ULPI_BYPASS_EN BIT(0)
64
65 /* ISCR, Interface Status and Control bits */
66 #define ISCR_ID_PULLUP_EN (1 << 17)
67 #define ISCR_DPDM_PULLUP_EN (1 << 16)
68 /* sunxi has the phy id/vbus pins not connected, so we use the force bits */
69 #define ISCR_FORCE_ID_MASK (3 << 14)
70 #define ISCR_FORCE_ID_LOW (2 << 14)
71 #define ISCR_FORCE_ID_HIGH (3 << 14)
72 #define ISCR_FORCE_VBUS_MASK (3 << 12)
73 #define ISCR_FORCE_VBUS_LOW (2 << 12)
74 #define ISCR_FORCE_VBUS_HIGH (3 << 12)
75
76 /* Common Control Bits for Both PHYs */
77 #define PHY_PLL_BW 0x03
78 #define PHY_RES45_CAL_EN 0x0c
79
80 /* Private Control Bits for Each PHY */
81 #define PHY_TX_AMPLITUDE_TUNE 0x20
82 #define PHY_TX_SLEWRATE_TUNE 0x22
83 #define PHY_VBUSVALID_TH_SEL 0x25
84 #define PHY_PULLUP_RES_SEL 0x27
85 #define PHY_OTG_FUNC_EN 0x28
86 #define PHY_VBUS_DET_EN 0x29
87 #define PHY_DISCON_TH_SEL 0x2a
88 #define PHY_SQUELCH_DETECT 0x3c
89
90 /* A83T specific control bits for PHY0 */
91 #define PHY_CTL_VBUSVLDEXT BIT(5)
92 #define PHY_CTL_SIDDQ BIT(3)
93
94 /* A83T specific control bits for PHY2 HSIC */
95 #define SUNXI_EHCI_HS_FORCE BIT(20)
96 #define SUNXI_HSIC_CONNECT_DET BIT(17)
97 #define SUNXI_HSIC_CONNECT_INT BIT(16)
98 #define SUNXI_HSIC BIT(1)
99
100 #define MAX_PHYS 4
101
102 /*
103 * Note do not raise the debounce time, we must report Vusb high within 100ms
104 * otherwise we get Vbus errors
105 */
106 #define DEBOUNCE_TIME msecs_to_jiffies(50)
107 #define POLL_TIME msecs_to_jiffies(250)
108
109 enum sun4i_usb_phy_type {
110 sun4i_a10_phy,
111 sun6i_a31_phy,
112 sun8i_a33_phy,
113 sun8i_a83t_phy,
114 sun8i_h3_phy,
115 sun8i_v3s_phy,
116 sun50i_a64_phy,
117 };
118
119 struct sun4i_usb_phy_cfg {
120 int num_phys;
121 int hsic_index;
122 enum sun4i_usb_phy_type type;
123 u32 disc_thresh;
124 u8 phyctl_offset;
125 bool dedicated_clocks;
126 bool enable_pmu_unk1;
127 bool phy0_dual_route;
128 int missing_phys;
129 };
130
131 struct sun4i_usb_phy_data {
132 void __iomem *base;
133 const struct sun4i_usb_phy_cfg *cfg;
134 enum usb_dr_mode dr_mode;
135 spinlock_t reg_lock; /* guard access to phyctl reg */
136 struct sun4i_usb_phy {
137 struct phy *phy;
138 void __iomem *pmu;
139 struct regulator *vbus;
140 struct reset_control *reset;
141 struct clk *clk;
142 struct clk *clk2;
143 bool regulator_on;
144 int index;
145 } phys[MAX_PHYS];
146 /* phy0 / otg related variables */
147 struct extcon_dev *extcon;
148 bool phy0_init;
149 struct gpio_desc *id_det_gpio;
150 struct gpio_desc *vbus_det_gpio;
151 struct power_supply *vbus_power_supply;
152 struct notifier_block vbus_power_nb;
153 bool vbus_power_nb_registered;
154 bool force_session_end;
155 int id_det_irq;
156 int vbus_det_irq;
157 int id_det;
158 int vbus_det;
159 struct delayed_work detect;
160 };
161
162 #define to_sun4i_usb_phy_data(phy) \
163 container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index])
164
sun4i_usb_phy0_update_iscr(struct phy * _phy,u32 clr,u32 set)165 static void sun4i_usb_phy0_update_iscr(struct phy *_phy, u32 clr, u32 set)
166 {
167 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
168 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
169 u32 iscr;
170
171 iscr = readl(data->base + REG_ISCR);
172 iscr &= ~clr;
173 iscr |= set;
174 writel(iscr, data->base + REG_ISCR);
175 }
176
sun4i_usb_phy0_set_id_detect(struct phy * phy,u32 val)177 static void sun4i_usb_phy0_set_id_detect(struct phy *phy, u32 val)
178 {
179 if (val)
180 val = ISCR_FORCE_ID_HIGH;
181 else
182 val = ISCR_FORCE_ID_LOW;
183
184 sun4i_usb_phy0_update_iscr(phy, ISCR_FORCE_ID_MASK, val);
185 }
186
sun4i_usb_phy0_set_vbus_detect(struct phy * phy,u32 val)187 static void sun4i_usb_phy0_set_vbus_detect(struct phy *phy, u32 val)
188 {
189 if (val)
190 val = ISCR_FORCE_VBUS_HIGH;
191 else
192 val = ISCR_FORCE_VBUS_LOW;
193
194 sun4i_usb_phy0_update_iscr(phy, ISCR_FORCE_VBUS_MASK, val);
195 }
196
sun4i_usb_phy_write(struct sun4i_usb_phy * phy,u32 addr,u32 data,int len)197 static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
198 int len)
199 {
200 struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
201 u32 temp, usbc_bit = BIT(phy->index * 2);
202 void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
203 unsigned long flags;
204 int i;
205
206 spin_lock_irqsave(&phy_data->reg_lock, flags);
207
208 if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
209 /* SoCs newer than A33 need us to set phyctl to 0 explicitly */
210 writel(0, phyctl);
211 }
212
213 for (i = 0; i < len; i++) {
214 temp = readl(phyctl);
215
216 /* clear the address portion */
217 temp &= ~(0xff << 8);
218
219 /* set the address */
220 temp |= ((addr + i) << 8);
221 writel(temp, phyctl);
222
223 /* set the data bit and clear usbc bit*/
224 temp = readb(phyctl);
225 if (data & 0x1)
226 temp |= PHYCTL_DATA;
227 else
228 temp &= ~PHYCTL_DATA;
229 temp &= ~usbc_bit;
230 writeb(temp, phyctl);
231
232 /* pulse usbc_bit */
233 temp = readb(phyctl);
234 temp |= usbc_bit;
235 writeb(temp, phyctl);
236
237 temp = readb(phyctl);
238 temp &= ~usbc_bit;
239 writeb(temp, phyctl);
240
241 data >>= 1;
242 }
243
244 spin_unlock_irqrestore(&phy_data->reg_lock, flags);
245 }
246
sun4i_usb_phy_passby(struct sun4i_usb_phy * phy,int enable)247 static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable)
248 {
249 struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
250 u32 bits, reg_value;
251
252 if (!phy->pmu)
253 return;
254
255 bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
256 SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
257
258 /* A83T USB2 is HSIC */
259 if (phy_data->cfg->type == sun8i_a83t_phy && phy->index == 2)
260 bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
261 SUNXI_HSIC;
262
263 reg_value = readl(phy->pmu);
264
265 if (enable)
266 reg_value |= bits;
267 else
268 reg_value &= ~bits;
269
270 writel(reg_value, phy->pmu);
271 }
272
sun4i_usb_phy_init(struct phy * _phy)273 static int sun4i_usb_phy_init(struct phy *_phy)
274 {
275 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
276 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
277 int ret;
278 u32 val;
279
280 ret = clk_prepare_enable(phy->clk);
281 if (ret)
282 return ret;
283
284 ret = clk_prepare_enable(phy->clk2);
285 if (ret) {
286 clk_disable_unprepare(phy->clk);
287 return ret;
288 }
289
290 ret = reset_control_deassert(phy->reset);
291 if (ret) {
292 clk_disable_unprepare(phy->clk2);
293 clk_disable_unprepare(phy->clk);
294 return ret;
295 }
296
297 if (data->cfg->type == sun8i_a83t_phy) {
298 if (phy->index == 0) {
299 val = readl(data->base + data->cfg->phyctl_offset);
300 val |= PHY_CTL_VBUSVLDEXT;
301 val &= ~PHY_CTL_SIDDQ;
302 writel(val, data->base + data->cfg->phyctl_offset);
303 }
304 } else {
305 if (phy->pmu && data->cfg->enable_pmu_unk1) {
306 val = readl(phy->pmu + REG_PMU_UNK1);
307 writel(val & ~2, phy->pmu + REG_PMU_UNK1);
308 }
309
310 /* Enable USB 45 Ohm resistor calibration */
311 if (phy->index == 0)
312 sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
313
314 /* Adjust PHY's magnitude and rate */
315 sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
316
317 /* Disconnect threshold adjustment */
318 sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
319 data->cfg->disc_thresh, 2);
320 }
321
322 sun4i_usb_phy_passby(phy, 1);
323
324 if (phy->index == 0) {
325 data->phy0_init = true;
326
327 /* Enable pull-ups */
328 sun4i_usb_phy0_update_iscr(_phy, 0, ISCR_DPDM_PULLUP_EN);
329 sun4i_usb_phy0_update_iscr(_phy, 0, ISCR_ID_PULLUP_EN);
330
331 /* Force ISCR and cable state updates */
332 data->id_det = -1;
333 data->vbus_det = -1;
334 queue_delayed_work(system_wq, &data->detect, 0);
335 }
336
337 return 0;
338 }
339
sun4i_usb_phy_exit(struct phy * _phy)340 static int sun4i_usb_phy_exit(struct phy *_phy)
341 {
342 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
343 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
344
345 if (phy->index == 0) {
346 if (data->cfg->type == sun8i_a83t_phy) {
347 void __iomem *phyctl = data->base +
348 data->cfg->phyctl_offset;
349
350 writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
351 }
352
353 /* Disable pull-ups */
354 sun4i_usb_phy0_update_iscr(_phy, ISCR_DPDM_PULLUP_EN, 0);
355 sun4i_usb_phy0_update_iscr(_phy, ISCR_ID_PULLUP_EN, 0);
356 data->phy0_init = false;
357 }
358
359 sun4i_usb_phy_passby(phy, 0);
360 reset_control_assert(phy->reset);
361 clk_disable_unprepare(phy->clk2);
362 clk_disable_unprepare(phy->clk);
363
364 return 0;
365 }
366
sun4i_usb_phy0_get_id_det(struct sun4i_usb_phy_data * data)367 static int sun4i_usb_phy0_get_id_det(struct sun4i_usb_phy_data *data)
368 {
369 switch (data->dr_mode) {
370 case USB_DR_MODE_OTG:
371 if (data->id_det_gpio)
372 return gpiod_get_value_cansleep(data->id_det_gpio);
373 else
374 return 1; /* Fallback to peripheral mode */
375 case USB_DR_MODE_HOST:
376 return 0;
377 case USB_DR_MODE_PERIPHERAL:
378 default:
379 return 1;
380 }
381 }
382
sun4i_usb_phy0_get_vbus_det(struct sun4i_usb_phy_data * data)383 static int sun4i_usb_phy0_get_vbus_det(struct sun4i_usb_phy_data *data)
384 {
385 if (data->vbus_det_gpio)
386 return gpiod_get_value_cansleep(data->vbus_det_gpio);
387
388 if (data->vbus_power_supply) {
389 union power_supply_propval val;
390 int r;
391
392 r = power_supply_get_property(data->vbus_power_supply,
393 POWER_SUPPLY_PROP_PRESENT, &val);
394 if (r == 0)
395 return val.intval;
396 }
397
398 /* Fallback: report vbus as high */
399 return 1;
400 }
401
sun4i_usb_phy0_have_vbus_det(struct sun4i_usb_phy_data * data)402 static bool sun4i_usb_phy0_have_vbus_det(struct sun4i_usb_phy_data *data)
403 {
404 return data->vbus_det_gpio || data->vbus_power_supply;
405 }
406
sun4i_usb_phy0_poll(struct sun4i_usb_phy_data * data)407 static bool sun4i_usb_phy0_poll(struct sun4i_usb_phy_data *data)
408 {
409 if ((data->id_det_gpio && data->id_det_irq <= 0) ||
410 (data->vbus_det_gpio && data->vbus_det_irq <= 0))
411 return true;
412
413 /*
414 * The A31/A23/A33 companion pmics (AXP221/AXP223) do not
415 * generate vbus change interrupts when the board is driving
416 * vbus using the N_VBUSEN pin on the pmic, so we must poll
417 * when using the pmic for vbus-det _and_ we're driving vbus.
418 */
419 if ((data->cfg->type == sun6i_a31_phy ||
420 data->cfg->type == sun8i_a33_phy) &&
421 data->vbus_power_supply && data->phys[0].regulator_on)
422 return true;
423
424 return false;
425 }
426
sun4i_usb_phy_power_on(struct phy * _phy)427 static int sun4i_usb_phy_power_on(struct phy *_phy)
428 {
429 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
430 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
431 int ret;
432
433 if (!phy->vbus || phy->regulator_on)
434 return 0;
435
436 /* For phy0 only turn on Vbus if we don't have an ext. Vbus */
437 if (phy->index == 0 && sun4i_usb_phy0_have_vbus_det(data) &&
438 data->vbus_det) {
439 dev_warn(&_phy->dev, "External vbus detected, not enabling our own vbus\n");
440 return 0;
441 }
442
443 ret = regulator_enable(phy->vbus);
444 if (ret)
445 return ret;
446
447 phy->regulator_on = true;
448
449 /* We must report Vbus high within OTG_TIME_A_WAIT_VRISE msec. */
450 if (phy->index == 0 && sun4i_usb_phy0_poll(data))
451 mod_delayed_work(system_wq, &data->detect, DEBOUNCE_TIME);
452
453 return 0;
454 }
455
sun4i_usb_phy_power_off(struct phy * _phy)456 static int sun4i_usb_phy_power_off(struct phy *_phy)
457 {
458 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
459 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
460
461 if (!phy->vbus || !phy->regulator_on)
462 return 0;
463
464 regulator_disable(phy->vbus);
465 phy->regulator_on = false;
466
467 /*
468 * phy0 vbus typically slowly discharges, sometimes this causes the
469 * Vbus gpio to not trigger an edge irq on Vbus off, so force a rescan.
470 */
471 if (phy->index == 0 && !sun4i_usb_phy0_poll(data))
472 mod_delayed_work(system_wq, &data->detect, POLL_TIME);
473
474 return 0;
475 }
476
sun4i_usb_phy_set_mode(struct phy * _phy,enum phy_mode mode)477 static int sun4i_usb_phy_set_mode(struct phy *_phy, enum phy_mode mode)
478 {
479 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
480 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
481 int new_mode;
482
483 if (phy->index != 0) {
484 if (mode == PHY_MODE_USB_HOST)
485 return 0;
486 return -EINVAL;
487 }
488
489 switch (mode) {
490 case PHY_MODE_USB_HOST:
491 new_mode = USB_DR_MODE_HOST;
492 break;
493 case PHY_MODE_USB_DEVICE:
494 new_mode = USB_DR_MODE_PERIPHERAL;
495 break;
496 case PHY_MODE_USB_OTG:
497 new_mode = USB_DR_MODE_OTG;
498 break;
499 default:
500 return -EINVAL;
501 }
502
503 if (new_mode != data->dr_mode) {
504 dev_info(&_phy->dev, "Changing dr_mode to %d\n", new_mode);
505 data->dr_mode = new_mode;
506 }
507
508 data->id_det = -1; /* Force reprocessing of id */
509 data->force_session_end = true;
510 queue_delayed_work(system_wq, &data->detect, 0);
511
512 return 0;
513 }
514
sun4i_usb_phy_set_squelch_detect(struct phy * _phy,bool enabled)515 void sun4i_usb_phy_set_squelch_detect(struct phy *_phy, bool enabled)
516 {
517 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
518
519 sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);
520 }
521 EXPORT_SYMBOL_GPL(sun4i_usb_phy_set_squelch_detect);
522
523 static const struct phy_ops sun4i_usb_phy_ops = {
524 .init = sun4i_usb_phy_init,
525 .exit = sun4i_usb_phy_exit,
526 .power_on = sun4i_usb_phy_power_on,
527 .power_off = sun4i_usb_phy_power_off,
528 .set_mode = sun4i_usb_phy_set_mode,
529 .owner = THIS_MODULE,
530 };
531
sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data * data,int id_det)532 static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, int id_det)
533 {
534 u32 regval;
535
536 regval = readl(data->base + REG_PHY_OTGCTL);
537 if (id_det == 0) {
538 /* Host mode. Route phy0 to EHCI/OHCI */
539 regval &= ~OTGCTL_ROUTE_MUSB;
540 } else {
541 /* Peripheral mode. Route phy0 to MUSB */
542 regval |= OTGCTL_ROUTE_MUSB;
543 }
544 writel(regval, data->base + REG_PHY_OTGCTL);
545 }
546
sun4i_usb_phy0_id_vbus_det_scan(struct work_struct * work)547 static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work)
548 {
549 struct sun4i_usb_phy_data *data =
550 container_of(work, struct sun4i_usb_phy_data, detect.work);
551 struct phy *phy0 = data->phys[0].phy;
552 struct sun4i_usb_phy *phy = phy_get_drvdata(phy0);
553 bool force_session_end, id_notify = false, vbus_notify = false;
554 int id_det, vbus_det;
555
556 if (phy0 == NULL)
557 return;
558
559 id_det = sun4i_usb_phy0_get_id_det(data);
560 vbus_det = sun4i_usb_phy0_get_vbus_det(data);
561
562 mutex_lock(&phy0->mutex);
563
564 if (!data->phy0_init) {
565 mutex_unlock(&phy0->mutex);
566 return;
567 }
568
569 force_session_end = data->force_session_end;
570 data->force_session_end = false;
571
572 if (id_det != data->id_det) {
573 /* id-change, force session end if we've no vbus detection */
574 if (data->dr_mode == USB_DR_MODE_OTG &&
575 !sun4i_usb_phy0_have_vbus_det(data))
576 force_session_end = true;
577
578 /* When entering host mode (id = 0) force end the session now */
579 if (force_session_end && id_det == 0) {
580 sun4i_usb_phy0_set_vbus_detect(phy0, 0);
581 msleep(200);
582 sun4i_usb_phy0_set_vbus_detect(phy0, 1);
583 }
584 sun4i_usb_phy0_set_id_detect(phy0, id_det);
585 data->id_det = id_det;
586 id_notify = true;
587 }
588
589 if (vbus_det != data->vbus_det) {
590 sun4i_usb_phy0_set_vbus_detect(phy0, vbus_det);
591 data->vbus_det = vbus_det;
592 vbus_notify = true;
593 }
594
595 mutex_unlock(&phy0->mutex);
596
597 if (id_notify) {
598 extcon_set_state_sync(data->extcon, EXTCON_USB_HOST,
599 !id_det);
600 /* When leaving host mode force end the session here */
601 if (force_session_end && id_det == 1) {
602 mutex_lock(&phy0->mutex);
603 sun4i_usb_phy0_set_vbus_detect(phy0, 0);
604 msleep(1000);
605 sun4i_usb_phy0_set_vbus_detect(phy0, 1);
606 mutex_unlock(&phy0->mutex);
607 }
608
609 /* Enable PHY0 passby for host mode only. */
610 sun4i_usb_phy_passby(phy, !id_det);
611
612 /* Re-route PHY0 if necessary */
613 if (data->cfg->phy0_dual_route)
614 sun4i_usb_phy0_reroute(data, id_det);
615 }
616
617 if (vbus_notify)
618 extcon_set_state_sync(data->extcon, EXTCON_USB, vbus_det);
619
620 if (sun4i_usb_phy0_poll(data))
621 queue_delayed_work(system_wq, &data->detect, POLL_TIME);
622 }
623
sun4i_usb_phy0_id_vbus_det_irq(int irq,void * dev_id)624 static irqreturn_t sun4i_usb_phy0_id_vbus_det_irq(int irq, void *dev_id)
625 {
626 struct sun4i_usb_phy_data *data = dev_id;
627
628 /* vbus or id changed, let the pins settle and then scan them */
629 mod_delayed_work(system_wq, &data->detect, DEBOUNCE_TIME);
630
631 return IRQ_HANDLED;
632 }
633
sun4i_usb_phy0_vbus_notify(struct notifier_block * nb,unsigned long val,void * v)634 static int sun4i_usb_phy0_vbus_notify(struct notifier_block *nb,
635 unsigned long val, void *v)
636 {
637 struct sun4i_usb_phy_data *data =
638 container_of(nb, struct sun4i_usb_phy_data, vbus_power_nb);
639 struct power_supply *psy = v;
640
641 /* Properties on the vbus_power_supply changed, scan vbus_det */
642 if (val == PSY_EVENT_PROP_CHANGED && psy == data->vbus_power_supply)
643 mod_delayed_work(system_wq, &data->detect, DEBOUNCE_TIME);
644
645 return NOTIFY_OK;
646 }
647
sun4i_usb_phy_xlate(struct device * dev,struct of_phandle_args * args)648 static struct phy *sun4i_usb_phy_xlate(struct device *dev,
649 struct of_phandle_args *args)
650 {
651 struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
652
653 if (args->args[0] >= data->cfg->num_phys)
654 return ERR_PTR(-ENODEV);
655
656 if (data->cfg->missing_phys & BIT(args->args[0]))
657 return ERR_PTR(-ENODEV);
658
659 return data->phys[args->args[0]].phy;
660 }
661
sun4i_usb_phy_remove(struct platform_device * pdev)662 static int sun4i_usb_phy_remove(struct platform_device *pdev)
663 {
664 struct device *dev = &pdev->dev;
665 struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
666
667 if (data->vbus_power_nb_registered)
668 power_supply_unreg_notifier(&data->vbus_power_nb);
669 if (data->id_det_irq > 0)
670 devm_free_irq(dev, data->id_det_irq, data);
671 if (data->vbus_det_irq > 0)
672 devm_free_irq(dev, data->vbus_det_irq, data);
673
674 cancel_delayed_work_sync(&data->detect);
675
676 return 0;
677 }
678
679 static const unsigned int sun4i_usb_phy0_cable[] = {
680 EXTCON_USB,
681 EXTCON_USB_HOST,
682 EXTCON_NONE,
683 };
684
sun4i_usb_phy_probe(struct platform_device * pdev)685 static int sun4i_usb_phy_probe(struct platform_device *pdev)
686 {
687 struct sun4i_usb_phy_data *data;
688 struct device *dev = &pdev->dev;
689 struct device_node *np = dev->of_node;
690 struct phy_provider *phy_provider;
691 struct resource *res;
692 int i, ret;
693
694 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
695 if (!data)
696 return -ENOMEM;
697
698 spin_lock_init(&data->reg_lock);
699 INIT_DELAYED_WORK(&data->detect, sun4i_usb_phy0_id_vbus_det_scan);
700 dev_set_drvdata(dev, data);
701 data->cfg = of_device_get_match_data(dev);
702 if (!data->cfg)
703 return -EINVAL;
704
705 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_ctrl");
706 data->base = devm_ioremap_resource(dev, res);
707 if (IS_ERR(data->base))
708 return PTR_ERR(data->base);
709
710 data->id_det_gpio = devm_gpiod_get_optional(dev, "usb0_id_det",
711 GPIOD_IN);
712 if (IS_ERR(data->id_det_gpio)) {
713 dev_err(dev, "Couldn't request ID GPIO\n");
714 return PTR_ERR(data->id_det_gpio);
715 }
716
717 data->vbus_det_gpio = devm_gpiod_get_optional(dev, "usb0_vbus_det",
718 GPIOD_IN);
719 if (IS_ERR(data->vbus_det_gpio)) {
720 dev_err(dev, "Couldn't request VBUS detect GPIO\n");
721 return PTR_ERR(data->vbus_det_gpio);
722 }
723
724 if (of_find_property(np, "usb0_vbus_power-supply", NULL)) {
725 data->vbus_power_supply = devm_power_supply_get_by_phandle(dev,
726 "usb0_vbus_power-supply");
727 if (IS_ERR(data->vbus_power_supply)) {
728 dev_err(dev, "Couldn't get the VBUS power supply\n");
729 return PTR_ERR(data->vbus_power_supply);
730 }
731
732 if (!data->vbus_power_supply)
733 return -EPROBE_DEFER;
734 }
735
736 data->dr_mode = of_usb_get_dr_mode_by_phy(np, 0);
737
738 data->extcon = devm_extcon_dev_allocate(dev, sun4i_usb_phy0_cable);
739 if (IS_ERR(data->extcon)) {
740 dev_err(dev, "Couldn't allocate our extcon device\n");
741 return PTR_ERR(data->extcon);
742 }
743
744 ret = devm_extcon_dev_register(dev, data->extcon);
745 if (ret) {
746 dev_err(dev, "failed to register extcon: %d\n", ret);
747 return ret;
748 }
749
750 for (i = 0; i < data->cfg->num_phys; i++) {
751 struct sun4i_usb_phy *phy = data->phys + i;
752 char name[16];
753
754 if (data->cfg->missing_phys & BIT(i))
755 continue;
756
757 snprintf(name, sizeof(name), "usb%d_vbus", i);
758 phy->vbus = devm_regulator_get_optional(dev, name);
759 if (IS_ERR(phy->vbus)) {
760 if (PTR_ERR(phy->vbus) == -EPROBE_DEFER) {
761 dev_err(dev,
762 "Couldn't get regulator %s... Deferring probe\n",
763 name);
764 return -EPROBE_DEFER;
765 }
766
767 phy->vbus = NULL;
768 }
769
770 if (data->cfg->dedicated_clocks)
771 snprintf(name, sizeof(name), "usb%d_phy", i);
772 else
773 strlcpy(name, "usb_phy", sizeof(name));
774
775 phy->clk = devm_clk_get(dev, name);
776 if (IS_ERR(phy->clk)) {
777 dev_err(dev, "failed to get clock %s\n", name);
778 return PTR_ERR(phy->clk);
779 }
780
781 /* The first PHY is always tied to OTG, and never HSIC */
782 if (data->cfg->hsic_index && i == data->cfg->hsic_index) {
783 /* HSIC needs secondary clock */
784 snprintf(name, sizeof(name), "usb%d_hsic_12M", i);
785 phy->clk2 = devm_clk_get(dev, name);
786 if (IS_ERR(phy->clk2)) {
787 dev_err(dev, "failed to get clock %s\n", name);
788 return PTR_ERR(phy->clk2);
789 }
790 }
791
792 snprintf(name, sizeof(name), "usb%d_reset", i);
793 phy->reset = devm_reset_control_get(dev, name);
794 if (IS_ERR(phy->reset)) {
795 dev_err(dev, "failed to get reset %s\n", name);
796 return PTR_ERR(phy->reset);
797 }
798
799 if (i || data->cfg->phy0_dual_route) { /* No pmu for musb */
800 snprintf(name, sizeof(name), "pmu%d", i);
801 res = platform_get_resource_byname(pdev,
802 IORESOURCE_MEM, name);
803 phy->pmu = devm_ioremap_resource(dev, res);
804 if (IS_ERR(phy->pmu))
805 return PTR_ERR(phy->pmu);
806 }
807
808 phy->phy = devm_phy_create(dev, NULL, &sun4i_usb_phy_ops);
809 if (IS_ERR(phy->phy)) {
810 dev_err(dev, "failed to create PHY %d\n", i);
811 return PTR_ERR(phy->phy);
812 }
813
814 phy->index = i;
815 phy_set_drvdata(phy->phy, &data->phys[i]);
816 }
817
818 data->id_det_irq = gpiod_to_irq(data->id_det_gpio);
819 if (data->id_det_irq > 0) {
820 ret = devm_request_irq(dev, data->id_det_irq,
821 sun4i_usb_phy0_id_vbus_det_irq,
822 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
823 "usb0-id-det", data);
824 if (ret) {
825 dev_err(dev, "Err requesting id-det-irq: %d\n", ret);
826 return ret;
827 }
828 }
829
830 data->vbus_det_irq = gpiod_to_irq(data->vbus_det_gpio);
831 if (data->vbus_det_irq > 0) {
832 ret = devm_request_irq(dev, data->vbus_det_irq,
833 sun4i_usb_phy0_id_vbus_det_irq,
834 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
835 "usb0-vbus-det", data);
836 if (ret) {
837 dev_err(dev, "Err requesting vbus-det-irq: %d\n", ret);
838 data->vbus_det_irq = -1;
839 sun4i_usb_phy_remove(pdev); /* Stop detect work */
840 return ret;
841 }
842 }
843
844 if (data->vbus_power_supply) {
845 data->vbus_power_nb.notifier_call = sun4i_usb_phy0_vbus_notify;
846 data->vbus_power_nb.priority = 0;
847 ret = power_supply_reg_notifier(&data->vbus_power_nb);
848 if (ret) {
849 sun4i_usb_phy_remove(pdev); /* Stop detect work */
850 return ret;
851 }
852 data->vbus_power_nb_registered = true;
853 }
854
855 phy_provider = devm_of_phy_provider_register(dev, sun4i_usb_phy_xlate);
856 if (IS_ERR(phy_provider)) {
857 sun4i_usb_phy_remove(pdev); /* Stop detect work */
858 return PTR_ERR(phy_provider);
859 }
860
861 dev_dbg(dev, "successfully loaded\n");
862
863 return 0;
864 }
865
866 static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
867 .num_phys = 3,
868 .type = sun4i_a10_phy,
869 .disc_thresh = 3,
870 .phyctl_offset = REG_PHYCTL_A10,
871 .dedicated_clocks = false,
872 .enable_pmu_unk1 = false,
873 };
874
875 static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
876 .num_phys = 2,
877 .type = sun4i_a10_phy,
878 .disc_thresh = 2,
879 .phyctl_offset = REG_PHYCTL_A10,
880 .dedicated_clocks = false,
881 .enable_pmu_unk1 = false,
882 };
883
884 static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
885 .num_phys = 3,
886 .type = sun6i_a31_phy,
887 .disc_thresh = 3,
888 .phyctl_offset = REG_PHYCTL_A10,
889 .dedicated_clocks = true,
890 .enable_pmu_unk1 = false,
891 };
892
893 static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
894 .num_phys = 3,
895 .type = sun4i_a10_phy,
896 .disc_thresh = 2,
897 .phyctl_offset = REG_PHYCTL_A10,
898 .dedicated_clocks = false,
899 .enable_pmu_unk1 = false,
900 };
901
902 static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
903 .num_phys = 2,
904 .type = sun6i_a31_phy,
905 .disc_thresh = 3,
906 .phyctl_offset = REG_PHYCTL_A10,
907 .dedicated_clocks = true,
908 .enable_pmu_unk1 = false,
909 };
910
911 static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
912 .num_phys = 2,
913 .type = sun8i_a33_phy,
914 .disc_thresh = 3,
915 .phyctl_offset = REG_PHYCTL_A33,
916 .dedicated_clocks = true,
917 .enable_pmu_unk1 = false,
918 };
919
920 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
921 .num_phys = 3,
922 .hsic_index = 2,
923 .type = sun8i_a83t_phy,
924 .phyctl_offset = REG_PHYCTL_A33,
925 .dedicated_clocks = true,
926 };
927
928 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
929 .num_phys = 4,
930 .type = sun8i_h3_phy,
931 .disc_thresh = 3,
932 .phyctl_offset = REG_PHYCTL_A33,
933 .dedicated_clocks = true,
934 .enable_pmu_unk1 = true,
935 .phy0_dual_route = true,
936 };
937
938 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
939 .num_phys = 1,
940 .type = sun8i_v3s_phy,
941 .disc_thresh = 3,
942 .phyctl_offset = REG_PHYCTL_A33,
943 .dedicated_clocks = true,
944 .enable_pmu_unk1 = true,
945 };
946
947 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
948 .num_phys = 2,
949 .type = sun50i_a64_phy,
950 .disc_thresh = 3,
951 .phyctl_offset = REG_PHYCTL_A33,
952 .dedicated_clocks = true,
953 .enable_pmu_unk1 = true,
954 .phy0_dual_route = true,
955 };
956
957 static const struct of_device_id sun4i_usb_phy_of_match[] = {
958 { .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
959 { .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
960 { .compatible = "allwinner,sun6i-a31-usb-phy", .data = &sun6i_a31_cfg },
961 { .compatible = "allwinner,sun7i-a20-usb-phy", .data = &sun7i_a20_cfg },
962 { .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg },
963 { .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
964 { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = &sun8i_a83t_cfg },
965 { .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg },
966 { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = &sun8i_v3s_cfg },
967 { .compatible = "allwinner,sun50i-a64-usb-phy",
968 .data = &sun50i_a64_cfg},
969 { },
970 };
971 MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
972
973 static struct platform_driver sun4i_usb_phy_driver = {
974 .probe = sun4i_usb_phy_probe,
975 .remove = sun4i_usb_phy_remove,
976 .driver = {
977 .of_match_table = sun4i_usb_phy_of_match,
978 .name = "sun4i-usb-phy",
979 }
980 };
981 module_platform_driver(sun4i_usb_phy_driver);
982
983 MODULE_DESCRIPTION("Allwinner sun4i USB phy driver");
984 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
985 MODULE_LICENSE("GPL v2");
986