1 /*
2 * R8A7795 ES2.0+ processor support - PFC hardware block.
3 *
4 * Copyright (C) 2015-2016 Renesas Electronics Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/sys_soc.h>
13
14 #include "core.h"
15 #include "sh_pfc.h"
16
17 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
18 SH_PFC_PIN_CFG_PULL_UP | \
19 SH_PFC_PIN_CFG_PULL_DOWN)
20
21 #define CPU_ALL_PORT(fn, sfx) \
22 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
34 /*
35 * F_() : just information
36 * FM() : macro for FN_xxx / xxx_MARK
37 */
38
39 /* GPSR0 */
40 #define GPSR0_15 F_(D15, IP7_11_8)
41 #define GPSR0_14 F_(D14, IP7_7_4)
42 #define GPSR0_13 F_(D13, IP7_3_0)
43 #define GPSR0_12 F_(D12, IP6_31_28)
44 #define GPSR0_11 F_(D11, IP6_27_24)
45 #define GPSR0_10 F_(D10, IP6_23_20)
46 #define GPSR0_9 F_(D9, IP6_19_16)
47 #define GPSR0_8 F_(D8, IP6_15_12)
48 #define GPSR0_7 F_(D7, IP6_11_8)
49 #define GPSR0_6 F_(D6, IP6_7_4)
50 #define GPSR0_5 F_(D5, IP6_3_0)
51 #define GPSR0_4 F_(D4, IP5_31_28)
52 #define GPSR0_3 F_(D3, IP5_27_24)
53 #define GPSR0_2 F_(D2, IP5_23_20)
54 #define GPSR0_1 F_(D1, IP5_19_16)
55 #define GPSR0_0 F_(D0, IP5_15_12)
56
57 /* GPSR1 */
58 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
59 #define GPSR1_26 F_(WE1_N, IP5_7_4)
60 #define GPSR1_25 F_(WE0_N, IP5_3_0)
61 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
62 #define GPSR1_23 F_(RD_N, IP4_27_24)
63 #define GPSR1_22 F_(BS_N, IP4_23_20)
64 #define GPSR1_21 F_(CS1_N, IP4_19_16)
65 #define GPSR1_20 F_(CS0_N, IP4_15_12)
66 #define GPSR1_19 F_(A19, IP4_11_8)
67 #define GPSR1_18 F_(A18, IP4_7_4)
68 #define GPSR1_17 F_(A17, IP4_3_0)
69 #define GPSR1_16 F_(A16, IP3_31_28)
70 #define GPSR1_15 F_(A15, IP3_27_24)
71 #define GPSR1_14 F_(A14, IP3_23_20)
72 #define GPSR1_13 F_(A13, IP3_19_16)
73 #define GPSR1_12 F_(A12, IP3_15_12)
74 #define GPSR1_11 F_(A11, IP3_11_8)
75 #define GPSR1_10 F_(A10, IP3_7_4)
76 #define GPSR1_9 F_(A9, IP3_3_0)
77 #define GPSR1_8 F_(A8, IP2_31_28)
78 #define GPSR1_7 F_(A7, IP2_27_24)
79 #define GPSR1_6 F_(A6, IP2_23_20)
80 #define GPSR1_5 F_(A5, IP2_19_16)
81 #define GPSR1_4 F_(A4, IP2_15_12)
82 #define GPSR1_3 F_(A3, IP2_11_8)
83 #define GPSR1_2 F_(A2, IP2_7_4)
84 #define GPSR1_1 F_(A1, IP2_3_0)
85 #define GPSR1_0 F_(A0, IP1_31_28)
86
87 /* GPSR2 */
88 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
89 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
90 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
91 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
92 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
93 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
94 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
95 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
96 #define GPSR2_6 F_(PWM0, IP1_19_16)
97 #define GPSR2_5 F_(IRQ5, IP1_15_12)
98 #define GPSR2_4 F_(IRQ4, IP1_11_8)
99 #define GPSR2_3 F_(IRQ3, IP1_7_4)
100 #define GPSR2_2 F_(IRQ2, IP1_3_0)
101 #define GPSR2_1 F_(IRQ1, IP0_31_28)
102 #define GPSR2_0 F_(IRQ0, IP0_27_24)
103
104 /* GPSR3 */
105 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
106 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
107 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
108 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
109 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
110 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
111 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
112 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
113 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
114 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
115 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
116 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
117 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
118 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
119 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
120 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
121
122 /* GPSR4 */
123 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
124 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
125 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
126 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
127 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
128 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
129 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
130 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
131 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
132 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
133 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
134 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
135 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
136 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
137 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
138 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
139 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
140 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
141
142 /* GPSR5 */
143 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
144 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
145 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
146 #define GPSR5_22 FM(MSIOF0_RXD)
147 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
148 #define GPSR5_20 FM(MSIOF0_TXD)
149 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
150 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
151 #define GPSR5_17 FM(MSIOF0_SCK)
152 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
153 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
154 #define GPSR5_14 F_(HTX0, IP13_19_16)
155 #define GPSR5_13 F_(HRX0, IP13_15_12)
156 #define GPSR5_12 F_(HSCK0, IP13_11_8)
157 #define GPSR5_11 F_(RX2_A, IP13_7_4)
158 #define GPSR5_10 F_(TX2_A, IP13_3_0)
159 #define GPSR5_9 F_(SCK2, IP12_31_28)
160 #define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24)
161 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
162 #define GPSR5_6 F_(TX1_A, IP12_19_16)
163 #define GPSR5_5 F_(RX1_A, IP12_15_12)
164 #define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8)
165 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
166 #define GPSR5_2 F_(TX0, IP12_3_0)
167 #define GPSR5_1 F_(RX0, IP11_31_28)
168 #define GPSR5_0 F_(SCK0, IP11_27_24)
169
170 /* GPSR6 */
171 #define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
172 #define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
173 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
174 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
175 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
176 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
177 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
178 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
179 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
180 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
181 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
182 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
183 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
184 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
185 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
186 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
187 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
188 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
189 #define GPSR6_13 FM(SSI_SDATA5)
190 #define GPSR6_12 FM(SSI_WS5)
191 #define GPSR6_11 FM(SSI_SCK5)
192 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
193 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
194 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
195 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
196 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
197 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
198 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
199 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
200 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
201 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
202 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
203
204 /* GPSR7 */
205 #define GPSR7_3 FM(HDMI1_CEC)
206 #define GPSR7_2 FM(HDMI0_CEC)
207 #define GPSR7_1 FM(AVS2)
208 #define GPSR7_0 FM(AVS1)
209
210
211 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
212 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231
232 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
233 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274
275 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
276 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306
307 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
308 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
329 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336
337 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
338 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
358 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
359 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
360 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
361 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
362 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
364 #define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
365
366 #define PINMUX_GPSR \
367 \
368 GPSR6_31 \
369 GPSR6_30 \
370 GPSR6_29 \
371 GPSR6_28 \
372 GPSR1_27 GPSR6_27 \
373 GPSR1_26 GPSR6_26 \
374 GPSR1_25 GPSR5_25 GPSR6_25 \
375 GPSR1_24 GPSR5_24 GPSR6_24 \
376 GPSR1_23 GPSR5_23 GPSR6_23 \
377 GPSR1_22 GPSR5_22 GPSR6_22 \
378 GPSR1_21 GPSR5_21 GPSR6_21 \
379 GPSR1_20 GPSR5_20 GPSR6_20 \
380 GPSR1_19 GPSR5_19 GPSR6_19 \
381 GPSR1_18 GPSR5_18 GPSR6_18 \
382 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
383 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
384 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
385 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
386 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
387 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
388 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
389 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
390 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
391 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
392 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
393 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
394 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
395 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
396 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
397 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
398 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
399 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
400
401 #define PINMUX_IPSR \
402 \
403 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
404 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
405 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
406 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
407 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
408 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
409 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
410 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
411 \
412 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
413 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
414 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
415 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
416 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
417 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
418 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
419 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
420 \
421 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
422 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
423 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
424 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
425 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
426 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
427 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
428 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
429 \
430 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
431 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
432 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
433 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
434 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
435 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
436 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
437 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
438 \
439 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
440 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
441 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
442 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
443 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
444 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
445 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
446 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
447
448 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
449 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
450 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
451 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
452 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
453 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
454 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
455 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
456 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
457 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
458 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
459 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
460 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
461 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
462 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
463 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
464 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
465 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
466 #define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
467
468 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
469 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
470 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
471 #define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
472 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
473 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
474 #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
475 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
476 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
477 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
478 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
479 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
480 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
481 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
482 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
483 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
484 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
485 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
486 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
487 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
488 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
489 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
490 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
491
492 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
493 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
494 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
495 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
496 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
497 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
498 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
499 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
500 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
501 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
502 #define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
503 #define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
504 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
505
506 #define PINMUX_MOD_SELS \
507 \
508 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
509 MOD_SEL2_30 \
510 MOD_SEL1_29_28_27 MOD_SEL2_29 \
511 MOD_SEL0_28_27 MOD_SEL2_28_27 \
512 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
513 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
514 MOD_SEL0_23 MOD_SEL1_23_22_21 \
515 MOD_SEL0_22 \
516 MOD_SEL0_21 MOD_SEL2_21 \
517 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
518 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
519 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
520 MOD_SEL2_17 \
521 MOD_SEL0_16 MOD_SEL1_16 \
522 MOD_SEL1_15_14 \
523 MOD_SEL0_14_13 \
524 MOD_SEL1_13 \
525 MOD_SEL0_12 MOD_SEL1_12 \
526 MOD_SEL0_11 MOD_SEL1_11 \
527 MOD_SEL0_10 MOD_SEL1_10 \
528 MOD_SEL0_9_8 MOD_SEL1_9 \
529 MOD_SEL0_7_6 \
530 MOD_SEL1_6 \
531 MOD_SEL0_5 MOD_SEL1_5 \
532 MOD_SEL0_4_3 MOD_SEL1_4 \
533 MOD_SEL1_3 \
534 MOD_SEL1_2 \
535 MOD_SEL1_1 \
536 MOD_SEL1_0 MOD_SEL2_0
537
538 /*
539 * These pins are not able to be muxed but have other properties
540 * that can be set, such as drive-strength or pull-up/pull-down enable.
541 */
542 #define PINMUX_STATIC \
543 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
544 FM(QSPI0_IO2) FM(QSPI0_IO3) \
545 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
546 FM(QSPI1_IO2) FM(QSPI1_IO3) \
547 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
548 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
549 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
550 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
551 FM(CLKOUT) FM(PRESETOUT) \
552 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
553 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
554
555 enum {
556 PINMUX_RESERVED = 0,
557
558 PINMUX_DATA_BEGIN,
559 GP_ALL(DATA),
560 PINMUX_DATA_END,
561
562 #define F_(x, y)
563 #define FM(x) FN_##x,
564 PINMUX_FUNCTION_BEGIN,
565 GP_ALL(FN),
566 PINMUX_GPSR
567 PINMUX_IPSR
568 PINMUX_MOD_SELS
569 PINMUX_FUNCTION_END,
570 #undef F_
571 #undef FM
572
573 #define F_(x, y)
574 #define FM(x) x##_MARK,
575 PINMUX_MARK_BEGIN,
576 PINMUX_GPSR
577 PINMUX_IPSR
578 PINMUX_MOD_SELS
579 PINMUX_STATIC
580 PINMUX_MARK_END,
581 #undef F_
582 #undef FM
583 };
584
585 static const u16 pinmux_data[] = {
586 PINMUX_DATA_GP_ALL(),
587
588 PINMUX_SINGLE(AVS1),
589 PINMUX_SINGLE(AVS2),
590 PINMUX_SINGLE(HDMI0_CEC),
591 PINMUX_SINGLE(HDMI1_CEC),
592 PINMUX_SINGLE(I2C_SEL_0_1),
593 PINMUX_SINGLE(I2C_SEL_3_1),
594 PINMUX_SINGLE(I2C_SEL_5_1),
595 PINMUX_SINGLE(MSIOF0_RXD),
596 PINMUX_SINGLE(MSIOF0_SCK),
597 PINMUX_SINGLE(MSIOF0_TXD),
598 PINMUX_SINGLE(SSI_SCK5),
599 PINMUX_SINGLE(SSI_SDATA5),
600 PINMUX_SINGLE(SSI_WS5),
601
602 /* IPSR0 */
603 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
604 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
605
606 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
607 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
608 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
609
610 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
611 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
612 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
613
614 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
615 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
616 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
617
618 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
619 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
620 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
621 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
622
623 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
624 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
625 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
626
627 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
628 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
629 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
630 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
631 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
632 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
633 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
634
635 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
636 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
637 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
638 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
639 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
640 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
641 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
642
643 /* IPSR1 */
644 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
645 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
646 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
647 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
648 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
649 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
650
651 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
652 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
653 PINMUX_IPSR_GPSR(IP1_7_4, A25),
654 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
655 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
656 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
657 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
658
659 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
660 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
661 PINMUX_IPSR_GPSR(IP1_11_8, A24),
662 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
663 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
664 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
665 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
666
667 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
668 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
669 PINMUX_IPSR_GPSR(IP1_15_12, A23),
670 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
671 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
672 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
673 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
674 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
675
676 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
677 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
678 PINMUX_IPSR_GPSR(IP1_19_16, A22),
679 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
680 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
681
682 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
683 PINMUX_IPSR_GPSR(IP1_23_20, A21),
684 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
685 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
686 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
687
688 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
689 PINMUX_IPSR_GPSR(IP1_27_24, A20),
690 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
691 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
692
693 PINMUX_IPSR_GPSR(IP1_31_28, A0),
694 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
695 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
696 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
697 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
698 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
699
700 /* IPSR2 */
701 PINMUX_IPSR_GPSR(IP2_3_0, A1),
702 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
703 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
704 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
705 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
706 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
707
708 PINMUX_IPSR_GPSR(IP2_7_4, A2),
709 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
710 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
711 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
712 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
713 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
714
715 PINMUX_IPSR_GPSR(IP2_11_8, A3),
716 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
717 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
718 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
719 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
720 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
721
722 PINMUX_IPSR_GPSR(IP2_15_12, A4),
723 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
724 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
725 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
726 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
727 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
728
729 PINMUX_IPSR_GPSR(IP2_19_16, A5),
730 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
731 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
732 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
733 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
734 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
735 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
736
737 PINMUX_IPSR_GPSR(IP2_23_20, A6),
738 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
739 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
740 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
741 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
742 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
743 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
744
745 PINMUX_IPSR_GPSR(IP2_27_24, A7),
746 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
747 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
748 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
749 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
750 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
751 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
752
753 PINMUX_IPSR_GPSR(IP2_31_28, A8),
754 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
755 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
756 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
757 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
758 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
759 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
760
761 /* IPSR3 */
762 PINMUX_IPSR_GPSR(IP3_3_0, A9),
763 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
764 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
765 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
766
767 PINMUX_IPSR_GPSR(IP3_7_4, A10),
768 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
769 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
770 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
771
772 PINMUX_IPSR_GPSR(IP3_11_8, A11),
773 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
774 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
775 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
776 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
777 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
778 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
779 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
780 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
781
782 PINMUX_IPSR_GPSR(IP3_15_12, A12),
783 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
784 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
785 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
786 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
787 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
788
789 PINMUX_IPSR_GPSR(IP3_19_16, A13),
790 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
791 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
792 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
793 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
794 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
795
796 PINMUX_IPSR_GPSR(IP3_23_20, A14),
797 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
798 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
799 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
800 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
801 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
802
803 PINMUX_IPSR_GPSR(IP3_27_24, A15),
804 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
805 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
806 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
807 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
808 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
809
810 PINMUX_IPSR_GPSR(IP3_31_28, A16),
811 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
812 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
813 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
814
815 /* IPSR4 */
816 PINMUX_IPSR_GPSR(IP4_3_0, A17),
817 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
818 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
819 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
820
821 PINMUX_IPSR_GPSR(IP4_7_4, A18),
822 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
823 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
824 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
825
826 PINMUX_IPSR_GPSR(IP4_11_8, A19),
827 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
828 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
829 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
830
831 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
832 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
833
834 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
835 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
836 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
837
838 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
839 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
840 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
841 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
842 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
843 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
844 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
845 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
846
847 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
848 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
849 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
850 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
851 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
852 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
853
854 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
855 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
856 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
857 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
858 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
859 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
860
861 /* IPSR5 */
862 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
863 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
864 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
865 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
866 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
867 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
868 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
869
870 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
871 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
872 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
873 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
874 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
875 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
876 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
877 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
878
879 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
880 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
881 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
882 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
883
884 PINMUX_IPSR_GPSR(IP5_15_12, D0),
885 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
886 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
887 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
888 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
889
890 PINMUX_IPSR_GPSR(IP5_19_16, D1),
891 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
892 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
893 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
894 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
895
896 PINMUX_IPSR_GPSR(IP5_23_20, D2),
897 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
898 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
899 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
900
901 PINMUX_IPSR_GPSR(IP5_27_24, D3),
902 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
903 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
904 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
905
906 PINMUX_IPSR_GPSR(IP5_31_28, D4),
907 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
908 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
909 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
910
911 /* IPSR6 */
912 PINMUX_IPSR_GPSR(IP6_3_0, D5),
913 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
914 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
915 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
916
917 PINMUX_IPSR_GPSR(IP6_7_4, D6),
918 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
919 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
920 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
921
922 PINMUX_IPSR_GPSR(IP6_11_8, D7),
923 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
924 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
925 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
926
927 PINMUX_IPSR_GPSR(IP6_15_12, D8),
928 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
929 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
930 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
931 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
932 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
933
934 PINMUX_IPSR_GPSR(IP6_19_16, D9),
935 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
936 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
937 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
938 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
939
940 PINMUX_IPSR_GPSR(IP6_23_20, D10),
941 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
942 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
943 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
944 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
945 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
946 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
947
948 PINMUX_IPSR_GPSR(IP6_27_24, D11),
949 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
950 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
951 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
952 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
953 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
954 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
955
956 PINMUX_IPSR_GPSR(IP6_31_28, D12),
957 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
958 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
959 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
960 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
961 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
962
963 /* IPSR7 */
964 PINMUX_IPSR_GPSR(IP7_3_0, D13),
965 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
966 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
967 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
968 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
969 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
970
971 PINMUX_IPSR_GPSR(IP7_7_4, D14),
972 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
973 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
974 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
975 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
976 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
977 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
978
979 PINMUX_IPSR_GPSR(IP7_11_8, D15),
980 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
981 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
982 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
983 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
984 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
985 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
986
987 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
988 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
989 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
990
991 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
992 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
993 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
994
995 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
996 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
997 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
998 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
999
1000 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1001 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1002 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1003 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1004
1005 /* IPSR8 */
1006 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1007 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1008 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1009 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1010
1011 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1012 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1013 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1014 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1015
1016 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1017 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1018 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1019
1020 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1021 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1022 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
1023 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1024 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1025
1026 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1027 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1028 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1029 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
1030 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1031 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1032
1033 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1034 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1035 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1036 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
1037 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1038 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1039
1040 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1041 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1042 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1043 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
1044 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1045 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1046
1047 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1048 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1049 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1050 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
1051 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1052 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1053
1054 /* IPSR9 */
1055 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1056 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1057
1058 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1059 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1060
1061 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1062 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1063
1064 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1065 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1066
1067 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1068 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1069
1070 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1071 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1072
1073 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1074 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1075 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1076
1077 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1078 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1079
1080 /* IPSR10 */
1081 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1082 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1083
1084 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1085 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1086
1087 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1088 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1089
1090 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1091 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1092
1093 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1094 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1095
1096 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1097 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1098 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1099
1100 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1101 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1102 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1103
1104 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1105 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1106 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1107
1108 /* IPSR11 */
1109 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1110 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1111 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1112
1113 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1114 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1115
1116 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1117 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1118 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1119
1120 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1121 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1122
1123 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1124 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1125
1126 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1127 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1128
1129 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1130 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1131 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1132 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1133 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1134 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1135 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1136 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1137 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1138 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1139
1140 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1141 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1142 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1143 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1144 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1145
1146 /* IPSR12 */
1147 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1148 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1149 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1150 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1151 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1152
1153 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1154 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1155 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1156 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1157 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1158 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1159 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1160 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1161
1162 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS),
1163 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1164 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1165 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1166 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1167 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1168 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1169 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1170
1171 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1172 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1173 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1174 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1175 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1176
1177 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1178 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1179 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1180 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1181 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1182
1183 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1184 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1185 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1186 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1187 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1188 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1189 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1190
1191 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS),
1192 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1193 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1194 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1195 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1196 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1197 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1198
1199 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1200 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1201 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1202 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1203 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1204 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1205 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1206
1207 /* IPSR13 */
1208 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1209 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1210 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1211 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1212 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1213 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1214
1215 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1216 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1217 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1218 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1219 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1220 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1221
1222 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1223 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1224 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1225 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
1226 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1227 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1228 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1229 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1230
1231 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1232 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1233 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
1234 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1235 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1236 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1237
1238 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1239 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1240 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
1241 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1242 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1243 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1244
1245 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1246 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1247 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1248 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
1249 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1250 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1251 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1252 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1253
1254 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1255 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1256 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1257 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
1258 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1259 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1260 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1261
1262 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1263 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1264 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1265 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1266
1267 /* IPSR14 */
1268 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1269 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1270 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
1271 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1272 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
1273 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1274 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1275 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
1276
1277 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1278 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1279 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1280 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1281 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
1282 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1283 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1284 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1285
1286 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1287 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1288 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1289
1290 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1291 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1292 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1293 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1294
1295 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1296 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1297 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1298
1299 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1300 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1301
1302 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1303 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1304
1305 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1306 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1307
1308 /* IPSR15 */
1309 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
1310
1311 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
1312 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
1313
1314 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1315 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1316 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1317
1318 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1319 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1320 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1321 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1322
1323 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1324 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1325 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1326 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1327 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1328 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1330
1331 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1332 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1333 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1334 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1335 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1336 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1338
1339 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1340 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1341 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1342 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1343 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1344 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1346
1347 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1348 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1349 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1350 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1351 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1352 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1354
1355 /* IPSR16 */
1356 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1357 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1358 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1359
1360 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1361 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1362 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1363
1364 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1365 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1366 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1367
1368 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1369 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1370 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1371 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1372 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1373 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1374 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1375
1376 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1377 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1378 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1379 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1380 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1381 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1382 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1383
1384 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1385 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1386 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1387 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1388 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1389 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1390 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1391 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1392
1393 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1394 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1395 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1396 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1397 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1398 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1399 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1400
1401 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
1402 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1403 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1404 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1405 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
1406 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1407 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1408 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1409
1410 /* IPSR17 */
1411 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1412 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1413
1414 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
1415 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1416 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1417 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1418 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
1419
1420 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1421 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1422 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1423 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1424 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1425 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1426 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1427
1428 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1429 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1430 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1431 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1432 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1433 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1434
1435 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1436 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1437 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
1438 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1439 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1440 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1441 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1442 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1443 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1444
1445 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1446 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1447 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
1448 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1449 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1450 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1451 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1452 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1453 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1454
1455 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1456 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1457 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
1458 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1459 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1460 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1461 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1462 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1463 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1464 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1465 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1466
1467 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1468 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1469 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
1470 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1471 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1472 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1473 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1474 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1475 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1476
1477 /* IPSR18 */
1478 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
1479 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1480 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
1481 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1482 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1483 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1484 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1485 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1486 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1487
1488 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
1489 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1490 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
1491 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1492 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1493 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1494 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1495 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1496 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1497
1498 /*
1499 * Static pins can not be muxed between different functions but
1500 * still needs a mark entry in the pinmux list. Add each static
1501 * pin to the list without an associated function. The sh-pfc
1502 * core will do the right thing and skip trying to mux then pin
1503 * while still applying configuration to it
1504 */
1505 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1506 PINMUX_STATIC
1507 #undef FM
1508 };
1509
1510 /*
1511 * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs.
1512 * Physical layout rows: A - AW, cols: 1 - 39.
1513 */
1514 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1515 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1516 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1517
1518 static const struct sh_pfc_pin pinmux_pins[] = {
1519 PINMUX_GPIO_GP_ALL(),
1520
1521 /*
1522 * Pins not associated with a GPIO port.
1523 *
1524 * The pin positions are different between different r8a7795
1525 * packages, all that is needed for the pfc driver is a unique
1526 * number for each pin. To this end use the pin layout from
1527 * R-Car H3SiP to calculate a unique number for each pin.
1528 */
1529 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1530 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1531 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1532 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1533 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1573 };
1574
1575 /* - EtherAVB --------------------------------------------------------------- */
1576 static const unsigned int avb_link_pins[] = {
1577 /* AVB_LINK */
1578 RCAR_GP_PIN(2, 12),
1579 };
1580 static const unsigned int avb_link_mux[] = {
1581 AVB_LINK_MARK,
1582 };
1583 static const unsigned int avb_magic_pins[] = {
1584 /* AVB_MAGIC_ */
1585 RCAR_GP_PIN(2, 10),
1586 };
1587 static const unsigned int avb_magic_mux[] = {
1588 AVB_MAGIC_MARK,
1589 };
1590 static const unsigned int avb_phy_int_pins[] = {
1591 /* AVB_PHY_INT */
1592 RCAR_GP_PIN(2, 11),
1593 };
1594 static const unsigned int avb_phy_int_mux[] = {
1595 AVB_PHY_INT_MARK,
1596 };
1597 static const unsigned int avb_mdc_pins[] = {
1598 /* AVB_MDC, AVB_MDIO */
1599 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1600 };
1601 static const unsigned int avb_mdc_mux[] = {
1602 AVB_MDC_MARK, AVB_MDIO_MARK,
1603 };
1604 static const unsigned int avb_mii_pins[] = {
1605 /*
1606 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1607 * AVB_TD1, AVB_TD2, AVB_TD3,
1608 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1609 * AVB_RD1, AVB_RD2, AVB_RD3,
1610 * AVB_TXCREFCLK
1611 */
1612 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1613 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1614 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1615 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1616 PIN_NUMBER('A', 12),
1617
1618 };
1619 static const unsigned int avb_mii_mux[] = {
1620 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1621 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1622 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1623 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1624 AVB_TXCREFCLK_MARK,
1625 };
1626 static const unsigned int avb_avtp_pps_pins[] = {
1627 /* AVB_AVTP_PPS */
1628 RCAR_GP_PIN(2, 6),
1629 };
1630 static const unsigned int avb_avtp_pps_mux[] = {
1631 AVB_AVTP_PPS_MARK,
1632 };
1633 static const unsigned int avb_avtp_match_a_pins[] = {
1634 /* AVB_AVTP_MATCH_A */
1635 RCAR_GP_PIN(2, 13),
1636 };
1637 static const unsigned int avb_avtp_match_a_mux[] = {
1638 AVB_AVTP_MATCH_A_MARK,
1639 };
1640 static const unsigned int avb_avtp_capture_a_pins[] = {
1641 /* AVB_AVTP_CAPTURE_A */
1642 RCAR_GP_PIN(2, 14),
1643 };
1644 static const unsigned int avb_avtp_capture_a_mux[] = {
1645 AVB_AVTP_CAPTURE_A_MARK,
1646 };
1647 static const unsigned int avb_avtp_match_b_pins[] = {
1648 /* AVB_AVTP_MATCH_B */
1649 RCAR_GP_PIN(1, 8),
1650 };
1651 static const unsigned int avb_avtp_match_b_mux[] = {
1652 AVB_AVTP_MATCH_B_MARK,
1653 };
1654 static const unsigned int avb_avtp_capture_b_pins[] = {
1655 /* AVB_AVTP_CAPTURE_B */
1656 RCAR_GP_PIN(1, 11),
1657 };
1658 static const unsigned int avb_avtp_capture_b_mux[] = {
1659 AVB_AVTP_CAPTURE_B_MARK,
1660 };
1661
1662 /* - DU --------------------------------------------------------------------- */
1663 static const unsigned int du_rgb666_pins[] = {
1664 /* R[7:2], G[7:2], B[7:2] */
1665 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1666 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1667 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1668 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1669 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1670 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1671 };
1672 static const unsigned int du_rgb666_mux[] = {
1673 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1674 DU_DR3_MARK, DU_DR2_MARK,
1675 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1676 DU_DG3_MARK, DU_DG2_MARK,
1677 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1678 DU_DB3_MARK, DU_DB2_MARK,
1679 };
1680 static const unsigned int du_rgb888_pins[] = {
1681 /* R[7:0], G[7:0], B[7:0] */
1682 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1683 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1684 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1685 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1686 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1687 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1688 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1689 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1690 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
1691 };
1692 static const unsigned int du_rgb888_mux[] = {
1693 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1694 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1695 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1696 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1697 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1698 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1699 };
1700 static const unsigned int du_clk_out_0_pins[] = {
1701 /* CLKOUT */
1702 RCAR_GP_PIN(1, 27),
1703 };
1704 static const unsigned int du_clk_out_0_mux[] = {
1705 DU_DOTCLKOUT0_MARK
1706 };
1707 static const unsigned int du_clk_out_1_pins[] = {
1708 /* CLKOUT */
1709 RCAR_GP_PIN(2, 3),
1710 };
1711 static const unsigned int du_clk_out_1_mux[] = {
1712 DU_DOTCLKOUT1_MARK
1713 };
1714 static const unsigned int du_sync_pins[] = {
1715 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1716 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
1717 };
1718 static const unsigned int du_sync_mux[] = {
1719 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
1720 };
1721 static const unsigned int du_oddf_pins[] = {
1722 /* EXDISP/EXODDF/EXCDE */
1723 RCAR_GP_PIN(2, 2),
1724 };
1725 static const unsigned int du_oddf_mux[] = {
1726 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1727 };
1728 static const unsigned int du_cde_pins[] = {
1729 /* CDE */
1730 RCAR_GP_PIN(2, 0),
1731 };
1732 static const unsigned int du_cde_mux[] = {
1733 DU_CDE_MARK,
1734 };
1735 static const unsigned int du_disp_pins[] = {
1736 /* DISP */
1737 RCAR_GP_PIN(2, 1),
1738 };
1739 static const unsigned int du_disp_mux[] = {
1740 DU_DISP_MARK,
1741 };
1742
1743 /* - MSIOF0 ----------------------------------------------------------------- */
1744 static const unsigned int msiof0_clk_pins[] = {
1745 /* SCK */
1746 RCAR_GP_PIN(5, 17),
1747 };
1748 static const unsigned int msiof0_clk_mux[] = {
1749 MSIOF0_SCK_MARK,
1750 };
1751 static const unsigned int msiof0_sync_pins[] = {
1752 /* SYNC */
1753 RCAR_GP_PIN(5, 18),
1754 };
1755 static const unsigned int msiof0_sync_mux[] = {
1756 MSIOF0_SYNC_MARK,
1757 };
1758 static const unsigned int msiof0_ss1_pins[] = {
1759 /* SS1 */
1760 RCAR_GP_PIN(5, 19),
1761 };
1762 static const unsigned int msiof0_ss1_mux[] = {
1763 MSIOF0_SS1_MARK,
1764 };
1765 static const unsigned int msiof0_ss2_pins[] = {
1766 /* SS2 */
1767 RCAR_GP_PIN(5, 21),
1768 };
1769 static const unsigned int msiof0_ss2_mux[] = {
1770 MSIOF0_SS2_MARK,
1771 };
1772 static const unsigned int msiof0_txd_pins[] = {
1773 /* TXD */
1774 RCAR_GP_PIN(5, 20),
1775 };
1776 static const unsigned int msiof0_txd_mux[] = {
1777 MSIOF0_TXD_MARK,
1778 };
1779 static const unsigned int msiof0_rxd_pins[] = {
1780 /* RXD */
1781 RCAR_GP_PIN(5, 22),
1782 };
1783 static const unsigned int msiof0_rxd_mux[] = {
1784 MSIOF0_RXD_MARK,
1785 };
1786 /* - MSIOF1 ----------------------------------------------------------------- */
1787 static const unsigned int msiof1_clk_a_pins[] = {
1788 /* SCK */
1789 RCAR_GP_PIN(6, 8),
1790 };
1791 static const unsigned int msiof1_clk_a_mux[] = {
1792 MSIOF1_SCK_A_MARK,
1793 };
1794 static const unsigned int msiof1_sync_a_pins[] = {
1795 /* SYNC */
1796 RCAR_GP_PIN(6, 9),
1797 };
1798 static const unsigned int msiof1_sync_a_mux[] = {
1799 MSIOF1_SYNC_A_MARK,
1800 };
1801 static const unsigned int msiof1_ss1_a_pins[] = {
1802 /* SS1 */
1803 RCAR_GP_PIN(6, 5),
1804 };
1805 static const unsigned int msiof1_ss1_a_mux[] = {
1806 MSIOF1_SS1_A_MARK,
1807 };
1808 static const unsigned int msiof1_ss2_a_pins[] = {
1809 /* SS2 */
1810 RCAR_GP_PIN(6, 6),
1811 };
1812 static const unsigned int msiof1_ss2_a_mux[] = {
1813 MSIOF1_SS2_A_MARK,
1814 };
1815 static const unsigned int msiof1_txd_a_pins[] = {
1816 /* TXD */
1817 RCAR_GP_PIN(6, 7),
1818 };
1819 static const unsigned int msiof1_txd_a_mux[] = {
1820 MSIOF1_TXD_A_MARK,
1821 };
1822 static const unsigned int msiof1_rxd_a_pins[] = {
1823 /* RXD */
1824 RCAR_GP_PIN(6, 10),
1825 };
1826 static const unsigned int msiof1_rxd_a_mux[] = {
1827 MSIOF1_RXD_A_MARK,
1828 };
1829 static const unsigned int msiof1_clk_b_pins[] = {
1830 /* SCK */
1831 RCAR_GP_PIN(5, 9),
1832 };
1833 static const unsigned int msiof1_clk_b_mux[] = {
1834 MSIOF1_SCK_B_MARK,
1835 };
1836 static const unsigned int msiof1_sync_b_pins[] = {
1837 /* SYNC */
1838 RCAR_GP_PIN(5, 3),
1839 };
1840 static const unsigned int msiof1_sync_b_mux[] = {
1841 MSIOF1_SYNC_B_MARK,
1842 };
1843 static const unsigned int msiof1_ss1_b_pins[] = {
1844 /* SS1 */
1845 RCAR_GP_PIN(5, 4),
1846 };
1847 static const unsigned int msiof1_ss1_b_mux[] = {
1848 MSIOF1_SS1_B_MARK,
1849 };
1850 static const unsigned int msiof1_ss2_b_pins[] = {
1851 /* SS2 */
1852 RCAR_GP_PIN(5, 0),
1853 };
1854 static const unsigned int msiof1_ss2_b_mux[] = {
1855 MSIOF1_SS2_B_MARK,
1856 };
1857 static const unsigned int msiof1_txd_b_pins[] = {
1858 /* TXD */
1859 RCAR_GP_PIN(5, 8),
1860 };
1861 static const unsigned int msiof1_txd_b_mux[] = {
1862 MSIOF1_TXD_B_MARK,
1863 };
1864 static const unsigned int msiof1_rxd_b_pins[] = {
1865 /* RXD */
1866 RCAR_GP_PIN(5, 7),
1867 };
1868 static const unsigned int msiof1_rxd_b_mux[] = {
1869 MSIOF1_RXD_B_MARK,
1870 };
1871 static const unsigned int msiof1_clk_c_pins[] = {
1872 /* SCK */
1873 RCAR_GP_PIN(6, 17),
1874 };
1875 static const unsigned int msiof1_clk_c_mux[] = {
1876 MSIOF1_SCK_C_MARK,
1877 };
1878 static const unsigned int msiof1_sync_c_pins[] = {
1879 /* SYNC */
1880 RCAR_GP_PIN(6, 18),
1881 };
1882 static const unsigned int msiof1_sync_c_mux[] = {
1883 MSIOF1_SYNC_C_MARK,
1884 };
1885 static const unsigned int msiof1_ss1_c_pins[] = {
1886 /* SS1 */
1887 RCAR_GP_PIN(6, 21),
1888 };
1889 static const unsigned int msiof1_ss1_c_mux[] = {
1890 MSIOF1_SS1_C_MARK,
1891 };
1892 static const unsigned int msiof1_ss2_c_pins[] = {
1893 /* SS2 */
1894 RCAR_GP_PIN(6, 27),
1895 };
1896 static const unsigned int msiof1_ss2_c_mux[] = {
1897 MSIOF1_SS2_C_MARK,
1898 };
1899 static const unsigned int msiof1_txd_c_pins[] = {
1900 /* TXD */
1901 RCAR_GP_PIN(6, 20),
1902 };
1903 static const unsigned int msiof1_txd_c_mux[] = {
1904 MSIOF1_TXD_C_MARK,
1905 };
1906 static const unsigned int msiof1_rxd_c_pins[] = {
1907 /* RXD */
1908 RCAR_GP_PIN(6, 19),
1909 };
1910 static const unsigned int msiof1_rxd_c_mux[] = {
1911 MSIOF1_RXD_C_MARK,
1912 };
1913 static const unsigned int msiof1_clk_d_pins[] = {
1914 /* SCK */
1915 RCAR_GP_PIN(5, 12),
1916 };
1917 static const unsigned int msiof1_clk_d_mux[] = {
1918 MSIOF1_SCK_D_MARK,
1919 };
1920 static const unsigned int msiof1_sync_d_pins[] = {
1921 /* SYNC */
1922 RCAR_GP_PIN(5, 15),
1923 };
1924 static const unsigned int msiof1_sync_d_mux[] = {
1925 MSIOF1_SYNC_D_MARK,
1926 };
1927 static const unsigned int msiof1_ss1_d_pins[] = {
1928 /* SS1 */
1929 RCAR_GP_PIN(5, 16),
1930 };
1931 static const unsigned int msiof1_ss1_d_mux[] = {
1932 MSIOF1_SS1_D_MARK,
1933 };
1934 static const unsigned int msiof1_ss2_d_pins[] = {
1935 /* SS2 */
1936 RCAR_GP_PIN(5, 21),
1937 };
1938 static const unsigned int msiof1_ss2_d_mux[] = {
1939 MSIOF1_SS2_D_MARK,
1940 };
1941 static const unsigned int msiof1_txd_d_pins[] = {
1942 /* TXD */
1943 RCAR_GP_PIN(5, 14),
1944 };
1945 static const unsigned int msiof1_txd_d_mux[] = {
1946 MSIOF1_TXD_D_MARK,
1947 };
1948 static const unsigned int msiof1_rxd_d_pins[] = {
1949 /* RXD */
1950 RCAR_GP_PIN(5, 13),
1951 };
1952 static const unsigned int msiof1_rxd_d_mux[] = {
1953 MSIOF1_RXD_D_MARK,
1954 };
1955 static const unsigned int msiof1_clk_e_pins[] = {
1956 /* SCK */
1957 RCAR_GP_PIN(3, 0),
1958 };
1959 static const unsigned int msiof1_clk_e_mux[] = {
1960 MSIOF1_SCK_E_MARK,
1961 };
1962 static const unsigned int msiof1_sync_e_pins[] = {
1963 /* SYNC */
1964 RCAR_GP_PIN(3, 1),
1965 };
1966 static const unsigned int msiof1_sync_e_mux[] = {
1967 MSIOF1_SYNC_E_MARK,
1968 };
1969 static const unsigned int msiof1_ss1_e_pins[] = {
1970 /* SS1 */
1971 RCAR_GP_PIN(3, 4),
1972 };
1973 static const unsigned int msiof1_ss1_e_mux[] = {
1974 MSIOF1_SS1_E_MARK,
1975 };
1976 static const unsigned int msiof1_ss2_e_pins[] = {
1977 /* SS2 */
1978 RCAR_GP_PIN(3, 5),
1979 };
1980 static const unsigned int msiof1_ss2_e_mux[] = {
1981 MSIOF1_SS2_E_MARK,
1982 };
1983 static const unsigned int msiof1_txd_e_pins[] = {
1984 /* TXD */
1985 RCAR_GP_PIN(3, 3),
1986 };
1987 static const unsigned int msiof1_txd_e_mux[] = {
1988 MSIOF1_TXD_E_MARK,
1989 };
1990 static const unsigned int msiof1_rxd_e_pins[] = {
1991 /* RXD */
1992 RCAR_GP_PIN(3, 2),
1993 };
1994 static const unsigned int msiof1_rxd_e_mux[] = {
1995 MSIOF1_RXD_E_MARK,
1996 };
1997 static const unsigned int msiof1_clk_f_pins[] = {
1998 /* SCK */
1999 RCAR_GP_PIN(5, 23),
2000 };
2001 static const unsigned int msiof1_clk_f_mux[] = {
2002 MSIOF1_SCK_F_MARK,
2003 };
2004 static const unsigned int msiof1_sync_f_pins[] = {
2005 /* SYNC */
2006 RCAR_GP_PIN(5, 24),
2007 };
2008 static const unsigned int msiof1_sync_f_mux[] = {
2009 MSIOF1_SYNC_F_MARK,
2010 };
2011 static const unsigned int msiof1_ss1_f_pins[] = {
2012 /* SS1 */
2013 RCAR_GP_PIN(6, 1),
2014 };
2015 static const unsigned int msiof1_ss1_f_mux[] = {
2016 MSIOF1_SS1_F_MARK,
2017 };
2018 static const unsigned int msiof1_ss2_f_pins[] = {
2019 /* SS2 */
2020 RCAR_GP_PIN(6, 2),
2021 };
2022 static const unsigned int msiof1_ss2_f_mux[] = {
2023 MSIOF1_SS2_F_MARK,
2024 };
2025 static const unsigned int msiof1_txd_f_pins[] = {
2026 /* TXD */
2027 RCAR_GP_PIN(6, 0),
2028 };
2029 static const unsigned int msiof1_txd_f_mux[] = {
2030 MSIOF1_TXD_F_MARK,
2031 };
2032 static const unsigned int msiof1_rxd_f_pins[] = {
2033 /* RXD */
2034 RCAR_GP_PIN(5, 25),
2035 };
2036 static const unsigned int msiof1_rxd_f_mux[] = {
2037 MSIOF1_RXD_F_MARK,
2038 };
2039 static const unsigned int msiof1_clk_g_pins[] = {
2040 /* SCK */
2041 RCAR_GP_PIN(3, 6),
2042 };
2043 static const unsigned int msiof1_clk_g_mux[] = {
2044 MSIOF1_SCK_G_MARK,
2045 };
2046 static const unsigned int msiof1_sync_g_pins[] = {
2047 /* SYNC */
2048 RCAR_GP_PIN(3, 7),
2049 };
2050 static const unsigned int msiof1_sync_g_mux[] = {
2051 MSIOF1_SYNC_G_MARK,
2052 };
2053 static const unsigned int msiof1_ss1_g_pins[] = {
2054 /* SS1 */
2055 RCAR_GP_PIN(3, 10),
2056 };
2057 static const unsigned int msiof1_ss1_g_mux[] = {
2058 MSIOF1_SS1_G_MARK,
2059 };
2060 static const unsigned int msiof1_ss2_g_pins[] = {
2061 /* SS2 */
2062 RCAR_GP_PIN(3, 11),
2063 };
2064 static const unsigned int msiof1_ss2_g_mux[] = {
2065 MSIOF1_SS2_G_MARK,
2066 };
2067 static const unsigned int msiof1_txd_g_pins[] = {
2068 /* TXD */
2069 RCAR_GP_PIN(3, 9),
2070 };
2071 static const unsigned int msiof1_txd_g_mux[] = {
2072 MSIOF1_TXD_G_MARK,
2073 };
2074 static const unsigned int msiof1_rxd_g_pins[] = {
2075 /* RXD */
2076 RCAR_GP_PIN(3, 8),
2077 };
2078 static const unsigned int msiof1_rxd_g_mux[] = {
2079 MSIOF1_RXD_G_MARK,
2080 };
2081 /* - MSIOF2 ----------------------------------------------------------------- */
2082 static const unsigned int msiof2_clk_a_pins[] = {
2083 /* SCK */
2084 RCAR_GP_PIN(1, 9),
2085 };
2086 static const unsigned int msiof2_clk_a_mux[] = {
2087 MSIOF2_SCK_A_MARK,
2088 };
2089 static const unsigned int msiof2_sync_a_pins[] = {
2090 /* SYNC */
2091 RCAR_GP_PIN(1, 8),
2092 };
2093 static const unsigned int msiof2_sync_a_mux[] = {
2094 MSIOF2_SYNC_A_MARK,
2095 };
2096 static const unsigned int msiof2_ss1_a_pins[] = {
2097 /* SS1 */
2098 RCAR_GP_PIN(1, 6),
2099 };
2100 static const unsigned int msiof2_ss1_a_mux[] = {
2101 MSIOF2_SS1_A_MARK,
2102 };
2103 static const unsigned int msiof2_ss2_a_pins[] = {
2104 /* SS2 */
2105 RCAR_GP_PIN(1, 7),
2106 };
2107 static const unsigned int msiof2_ss2_a_mux[] = {
2108 MSIOF2_SS2_A_MARK,
2109 };
2110 static const unsigned int msiof2_txd_a_pins[] = {
2111 /* TXD */
2112 RCAR_GP_PIN(1, 11),
2113 };
2114 static const unsigned int msiof2_txd_a_mux[] = {
2115 MSIOF2_TXD_A_MARK,
2116 };
2117 static const unsigned int msiof2_rxd_a_pins[] = {
2118 /* RXD */
2119 RCAR_GP_PIN(1, 10),
2120 };
2121 static const unsigned int msiof2_rxd_a_mux[] = {
2122 MSIOF2_RXD_A_MARK,
2123 };
2124 static const unsigned int msiof2_clk_b_pins[] = {
2125 /* SCK */
2126 RCAR_GP_PIN(0, 4),
2127 };
2128 static const unsigned int msiof2_clk_b_mux[] = {
2129 MSIOF2_SCK_B_MARK,
2130 };
2131 static const unsigned int msiof2_sync_b_pins[] = {
2132 /* SYNC */
2133 RCAR_GP_PIN(0, 5),
2134 };
2135 static const unsigned int msiof2_sync_b_mux[] = {
2136 MSIOF2_SYNC_B_MARK,
2137 };
2138 static const unsigned int msiof2_ss1_b_pins[] = {
2139 /* SS1 */
2140 RCAR_GP_PIN(0, 0),
2141 };
2142 static const unsigned int msiof2_ss1_b_mux[] = {
2143 MSIOF2_SS1_B_MARK,
2144 };
2145 static const unsigned int msiof2_ss2_b_pins[] = {
2146 /* SS2 */
2147 RCAR_GP_PIN(0, 1),
2148 };
2149 static const unsigned int msiof2_ss2_b_mux[] = {
2150 MSIOF2_SS2_B_MARK,
2151 };
2152 static const unsigned int msiof2_txd_b_pins[] = {
2153 /* TXD */
2154 RCAR_GP_PIN(0, 7),
2155 };
2156 static const unsigned int msiof2_txd_b_mux[] = {
2157 MSIOF2_TXD_B_MARK,
2158 };
2159 static const unsigned int msiof2_rxd_b_pins[] = {
2160 /* RXD */
2161 RCAR_GP_PIN(0, 6),
2162 };
2163 static const unsigned int msiof2_rxd_b_mux[] = {
2164 MSIOF2_RXD_B_MARK,
2165 };
2166 static const unsigned int msiof2_clk_c_pins[] = {
2167 /* SCK */
2168 RCAR_GP_PIN(2, 12),
2169 };
2170 static const unsigned int msiof2_clk_c_mux[] = {
2171 MSIOF2_SCK_C_MARK,
2172 };
2173 static const unsigned int msiof2_sync_c_pins[] = {
2174 /* SYNC */
2175 RCAR_GP_PIN(2, 11),
2176 };
2177 static const unsigned int msiof2_sync_c_mux[] = {
2178 MSIOF2_SYNC_C_MARK,
2179 };
2180 static const unsigned int msiof2_ss1_c_pins[] = {
2181 /* SS1 */
2182 RCAR_GP_PIN(2, 10),
2183 };
2184 static const unsigned int msiof2_ss1_c_mux[] = {
2185 MSIOF2_SS1_C_MARK,
2186 };
2187 static const unsigned int msiof2_ss2_c_pins[] = {
2188 /* SS2 */
2189 RCAR_GP_PIN(2, 9),
2190 };
2191 static const unsigned int msiof2_ss2_c_mux[] = {
2192 MSIOF2_SS2_C_MARK,
2193 };
2194 static const unsigned int msiof2_txd_c_pins[] = {
2195 /* TXD */
2196 RCAR_GP_PIN(2, 14),
2197 };
2198 static const unsigned int msiof2_txd_c_mux[] = {
2199 MSIOF2_TXD_C_MARK,
2200 };
2201 static const unsigned int msiof2_rxd_c_pins[] = {
2202 /* RXD */
2203 RCAR_GP_PIN(2, 13),
2204 };
2205 static const unsigned int msiof2_rxd_c_mux[] = {
2206 MSIOF2_RXD_C_MARK,
2207 };
2208 static const unsigned int msiof2_clk_d_pins[] = {
2209 /* SCK */
2210 RCAR_GP_PIN(0, 8),
2211 };
2212 static const unsigned int msiof2_clk_d_mux[] = {
2213 MSIOF2_SCK_D_MARK,
2214 };
2215 static const unsigned int msiof2_sync_d_pins[] = {
2216 /* SYNC */
2217 RCAR_GP_PIN(0, 9),
2218 };
2219 static const unsigned int msiof2_sync_d_mux[] = {
2220 MSIOF2_SYNC_D_MARK,
2221 };
2222 static const unsigned int msiof2_ss1_d_pins[] = {
2223 /* SS1 */
2224 RCAR_GP_PIN(0, 12),
2225 };
2226 static const unsigned int msiof2_ss1_d_mux[] = {
2227 MSIOF2_SS1_D_MARK,
2228 };
2229 static const unsigned int msiof2_ss2_d_pins[] = {
2230 /* SS2 */
2231 RCAR_GP_PIN(0, 13),
2232 };
2233 static const unsigned int msiof2_ss2_d_mux[] = {
2234 MSIOF2_SS2_D_MARK,
2235 };
2236 static const unsigned int msiof2_txd_d_pins[] = {
2237 /* TXD */
2238 RCAR_GP_PIN(0, 11),
2239 };
2240 static const unsigned int msiof2_txd_d_mux[] = {
2241 MSIOF2_TXD_D_MARK,
2242 };
2243 static const unsigned int msiof2_rxd_d_pins[] = {
2244 /* RXD */
2245 RCAR_GP_PIN(0, 10),
2246 };
2247 static const unsigned int msiof2_rxd_d_mux[] = {
2248 MSIOF2_RXD_D_MARK,
2249 };
2250 /* - MSIOF3 ----------------------------------------------------------------- */
2251 static const unsigned int msiof3_clk_a_pins[] = {
2252 /* SCK */
2253 RCAR_GP_PIN(0, 0),
2254 };
2255 static const unsigned int msiof3_clk_a_mux[] = {
2256 MSIOF3_SCK_A_MARK,
2257 };
2258 static const unsigned int msiof3_sync_a_pins[] = {
2259 /* SYNC */
2260 RCAR_GP_PIN(0, 1),
2261 };
2262 static const unsigned int msiof3_sync_a_mux[] = {
2263 MSIOF3_SYNC_A_MARK,
2264 };
2265 static const unsigned int msiof3_ss1_a_pins[] = {
2266 /* SS1 */
2267 RCAR_GP_PIN(0, 14),
2268 };
2269 static const unsigned int msiof3_ss1_a_mux[] = {
2270 MSIOF3_SS1_A_MARK,
2271 };
2272 static const unsigned int msiof3_ss2_a_pins[] = {
2273 /* SS2 */
2274 RCAR_GP_PIN(0, 15),
2275 };
2276 static const unsigned int msiof3_ss2_a_mux[] = {
2277 MSIOF3_SS2_A_MARK,
2278 };
2279 static const unsigned int msiof3_txd_a_pins[] = {
2280 /* TXD */
2281 RCAR_GP_PIN(0, 3),
2282 };
2283 static const unsigned int msiof3_txd_a_mux[] = {
2284 MSIOF3_TXD_A_MARK,
2285 };
2286 static const unsigned int msiof3_rxd_a_pins[] = {
2287 /* RXD */
2288 RCAR_GP_PIN(0, 2),
2289 };
2290 static const unsigned int msiof3_rxd_a_mux[] = {
2291 MSIOF3_RXD_A_MARK,
2292 };
2293 static const unsigned int msiof3_clk_b_pins[] = {
2294 /* SCK */
2295 RCAR_GP_PIN(1, 2),
2296 };
2297 static const unsigned int msiof3_clk_b_mux[] = {
2298 MSIOF3_SCK_B_MARK,
2299 };
2300 static const unsigned int msiof3_sync_b_pins[] = {
2301 /* SYNC */
2302 RCAR_GP_PIN(1, 0),
2303 };
2304 static const unsigned int msiof3_sync_b_mux[] = {
2305 MSIOF3_SYNC_B_MARK,
2306 };
2307 static const unsigned int msiof3_ss1_b_pins[] = {
2308 /* SS1 */
2309 RCAR_GP_PIN(1, 4),
2310 };
2311 static const unsigned int msiof3_ss1_b_mux[] = {
2312 MSIOF3_SS1_B_MARK,
2313 };
2314 static const unsigned int msiof3_ss2_b_pins[] = {
2315 /* SS2 */
2316 RCAR_GP_PIN(1, 5),
2317 };
2318 static const unsigned int msiof3_ss2_b_mux[] = {
2319 MSIOF3_SS2_B_MARK,
2320 };
2321 static const unsigned int msiof3_txd_b_pins[] = {
2322 /* TXD */
2323 RCAR_GP_PIN(1, 1),
2324 };
2325 static const unsigned int msiof3_txd_b_mux[] = {
2326 MSIOF3_TXD_B_MARK,
2327 };
2328 static const unsigned int msiof3_rxd_b_pins[] = {
2329 /* RXD */
2330 RCAR_GP_PIN(1, 3),
2331 };
2332 static const unsigned int msiof3_rxd_b_mux[] = {
2333 MSIOF3_RXD_B_MARK,
2334 };
2335 static const unsigned int msiof3_clk_c_pins[] = {
2336 /* SCK */
2337 RCAR_GP_PIN(1, 12),
2338 };
2339 static const unsigned int msiof3_clk_c_mux[] = {
2340 MSIOF3_SCK_C_MARK,
2341 };
2342 static const unsigned int msiof3_sync_c_pins[] = {
2343 /* SYNC */
2344 RCAR_GP_PIN(1, 13),
2345 };
2346 static const unsigned int msiof3_sync_c_mux[] = {
2347 MSIOF3_SYNC_C_MARK,
2348 };
2349 static const unsigned int msiof3_txd_c_pins[] = {
2350 /* TXD */
2351 RCAR_GP_PIN(1, 15),
2352 };
2353 static const unsigned int msiof3_txd_c_mux[] = {
2354 MSIOF3_TXD_C_MARK,
2355 };
2356 static const unsigned int msiof3_rxd_c_pins[] = {
2357 /* RXD */
2358 RCAR_GP_PIN(1, 14),
2359 };
2360 static const unsigned int msiof3_rxd_c_mux[] = {
2361 MSIOF3_RXD_C_MARK,
2362 };
2363 static const unsigned int msiof3_clk_d_pins[] = {
2364 /* SCK */
2365 RCAR_GP_PIN(1, 22),
2366 };
2367 static const unsigned int msiof3_clk_d_mux[] = {
2368 MSIOF3_SCK_D_MARK,
2369 };
2370 static const unsigned int msiof3_sync_d_pins[] = {
2371 /* SYNC */
2372 RCAR_GP_PIN(1, 23),
2373 };
2374 static const unsigned int msiof3_sync_d_mux[] = {
2375 MSIOF3_SYNC_D_MARK,
2376 };
2377 static const unsigned int msiof3_ss1_d_pins[] = {
2378 /* SS1 */
2379 RCAR_GP_PIN(1, 26),
2380 };
2381 static const unsigned int msiof3_ss1_d_mux[] = {
2382 MSIOF3_SS1_D_MARK,
2383 };
2384 static const unsigned int msiof3_txd_d_pins[] = {
2385 /* TXD */
2386 RCAR_GP_PIN(1, 25),
2387 };
2388 static const unsigned int msiof3_txd_d_mux[] = {
2389 MSIOF3_TXD_D_MARK,
2390 };
2391 static const unsigned int msiof3_rxd_d_pins[] = {
2392 /* RXD */
2393 RCAR_GP_PIN(1, 24),
2394 };
2395 static const unsigned int msiof3_rxd_d_mux[] = {
2396 MSIOF3_RXD_D_MARK,
2397 };
2398 static const unsigned int msiof3_clk_e_pins[] = {
2399 /* SCK */
2400 RCAR_GP_PIN(2, 3),
2401 };
2402 static const unsigned int msiof3_clk_e_mux[] = {
2403 MSIOF3_SCK_E_MARK,
2404 };
2405 static const unsigned int msiof3_sync_e_pins[] = {
2406 /* SYNC */
2407 RCAR_GP_PIN(2, 2),
2408 };
2409 static const unsigned int msiof3_sync_e_mux[] = {
2410 MSIOF3_SYNC_E_MARK,
2411 };
2412 static const unsigned int msiof3_ss1_e_pins[] = {
2413 /* SS1 */
2414 RCAR_GP_PIN(2, 1),
2415 };
2416 static const unsigned int msiof3_ss1_e_mux[] = {
2417 MSIOF3_SS1_E_MARK,
2418 };
2419 static const unsigned int msiof3_ss2_e_pins[] = {
2420 /* SS1 */
2421 RCAR_GP_PIN(2, 0),
2422 };
2423 static const unsigned int msiof3_ss2_e_mux[] = {
2424 MSIOF3_SS2_E_MARK,
2425 };
2426 static const unsigned int msiof3_txd_e_pins[] = {
2427 /* TXD */
2428 RCAR_GP_PIN(2, 5),
2429 };
2430 static const unsigned int msiof3_txd_e_mux[] = {
2431 MSIOF3_TXD_E_MARK,
2432 };
2433 static const unsigned int msiof3_rxd_e_pins[] = {
2434 /* RXD */
2435 RCAR_GP_PIN(2, 4),
2436 };
2437 static const unsigned int msiof3_rxd_e_mux[] = {
2438 MSIOF3_RXD_E_MARK,
2439 };
2440
2441 /* - PWM0 --------------------------------------------------------------------*/
2442 static const unsigned int pwm0_pins[] = {
2443 /* PWM */
2444 RCAR_GP_PIN(2, 6),
2445 };
2446 static const unsigned int pwm0_mux[] = {
2447 PWM0_MARK,
2448 };
2449 /* - PWM1 --------------------------------------------------------------------*/
2450 static const unsigned int pwm1_a_pins[] = {
2451 /* PWM */
2452 RCAR_GP_PIN(2, 7),
2453 };
2454 static const unsigned int pwm1_a_mux[] = {
2455 PWM1_A_MARK,
2456 };
2457 static const unsigned int pwm1_b_pins[] = {
2458 /* PWM */
2459 RCAR_GP_PIN(1, 8),
2460 };
2461 static const unsigned int pwm1_b_mux[] = {
2462 PWM1_B_MARK,
2463 };
2464 /* - PWM2 --------------------------------------------------------------------*/
2465 static const unsigned int pwm2_a_pins[] = {
2466 /* PWM */
2467 RCAR_GP_PIN(2, 8),
2468 };
2469 static const unsigned int pwm2_a_mux[] = {
2470 PWM2_A_MARK,
2471 };
2472 static const unsigned int pwm2_b_pins[] = {
2473 /* PWM */
2474 RCAR_GP_PIN(1, 11),
2475 };
2476 static const unsigned int pwm2_b_mux[] = {
2477 PWM2_B_MARK,
2478 };
2479 /* - PWM3 --------------------------------------------------------------------*/
2480 static const unsigned int pwm3_a_pins[] = {
2481 /* PWM */
2482 RCAR_GP_PIN(1, 0),
2483 };
2484 static const unsigned int pwm3_a_mux[] = {
2485 PWM3_A_MARK,
2486 };
2487 static const unsigned int pwm3_b_pins[] = {
2488 /* PWM */
2489 RCAR_GP_PIN(2, 2),
2490 };
2491 static const unsigned int pwm3_b_mux[] = {
2492 PWM3_B_MARK,
2493 };
2494 /* - PWM4 --------------------------------------------------------------------*/
2495 static const unsigned int pwm4_a_pins[] = {
2496 /* PWM */
2497 RCAR_GP_PIN(1, 1),
2498 };
2499 static const unsigned int pwm4_a_mux[] = {
2500 PWM4_A_MARK,
2501 };
2502 static const unsigned int pwm4_b_pins[] = {
2503 /* PWM */
2504 RCAR_GP_PIN(2, 3),
2505 };
2506 static const unsigned int pwm4_b_mux[] = {
2507 PWM4_B_MARK,
2508 };
2509 /* - PWM5 --------------------------------------------------------------------*/
2510 static const unsigned int pwm5_a_pins[] = {
2511 /* PWM */
2512 RCAR_GP_PIN(1, 2),
2513 };
2514 static const unsigned int pwm5_a_mux[] = {
2515 PWM5_A_MARK,
2516 };
2517 static const unsigned int pwm5_b_pins[] = {
2518 /* PWM */
2519 RCAR_GP_PIN(2, 4),
2520 };
2521 static const unsigned int pwm5_b_mux[] = {
2522 PWM5_B_MARK,
2523 };
2524 /* - PWM6 --------------------------------------------------------------------*/
2525 static const unsigned int pwm6_a_pins[] = {
2526 /* PWM */
2527 RCAR_GP_PIN(1, 3),
2528 };
2529 static const unsigned int pwm6_a_mux[] = {
2530 PWM6_A_MARK,
2531 };
2532 static const unsigned int pwm6_b_pins[] = {
2533 /* PWM */
2534 RCAR_GP_PIN(2, 5),
2535 };
2536 static const unsigned int pwm6_b_mux[] = {
2537 PWM6_B_MARK,
2538 };
2539
2540 /* - SCIF0 ------------------------------------------------------------------ */
2541 static const unsigned int scif0_data_pins[] = {
2542 /* RX, TX */
2543 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2544 };
2545 static const unsigned int scif0_data_mux[] = {
2546 RX0_MARK, TX0_MARK,
2547 };
2548 static const unsigned int scif0_clk_pins[] = {
2549 /* SCK */
2550 RCAR_GP_PIN(5, 0),
2551 };
2552 static const unsigned int scif0_clk_mux[] = {
2553 SCK0_MARK,
2554 };
2555 static const unsigned int scif0_ctrl_pins[] = {
2556 /* RTS, CTS */
2557 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2558 };
2559 static const unsigned int scif0_ctrl_mux[] = {
2560 RTS0_N_TANS_MARK, CTS0_N_MARK,
2561 };
2562 /* - SCIF1 ------------------------------------------------------------------ */
2563 static const unsigned int scif1_data_a_pins[] = {
2564 /* RX, TX */
2565 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2566 };
2567 static const unsigned int scif1_data_a_mux[] = {
2568 RX1_A_MARK, TX1_A_MARK,
2569 };
2570 static const unsigned int scif1_clk_pins[] = {
2571 /* SCK */
2572 RCAR_GP_PIN(6, 21),
2573 };
2574 static const unsigned int scif1_clk_mux[] = {
2575 SCK1_MARK,
2576 };
2577 static const unsigned int scif1_ctrl_pins[] = {
2578 /* RTS, CTS */
2579 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2580 };
2581 static const unsigned int scif1_ctrl_mux[] = {
2582 RTS1_N_TANS_MARK, CTS1_N_MARK,
2583 };
2584
2585 static const unsigned int scif1_data_b_pins[] = {
2586 /* RX, TX */
2587 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2588 };
2589 static const unsigned int scif1_data_b_mux[] = {
2590 RX1_B_MARK, TX1_B_MARK,
2591 };
2592 /* - SCIF2 ------------------------------------------------------------------ */
2593 static const unsigned int scif2_data_a_pins[] = {
2594 /* RX, TX */
2595 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2596 };
2597 static const unsigned int scif2_data_a_mux[] = {
2598 RX2_A_MARK, TX2_A_MARK,
2599 };
2600 static const unsigned int scif2_clk_pins[] = {
2601 /* SCK */
2602 RCAR_GP_PIN(5, 9),
2603 };
2604 static const unsigned int scif2_clk_mux[] = {
2605 SCK2_MARK,
2606 };
2607 static const unsigned int scif2_data_b_pins[] = {
2608 /* RX, TX */
2609 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2610 };
2611 static const unsigned int scif2_data_b_mux[] = {
2612 RX2_B_MARK, TX2_B_MARK,
2613 };
2614 /* - SCIF3 ------------------------------------------------------------------ */
2615 static const unsigned int scif3_data_a_pins[] = {
2616 /* RX, TX */
2617 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2618 };
2619 static const unsigned int scif3_data_a_mux[] = {
2620 RX3_A_MARK, TX3_A_MARK,
2621 };
2622 static const unsigned int scif3_clk_pins[] = {
2623 /* SCK */
2624 RCAR_GP_PIN(1, 22),
2625 };
2626 static const unsigned int scif3_clk_mux[] = {
2627 SCK3_MARK,
2628 };
2629 static const unsigned int scif3_ctrl_pins[] = {
2630 /* RTS, CTS */
2631 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2632 };
2633 static const unsigned int scif3_ctrl_mux[] = {
2634 RTS3_N_TANS_MARK, CTS3_N_MARK,
2635 };
2636 static const unsigned int scif3_data_b_pins[] = {
2637 /* RX, TX */
2638 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2639 };
2640 static const unsigned int scif3_data_b_mux[] = {
2641 RX3_B_MARK, TX3_B_MARK,
2642 };
2643 /* - SCIF4 ------------------------------------------------------------------ */
2644 static const unsigned int scif4_data_a_pins[] = {
2645 /* RX, TX */
2646 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2647 };
2648 static const unsigned int scif4_data_a_mux[] = {
2649 RX4_A_MARK, TX4_A_MARK,
2650 };
2651 static const unsigned int scif4_clk_a_pins[] = {
2652 /* SCK */
2653 RCAR_GP_PIN(2, 10),
2654 };
2655 static const unsigned int scif4_clk_a_mux[] = {
2656 SCK4_A_MARK,
2657 };
2658 static const unsigned int scif4_ctrl_a_pins[] = {
2659 /* RTS, CTS */
2660 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2661 };
2662 static const unsigned int scif4_ctrl_a_mux[] = {
2663 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
2664 };
2665 static const unsigned int scif4_data_b_pins[] = {
2666 /* RX, TX */
2667 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2668 };
2669 static const unsigned int scif4_data_b_mux[] = {
2670 RX4_B_MARK, TX4_B_MARK,
2671 };
2672 static const unsigned int scif4_clk_b_pins[] = {
2673 /* SCK */
2674 RCAR_GP_PIN(1, 5),
2675 };
2676 static const unsigned int scif4_clk_b_mux[] = {
2677 SCK4_B_MARK,
2678 };
2679 static const unsigned int scif4_ctrl_b_pins[] = {
2680 /* RTS, CTS */
2681 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
2682 };
2683 static const unsigned int scif4_ctrl_b_mux[] = {
2684 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
2685 };
2686 static const unsigned int scif4_data_c_pins[] = {
2687 /* RX, TX */
2688 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
2689 };
2690 static const unsigned int scif4_data_c_mux[] = {
2691 RX4_C_MARK, TX4_C_MARK,
2692 };
2693 static const unsigned int scif4_clk_c_pins[] = {
2694 /* SCK */
2695 RCAR_GP_PIN(0, 8),
2696 };
2697 static const unsigned int scif4_clk_c_mux[] = {
2698 SCK4_C_MARK,
2699 };
2700 static const unsigned int scif4_ctrl_c_pins[] = {
2701 /* RTS, CTS */
2702 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2703 };
2704 static const unsigned int scif4_ctrl_c_mux[] = {
2705 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
2706 };
2707 /* - SCIF5 ------------------------------------------------------------------ */
2708 static const unsigned int scif5_data_a_pins[] = {
2709 /* RX, TX */
2710 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
2711 };
2712 static const unsigned int scif5_data_a_mux[] = {
2713 RX5_A_MARK, TX5_A_MARK,
2714 };
2715 static const unsigned int scif5_clk_a_pins[] = {
2716 /* SCK */
2717 RCAR_GP_PIN(6, 21),
2718 };
2719 static const unsigned int scif5_clk_a_mux[] = {
2720 SCK5_A_MARK,
2721 };
2722 static const unsigned int scif5_data_b_pins[] = {
2723 /* RX, TX */
2724 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
2725 };
2726 static const unsigned int scif5_data_b_mux[] = {
2727 RX5_B_MARK, TX5_B_MARK,
2728 };
2729 static const unsigned int scif5_clk_b_pins[] = {
2730 /* SCK */
2731 RCAR_GP_PIN(5, 0),
2732 };
2733 static const unsigned int scif5_clk_b_mux[] = {
2734 SCK5_B_MARK,
2735 };
2736
2737 /* - SCIF Clock ------------------------------------------------------------- */
2738 static const unsigned int scif_clk_a_pins[] = {
2739 /* SCIF_CLK */
2740 RCAR_GP_PIN(6, 23),
2741 };
2742 static const unsigned int scif_clk_a_mux[] = {
2743 SCIF_CLK_A_MARK,
2744 };
2745 static const unsigned int scif_clk_b_pins[] = {
2746 /* SCIF_CLK */
2747 RCAR_GP_PIN(5, 9),
2748 };
2749 static const unsigned int scif_clk_b_mux[] = {
2750 SCIF_CLK_B_MARK,
2751 };
2752
2753 /* - USB0 ------------------------------------------------------------------- */
2754 static const unsigned int usb0_pins[] = {
2755 /* PWEN, OVC */
2756 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2757 };
2758 static const unsigned int usb0_mux[] = {
2759 USB0_PWEN_MARK, USB0_OVC_MARK,
2760 };
2761 /* - USB1 ------------------------------------------------------------------- */
2762 static const unsigned int usb1_pins[] = {
2763 /* PWEN, OVC */
2764 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
2765 };
2766 static const unsigned int usb1_mux[] = {
2767 USB1_PWEN_MARK, USB1_OVC_MARK,
2768 };
2769 /* - USB2 ------------------------------------------------------------------- */
2770 static const unsigned int usb2_pins[] = {
2771 /* PWEN, OVC */
2772 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
2773 };
2774 static const unsigned int usb2_mux[] = {
2775 USB2_PWEN_MARK, USB2_OVC_MARK,
2776 };
2777 /* - USB2_CH3 --------------------------------------------------------------- */
2778 static const unsigned int usb2_ch3_pins[] = {
2779 /* PWEN, OVC */
2780 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
2781 };
2782 static const unsigned int usb2_ch3_mux[] = {
2783 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
2784 };
2785
2786 static const struct sh_pfc_pin_group pinmux_groups[] = {
2787 SH_PFC_PIN_GROUP(avb_link),
2788 SH_PFC_PIN_GROUP(avb_magic),
2789 SH_PFC_PIN_GROUP(avb_phy_int),
2790 SH_PFC_PIN_GROUP(avb_mdc),
2791 SH_PFC_PIN_GROUP(avb_mii),
2792 SH_PFC_PIN_GROUP(avb_avtp_pps),
2793 SH_PFC_PIN_GROUP(avb_avtp_match_a),
2794 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
2795 SH_PFC_PIN_GROUP(avb_avtp_match_b),
2796 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
2797 SH_PFC_PIN_GROUP(du_rgb666),
2798 SH_PFC_PIN_GROUP(du_rgb888),
2799 SH_PFC_PIN_GROUP(du_clk_out_0),
2800 SH_PFC_PIN_GROUP(du_clk_out_1),
2801 SH_PFC_PIN_GROUP(du_sync),
2802 SH_PFC_PIN_GROUP(du_oddf),
2803 SH_PFC_PIN_GROUP(du_cde),
2804 SH_PFC_PIN_GROUP(du_disp),
2805 SH_PFC_PIN_GROUP(msiof0_clk),
2806 SH_PFC_PIN_GROUP(msiof0_sync),
2807 SH_PFC_PIN_GROUP(msiof0_ss1),
2808 SH_PFC_PIN_GROUP(msiof0_ss2),
2809 SH_PFC_PIN_GROUP(msiof0_txd),
2810 SH_PFC_PIN_GROUP(msiof0_rxd),
2811 SH_PFC_PIN_GROUP(msiof1_clk_a),
2812 SH_PFC_PIN_GROUP(msiof1_sync_a),
2813 SH_PFC_PIN_GROUP(msiof1_ss1_a),
2814 SH_PFC_PIN_GROUP(msiof1_ss2_a),
2815 SH_PFC_PIN_GROUP(msiof1_txd_a),
2816 SH_PFC_PIN_GROUP(msiof1_rxd_a),
2817 SH_PFC_PIN_GROUP(msiof1_clk_b),
2818 SH_PFC_PIN_GROUP(msiof1_sync_b),
2819 SH_PFC_PIN_GROUP(msiof1_ss1_b),
2820 SH_PFC_PIN_GROUP(msiof1_ss2_b),
2821 SH_PFC_PIN_GROUP(msiof1_txd_b),
2822 SH_PFC_PIN_GROUP(msiof1_rxd_b),
2823 SH_PFC_PIN_GROUP(msiof1_clk_c),
2824 SH_PFC_PIN_GROUP(msiof1_sync_c),
2825 SH_PFC_PIN_GROUP(msiof1_ss1_c),
2826 SH_PFC_PIN_GROUP(msiof1_ss2_c),
2827 SH_PFC_PIN_GROUP(msiof1_txd_c),
2828 SH_PFC_PIN_GROUP(msiof1_rxd_c),
2829 SH_PFC_PIN_GROUP(msiof1_clk_d),
2830 SH_PFC_PIN_GROUP(msiof1_sync_d),
2831 SH_PFC_PIN_GROUP(msiof1_ss1_d),
2832 SH_PFC_PIN_GROUP(msiof1_ss2_d),
2833 SH_PFC_PIN_GROUP(msiof1_txd_d),
2834 SH_PFC_PIN_GROUP(msiof1_rxd_d),
2835 SH_PFC_PIN_GROUP(msiof1_clk_e),
2836 SH_PFC_PIN_GROUP(msiof1_sync_e),
2837 SH_PFC_PIN_GROUP(msiof1_ss1_e),
2838 SH_PFC_PIN_GROUP(msiof1_ss2_e),
2839 SH_PFC_PIN_GROUP(msiof1_txd_e),
2840 SH_PFC_PIN_GROUP(msiof1_rxd_e),
2841 SH_PFC_PIN_GROUP(msiof1_clk_f),
2842 SH_PFC_PIN_GROUP(msiof1_sync_f),
2843 SH_PFC_PIN_GROUP(msiof1_ss1_f),
2844 SH_PFC_PIN_GROUP(msiof1_ss2_f),
2845 SH_PFC_PIN_GROUP(msiof1_txd_f),
2846 SH_PFC_PIN_GROUP(msiof1_rxd_f),
2847 SH_PFC_PIN_GROUP(msiof1_clk_g),
2848 SH_PFC_PIN_GROUP(msiof1_sync_g),
2849 SH_PFC_PIN_GROUP(msiof1_ss1_g),
2850 SH_PFC_PIN_GROUP(msiof1_ss2_g),
2851 SH_PFC_PIN_GROUP(msiof1_txd_g),
2852 SH_PFC_PIN_GROUP(msiof1_rxd_g),
2853 SH_PFC_PIN_GROUP(msiof2_clk_a),
2854 SH_PFC_PIN_GROUP(msiof2_sync_a),
2855 SH_PFC_PIN_GROUP(msiof2_ss1_a),
2856 SH_PFC_PIN_GROUP(msiof2_ss2_a),
2857 SH_PFC_PIN_GROUP(msiof2_txd_a),
2858 SH_PFC_PIN_GROUP(msiof2_rxd_a),
2859 SH_PFC_PIN_GROUP(msiof2_clk_b),
2860 SH_PFC_PIN_GROUP(msiof2_sync_b),
2861 SH_PFC_PIN_GROUP(msiof2_ss1_b),
2862 SH_PFC_PIN_GROUP(msiof2_ss2_b),
2863 SH_PFC_PIN_GROUP(msiof2_txd_b),
2864 SH_PFC_PIN_GROUP(msiof2_rxd_b),
2865 SH_PFC_PIN_GROUP(msiof2_clk_c),
2866 SH_PFC_PIN_GROUP(msiof2_sync_c),
2867 SH_PFC_PIN_GROUP(msiof2_ss1_c),
2868 SH_PFC_PIN_GROUP(msiof2_ss2_c),
2869 SH_PFC_PIN_GROUP(msiof2_txd_c),
2870 SH_PFC_PIN_GROUP(msiof2_rxd_c),
2871 SH_PFC_PIN_GROUP(msiof2_clk_d),
2872 SH_PFC_PIN_GROUP(msiof2_sync_d),
2873 SH_PFC_PIN_GROUP(msiof2_ss1_d),
2874 SH_PFC_PIN_GROUP(msiof2_ss2_d),
2875 SH_PFC_PIN_GROUP(msiof2_txd_d),
2876 SH_PFC_PIN_GROUP(msiof2_rxd_d),
2877 SH_PFC_PIN_GROUP(msiof3_clk_a),
2878 SH_PFC_PIN_GROUP(msiof3_sync_a),
2879 SH_PFC_PIN_GROUP(msiof3_ss1_a),
2880 SH_PFC_PIN_GROUP(msiof3_ss2_a),
2881 SH_PFC_PIN_GROUP(msiof3_txd_a),
2882 SH_PFC_PIN_GROUP(msiof3_rxd_a),
2883 SH_PFC_PIN_GROUP(msiof3_clk_b),
2884 SH_PFC_PIN_GROUP(msiof3_sync_b),
2885 SH_PFC_PIN_GROUP(msiof3_ss1_b),
2886 SH_PFC_PIN_GROUP(msiof3_ss2_b),
2887 SH_PFC_PIN_GROUP(msiof3_txd_b),
2888 SH_PFC_PIN_GROUP(msiof3_rxd_b),
2889 SH_PFC_PIN_GROUP(msiof3_clk_c),
2890 SH_PFC_PIN_GROUP(msiof3_sync_c),
2891 SH_PFC_PIN_GROUP(msiof3_txd_c),
2892 SH_PFC_PIN_GROUP(msiof3_rxd_c),
2893 SH_PFC_PIN_GROUP(msiof3_clk_d),
2894 SH_PFC_PIN_GROUP(msiof3_sync_d),
2895 SH_PFC_PIN_GROUP(msiof3_ss1_d),
2896 SH_PFC_PIN_GROUP(msiof3_txd_d),
2897 SH_PFC_PIN_GROUP(msiof3_rxd_d),
2898 SH_PFC_PIN_GROUP(msiof3_clk_e),
2899 SH_PFC_PIN_GROUP(msiof3_sync_e),
2900 SH_PFC_PIN_GROUP(msiof3_ss1_e),
2901 SH_PFC_PIN_GROUP(msiof3_ss2_e),
2902 SH_PFC_PIN_GROUP(msiof3_txd_e),
2903 SH_PFC_PIN_GROUP(msiof3_rxd_e),
2904 SH_PFC_PIN_GROUP(pwm0),
2905 SH_PFC_PIN_GROUP(pwm1_a),
2906 SH_PFC_PIN_GROUP(pwm1_b),
2907 SH_PFC_PIN_GROUP(pwm2_a),
2908 SH_PFC_PIN_GROUP(pwm2_b),
2909 SH_PFC_PIN_GROUP(pwm3_a),
2910 SH_PFC_PIN_GROUP(pwm3_b),
2911 SH_PFC_PIN_GROUP(pwm4_a),
2912 SH_PFC_PIN_GROUP(pwm4_b),
2913 SH_PFC_PIN_GROUP(pwm5_a),
2914 SH_PFC_PIN_GROUP(pwm5_b),
2915 SH_PFC_PIN_GROUP(pwm6_a),
2916 SH_PFC_PIN_GROUP(pwm6_b),
2917 SH_PFC_PIN_GROUP(scif0_data),
2918 SH_PFC_PIN_GROUP(scif0_clk),
2919 SH_PFC_PIN_GROUP(scif0_ctrl),
2920 SH_PFC_PIN_GROUP(scif1_data_a),
2921 SH_PFC_PIN_GROUP(scif1_clk),
2922 SH_PFC_PIN_GROUP(scif1_ctrl),
2923 SH_PFC_PIN_GROUP(scif1_data_b),
2924 SH_PFC_PIN_GROUP(scif2_data_a),
2925 SH_PFC_PIN_GROUP(scif2_clk),
2926 SH_PFC_PIN_GROUP(scif2_data_b),
2927 SH_PFC_PIN_GROUP(scif3_data_a),
2928 SH_PFC_PIN_GROUP(scif3_clk),
2929 SH_PFC_PIN_GROUP(scif3_ctrl),
2930 SH_PFC_PIN_GROUP(scif3_data_b),
2931 SH_PFC_PIN_GROUP(scif4_data_a),
2932 SH_PFC_PIN_GROUP(scif4_clk_a),
2933 SH_PFC_PIN_GROUP(scif4_ctrl_a),
2934 SH_PFC_PIN_GROUP(scif4_data_b),
2935 SH_PFC_PIN_GROUP(scif4_clk_b),
2936 SH_PFC_PIN_GROUP(scif4_ctrl_b),
2937 SH_PFC_PIN_GROUP(scif4_data_c),
2938 SH_PFC_PIN_GROUP(scif4_clk_c),
2939 SH_PFC_PIN_GROUP(scif4_ctrl_c),
2940 SH_PFC_PIN_GROUP(scif5_data_a),
2941 SH_PFC_PIN_GROUP(scif5_clk_a),
2942 SH_PFC_PIN_GROUP(scif5_data_b),
2943 SH_PFC_PIN_GROUP(scif5_clk_b),
2944 SH_PFC_PIN_GROUP(scif_clk_a),
2945 SH_PFC_PIN_GROUP(scif_clk_b),
2946 SH_PFC_PIN_GROUP(usb0),
2947 SH_PFC_PIN_GROUP(usb1),
2948 SH_PFC_PIN_GROUP(usb2),
2949 SH_PFC_PIN_GROUP(usb2_ch3),
2950 };
2951
2952 static const char * const avb_groups[] = {
2953 "avb_link",
2954 "avb_magic",
2955 "avb_phy_int",
2956 "avb_mdc",
2957 "avb_mii",
2958 "avb_avtp_pps",
2959 "avb_avtp_match_a",
2960 "avb_avtp_capture_a",
2961 "avb_avtp_match_b",
2962 "avb_avtp_capture_b",
2963 };
2964
2965 static const char * const du_groups[] = {
2966 "du_rgb666",
2967 "du_rgb888",
2968 "du_clk_out_0",
2969 "du_clk_out_1",
2970 "du_sync",
2971 "du_oddf",
2972 "du_cde",
2973 "du_disp",
2974 };
2975
2976 static const char * const msiof0_groups[] = {
2977 "msiof0_clk",
2978 "msiof0_sync",
2979 "msiof0_ss1",
2980 "msiof0_ss2",
2981 "msiof0_txd",
2982 "msiof0_rxd",
2983 };
2984
2985 static const char * const msiof1_groups[] = {
2986 "msiof1_clk_a",
2987 "msiof1_sync_a",
2988 "msiof1_ss1_a",
2989 "msiof1_ss2_a",
2990 "msiof1_txd_a",
2991 "msiof1_rxd_a",
2992 "msiof1_clk_b",
2993 "msiof1_sync_b",
2994 "msiof1_ss1_b",
2995 "msiof1_ss2_b",
2996 "msiof1_txd_b",
2997 "msiof1_rxd_b",
2998 "msiof1_clk_c",
2999 "msiof1_sync_c",
3000 "msiof1_ss1_c",
3001 "msiof1_ss2_c",
3002 "msiof1_txd_c",
3003 "msiof1_rxd_c",
3004 "msiof1_clk_d",
3005 "msiof1_sync_d",
3006 "msiof1_ss1_d",
3007 "msiof1_ss2_d",
3008 "msiof1_txd_d",
3009 "msiof1_rxd_d",
3010 "msiof1_clk_e",
3011 "msiof1_sync_e",
3012 "msiof1_ss1_e",
3013 "msiof1_ss2_e",
3014 "msiof1_txd_e",
3015 "msiof1_rxd_e",
3016 "msiof1_clk_f",
3017 "msiof1_sync_f",
3018 "msiof1_ss1_f",
3019 "msiof1_ss2_f",
3020 "msiof1_txd_f",
3021 "msiof1_rxd_f",
3022 "msiof1_clk_g",
3023 "msiof1_sync_g",
3024 "msiof1_ss1_g",
3025 "msiof1_ss2_g",
3026 "msiof1_txd_g",
3027 "msiof1_rxd_g",
3028 };
3029
3030 static const char * const msiof2_groups[] = {
3031 "msiof2_clk_a",
3032 "msiof2_sync_a",
3033 "msiof2_ss1_a",
3034 "msiof2_ss2_a",
3035 "msiof2_txd_a",
3036 "msiof2_rxd_a",
3037 "msiof2_clk_b",
3038 "msiof2_sync_b",
3039 "msiof2_ss1_b",
3040 "msiof2_ss2_b",
3041 "msiof2_txd_b",
3042 "msiof2_rxd_b",
3043 "msiof2_clk_c",
3044 "msiof2_sync_c",
3045 "msiof2_ss1_c",
3046 "msiof2_ss2_c",
3047 "msiof2_txd_c",
3048 "msiof2_rxd_c",
3049 "msiof2_clk_d",
3050 "msiof2_sync_d",
3051 "msiof2_ss1_d",
3052 "msiof2_ss2_d",
3053 "msiof2_txd_d",
3054 "msiof2_rxd_d",
3055 };
3056
3057 static const char * const msiof3_groups[] = {
3058 "msiof3_clk_a",
3059 "msiof3_sync_a",
3060 "msiof3_ss1_a",
3061 "msiof3_ss2_a",
3062 "msiof3_txd_a",
3063 "msiof3_rxd_a",
3064 "msiof3_clk_b",
3065 "msiof3_sync_b",
3066 "msiof3_ss1_b",
3067 "msiof3_ss2_b",
3068 "msiof3_txd_b",
3069 "msiof3_rxd_b",
3070 "msiof3_clk_c",
3071 "msiof3_sync_c",
3072 "msiof3_txd_c",
3073 "msiof3_rxd_c",
3074 "msiof3_clk_d",
3075 "msiof3_sync_d",
3076 "msiof3_ss1_d",
3077 "msiof3_txd_d",
3078 "msiof3_rxd_d",
3079 "msiof3_clk_e",
3080 "msiof3_sync_e",
3081 "msiof3_ss1_e",
3082 "msiof3_ss2_e",
3083 "msiof3_txd_e",
3084 "msiof3_rxd_e",
3085 };
3086
3087 static const char * const pwm0_groups[] = {
3088 "pwm0",
3089 };
3090
3091 static const char * const pwm1_groups[] = {
3092 "pwm1_a",
3093 "pwm1_b",
3094 };
3095
3096 static const char * const pwm2_groups[] = {
3097 "pwm2_a",
3098 "pwm2_b",
3099 };
3100
3101 static const char * const pwm3_groups[] = {
3102 "pwm3_a",
3103 "pwm3_b",
3104 };
3105
3106 static const char * const pwm4_groups[] = {
3107 "pwm4_a",
3108 "pwm4_b",
3109 };
3110
3111 static const char * const pwm5_groups[] = {
3112 "pwm5_a",
3113 "pwm5_b",
3114 };
3115
3116 static const char * const pwm6_groups[] = {
3117 "pwm6_a",
3118 "pwm6_b",
3119 };
3120
3121 static const char * const scif0_groups[] = {
3122 "scif0_data",
3123 "scif0_clk",
3124 "scif0_ctrl",
3125 };
3126
3127 static const char * const scif1_groups[] = {
3128 "scif1_data_a",
3129 "scif1_clk",
3130 "scif1_ctrl",
3131 "scif1_data_b",
3132 };
3133
3134 static const char * const scif2_groups[] = {
3135 "scif2_data_a",
3136 "scif2_clk",
3137 "scif2_data_b",
3138 };
3139
3140 static const char * const scif3_groups[] = {
3141 "scif3_data_a",
3142 "scif3_clk",
3143 "scif3_ctrl",
3144 "scif3_data_b",
3145 };
3146
3147 static const char * const scif4_groups[] = {
3148 "scif4_data_a",
3149 "scif4_clk_a",
3150 "scif4_ctrl_a",
3151 "scif4_data_b",
3152 "scif4_clk_b",
3153 "scif4_ctrl_b",
3154 "scif4_data_c",
3155 "scif4_clk_c",
3156 "scif4_ctrl_c",
3157 };
3158
3159 static const char * const scif5_groups[] = {
3160 "scif5_data_a",
3161 "scif5_clk_a",
3162 "scif5_data_b",
3163 "scif5_clk_b",
3164 };
3165
3166 static const char * const scif_clk_groups[] = {
3167 "scif_clk_a",
3168 "scif_clk_b",
3169 };
3170
3171 static const char * const usb0_groups[] = {
3172 "usb0",
3173 };
3174
3175 static const char * const usb1_groups[] = {
3176 "usb1",
3177 };
3178
3179 static const char * const usb2_groups[] = {
3180 "usb2",
3181 };
3182
3183 static const char * const usb2_ch3_groups[] = {
3184 "usb2_ch3",
3185 };
3186
3187 static const struct sh_pfc_function pinmux_functions[] = {
3188 SH_PFC_FUNCTION(avb),
3189 SH_PFC_FUNCTION(du),
3190 SH_PFC_FUNCTION(msiof0),
3191 SH_PFC_FUNCTION(msiof1),
3192 SH_PFC_FUNCTION(msiof2),
3193 SH_PFC_FUNCTION(msiof3),
3194 SH_PFC_FUNCTION(pwm0),
3195 SH_PFC_FUNCTION(pwm1),
3196 SH_PFC_FUNCTION(pwm2),
3197 SH_PFC_FUNCTION(pwm3),
3198 SH_PFC_FUNCTION(pwm4),
3199 SH_PFC_FUNCTION(pwm5),
3200 SH_PFC_FUNCTION(pwm6),
3201 SH_PFC_FUNCTION(scif0),
3202 SH_PFC_FUNCTION(scif1),
3203 SH_PFC_FUNCTION(scif2),
3204 SH_PFC_FUNCTION(scif3),
3205 SH_PFC_FUNCTION(scif4),
3206 SH_PFC_FUNCTION(scif5),
3207 SH_PFC_FUNCTION(scif_clk),
3208 SH_PFC_FUNCTION(usb0),
3209 SH_PFC_FUNCTION(usb1),
3210 SH_PFC_FUNCTION(usb2),
3211 SH_PFC_FUNCTION(usb2_ch3),
3212 };
3213
3214 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3215 #define F_(x, y) FN_##y
3216 #define FM(x) FN_##x
3217 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
3218 0, 0,
3219 0, 0,
3220 0, 0,
3221 0, 0,
3222 0, 0,
3223 0, 0,
3224 0, 0,
3225 0, 0,
3226 0, 0,
3227 0, 0,
3228 0, 0,
3229 0, 0,
3230 0, 0,
3231 0, 0,
3232 0, 0,
3233 0, 0,
3234 GP_0_15_FN, GPSR0_15,
3235 GP_0_14_FN, GPSR0_14,
3236 GP_0_13_FN, GPSR0_13,
3237 GP_0_12_FN, GPSR0_12,
3238 GP_0_11_FN, GPSR0_11,
3239 GP_0_10_FN, GPSR0_10,
3240 GP_0_9_FN, GPSR0_9,
3241 GP_0_8_FN, GPSR0_8,
3242 GP_0_7_FN, GPSR0_7,
3243 GP_0_6_FN, GPSR0_6,
3244 GP_0_5_FN, GPSR0_5,
3245 GP_0_4_FN, GPSR0_4,
3246 GP_0_3_FN, GPSR0_3,
3247 GP_0_2_FN, GPSR0_2,
3248 GP_0_1_FN, GPSR0_1,
3249 GP_0_0_FN, GPSR0_0, }
3250 },
3251 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
3252 0, 0,
3253 0, 0,
3254 0, 0,
3255 0, 0,
3256 GP_1_27_FN, GPSR1_27,
3257 GP_1_26_FN, GPSR1_26,
3258 GP_1_25_FN, GPSR1_25,
3259 GP_1_24_FN, GPSR1_24,
3260 GP_1_23_FN, GPSR1_23,
3261 GP_1_22_FN, GPSR1_22,
3262 GP_1_21_FN, GPSR1_21,
3263 GP_1_20_FN, GPSR1_20,
3264 GP_1_19_FN, GPSR1_19,
3265 GP_1_18_FN, GPSR1_18,
3266 GP_1_17_FN, GPSR1_17,
3267 GP_1_16_FN, GPSR1_16,
3268 GP_1_15_FN, GPSR1_15,
3269 GP_1_14_FN, GPSR1_14,
3270 GP_1_13_FN, GPSR1_13,
3271 GP_1_12_FN, GPSR1_12,
3272 GP_1_11_FN, GPSR1_11,
3273 GP_1_10_FN, GPSR1_10,
3274 GP_1_9_FN, GPSR1_9,
3275 GP_1_8_FN, GPSR1_8,
3276 GP_1_7_FN, GPSR1_7,
3277 GP_1_6_FN, GPSR1_6,
3278 GP_1_5_FN, GPSR1_5,
3279 GP_1_4_FN, GPSR1_4,
3280 GP_1_3_FN, GPSR1_3,
3281 GP_1_2_FN, GPSR1_2,
3282 GP_1_1_FN, GPSR1_1,
3283 GP_1_0_FN, GPSR1_0, }
3284 },
3285 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
3286 0, 0,
3287 0, 0,
3288 0, 0,
3289 0, 0,
3290 0, 0,
3291 0, 0,
3292 0, 0,
3293 0, 0,
3294 0, 0,
3295 0, 0,
3296 0, 0,
3297 0, 0,
3298 0, 0,
3299 0, 0,
3300 0, 0,
3301 0, 0,
3302 0, 0,
3303 GP_2_14_FN, GPSR2_14,
3304 GP_2_13_FN, GPSR2_13,
3305 GP_2_12_FN, GPSR2_12,
3306 GP_2_11_FN, GPSR2_11,
3307 GP_2_10_FN, GPSR2_10,
3308 GP_2_9_FN, GPSR2_9,
3309 GP_2_8_FN, GPSR2_8,
3310 GP_2_7_FN, GPSR2_7,
3311 GP_2_6_FN, GPSR2_6,
3312 GP_2_5_FN, GPSR2_5,
3313 GP_2_4_FN, GPSR2_4,
3314 GP_2_3_FN, GPSR2_3,
3315 GP_2_2_FN, GPSR2_2,
3316 GP_2_1_FN, GPSR2_1,
3317 GP_2_0_FN, GPSR2_0, }
3318 },
3319 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
3320 0, 0,
3321 0, 0,
3322 0, 0,
3323 0, 0,
3324 0, 0,
3325 0, 0,
3326 0, 0,
3327 0, 0,
3328 0, 0,
3329 0, 0,
3330 0, 0,
3331 0, 0,
3332 0, 0,
3333 0, 0,
3334 0, 0,
3335 0, 0,
3336 GP_3_15_FN, GPSR3_15,
3337 GP_3_14_FN, GPSR3_14,
3338 GP_3_13_FN, GPSR3_13,
3339 GP_3_12_FN, GPSR3_12,
3340 GP_3_11_FN, GPSR3_11,
3341 GP_3_10_FN, GPSR3_10,
3342 GP_3_9_FN, GPSR3_9,
3343 GP_3_8_FN, GPSR3_8,
3344 GP_3_7_FN, GPSR3_7,
3345 GP_3_6_FN, GPSR3_6,
3346 GP_3_5_FN, GPSR3_5,
3347 GP_3_4_FN, GPSR3_4,
3348 GP_3_3_FN, GPSR3_3,
3349 GP_3_2_FN, GPSR3_2,
3350 GP_3_1_FN, GPSR3_1,
3351 GP_3_0_FN, GPSR3_0, }
3352 },
3353 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
3354 0, 0,
3355 0, 0,
3356 0, 0,
3357 0, 0,
3358 0, 0,
3359 0, 0,
3360 0, 0,
3361 0, 0,
3362 0, 0,
3363 0, 0,
3364 0, 0,
3365 0, 0,
3366 0, 0,
3367 0, 0,
3368 GP_4_17_FN, GPSR4_17,
3369 GP_4_16_FN, GPSR4_16,
3370 GP_4_15_FN, GPSR4_15,
3371 GP_4_14_FN, GPSR4_14,
3372 GP_4_13_FN, GPSR4_13,
3373 GP_4_12_FN, GPSR4_12,
3374 GP_4_11_FN, GPSR4_11,
3375 GP_4_10_FN, GPSR4_10,
3376 GP_4_9_FN, GPSR4_9,
3377 GP_4_8_FN, GPSR4_8,
3378 GP_4_7_FN, GPSR4_7,
3379 GP_4_6_FN, GPSR4_6,
3380 GP_4_5_FN, GPSR4_5,
3381 GP_4_4_FN, GPSR4_4,
3382 GP_4_3_FN, GPSR4_3,
3383 GP_4_2_FN, GPSR4_2,
3384 GP_4_1_FN, GPSR4_1,
3385 GP_4_0_FN, GPSR4_0, }
3386 },
3387 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
3388 0, 0,
3389 0, 0,
3390 0, 0,
3391 0, 0,
3392 0, 0,
3393 0, 0,
3394 GP_5_25_FN, GPSR5_25,
3395 GP_5_24_FN, GPSR5_24,
3396 GP_5_23_FN, GPSR5_23,
3397 GP_5_22_FN, GPSR5_22,
3398 GP_5_21_FN, GPSR5_21,
3399 GP_5_20_FN, GPSR5_20,
3400 GP_5_19_FN, GPSR5_19,
3401 GP_5_18_FN, GPSR5_18,
3402 GP_5_17_FN, GPSR5_17,
3403 GP_5_16_FN, GPSR5_16,
3404 GP_5_15_FN, GPSR5_15,
3405 GP_5_14_FN, GPSR5_14,
3406 GP_5_13_FN, GPSR5_13,
3407 GP_5_12_FN, GPSR5_12,
3408 GP_5_11_FN, GPSR5_11,
3409 GP_5_10_FN, GPSR5_10,
3410 GP_5_9_FN, GPSR5_9,
3411 GP_5_8_FN, GPSR5_8,
3412 GP_5_7_FN, GPSR5_7,
3413 GP_5_6_FN, GPSR5_6,
3414 GP_5_5_FN, GPSR5_5,
3415 GP_5_4_FN, GPSR5_4,
3416 GP_5_3_FN, GPSR5_3,
3417 GP_5_2_FN, GPSR5_2,
3418 GP_5_1_FN, GPSR5_1,
3419 GP_5_0_FN, GPSR5_0, }
3420 },
3421 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
3422 GP_6_31_FN, GPSR6_31,
3423 GP_6_30_FN, GPSR6_30,
3424 GP_6_29_FN, GPSR6_29,
3425 GP_6_28_FN, GPSR6_28,
3426 GP_6_27_FN, GPSR6_27,
3427 GP_6_26_FN, GPSR6_26,
3428 GP_6_25_FN, GPSR6_25,
3429 GP_6_24_FN, GPSR6_24,
3430 GP_6_23_FN, GPSR6_23,
3431 GP_6_22_FN, GPSR6_22,
3432 GP_6_21_FN, GPSR6_21,
3433 GP_6_20_FN, GPSR6_20,
3434 GP_6_19_FN, GPSR6_19,
3435 GP_6_18_FN, GPSR6_18,
3436 GP_6_17_FN, GPSR6_17,
3437 GP_6_16_FN, GPSR6_16,
3438 GP_6_15_FN, GPSR6_15,
3439 GP_6_14_FN, GPSR6_14,
3440 GP_6_13_FN, GPSR6_13,
3441 GP_6_12_FN, GPSR6_12,
3442 GP_6_11_FN, GPSR6_11,
3443 GP_6_10_FN, GPSR6_10,
3444 GP_6_9_FN, GPSR6_9,
3445 GP_6_8_FN, GPSR6_8,
3446 GP_6_7_FN, GPSR6_7,
3447 GP_6_6_FN, GPSR6_6,
3448 GP_6_5_FN, GPSR6_5,
3449 GP_6_4_FN, GPSR6_4,
3450 GP_6_3_FN, GPSR6_3,
3451 GP_6_2_FN, GPSR6_2,
3452 GP_6_1_FN, GPSR6_1,
3453 GP_6_0_FN, GPSR6_0, }
3454 },
3455 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
3456 0, 0,
3457 0, 0,
3458 0, 0,
3459 0, 0,
3460 0, 0,
3461 0, 0,
3462 0, 0,
3463 0, 0,
3464 0, 0,
3465 0, 0,
3466 0, 0,
3467 0, 0,
3468 0, 0,
3469 0, 0,
3470 0, 0,
3471 0, 0,
3472 0, 0,
3473 0, 0,
3474 0, 0,
3475 0, 0,
3476 0, 0,
3477 0, 0,
3478 0, 0,
3479 0, 0,
3480 0, 0,
3481 0, 0,
3482 0, 0,
3483 0, 0,
3484 GP_7_3_FN, GPSR7_3,
3485 GP_7_2_FN, GPSR7_2,
3486 GP_7_1_FN, GPSR7_1,
3487 GP_7_0_FN, GPSR7_0, }
3488 },
3489 #undef F_
3490 #undef FM
3491
3492 #define F_(x, y) x,
3493 #define FM(x) FN_##x,
3494 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
3495 IP0_31_28
3496 IP0_27_24
3497 IP0_23_20
3498 IP0_19_16
3499 IP0_15_12
3500 IP0_11_8
3501 IP0_7_4
3502 IP0_3_0 }
3503 },
3504 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
3505 IP1_31_28
3506 IP1_27_24
3507 IP1_23_20
3508 IP1_19_16
3509 IP1_15_12
3510 IP1_11_8
3511 IP1_7_4
3512 IP1_3_0 }
3513 },
3514 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
3515 IP2_31_28
3516 IP2_27_24
3517 IP2_23_20
3518 IP2_19_16
3519 IP2_15_12
3520 IP2_11_8
3521 IP2_7_4
3522 IP2_3_0 }
3523 },
3524 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
3525 IP3_31_28
3526 IP3_27_24
3527 IP3_23_20
3528 IP3_19_16
3529 IP3_15_12
3530 IP3_11_8
3531 IP3_7_4
3532 IP3_3_0 }
3533 },
3534 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
3535 IP4_31_28
3536 IP4_27_24
3537 IP4_23_20
3538 IP4_19_16
3539 IP4_15_12
3540 IP4_11_8
3541 IP4_7_4
3542 IP4_3_0 }
3543 },
3544 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
3545 IP5_31_28
3546 IP5_27_24
3547 IP5_23_20
3548 IP5_19_16
3549 IP5_15_12
3550 IP5_11_8
3551 IP5_7_4
3552 IP5_3_0 }
3553 },
3554 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
3555 IP6_31_28
3556 IP6_27_24
3557 IP6_23_20
3558 IP6_19_16
3559 IP6_15_12
3560 IP6_11_8
3561 IP6_7_4
3562 IP6_3_0 }
3563 },
3564 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
3565 IP7_31_28
3566 IP7_27_24
3567 IP7_23_20
3568 IP7_19_16
3569 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3570 IP7_11_8
3571 IP7_7_4
3572 IP7_3_0 }
3573 },
3574 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
3575 IP8_31_28
3576 IP8_27_24
3577 IP8_23_20
3578 IP8_19_16
3579 IP8_15_12
3580 IP8_11_8
3581 IP8_7_4
3582 IP8_3_0 }
3583 },
3584 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
3585 IP9_31_28
3586 IP9_27_24
3587 IP9_23_20
3588 IP9_19_16
3589 IP9_15_12
3590 IP9_11_8
3591 IP9_7_4
3592 IP9_3_0 }
3593 },
3594 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
3595 IP10_31_28
3596 IP10_27_24
3597 IP10_23_20
3598 IP10_19_16
3599 IP10_15_12
3600 IP10_11_8
3601 IP10_7_4
3602 IP10_3_0 }
3603 },
3604 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
3605 IP11_31_28
3606 IP11_27_24
3607 IP11_23_20
3608 IP11_19_16
3609 IP11_15_12
3610 IP11_11_8
3611 IP11_7_4
3612 IP11_3_0 }
3613 },
3614 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
3615 IP12_31_28
3616 IP12_27_24
3617 IP12_23_20
3618 IP12_19_16
3619 IP12_15_12
3620 IP12_11_8
3621 IP12_7_4
3622 IP12_3_0 }
3623 },
3624 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
3625 IP13_31_28
3626 IP13_27_24
3627 IP13_23_20
3628 IP13_19_16
3629 IP13_15_12
3630 IP13_11_8
3631 IP13_7_4
3632 IP13_3_0 }
3633 },
3634 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
3635 IP14_31_28
3636 IP14_27_24
3637 IP14_23_20
3638 IP14_19_16
3639 IP14_15_12
3640 IP14_11_8
3641 IP14_7_4
3642 IP14_3_0 }
3643 },
3644 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
3645 IP15_31_28
3646 IP15_27_24
3647 IP15_23_20
3648 IP15_19_16
3649 IP15_15_12
3650 IP15_11_8
3651 IP15_7_4
3652 IP15_3_0 }
3653 },
3654 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
3655 IP16_31_28
3656 IP16_27_24
3657 IP16_23_20
3658 IP16_19_16
3659 IP16_15_12
3660 IP16_11_8
3661 IP16_7_4
3662 IP16_3_0 }
3663 },
3664 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
3665 IP17_31_28
3666 IP17_27_24
3667 IP17_23_20
3668 IP17_19_16
3669 IP17_15_12
3670 IP17_11_8
3671 IP17_7_4
3672 IP17_3_0 }
3673 },
3674 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
3675 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3676 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3677 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3678 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3679 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3680 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3681 IP18_7_4
3682 IP18_3_0 }
3683 },
3684 #undef F_
3685 #undef FM
3686
3687 #define F_(x, y) x,
3688 #define FM(x) FN_##x,
3689 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
3690 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
3691 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
3692 MOD_SEL0_31_30_29
3693 MOD_SEL0_28_27
3694 MOD_SEL0_26_25_24
3695 MOD_SEL0_23
3696 MOD_SEL0_22
3697 MOD_SEL0_21
3698 MOD_SEL0_20
3699 MOD_SEL0_19
3700 MOD_SEL0_18_17
3701 MOD_SEL0_16
3702 0, 0, /* RESERVED 15 */
3703 MOD_SEL0_14_13
3704 MOD_SEL0_12
3705 MOD_SEL0_11
3706 MOD_SEL0_10
3707 MOD_SEL0_9_8
3708 MOD_SEL0_7_6
3709 MOD_SEL0_5
3710 MOD_SEL0_4_3
3711 /* RESERVED 2, 1, 0 */
3712 0, 0, 0, 0, 0, 0, 0, 0 }
3713 },
3714 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
3715 2, 3, 1, 2, 3, 1, 1, 2, 1,
3716 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
3717 MOD_SEL1_31_30
3718 MOD_SEL1_29_28_27
3719 MOD_SEL1_26
3720 MOD_SEL1_25_24
3721 MOD_SEL1_23_22_21
3722 MOD_SEL1_20
3723 MOD_SEL1_19
3724 MOD_SEL1_18_17
3725 MOD_SEL1_16
3726 MOD_SEL1_15_14
3727 MOD_SEL1_13
3728 MOD_SEL1_12
3729 MOD_SEL1_11
3730 MOD_SEL1_10
3731 MOD_SEL1_9
3732 0, 0, 0, 0, /* RESERVED 8, 7 */
3733 MOD_SEL1_6
3734 MOD_SEL1_5
3735 MOD_SEL1_4
3736 MOD_SEL1_3
3737 MOD_SEL1_2
3738 MOD_SEL1_1
3739 MOD_SEL1_0 }
3740 },
3741 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
3742 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
3743 4, 4, 4, 3, 1) {
3744 MOD_SEL2_31
3745 MOD_SEL2_30
3746 MOD_SEL2_29
3747 MOD_SEL2_28_27
3748 MOD_SEL2_26
3749 MOD_SEL2_25_24_23
3750 /* RESERVED 22 */
3751 0, 0,
3752 MOD_SEL2_21
3753 MOD_SEL2_20
3754 MOD_SEL2_19
3755 MOD_SEL2_18
3756 MOD_SEL2_17
3757 /* RESERVED 16 */
3758 0, 0,
3759 /* RESERVED 15, 14, 13, 12 */
3760 0, 0, 0, 0, 0, 0, 0, 0,
3761 0, 0, 0, 0, 0, 0, 0, 0,
3762 /* RESERVED 11, 10, 9, 8 */
3763 0, 0, 0, 0, 0, 0, 0, 0,
3764 0, 0, 0, 0, 0, 0, 0, 0,
3765 /* RESERVED 7, 6, 5, 4 */
3766 0, 0, 0, 0, 0, 0, 0, 0,
3767 0, 0, 0, 0, 0, 0, 0, 0,
3768 /* RESERVED 3, 2, 1 */
3769 0, 0, 0, 0, 0, 0, 0, 0,
3770 MOD_SEL2_0 }
3771 },
3772 { },
3773 };
3774
3775 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
3776 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
3777 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
3778 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
3779 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
3780 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
3781 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
3782 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
3783 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
3784 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
3785 } },
3786 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
3787 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
3788 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
3789 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
3790 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
3791 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
3792 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
3793 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
3794 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
3795 } },
3796 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
3797 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
3798 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
3799 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
3800 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
3801 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
3802 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
3803 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
3804 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
3805 } },
3806 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
3807 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
3808 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
3809 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
3810 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
3811 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
3812 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
3813 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
3814 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
3815 } },
3816 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
3817 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
3818 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
3819 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
3820 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
3821 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
3822 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
3823 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
3824 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
3825 } },
3826 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
3827 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
3828 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
3829 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
3830 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
3831 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
3832 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
3833 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
3834 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
3835 } },
3836 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
3837 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
3838 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
3839 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
3840 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
3841 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
3842 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
3843 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
3844 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
3845 } },
3846 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
3847 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
3848 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
3849 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
3850 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
3851 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
3852 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
3853 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
3854 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
3855 } },
3856 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
3857 { PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */
3858 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
3859 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
3860 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
3861 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
3862 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
3863 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
3864 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
3865 } },
3866 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
3867 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
3868 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
3869 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
3870 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
3871 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
3872 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
3873 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
3874 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
3875 } },
3876 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
3877 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
3878 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
3879 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
3880 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
3881 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
3882 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
3883 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
3884 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
3885 } },
3886 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
3887 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
3888 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
3889 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
3890 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
3891 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
3892 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
3893 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
3894 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
3895 } },
3896 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
3897 { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
3898 { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
3899 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
3900 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
3901 } },
3902 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
3903 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
3904 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
3905 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
3906 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
3907 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
3908 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
3909 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
3910 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
3911 } },
3912 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
3913 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
3914 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
3915 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
3916 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
3917 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
3918 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
3919 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
3920 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
3921 } },
3922 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
3923 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
3924 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
3925 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
3926 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
3927 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
3928 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
3929 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
3930 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
3931 } },
3932 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
3933 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
3934 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
3935 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
3936 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
3937 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
3938 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
3939 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
3940 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
3941 } },
3942 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
3943 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
3944 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
3945 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
3946 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
3947 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
3948 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
3949 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
3950 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
3951 } },
3952 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
3953 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
3954 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
3955 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
3956 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
3957 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
3958 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
3959 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
3960 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
3961 } },
3962 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
3963 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
3964 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
3965 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
3966 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
3967 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
3968 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
3969 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
3970 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
3971 } },
3972 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
3973 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
3974 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
3975 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
3976 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
3977 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
3978 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
3979 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
3980 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
3981 } },
3982 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
3983 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
3984 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
3985 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
3986 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
3987 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
3988 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
3989 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
3990 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
3991 } },
3992 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
3993 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
3994 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
3995 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
3996 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
3997 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
3998 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
3999 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
4000 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
4001 } },
4002 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
4003 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
4004 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
4005 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
4006 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
4007 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
4008 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
4009 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
4010 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
4011 } },
4012 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
4013 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
4014 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
4015 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
4016 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
4017 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
4018 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */
4019 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */
4020 } },
4021 { },
4022 };
4023
r8a7795_pin_to_pocctrl(struct sh_pfc * pfc,unsigned int pin,u32 * pocctrl)4024 static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
4025 {
4026 int bit = -EINVAL;
4027
4028 *pocctrl = 0xe6060380;
4029
4030 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
4031 bit = pin & 0x1f;
4032
4033 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
4034 bit = (pin & 0x1f) + 12;
4035
4036 return bit;
4037 }
4038
4039 #define PUEN 0xe6060400
4040 #define PUD 0xe6060440
4041
4042 #define PU0 0x00
4043 #define PU1 0x04
4044 #define PU2 0x08
4045 #define PU3 0x0c
4046 #define PU4 0x10
4047 #define PU5 0x14
4048 #define PU6 0x18
4049
4050 static const struct sh_pfc_bias_info bias_info[] = {
4051 { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
4052 { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
4053 { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
4054 { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */
4055 { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */
4056 { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */
4057 { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */
4058 { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */
4059 { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */
4060 { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */
4061 { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */
4062 { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */
4063 { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */
4064 { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */
4065 { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */
4066 { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */
4067 { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */
4068 { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */
4069 { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */
4070 { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */
4071 { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */
4072 { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */
4073 { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */
4074 { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */
4075 { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */
4076 { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */
4077 { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */
4078 { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */
4079 { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */
4080 { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */
4081 { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */
4082 { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */
4083
4084 { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
4085 { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
4086 { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
4087 { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
4088 { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
4089 { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
4090 { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
4091 { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
4092 { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
4093 { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
4094 { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
4095 { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
4096 { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
4097 { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
4098 { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
4099 { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
4100 { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
4101 { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
4102 { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
4103 { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
4104 { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
4105 { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
4106 { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
4107 { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
4108 { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
4109 { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
4110 { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
4111 { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
4112 { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
4113 { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
4114 { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
4115 { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
4116
4117 { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */
4118 { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */
4119 { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
4120 { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
4121 { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
4122 { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
4123 { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
4124 { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
4125 { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
4126 { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
4127 { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
4128 { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
4129 { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
4130 { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
4131 { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
4132 { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
4133 { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
4134 { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
4135 { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
4136 { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
4137 { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
4138 { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
4139 { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */
4140 { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
4141 { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
4142 { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
4143 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
4144 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
4145 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
4146 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N */
4147 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
4148 { PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */
4149
4150 { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
4151 { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
4152 { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
4153 { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
4154 { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
4155 { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
4156 { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
4157 { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
4158 { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
4159 { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
4160 { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
4161 { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
4162 { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
4163 { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
4164 { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
4165 { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
4166 { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
4167 { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
4168 { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
4169 { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
4170 { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
4171 { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
4172 { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */
4173 /* bit 8 n/a */
4174 { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */
4175 { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */
4176 { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */
4177 { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */
4178 { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/
4179 { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST# */
4180 { PIN_A_NUMBER('R', 8), PU3, 1 }, /* DU_DOTCLKIN3 */
4181 { PIN_A_NUMBER('R', 7), PU3, 0 }, /* DU_DOTCLKIN2 */
4182
4183 { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
4184 { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
4185 { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
4186 { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
4187 { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
4188 { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
4189 { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
4190 { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
4191 { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
4192 { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
4193 { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
4194 { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
4195 { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
4196 { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
4197 { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
4198 { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
4199 { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
4200 { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
4201 { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
4202 { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
4203 { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
4204 { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
4205 { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
4206 { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
4207 { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
4208 { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
4209 { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
4210 { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
4211 { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
4212 { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
4213 { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
4214 { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
4215
4216 { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
4217 { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
4218 { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
4219 { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
4220 { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
4221 { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
4222 { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
4223 { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
4224 { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
4225 { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
4226 { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
4227 { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
4228 { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
4229 { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
4230 { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
4231 { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
4232 { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
4233 { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
4234 { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */
4235 { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */
4236 { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
4237 { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
4238 { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
4239 { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
4240 { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
4241 { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */
4242 { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
4243 { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
4244 { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
4245 { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
4246 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
4247 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
4248
4249 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB2_CH3_OVC */
4250 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB2_CH3_PWEN */
4251 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
4252 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
4253 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
4254 { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
4255 { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
4256 };
4257
r8a7795_pinmux_get_bias(struct sh_pfc * pfc,unsigned int pin)4258 static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
4259 unsigned int pin)
4260 {
4261 const struct sh_pfc_bias_info *info;
4262 u32 reg;
4263 u32 bit;
4264
4265 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
4266 if (!info)
4267 return PIN_CONFIG_BIAS_DISABLE;
4268
4269 reg = info->reg;
4270 bit = BIT(info->bit);
4271
4272 if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
4273 return PIN_CONFIG_BIAS_DISABLE;
4274 else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
4275 return PIN_CONFIG_BIAS_PULL_UP;
4276 else
4277 return PIN_CONFIG_BIAS_PULL_DOWN;
4278 }
4279
r8a7795_pinmux_set_bias(struct sh_pfc * pfc,unsigned int pin,unsigned int bias)4280 static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
4281 unsigned int bias)
4282 {
4283 const struct sh_pfc_bias_info *info;
4284 u32 enable, updown;
4285 u32 reg;
4286 u32 bit;
4287
4288 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
4289 if (!info)
4290 return;
4291
4292 reg = info->reg;
4293 bit = BIT(info->bit);
4294
4295 enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
4296 if (bias != PIN_CONFIG_BIAS_DISABLE)
4297 enable |= bit;
4298
4299 updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
4300 if (bias == PIN_CONFIG_BIAS_PULL_UP)
4301 updown |= bit;
4302
4303 sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
4304 sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
4305 }
4306
4307 static const struct soc_device_attribute r8a7795es1[] = {
4308 { .soc_id = "r8a7795", .revision = "ES1.*" },
4309 { /* sentinel */ }
4310 };
4311
r8a7795_pinmux_init(struct sh_pfc * pfc)4312 static int r8a7795_pinmux_init(struct sh_pfc *pfc)
4313 {
4314 if (soc_device_match(r8a7795es1))
4315 pfc->info = &r8a7795es1_pinmux_info;
4316
4317 return 0;
4318 }
4319
4320 static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
4321 .init = r8a7795_pinmux_init,
4322 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
4323 .get_bias = r8a7795_pinmux_get_bias,
4324 .set_bias = r8a7795_pinmux_set_bias,
4325 };
4326
4327 const struct sh_pfc_soc_info r8a7795_pinmux_info = {
4328 .name = "r8a77951_pfc",
4329 .ops = &r8a7795_pinmux_ops,
4330 .unlock_reg = 0xe6060000, /* PMMR */
4331
4332 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4333
4334 .pins = pinmux_pins,
4335 .nr_pins = ARRAY_SIZE(pinmux_pins),
4336 .groups = pinmux_groups,
4337 .nr_groups = ARRAY_SIZE(pinmux_groups),
4338 .functions = pinmux_functions,
4339 .nr_functions = ARRAY_SIZE(pinmux_functions),
4340
4341 .cfg_regs = pinmux_config_regs,
4342 .drive_regs = pinmux_drive_regs,
4343
4344 .pinmux_data = pinmux_data,
4345 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
4346 };
4347