1 /*
2 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/err.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/regulator/of_regulator.h>
25 #include <linux/platform_device.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/machine.h>
28 #include <linux/regulator/pfuze100.h>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/regmap.h>
32
33 #define PFUZE_NUMREGS 128
34 #define PFUZE100_VOL_OFFSET 0
35 #define PFUZE100_STANDBY_OFFSET 1
36 #define PFUZE100_MODE_OFFSET 3
37 #define PFUZE100_CONF_OFFSET 4
38
39 #define PFUZE100_DEVICEID 0x0
40 #define PFUZE100_REVID 0x3
41 #define PFUZE100_FABID 0x4
42
43 #define PFUZE100_COINVOL 0x1a
44 #define PFUZE100_SW1ABVOL 0x20
45 #define PFUZE100_SW1CVOL 0x2e
46 #define PFUZE100_SW2VOL 0x35
47 #define PFUZE100_SW3AVOL 0x3c
48 #define PFUZE100_SW3BVOL 0x43
49 #define PFUZE100_SW4VOL 0x4a
50 #define PFUZE100_SWBSTCON1 0x66
51 #define PFUZE100_VREFDDRCON 0x6a
52 #define PFUZE100_VSNVSVOL 0x6b
53 #define PFUZE100_VGEN1VOL 0x6c
54 #define PFUZE100_VGEN2VOL 0x6d
55 #define PFUZE100_VGEN3VOL 0x6e
56 #define PFUZE100_VGEN4VOL 0x6f
57 #define PFUZE100_VGEN5VOL 0x70
58 #define PFUZE100_VGEN6VOL 0x71
59
60 enum chips { PFUZE100, PFUZE200, PFUZE3000 = 3 };
61
62 struct pfuze_regulator {
63 struct regulator_desc desc;
64 unsigned char stby_reg;
65 unsigned char stby_mask;
66 };
67
68 struct pfuze_chip {
69 int chip_id;
70 struct regmap *regmap;
71 struct device *dev;
72 struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR];
73 struct regulator_dev *regulators[PFUZE100_MAX_REGULATOR];
74 struct pfuze_regulator *pfuze_regulators;
75 };
76
77 static const int pfuze100_swbst[] = {
78 5000000, 5050000, 5100000, 5150000,
79 };
80
81 static const int pfuze100_vsnvs[] = {
82 1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000,
83 };
84
85 static const int pfuze100_coin[] = {
86 2500000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000,
87 };
88
89 static const int pfuze3000_sw2lo[] = {
90 1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000,
91 };
92
93 static const int pfuze3000_sw2hi[] = {
94 2500000, 2800000, 2850000, 3000000, 3100000, 3150000, 3200000, 3300000,
95 };
96
97 static const struct i2c_device_id pfuze_device_id[] = {
98 {.name = "pfuze100", .driver_data = PFUZE100},
99 {.name = "pfuze200", .driver_data = PFUZE200},
100 {.name = "pfuze3000", .driver_data = PFUZE3000},
101 { }
102 };
103 MODULE_DEVICE_TABLE(i2c, pfuze_device_id);
104
105 static const struct of_device_id pfuze_dt_ids[] = {
106 { .compatible = "fsl,pfuze100", .data = (void *)PFUZE100},
107 { .compatible = "fsl,pfuze200", .data = (void *)PFUZE200},
108 { .compatible = "fsl,pfuze3000", .data = (void *)PFUZE3000},
109 { }
110 };
111 MODULE_DEVICE_TABLE(of, pfuze_dt_ids);
112
pfuze100_set_ramp_delay(struct regulator_dev * rdev,int ramp_delay)113 static int pfuze100_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
114 {
115 struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev);
116 int id = rdev_get_id(rdev);
117 unsigned int ramp_bits;
118 int ret;
119
120 if (id < PFUZE100_SWBST) {
121 ramp_delay = 12500 / ramp_delay;
122 ramp_bits = (ramp_delay >> 1) - (ramp_delay >> 3);
123 ret = regmap_update_bits(pfuze100->regmap,
124 rdev->desc->vsel_reg + 4,
125 0xc0, ramp_bits << 6);
126 if (ret < 0)
127 dev_err(pfuze100->dev, "ramp failed, err %d\n", ret);
128 } else
129 ret = -EACCES;
130
131 return ret;
132 }
133
134 static const struct regulator_ops pfuze100_ldo_regulator_ops = {
135 .enable = regulator_enable_regmap,
136 .disable = regulator_disable_regmap,
137 .is_enabled = regulator_is_enabled_regmap,
138 .list_voltage = regulator_list_voltage_linear,
139 .set_voltage_sel = regulator_set_voltage_sel_regmap,
140 .get_voltage_sel = regulator_get_voltage_sel_regmap,
141 };
142
143 static const struct regulator_ops pfuze100_fixed_regulator_ops = {
144 .enable = regulator_enable_regmap,
145 .disable = regulator_disable_regmap,
146 .is_enabled = regulator_is_enabled_regmap,
147 .list_voltage = regulator_list_voltage_linear,
148 };
149
150 static const struct regulator_ops pfuze100_sw_regulator_ops = {
151 .list_voltage = regulator_list_voltage_linear,
152 .set_voltage_sel = regulator_set_voltage_sel_regmap,
153 .get_voltage_sel = regulator_get_voltage_sel_regmap,
154 .set_voltage_time_sel = regulator_set_voltage_time_sel,
155 .set_ramp_delay = pfuze100_set_ramp_delay,
156 };
157
158 static const struct regulator_ops pfuze100_swb_regulator_ops = {
159 .enable = regulator_enable_regmap,
160 .disable = regulator_disable_regmap,
161 .is_enabled = regulator_is_enabled_regmap,
162 .list_voltage = regulator_list_voltage_table,
163 .map_voltage = regulator_map_voltage_ascend,
164 .set_voltage_sel = regulator_set_voltage_sel_regmap,
165 .get_voltage_sel = regulator_get_voltage_sel_regmap,
166
167 };
168
169 #define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \
170 [_chip ## _ ## _name] = { \
171 .desc = { \
172 .name = #_name, \
173 .n_voltages = 1, \
174 .ops = &pfuze100_fixed_regulator_ops, \
175 .type = REGULATOR_VOLTAGE, \
176 .id = _chip ## _ ## _name, \
177 .owner = THIS_MODULE, \
178 .min_uV = (voltage), \
179 .enable_reg = (base), \
180 .enable_mask = 0x10, \
181 }, \
182 }
183
184 #define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \
185 [_chip ## _ ## _name] = { \
186 .desc = { \
187 .name = #_name,\
188 .n_voltages = ((max) - (min)) / (step) + 1, \
189 .ops = &pfuze100_sw_regulator_ops, \
190 .type = REGULATOR_VOLTAGE, \
191 .id = _chip ## _ ## _name, \
192 .owner = THIS_MODULE, \
193 .min_uV = (min), \
194 .uV_step = (step), \
195 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
196 .vsel_mask = 0x3f, \
197 }, \
198 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
199 .stby_mask = 0x3f, \
200 }
201
202 #define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \
203 [_chip ## _ ## _name] = { \
204 .desc = { \
205 .name = #_name, \
206 .n_voltages = ARRAY_SIZE(voltages), \
207 .ops = &pfuze100_swb_regulator_ops, \
208 .type = REGULATOR_VOLTAGE, \
209 .id = _chip ## _ ## _name, \
210 .owner = THIS_MODULE, \
211 .volt_table = voltages, \
212 .vsel_reg = (base), \
213 .vsel_mask = (mask), \
214 .enable_reg = (base), \
215 .enable_mask = 0x48, \
216 }, \
217 }
218
219 #define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step) \
220 [_chip ## _ ## _name] = { \
221 .desc = { \
222 .name = #_name, \
223 .n_voltages = ((max) - (min)) / (step) + 1, \
224 .ops = &pfuze100_ldo_regulator_ops, \
225 .type = REGULATOR_VOLTAGE, \
226 .id = _chip ## _ ## _name, \
227 .owner = THIS_MODULE, \
228 .min_uV = (min), \
229 .uV_step = (step), \
230 .vsel_reg = (base), \
231 .vsel_mask = 0xf, \
232 .enable_reg = (base), \
233 .enable_mask = 0x10, \
234 }, \
235 .stby_reg = (base), \
236 .stby_mask = 0x20, \
237 }
238
239 #define PFUZE100_COIN_REG(_chip, _name, base, mask, voltages) \
240 [_chip ## _ ## _name] = { \
241 .desc = { \
242 .name = #_name, \
243 .n_voltages = ARRAY_SIZE(voltages), \
244 .ops = &pfuze100_swb_regulator_ops, \
245 .type = REGULATOR_VOLTAGE, \
246 .id = _chip ## _ ## _name, \
247 .owner = THIS_MODULE, \
248 .volt_table = voltages, \
249 .vsel_reg = (base), \
250 .vsel_mask = (mask), \
251 .enable_reg = (base), \
252 .enable_mask = 0x8, \
253 }, \
254 }
255
256 #define PFUZE3000_VCC_REG(_chip, _name, base, min, max, step) { \
257 .desc = { \
258 .name = #_name, \
259 .n_voltages = ((max) - (min)) / (step) + 1, \
260 .ops = &pfuze100_ldo_regulator_ops, \
261 .type = REGULATOR_VOLTAGE, \
262 .id = _chip ## _ ## _name, \
263 .owner = THIS_MODULE, \
264 .min_uV = (min), \
265 .uV_step = (step), \
266 .vsel_reg = (base), \
267 .vsel_mask = 0x3, \
268 .enable_reg = (base), \
269 .enable_mask = 0x10, \
270 }, \
271 .stby_reg = (base), \
272 .stby_mask = 0x20, \
273 }
274
275
276 #define PFUZE3000_SW2_REG(_chip, _name, base, min, max, step) { \
277 .desc = { \
278 .name = #_name,\
279 .n_voltages = ((max) - (min)) / (step) + 1, \
280 .ops = &pfuze100_sw_regulator_ops, \
281 .type = REGULATOR_VOLTAGE, \
282 .id = _chip ## _ ## _name, \
283 .owner = THIS_MODULE, \
284 .min_uV = (min), \
285 .uV_step = (step), \
286 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
287 .vsel_mask = 0x7, \
288 }, \
289 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
290 .stby_mask = 0x7, \
291 }
292
293 #define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step) { \
294 .desc = { \
295 .name = #_name,\
296 .n_voltages = ((max) - (min)) / (step) + 1, \
297 .ops = &pfuze100_sw_regulator_ops, \
298 .type = REGULATOR_VOLTAGE, \
299 .id = _chip ## _ ## _name, \
300 .owner = THIS_MODULE, \
301 .min_uV = (min), \
302 .uV_step = (step), \
303 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
304 .vsel_mask = 0xf, \
305 }, \
306 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
307 .stby_mask = 0xf, \
308 }
309
310 /* PFUZE100 */
311 static struct pfuze_regulator pfuze100_regulators[] = {
312 PFUZE100_SW_REG(PFUZE100, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
313 PFUZE100_SW_REG(PFUZE100, SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000),
314 PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
315 PFUZE100_SW_REG(PFUZE100, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
316 PFUZE100_SW_REG(PFUZE100, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
317 PFUZE100_SW_REG(PFUZE100, SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000),
318 PFUZE100_SWB_REG(PFUZE100, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
319 PFUZE100_SWB_REG(PFUZE100, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
320 PFUZE100_FIXED_REG(PFUZE100, VREFDDR, PFUZE100_VREFDDRCON, 750000),
321 PFUZE100_VGEN_REG(PFUZE100, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
322 PFUZE100_VGEN_REG(PFUZE100, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
323 PFUZE100_VGEN_REG(PFUZE100, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
324 PFUZE100_VGEN_REG(PFUZE100, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
325 PFUZE100_VGEN_REG(PFUZE100, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
326 PFUZE100_VGEN_REG(PFUZE100, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
327 };
328
329 static struct pfuze_regulator pfuze200_regulators[] = {
330 PFUZE100_SW_REG(PFUZE200, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
331 PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
332 PFUZE100_SW_REG(PFUZE200, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
333 PFUZE100_SW_REG(PFUZE200, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
334 PFUZE100_SWB_REG(PFUZE200, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
335 PFUZE100_SWB_REG(PFUZE200, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
336 PFUZE100_FIXED_REG(PFUZE200, VREFDDR, PFUZE100_VREFDDRCON, 750000),
337 PFUZE100_VGEN_REG(PFUZE200, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
338 PFUZE100_VGEN_REG(PFUZE200, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
339 PFUZE100_VGEN_REG(PFUZE200, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
340 PFUZE100_VGEN_REG(PFUZE200, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
341 PFUZE100_VGEN_REG(PFUZE200, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
342 PFUZE100_VGEN_REG(PFUZE200, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
343 PFUZE100_COIN_REG(PFUZE200, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin),
344 };
345
346 static struct pfuze_regulator pfuze3000_regulators[] = {
347 PFUZE100_SW_REG(PFUZE3000, SW1A, PFUZE100_SW1ABVOL, 700000, 1475000, 25000),
348 PFUZE100_SW_REG(PFUZE3000, SW1B, PFUZE100_SW1CVOL, 700000, 1475000, 25000),
349 PFUZE100_SWB_REG(PFUZE3000, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
350 PFUZE3000_SW3_REG(PFUZE3000, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
351 PFUZE100_SWB_REG(PFUZE3000, SWBST, PFUZE100_SWBSTCON1, 0x3, pfuze100_swbst),
352 PFUZE100_SWB_REG(PFUZE3000, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
353 PFUZE100_FIXED_REG(PFUZE3000, VREFDDR, PFUZE100_VREFDDRCON, 750000),
354 PFUZE100_VGEN_REG(PFUZE3000, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
355 PFUZE100_VGEN_REG(PFUZE3000, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
356 PFUZE3000_VCC_REG(PFUZE3000, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
357 PFUZE3000_VCC_REG(PFUZE3000, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
358 PFUZE100_VGEN_REG(PFUZE3000, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
359 PFUZE100_VGEN_REG(PFUZE3000, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
360 };
361
362 #ifdef CONFIG_OF
363 /* PFUZE100 */
364 static struct of_regulator_match pfuze100_matches[] = {
365 { .name = "sw1ab", },
366 { .name = "sw1c", },
367 { .name = "sw2", },
368 { .name = "sw3a", },
369 { .name = "sw3b", },
370 { .name = "sw4", },
371 { .name = "swbst", },
372 { .name = "vsnvs", },
373 { .name = "vrefddr", },
374 { .name = "vgen1", },
375 { .name = "vgen2", },
376 { .name = "vgen3", },
377 { .name = "vgen4", },
378 { .name = "vgen5", },
379 { .name = "vgen6", },
380 };
381
382 /* PFUZE200 */
383 static struct of_regulator_match pfuze200_matches[] = {
384
385 { .name = "sw1ab", },
386 { .name = "sw2", },
387 { .name = "sw3a", },
388 { .name = "sw3b", },
389 { .name = "swbst", },
390 { .name = "vsnvs", },
391 { .name = "vrefddr", },
392 { .name = "vgen1", },
393 { .name = "vgen2", },
394 { .name = "vgen3", },
395 { .name = "vgen4", },
396 { .name = "vgen5", },
397 { .name = "vgen6", },
398 { .name = "coin", },
399 };
400
401 /* PFUZE3000 */
402 static struct of_regulator_match pfuze3000_matches[] = {
403
404 { .name = "sw1a", },
405 { .name = "sw1b", },
406 { .name = "sw2", },
407 { .name = "sw3", },
408 { .name = "swbst", },
409 { .name = "vsnvs", },
410 { .name = "vrefddr", },
411 { .name = "vldo1", },
412 { .name = "vldo2", },
413 { .name = "vccsd", },
414 { .name = "v33", },
415 { .name = "vldo3", },
416 { .name = "vldo4", },
417 };
418
419 static struct of_regulator_match *pfuze_matches;
420
pfuze_parse_regulators_dt(struct pfuze_chip * chip)421 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
422 {
423 struct device *dev = chip->dev;
424 struct device_node *np, *parent;
425 int ret;
426
427 np = of_node_get(dev->of_node);
428 if (!np)
429 return -EINVAL;
430
431 parent = of_get_child_by_name(np, "regulators");
432 if (!parent) {
433 dev_err(dev, "regulators node not found\n");
434 return -EINVAL;
435 }
436
437 switch (chip->chip_id) {
438 case PFUZE3000:
439 pfuze_matches = pfuze3000_matches;
440 ret = of_regulator_match(dev, parent, pfuze3000_matches,
441 ARRAY_SIZE(pfuze3000_matches));
442 break;
443 case PFUZE200:
444 pfuze_matches = pfuze200_matches;
445 ret = of_regulator_match(dev, parent, pfuze200_matches,
446 ARRAY_SIZE(pfuze200_matches));
447 break;
448
449 case PFUZE100:
450 default:
451 pfuze_matches = pfuze100_matches;
452 ret = of_regulator_match(dev, parent, pfuze100_matches,
453 ARRAY_SIZE(pfuze100_matches));
454 break;
455 }
456
457 of_node_put(parent);
458 if (ret < 0) {
459 dev_err(dev, "Error parsing regulator init data: %d\n",
460 ret);
461 return ret;
462 }
463
464 return 0;
465 }
466
match_init_data(int index)467 static inline struct regulator_init_data *match_init_data(int index)
468 {
469 return pfuze_matches[index].init_data;
470 }
471
match_of_node(int index)472 static inline struct device_node *match_of_node(int index)
473 {
474 return pfuze_matches[index].of_node;
475 }
476 #else
pfuze_parse_regulators_dt(struct pfuze_chip * chip)477 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
478 {
479 return 0;
480 }
481
match_init_data(int index)482 static inline struct regulator_init_data *match_init_data(int index)
483 {
484 return NULL;
485 }
486
match_of_node(int index)487 static inline struct device_node *match_of_node(int index)
488 {
489 return NULL;
490 }
491 #endif
492
pfuze_identify(struct pfuze_chip * pfuze_chip)493 static int pfuze_identify(struct pfuze_chip *pfuze_chip)
494 {
495 unsigned int value;
496 int ret;
497
498 ret = regmap_read(pfuze_chip->regmap, PFUZE100_DEVICEID, &value);
499 if (ret)
500 return ret;
501
502 if (((value & 0x0f) == 0x8) && (pfuze_chip->chip_id == PFUZE100)) {
503 /*
504 * Freescale misprogrammed 1-3% of parts prior to week 8 of 2013
505 * as ID=8 in PFUZE100
506 */
507 dev_info(pfuze_chip->dev, "Assuming misprogrammed ID=0x8");
508 } else if ((value & 0x0f) != pfuze_chip->chip_id &&
509 (value & 0xf0) >> 4 != pfuze_chip->chip_id) {
510 /* device id NOT match with your setting */
511 dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
512 return -ENODEV;
513 }
514
515 ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value);
516 if (ret)
517 return ret;
518 dev_info(pfuze_chip->dev,
519 "Full layer: %x, Metal layer: %x\n",
520 (value & 0xf0) >> 4, value & 0x0f);
521
522 ret = regmap_read(pfuze_chip->regmap, PFUZE100_FABID, &value);
523 if (ret)
524 return ret;
525 dev_info(pfuze_chip->dev, "FAB: %x, FIN: %x\n",
526 (value & 0xc) >> 2, value & 0x3);
527
528 return 0;
529 }
530
531 static const struct regmap_config pfuze_regmap_config = {
532 .reg_bits = 8,
533 .val_bits = 8,
534 .max_register = PFUZE_NUMREGS - 1,
535 .cache_type = REGCACHE_RBTREE,
536 };
537
pfuze100_regulator_probe(struct i2c_client * client,const struct i2c_device_id * id)538 static int pfuze100_regulator_probe(struct i2c_client *client,
539 const struct i2c_device_id *id)
540 {
541 struct pfuze_chip *pfuze_chip;
542 struct pfuze_regulator_platform_data *pdata =
543 dev_get_platdata(&client->dev);
544 struct regulator_config config = { };
545 int i, ret;
546 const struct of_device_id *match;
547 u32 regulator_num;
548 u32 sw_check_start, sw_check_end, sw_hi = 0x40;
549
550 pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip),
551 GFP_KERNEL);
552 if (!pfuze_chip)
553 return -ENOMEM;
554
555 if (client->dev.of_node) {
556 match = of_match_device(of_match_ptr(pfuze_dt_ids),
557 &client->dev);
558 if (!match) {
559 dev_err(&client->dev, "Error: No device match found\n");
560 return -ENODEV;
561 }
562 pfuze_chip->chip_id = (int)(long)match->data;
563 } else if (id) {
564 pfuze_chip->chip_id = id->driver_data;
565 } else {
566 dev_err(&client->dev, "No dts match or id table match found\n");
567 return -ENODEV;
568 }
569
570 i2c_set_clientdata(client, pfuze_chip);
571 pfuze_chip->dev = &client->dev;
572
573 pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config);
574 if (IS_ERR(pfuze_chip->regmap)) {
575 ret = PTR_ERR(pfuze_chip->regmap);
576 dev_err(&client->dev,
577 "regmap allocation failed with err %d\n", ret);
578 return ret;
579 }
580
581 ret = pfuze_identify(pfuze_chip);
582 if (ret) {
583 dev_err(&client->dev, "unrecognized pfuze chip ID!\n");
584 return ret;
585 }
586
587 /* use the right regulators after identify the right device */
588 switch (pfuze_chip->chip_id) {
589 case PFUZE3000:
590 pfuze_chip->pfuze_regulators = pfuze3000_regulators;
591 regulator_num = ARRAY_SIZE(pfuze3000_regulators);
592 sw_check_start = PFUZE3000_SW2;
593 sw_check_end = PFUZE3000_SW2;
594 sw_hi = 1 << 3;
595 break;
596 case PFUZE200:
597 pfuze_chip->pfuze_regulators = pfuze200_regulators;
598 regulator_num = ARRAY_SIZE(pfuze200_regulators);
599 sw_check_start = PFUZE200_SW2;
600 sw_check_end = PFUZE200_SW3B;
601 break;
602 case PFUZE100:
603 default:
604 pfuze_chip->pfuze_regulators = pfuze100_regulators;
605 regulator_num = ARRAY_SIZE(pfuze100_regulators);
606 sw_check_start = PFUZE100_SW2;
607 sw_check_end = PFUZE100_SW4;
608 break;
609 }
610 dev_info(&client->dev, "pfuze%s found.\n",
611 (pfuze_chip->chip_id == PFUZE100) ? "100" :
612 ((pfuze_chip->chip_id == PFUZE200) ? "200" : "3000"));
613
614 memcpy(pfuze_chip->regulator_descs, pfuze_chip->pfuze_regulators,
615 sizeof(pfuze_chip->regulator_descs));
616
617 ret = pfuze_parse_regulators_dt(pfuze_chip);
618 if (ret)
619 return ret;
620
621 for (i = 0; i < regulator_num; i++) {
622 struct regulator_init_data *init_data;
623 struct regulator_desc *desc;
624 int val;
625
626 desc = &pfuze_chip->regulator_descs[i].desc;
627
628 if (pdata)
629 init_data = pdata->init_data[i];
630 else
631 init_data = match_init_data(i);
632
633 /* SW2~SW4 high bit check and modify the voltage value table */
634 if (i >= sw_check_start && i <= sw_check_end) {
635 ret = regmap_read(pfuze_chip->regmap,
636 desc->vsel_reg, &val);
637 if (ret) {
638 dev_err(&client->dev, "Fails to read from the register.\n");
639 return ret;
640 }
641
642 if (val & sw_hi) {
643 if (pfuze_chip->chip_id == PFUZE3000) {
644 desc->volt_table = pfuze3000_sw2hi;
645 desc->n_voltages = ARRAY_SIZE(pfuze3000_sw2hi);
646 } else {
647 desc->min_uV = 800000;
648 desc->uV_step = 50000;
649 desc->n_voltages = 51;
650 }
651 }
652 }
653
654 config.dev = &client->dev;
655 config.init_data = init_data;
656 config.driver_data = pfuze_chip;
657 config.of_node = match_of_node(i);
658 config.ena_gpio = -EINVAL;
659
660 pfuze_chip->regulators[i] =
661 devm_regulator_register(&client->dev, desc, &config);
662 if (IS_ERR(pfuze_chip->regulators[i])) {
663 dev_err(&client->dev, "register regulator%s failed\n",
664 pfuze_chip->pfuze_regulators[i].desc.name);
665 return PTR_ERR(pfuze_chip->regulators[i]);
666 }
667 }
668
669 return 0;
670 }
671
672 static struct i2c_driver pfuze_driver = {
673 .id_table = pfuze_device_id,
674 .driver = {
675 .name = "pfuze100-regulator",
676 .of_match_table = pfuze_dt_ids,
677 },
678 .probe = pfuze100_regulator_probe,
679 };
680 module_i2c_driver(pfuze_driver);
681
682 MODULE_AUTHOR("Robin Gong <b38343@freescale.com>");
683 MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100/200/3000 PMIC");
684 MODULE_LICENSE("GPL v2");
685