1 /*
2 * Exynos Generic power domain support.
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Implementation of Exynos specific power domain control which is used in
8 * conjunction with runtime-pm. Support for both device-tree and non-device-tree
9 * based power domain support is included.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16 #include <linux/io.h>
17 #include <linux/err.h>
18 #include <linux/slab.h>
19 #include <linux/pm_domain.h>
20 #include <linux/clk.h>
21 #include <linux/delay.h>
22 #include <linux/of_address.h>
23 #include <linux/of_platform.h>
24 #include <linux/sched.h>
25
26 #define MAX_CLK_PER_DOMAIN 4
27
28 struct exynos_pm_domain_config {
29 /* Value for LOCAL_PWR_CFG and STATUS fields for each domain */
30 u32 local_pwr_cfg;
31 };
32
33 /*
34 * Exynos specific wrapper around the generic power domain
35 */
36 struct exynos_pm_domain {
37 void __iomem *base;
38 bool is_off;
39 struct generic_pm_domain pd;
40 struct clk *oscclk;
41 struct clk *clk[MAX_CLK_PER_DOMAIN];
42 struct clk *pclk[MAX_CLK_PER_DOMAIN];
43 struct clk *asb_clk[MAX_CLK_PER_DOMAIN];
44 u32 local_pwr_cfg;
45 };
46
exynos_pd_power(struct generic_pm_domain * domain,bool power_on)47 static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
48 {
49 struct exynos_pm_domain *pd;
50 void __iomem *base;
51 u32 timeout, pwr;
52 char *op;
53 int i;
54
55 pd = container_of(domain, struct exynos_pm_domain, pd);
56 base = pd->base;
57
58 for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
59 if (IS_ERR(pd->asb_clk[i]))
60 break;
61 clk_prepare_enable(pd->asb_clk[i]);
62 }
63
64 /* Set oscclk before powering off a domain*/
65 if (!power_on) {
66 for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
67 if (IS_ERR(pd->clk[i]))
68 break;
69 pd->pclk[i] = clk_get_parent(pd->clk[i]);
70 if (clk_set_parent(pd->clk[i], pd->oscclk))
71 pr_err("%s: error setting oscclk as parent to clock %d\n",
72 domain->name, i);
73 }
74 }
75
76 pwr = power_on ? pd->local_pwr_cfg : 0;
77 writel_relaxed(pwr, base);
78
79 /* Wait max 1ms */
80 timeout = 10;
81
82 while ((readl_relaxed(base + 0x4) & pd->local_pwr_cfg) != pwr) {
83 if (!timeout) {
84 op = (power_on) ? "enable" : "disable";
85 pr_err("Power domain %s %s failed\n", domain->name, op);
86 return -ETIMEDOUT;
87 }
88 timeout--;
89 cpu_relax();
90 usleep_range(80, 100);
91 }
92
93 /* Restore clocks after powering on a domain*/
94 if (power_on) {
95 for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
96 if (IS_ERR(pd->clk[i]))
97 break;
98
99 if (IS_ERR(pd->pclk[i]))
100 continue; /* Skip on first power up */
101 if (clk_set_parent(pd->clk[i], pd->pclk[i]))
102 pr_err("%s: error setting parent to clock%d\n",
103 domain->name, i);
104 }
105 }
106
107 for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
108 if (IS_ERR(pd->asb_clk[i]))
109 break;
110 clk_disable_unprepare(pd->asb_clk[i]);
111 }
112
113 return 0;
114 }
115
exynos_pd_power_on(struct generic_pm_domain * domain)116 static int exynos_pd_power_on(struct generic_pm_domain *domain)
117 {
118 return exynos_pd_power(domain, true);
119 }
120
exynos_pd_power_off(struct generic_pm_domain * domain)121 static int exynos_pd_power_off(struct generic_pm_domain *domain)
122 {
123 return exynos_pd_power(domain, false);
124 }
125
126 static const struct exynos_pm_domain_config exynos4210_cfg __initconst = {
127 .local_pwr_cfg = 0x7,
128 };
129
130 static const struct exynos_pm_domain_config exynos5433_cfg __initconst = {
131 .local_pwr_cfg = 0xf,
132 };
133
134 static const struct of_device_id exynos_pm_domain_of_match[] __initconst = {
135 {
136 .compatible = "samsung,exynos4210-pd",
137 .data = &exynos4210_cfg,
138 }, {
139 .compatible = "samsung,exynos5433-pd",
140 .data = &exynos5433_cfg,
141 },
142 { },
143 };
144
exynos_get_domain_name(struct device_node * node)145 static __init const char *exynos_get_domain_name(struct device_node *node)
146 {
147 const char *name;
148
149 if (of_property_read_string(node, "label", &name) < 0)
150 name = kbasename(node->full_name);
151 return kstrdup_const(name, GFP_KERNEL);
152 }
153
exynos4_pm_init_power_domain(void)154 static __init int exynos4_pm_init_power_domain(void)
155 {
156 struct device_node *np;
157 const struct of_device_id *match;
158
159 for_each_matching_node_and_match(np, exynos_pm_domain_of_match, &match) {
160 const struct exynos_pm_domain_config *pm_domain_cfg;
161 struct exynos_pm_domain *pd;
162 int on, i;
163
164 pm_domain_cfg = match->data;
165
166 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
167 if (!pd) {
168 of_node_put(np);
169 return -ENOMEM;
170 }
171 pd->pd.name = exynos_get_domain_name(np);
172 if (!pd->pd.name) {
173 kfree(pd);
174 of_node_put(np);
175 return -ENOMEM;
176 }
177
178 pd->base = of_iomap(np, 0);
179 if (!pd->base) {
180 pr_warn("%s: failed to map memory\n", __func__);
181 kfree_const(pd->pd.name);
182 kfree(pd);
183 continue;
184 }
185
186 pd->pd.power_off = exynos_pd_power_off;
187 pd->pd.power_on = exynos_pd_power_on;
188 pd->local_pwr_cfg = pm_domain_cfg->local_pwr_cfg;
189
190 for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
191 char clk_name[8];
192
193 snprintf(clk_name, sizeof(clk_name), "asb%d", i);
194 pd->asb_clk[i] = of_clk_get_by_name(np, clk_name);
195 if (IS_ERR(pd->asb_clk[i]))
196 break;
197 }
198
199 pd->oscclk = of_clk_get_by_name(np, "oscclk");
200 if (IS_ERR(pd->oscclk))
201 goto no_clk;
202
203 for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
204 char clk_name[8];
205
206 snprintf(clk_name, sizeof(clk_name), "clk%d", i);
207 pd->clk[i] = of_clk_get_by_name(np, clk_name);
208 if (IS_ERR(pd->clk[i]))
209 break;
210 /*
211 * Skip setting parent on first power up.
212 * The parent at this time may not be useful at all.
213 */
214 pd->pclk[i] = ERR_PTR(-EINVAL);
215 }
216
217 if (IS_ERR(pd->clk[0]))
218 clk_put(pd->oscclk);
219
220 no_clk:
221 on = readl_relaxed(pd->base + 0x4) & pd->local_pwr_cfg;
222
223 pm_genpd_init(&pd->pd, NULL, !on);
224 of_genpd_add_provider_simple(np, &pd->pd);
225 }
226
227 /* Assign the child power domains to their parents */
228 for_each_matching_node(np, exynos_pm_domain_of_match) {
229 struct of_phandle_args child, parent;
230
231 child.np = np;
232 child.args_count = 0;
233
234 if (of_parse_phandle_with_args(np, "power-domains",
235 "#power-domain-cells", 0,
236 &parent) != 0)
237 continue;
238
239 if (of_genpd_add_subdomain(&parent, &child))
240 pr_warn("%pOF failed to add subdomain: %pOF\n",
241 parent.np, child.np);
242 else
243 pr_info("%pOF has as child subdomain: %pOF.\n",
244 parent.np, child.np);
245 }
246
247 return 0;
248 }
249 core_initcall(exynos4_pm_init_power_domain);
250