1 /*
2 * Driver for Broadcom BCM2835 auxiliary SPI Controllers
3 *
4 * the driver does not rely on the native chipselects at all
5 * but only uses the gpio type chipselects
6 *
7 * Based on: spi-bcm2835.c
8 *
9 * Copyright (C) 2015 Martin Sperl
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22 #include <linux/clk.h>
23 #include <linux/completion.h>
24 #include <linux/delay.h>
25 #include <linux/err.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/of.h>
31 #include <linux/of_address.h>
32 #include <linux/of_device.h>
33 #include <linux/of_gpio.h>
34 #include <linux/of_irq.h>
35 #include <linux/regmap.h>
36 #include <linux/spi/spi.h>
37 #include <linux/spinlock.h>
38
39 /*
40 * spi register defines
41 *
42 * note there is garbage in the "official" documentation,
43 * so some data is taken from the file:
44 * brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h
45 * inside of:
46 * http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz
47 */
48
49 /* SPI register offsets */
50 #define BCM2835_AUX_SPI_CNTL0 0x00
51 #define BCM2835_AUX_SPI_CNTL1 0x04
52 #define BCM2835_AUX_SPI_STAT 0x08
53 #define BCM2835_AUX_SPI_PEEK 0x0C
54 #define BCM2835_AUX_SPI_IO 0x20
55 #define BCM2835_AUX_SPI_TXHOLD 0x30
56
57 /* Bitfields in CNTL0 */
58 #define BCM2835_AUX_SPI_CNTL0_SPEED 0xFFF00000
59 #define BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF
60 #define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT 20
61 #define BCM2835_AUX_SPI_CNTL0_CS 0x000E0000
62 #define BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x00010000
63 #define BCM2835_AUX_SPI_CNTL0_VAR_CS 0x00008000
64 #define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000
65 #define BCM2835_AUX_SPI_CNTL0_DOUTHOLD 0x00003000
66 #define BCM2835_AUX_SPI_CNTL0_ENABLE 0x00000800
67 #define BCM2835_AUX_SPI_CNTL0_IN_RISING 0x00000400
68 #define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200
69 #define BCM2835_AUX_SPI_CNTL0_OUT_RISING 0x00000100
70 #define BCM2835_AUX_SPI_CNTL0_CPOL 0x00000080
71 #define BCM2835_AUX_SPI_CNTL0_MSBF_OUT 0x00000040
72 #define BCM2835_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F
73
74 /* Bitfields in CNTL1 */
75 #define BCM2835_AUX_SPI_CNTL1_CSHIGH 0x00000700
76 #define BCM2835_AUX_SPI_CNTL1_TXEMPTY 0x00000080
77 #define BCM2835_AUX_SPI_CNTL1_IDLE 0x00000040
78 #define BCM2835_AUX_SPI_CNTL1_MSBF_IN 0x00000002
79 #define BCM2835_AUX_SPI_CNTL1_KEEP_IN 0x00000001
80
81 /* Bitfields in STAT */
82 #define BCM2835_AUX_SPI_STAT_TX_LVL 0xFF000000
83 #define BCM2835_AUX_SPI_STAT_RX_LVL 0x00FF0000
84 #define BCM2835_AUX_SPI_STAT_TX_FULL 0x00000400
85 #define BCM2835_AUX_SPI_STAT_TX_EMPTY 0x00000200
86 #define BCM2835_AUX_SPI_STAT_RX_FULL 0x00000100
87 #define BCM2835_AUX_SPI_STAT_RX_EMPTY 0x00000080
88 #define BCM2835_AUX_SPI_STAT_BUSY 0x00000040
89 #define BCM2835_AUX_SPI_STAT_BITCOUNT 0x0000003F
90
91 /* timeout values */
92 #define BCM2835_AUX_SPI_POLLING_LIMIT_US 30
93 #define BCM2835_AUX_SPI_POLLING_JIFFIES 2
94
95 struct bcm2835aux_spi {
96 void __iomem *regs;
97 struct clk *clk;
98 int irq;
99 u32 cntl[2];
100 const u8 *tx_buf;
101 u8 *rx_buf;
102 int tx_len;
103 int rx_len;
104 int pending;
105 };
106
bcm2835aux_rd(struct bcm2835aux_spi * bs,unsigned reg)107 static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned reg)
108 {
109 return readl(bs->regs + reg);
110 }
111
bcm2835aux_wr(struct bcm2835aux_spi * bs,unsigned reg,u32 val)112 static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned reg,
113 u32 val)
114 {
115 writel(val, bs->regs + reg);
116 }
117
bcm2835aux_rd_fifo(struct bcm2835aux_spi * bs)118 static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs)
119 {
120 u32 data;
121 int count = min(bs->rx_len, 3);
122
123 data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO);
124 if (bs->rx_buf) {
125 switch (count) {
126 case 4:
127 *bs->rx_buf++ = (data >> 24) & 0xff;
128 /* fallthrough */
129 case 3:
130 *bs->rx_buf++ = (data >> 16) & 0xff;
131 /* fallthrough */
132 case 2:
133 *bs->rx_buf++ = (data >> 8) & 0xff;
134 /* fallthrough */
135 case 1:
136 *bs->rx_buf++ = (data >> 0) & 0xff;
137 /* fallthrough - no default */
138 }
139 }
140 bs->rx_len -= count;
141 bs->pending -= count;
142 }
143
bcm2835aux_wr_fifo(struct bcm2835aux_spi * bs)144 static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs)
145 {
146 u32 data;
147 u8 byte;
148 int count;
149 int i;
150
151 /* gather up to 3 bytes to write to the FIFO */
152 count = min(bs->tx_len, 3);
153 data = 0;
154 for (i = 0; i < count; i++) {
155 byte = bs->tx_buf ? *bs->tx_buf++ : 0;
156 data |= byte << (8 * (2 - i));
157 }
158
159 /* and set the variable bit-length */
160 data |= (count * 8) << 24;
161
162 /* and decrement length */
163 bs->tx_len -= count;
164 bs->pending += count;
165
166 /* write to the correct TX-register */
167 if (bs->tx_len)
168 bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data);
169 else
170 bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data);
171 }
172
bcm2835aux_spi_reset_hw(struct bcm2835aux_spi * bs)173 static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs)
174 {
175 /* disable spi clearing fifo and interrupts */
176 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0);
177 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0,
178 BCM2835_AUX_SPI_CNTL0_CLEARFIFO);
179 }
180
bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi * bs)181 static void bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi *bs)
182 {
183 u32 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT);
184
185 /* check if we have data to read */
186 for (; bs->rx_len && (stat & BCM2835_AUX_SPI_STAT_RX_LVL);
187 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT))
188 bcm2835aux_rd_fifo(bs);
189
190 /* check if we have data to write */
191 while (bs->tx_len &&
192 (bs->pending < 12) &&
193 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
194 BCM2835_AUX_SPI_STAT_TX_FULL))) {
195 bcm2835aux_wr_fifo(bs);
196 }
197 }
198
bcm2835aux_spi_interrupt(int irq,void * dev_id)199 static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
200 {
201 struct spi_master *master = dev_id;
202 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
203
204 /* IRQ may be shared, so return if our interrupts are disabled */
205 if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) &
206 (BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE)))
207 return IRQ_NONE;
208
209 /* do common fifo handling */
210 bcm2835aux_spi_transfer_helper(bs);
211
212 if (!bs->tx_len) {
213 /* disable tx fifo empty interrupt */
214 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
215 BCM2835_AUX_SPI_CNTL1_IDLE);
216 }
217
218 /* and if rx_len is 0 then disable interrupts and wake up completion */
219 if (!bs->rx_len) {
220 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
221 complete(&master->xfer_completion);
222 }
223
224 return IRQ_HANDLED;
225 }
226
__bcm2835aux_spi_transfer_one_irq(struct spi_master * master,struct spi_device * spi,struct spi_transfer * tfr)227 static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
228 struct spi_device *spi,
229 struct spi_transfer *tfr)
230 {
231 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
232
233 /* enable interrupts */
234 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
235 BCM2835_AUX_SPI_CNTL1_TXEMPTY |
236 BCM2835_AUX_SPI_CNTL1_IDLE);
237
238 /* and wait for finish... */
239 return 1;
240 }
241
bcm2835aux_spi_transfer_one_irq(struct spi_master * master,struct spi_device * spi,struct spi_transfer * tfr)242 static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
243 struct spi_device *spi,
244 struct spi_transfer *tfr)
245 {
246 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
247
248 /* fill in registers and fifos before enabling interrupts */
249 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
250 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
251
252 /* fill in tx fifo with data before enabling interrupts */
253 while ((bs->tx_len) &&
254 (bs->pending < 12) &&
255 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
256 BCM2835_AUX_SPI_STAT_TX_FULL))) {
257 bcm2835aux_wr_fifo(bs);
258 }
259
260 /* now run the interrupt mode */
261 return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
262 }
263
bcm2835aux_spi_transfer_one_poll(struct spi_master * master,struct spi_device * spi,struct spi_transfer * tfr)264 static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master,
265 struct spi_device *spi,
266 struct spi_transfer *tfr)
267 {
268 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
269 unsigned long timeout;
270
271 /* configure spi */
272 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
273 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
274
275 /* set the timeout */
276 timeout = jiffies + BCM2835_AUX_SPI_POLLING_JIFFIES;
277
278 /* loop until finished the transfer */
279 while (bs->rx_len) {
280
281 /* do common fifo handling */
282 bcm2835aux_spi_transfer_helper(bs);
283
284 /* there is still data pending to read check the timeout */
285 if (bs->rx_len && time_after(jiffies, timeout)) {
286 dev_dbg_ratelimited(&spi->dev,
287 "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
288 jiffies - timeout,
289 bs->tx_len, bs->rx_len);
290 /* forward to interrupt handler */
291 return __bcm2835aux_spi_transfer_one_irq(master,
292 spi, tfr);
293 }
294 }
295
296 /* and return without waiting for completion */
297 return 0;
298 }
299
bcm2835aux_spi_transfer_one(struct spi_master * master,struct spi_device * spi,struct spi_transfer * tfr)300 static int bcm2835aux_spi_transfer_one(struct spi_master *master,
301 struct spi_device *spi,
302 struct spi_transfer *tfr)
303 {
304 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
305 unsigned long spi_hz, clk_hz, speed;
306 unsigned long spi_used_hz;
307 unsigned long long xfer_time_us;
308
309 /* calculate the registers to handle
310 *
311 * note that we use the variable data mode, which
312 * is not optimal for longer transfers as we waste registers
313 * resulting (potentially) in more interrupts when transferring
314 * more than 12 bytes
315 */
316
317 /* set clock */
318 spi_hz = tfr->speed_hz;
319 clk_hz = clk_get_rate(bs->clk);
320
321 if (spi_hz >= clk_hz / 2) {
322 speed = 0;
323 } else if (spi_hz) {
324 speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;
325 if (speed > BCM2835_AUX_SPI_CNTL0_SPEED_MAX)
326 speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
327 } else { /* the slowest we can go */
328 speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
329 }
330 /* mask out old speed from previous spi_transfer */
331 bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED);
332 /* set the new speed */
333 bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT;
334
335 spi_used_hz = clk_hz / (2 * (speed + 1));
336
337 /* set transmit buffers and length */
338 bs->tx_buf = tfr->tx_buf;
339 bs->rx_buf = tfr->rx_buf;
340 bs->tx_len = tfr->len;
341 bs->rx_len = tfr->len;
342 bs->pending = 0;
343
344 /* calculate the estimated time in us the transfer runs
345 * note that there are are 2 idle clocks after each
346 * chunk getting transferred - in our case the chunk size
347 * is 3 bytes, so we approximate this by 9 bits/byte
348 */
349 xfer_time_us = tfr->len * 9 * 1000000;
350 do_div(xfer_time_us, spi_used_hz);
351
352 /* run in polling mode for short transfers */
353 if (xfer_time_us < BCM2835_AUX_SPI_POLLING_LIMIT_US)
354 return bcm2835aux_spi_transfer_one_poll(master, spi, tfr);
355
356 /* run in interrupt mode for all others */
357 return bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
358 }
359
bcm2835aux_spi_prepare_message(struct spi_master * master,struct spi_message * msg)360 static int bcm2835aux_spi_prepare_message(struct spi_master *master,
361 struct spi_message *msg)
362 {
363 struct spi_device *spi = msg->spi;
364 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
365
366 bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE |
367 BCM2835_AUX_SPI_CNTL0_VAR_WIDTH |
368 BCM2835_AUX_SPI_CNTL0_MSBF_OUT;
369 bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;
370
371 /* handle all the modes */
372 if (spi->mode & SPI_CPOL) {
373 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;
374 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_OUT_RISING;
375 } else {
376 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_IN_RISING;
377 }
378 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
379 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
380
381 return 0;
382 }
383
bcm2835aux_spi_unprepare_message(struct spi_master * master,struct spi_message * msg)384 static int bcm2835aux_spi_unprepare_message(struct spi_master *master,
385 struct spi_message *msg)
386 {
387 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
388
389 bcm2835aux_spi_reset_hw(bs);
390
391 return 0;
392 }
393
bcm2835aux_spi_handle_err(struct spi_master * master,struct spi_message * msg)394 static void bcm2835aux_spi_handle_err(struct spi_master *master,
395 struct spi_message *msg)
396 {
397 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
398
399 bcm2835aux_spi_reset_hw(bs);
400 }
401
bcm2835aux_spi_probe(struct platform_device * pdev)402 static int bcm2835aux_spi_probe(struct platform_device *pdev)
403 {
404 struct spi_master *master;
405 struct bcm2835aux_spi *bs;
406 struct resource *res;
407 unsigned long clk_hz;
408 int err;
409
410 master = spi_alloc_master(&pdev->dev, sizeof(*bs));
411 if (!master) {
412 dev_err(&pdev->dev, "spi_alloc_master() failed\n");
413 return -ENOMEM;
414 }
415
416 platform_set_drvdata(pdev, master);
417 master->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS);
418 master->bits_per_word_mask = SPI_BPW_MASK(8);
419 /* even though the driver never officially supported native CS
420 * allow a single native CS for legacy DT support purposes when
421 * no cs-gpio is configured.
422 * Known limitations for native cs are:
423 * * multiple chip-selects: cs0-cs2 are all simultaniously asserted
424 * whenever there is a transfer - this even includes SPI_NO_CS
425 * * SPI_CS_HIGH: is ignores - cs are always asserted low
426 * * cs_change: cs is deasserted after each spi_transfer
427 * * cs_delay_usec: cs is always deasserted one SCK cycle after
428 * a spi_transfer
429 */
430 master->num_chipselect = 1;
431 master->transfer_one = bcm2835aux_spi_transfer_one;
432 master->handle_err = bcm2835aux_spi_handle_err;
433 master->prepare_message = bcm2835aux_spi_prepare_message;
434 master->unprepare_message = bcm2835aux_spi_unprepare_message;
435 master->dev.of_node = pdev->dev.of_node;
436
437 bs = spi_master_get_devdata(master);
438
439 /* the main area */
440 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
441 bs->regs = devm_ioremap_resource(&pdev->dev, res);
442 if (IS_ERR(bs->regs)) {
443 err = PTR_ERR(bs->regs);
444 goto out_master_put;
445 }
446
447 bs->clk = devm_clk_get(&pdev->dev, NULL);
448 if ((!bs->clk) || (IS_ERR(bs->clk))) {
449 err = PTR_ERR(bs->clk);
450 dev_err(&pdev->dev, "could not get clk: %d\n", err);
451 goto out_master_put;
452 }
453
454 bs->irq = platform_get_irq(pdev, 0);
455 if (bs->irq <= 0) {
456 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
457 err = bs->irq ? bs->irq : -ENODEV;
458 goto out_master_put;
459 }
460
461 /* this also enables the HW block */
462 err = clk_prepare_enable(bs->clk);
463 if (err) {
464 dev_err(&pdev->dev, "could not prepare clock: %d\n", err);
465 goto out_master_put;
466 }
467
468 /* just checking if the clock returns a sane value */
469 clk_hz = clk_get_rate(bs->clk);
470 if (!clk_hz) {
471 dev_err(&pdev->dev, "clock returns 0 Hz\n");
472 err = -ENODEV;
473 goto out_clk_disable;
474 }
475
476 /* reset SPI-HW block */
477 bcm2835aux_spi_reset_hw(bs);
478
479 err = devm_request_irq(&pdev->dev, bs->irq,
480 bcm2835aux_spi_interrupt,
481 IRQF_SHARED,
482 dev_name(&pdev->dev), master);
483 if (err) {
484 dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
485 goto out_clk_disable;
486 }
487
488 err = devm_spi_register_master(&pdev->dev, master);
489 if (err) {
490 dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
491 goto out_clk_disable;
492 }
493
494 return 0;
495
496 out_clk_disable:
497 clk_disable_unprepare(bs->clk);
498 out_master_put:
499 spi_master_put(master);
500 return err;
501 }
502
bcm2835aux_spi_remove(struct platform_device * pdev)503 static int bcm2835aux_spi_remove(struct platform_device *pdev)
504 {
505 struct spi_master *master = platform_get_drvdata(pdev);
506 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
507
508 bcm2835aux_spi_reset_hw(bs);
509
510 /* disable the HW block by releasing the clock */
511 clk_disable_unprepare(bs->clk);
512
513 return 0;
514 }
515
516 static const struct of_device_id bcm2835aux_spi_match[] = {
517 { .compatible = "brcm,bcm2835-aux-spi", },
518 {}
519 };
520 MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match);
521
522 static struct platform_driver bcm2835aux_spi_driver = {
523 .driver = {
524 .name = "spi-bcm2835aux",
525 .of_match_table = bcm2835aux_spi_match,
526 },
527 .probe = bcm2835aux_spi_probe,
528 .remove = bcm2835aux_spi_remove,
529 };
530 module_platform_driver(bcm2835aux_spi_driver);
531
532 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux");
533 MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>");
534 MODULE_LICENSE("GPL v2");
535