1 /*
2 * Copyright (C) 2012-2017 ARM Limited or its affiliates.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #include <linux/platform_device.h>
18 #include <crypto/ctr.h>
19 #include "ssi_config.h"
20 #include "ssi_driver.h"
21 #include "ssi_ivgen.h"
22 #include "ssi_request_mgr.h"
23 #include "ssi_sram_mgr.h"
24 #include "ssi_buffer_mgr.h"
25
26 /* The max. size of pool *MUST* be <= SRAM total size */
27 #define SSI_IVPOOL_SIZE 1024
28 /* The first 32B fraction of pool are dedicated to the
29 * next encryption "key" & "IV" for pool regeneration
30 */
31 #define SSI_IVPOOL_META_SIZE (CC_AES_IV_SIZE + AES_KEYSIZE_128)
32 #define SSI_IVPOOL_GEN_SEQ_LEN 4
33
34 /**
35 * struct ssi_ivgen_ctx -IV pool generation context
36 * @pool: the start address of the iv-pool resides in internal RAM
37 * @ctr_key_dma: address of pool's encryption key material in internal RAM
38 * @ctr_iv_dma: address of pool's counter iv in internal RAM
39 * @next_iv_ofs: the offset to the next available IV in pool
40 * @pool_meta: virt. address of the initial enc. key/IV
41 * @pool_meta_dma: phys. address of the initial enc. key/IV
42 */
43 struct ssi_ivgen_ctx {
44 ssi_sram_addr_t pool;
45 ssi_sram_addr_t ctr_key;
46 ssi_sram_addr_t ctr_iv;
47 u32 next_iv_ofs;
48 u8 *pool_meta;
49 dma_addr_t pool_meta_dma;
50 };
51
52 /*!
53 * Generates SSI_IVPOOL_SIZE of random bytes by
54 * encrypting 0's using AES128-CTR.
55 *
56 * \param ivgen iv-pool context
57 * \param iv_seq IN/OUT array to the descriptors sequence
58 * \param iv_seq_len IN/OUT pointer to the sequence length
59 */
ssi_ivgen_generate_pool(struct ssi_ivgen_ctx * ivgen_ctx,struct cc_hw_desc iv_seq[],unsigned int * iv_seq_len)60 static int ssi_ivgen_generate_pool(
61 struct ssi_ivgen_ctx *ivgen_ctx,
62 struct cc_hw_desc iv_seq[],
63 unsigned int *iv_seq_len)
64 {
65 unsigned int idx = *iv_seq_len;
66
67 if ((*iv_seq_len + SSI_IVPOOL_GEN_SEQ_LEN) > SSI_IVPOOL_SEQ_LEN) {
68 /* The sequence will be longer than allowed */
69 return -EINVAL;
70 }
71 /* Setup key */
72 hw_desc_init(&iv_seq[idx]);
73 set_din_sram(&iv_seq[idx], ivgen_ctx->ctr_key, AES_KEYSIZE_128);
74 set_setup_mode(&iv_seq[idx], SETUP_LOAD_KEY0);
75 set_cipher_config0(&iv_seq[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);
76 set_flow_mode(&iv_seq[idx], S_DIN_to_AES);
77 set_key_size_aes(&iv_seq[idx], CC_AES_128_BIT_KEY_SIZE);
78 set_cipher_mode(&iv_seq[idx], DRV_CIPHER_CTR);
79 idx++;
80
81 /* Setup cipher state */
82 hw_desc_init(&iv_seq[idx]);
83 set_din_sram(&iv_seq[idx], ivgen_ctx->ctr_iv, CC_AES_IV_SIZE);
84 set_cipher_config0(&iv_seq[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);
85 set_flow_mode(&iv_seq[idx], S_DIN_to_AES);
86 set_setup_mode(&iv_seq[idx], SETUP_LOAD_STATE1);
87 set_key_size_aes(&iv_seq[idx], CC_AES_128_BIT_KEY_SIZE);
88 set_cipher_mode(&iv_seq[idx], DRV_CIPHER_CTR);
89 idx++;
90
91 /* Perform dummy encrypt to skip first block */
92 hw_desc_init(&iv_seq[idx]);
93 set_din_const(&iv_seq[idx], 0, CC_AES_IV_SIZE);
94 set_dout_sram(&iv_seq[idx], ivgen_ctx->pool, CC_AES_IV_SIZE);
95 set_flow_mode(&iv_seq[idx], DIN_AES_DOUT);
96 idx++;
97
98 /* Generate IV pool */
99 hw_desc_init(&iv_seq[idx]);
100 set_din_const(&iv_seq[idx], 0, SSI_IVPOOL_SIZE);
101 set_dout_sram(&iv_seq[idx], ivgen_ctx->pool, SSI_IVPOOL_SIZE);
102 set_flow_mode(&iv_seq[idx], DIN_AES_DOUT);
103 idx++;
104
105 *iv_seq_len = idx; /* Update sequence length */
106
107 /* queue ordering assures pool readiness */
108 ivgen_ctx->next_iv_ofs = SSI_IVPOOL_META_SIZE;
109
110 return 0;
111 }
112
113 /*!
114 * Generates the initial pool in SRAM.
115 * This function should be invoked when resuming DX driver.
116 *
117 * \param drvdata
118 *
119 * \return int Zero for success, negative value otherwise.
120 */
ssi_ivgen_init_sram_pool(struct ssi_drvdata * drvdata)121 int ssi_ivgen_init_sram_pool(struct ssi_drvdata *drvdata)
122 {
123 struct ssi_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle;
124 struct cc_hw_desc iv_seq[SSI_IVPOOL_SEQ_LEN];
125 unsigned int iv_seq_len = 0;
126 int rc;
127
128 /* Generate initial enc. key/iv */
129 get_random_bytes(ivgen_ctx->pool_meta, SSI_IVPOOL_META_SIZE);
130
131 /* The first 32B reserved for the enc. Key/IV */
132 ivgen_ctx->ctr_key = ivgen_ctx->pool;
133 ivgen_ctx->ctr_iv = ivgen_ctx->pool + AES_KEYSIZE_128;
134
135 /* Copy initial enc. key and IV to SRAM at a single descriptor */
136 hw_desc_init(&iv_seq[iv_seq_len]);
137 set_din_type(&iv_seq[iv_seq_len], DMA_DLLI, ivgen_ctx->pool_meta_dma,
138 SSI_IVPOOL_META_SIZE, NS_BIT);
139 set_dout_sram(&iv_seq[iv_seq_len], ivgen_ctx->pool,
140 SSI_IVPOOL_META_SIZE);
141 set_flow_mode(&iv_seq[iv_seq_len], BYPASS);
142 iv_seq_len++;
143
144 /* Generate initial pool */
145 rc = ssi_ivgen_generate_pool(ivgen_ctx, iv_seq, &iv_seq_len);
146 if (unlikely(rc != 0))
147 return rc;
148
149 /* Fire-and-forget */
150 return send_request_init(drvdata, iv_seq, iv_seq_len);
151 }
152
153 /*!
154 * Free iv-pool and ivgen context.
155 *
156 * \param drvdata
157 */
ssi_ivgen_fini(struct ssi_drvdata * drvdata)158 void ssi_ivgen_fini(struct ssi_drvdata *drvdata)
159 {
160 struct ssi_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle;
161 struct device *device = &drvdata->plat_dev->dev;
162
163 if (!ivgen_ctx)
164 return;
165
166 if (ivgen_ctx->pool_meta) {
167 memset(ivgen_ctx->pool_meta, 0, SSI_IVPOOL_META_SIZE);
168 dma_free_coherent(device, SSI_IVPOOL_META_SIZE,
169 ivgen_ctx->pool_meta,
170 ivgen_ctx->pool_meta_dma);
171 }
172
173 ivgen_ctx->pool = NULL_SRAM_ADDR;
174
175 /* release "this" context */
176 kfree(ivgen_ctx);
177 }
178
179 /*!
180 * Allocates iv-pool and maps resources.
181 * This function generates the first IV pool.
182 *
183 * \param drvdata Driver's private context
184 *
185 * \return int Zero for success, negative value otherwise.
186 */
ssi_ivgen_init(struct ssi_drvdata * drvdata)187 int ssi_ivgen_init(struct ssi_drvdata *drvdata)
188 {
189 struct ssi_ivgen_ctx *ivgen_ctx;
190 struct device *device = &drvdata->plat_dev->dev;
191 int rc;
192
193 /* Allocate "this" context */
194 drvdata->ivgen_handle = kzalloc(sizeof(*drvdata->ivgen_handle),
195 GFP_KERNEL);
196 if (!drvdata->ivgen_handle) {
197 SSI_LOG_ERR("Not enough memory to allocate IVGEN context "
198 "(%zu B)\n", sizeof(*drvdata->ivgen_handle));
199 rc = -ENOMEM;
200 goto out;
201 }
202 ivgen_ctx = drvdata->ivgen_handle;
203
204 /* Allocate pool's header for intial enc. key/IV */
205 ivgen_ctx->pool_meta = dma_alloc_coherent(device, SSI_IVPOOL_META_SIZE,
206 &ivgen_ctx->pool_meta_dma,
207 GFP_KERNEL);
208 if (!ivgen_ctx->pool_meta) {
209 SSI_LOG_ERR("Not enough memory to allocate DMA of pool_meta "
210 "(%u B)\n", SSI_IVPOOL_META_SIZE);
211 rc = -ENOMEM;
212 goto out;
213 }
214 /* Allocate IV pool in SRAM */
215 ivgen_ctx->pool = ssi_sram_mgr_alloc(drvdata, SSI_IVPOOL_SIZE);
216 if (ivgen_ctx->pool == NULL_SRAM_ADDR) {
217 SSI_LOG_ERR("SRAM pool exhausted\n");
218 rc = -ENOMEM;
219 goto out;
220 }
221
222 return ssi_ivgen_init_sram_pool(drvdata);
223
224 out:
225 ssi_ivgen_fini(drvdata);
226 return rc;
227 }
228
229 /*!
230 * Acquires 16 Bytes IV from the iv-pool
231 *
232 * \param drvdata Driver private context
233 * \param iv_out_dma Array of physical IV out addresses
234 * \param iv_out_dma_len Length of iv_out_dma array (additional elements of iv_out_dma array are ignore)
235 * \param iv_out_size May be 8 or 16 bytes long
236 * \param iv_seq IN/OUT array to the descriptors sequence
237 * \param iv_seq_len IN/OUT pointer to the sequence length
238 *
239 * \return int Zero for success, negative value otherwise.
240 */
ssi_ivgen_getiv(struct ssi_drvdata * drvdata,dma_addr_t iv_out_dma[],unsigned int iv_out_dma_len,unsigned int iv_out_size,struct cc_hw_desc iv_seq[],unsigned int * iv_seq_len)241 int ssi_ivgen_getiv(
242 struct ssi_drvdata *drvdata,
243 dma_addr_t iv_out_dma[],
244 unsigned int iv_out_dma_len,
245 unsigned int iv_out_size,
246 struct cc_hw_desc iv_seq[],
247 unsigned int *iv_seq_len)
248 {
249 struct ssi_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle;
250 unsigned int idx = *iv_seq_len;
251 unsigned int t;
252
253 if ((iv_out_size != CC_AES_IV_SIZE) &&
254 (iv_out_size != CTR_RFC3686_IV_SIZE)) {
255 return -EINVAL;
256 }
257 if ((iv_out_dma_len + 1) > SSI_IVPOOL_SEQ_LEN) {
258 /* The sequence will be longer than allowed */
259 return -EINVAL;
260 }
261
262 //check that number of generated IV is limited to max dma address iv buffer size
263 if (iv_out_dma_len > SSI_MAX_IVGEN_DMA_ADDRESSES) {
264 /* The sequence will be longer than allowed */
265 return -EINVAL;
266 }
267
268 for (t = 0; t < iv_out_dma_len; t++) {
269 /* Acquire IV from pool */
270 hw_desc_init(&iv_seq[idx]);
271 set_din_sram(&iv_seq[idx], (ivgen_ctx->pool +
272 ivgen_ctx->next_iv_ofs),
273 iv_out_size);
274 set_dout_dlli(&iv_seq[idx], iv_out_dma[t], iv_out_size,
275 NS_BIT, 0);
276 set_flow_mode(&iv_seq[idx], BYPASS);
277 idx++;
278 }
279
280 /* Bypass operation is proceeded by crypto sequence, hence must
281 * assure bypass-write-transaction by a memory barrier
282 */
283 hw_desc_init(&iv_seq[idx]);
284 set_din_no_dma(&iv_seq[idx], 0, 0xfffff0);
285 set_dout_no_dma(&iv_seq[idx], 0, 0, 1);
286 idx++;
287
288 *iv_seq_len = idx; /* update seq length */
289
290 /* Update iv index */
291 ivgen_ctx->next_iv_ofs += iv_out_size;
292
293 if ((SSI_IVPOOL_SIZE - ivgen_ctx->next_iv_ofs) < CC_AES_IV_SIZE) {
294 SSI_LOG_DEBUG("Pool exhausted, regenerating iv-pool\n");
295 /* pool is drained -regenerate it! */
296 return ssi_ivgen_generate_pool(ivgen_ctx, iv_seq, iv_seq_len);
297 }
298
299 return 0;
300 }
301
302