1 /* 2 * Support for OmniVision OV2722 1080p HD camera sensor. 3 * 4 * Copyright (c) 2013 Intel Corporation. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License version 8 * 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 18 * 02110-1301, USA. 19 * 20 */ 21 22 #ifndef __OV2722_H__ 23 #define __OV2722_H__ 24 #include <linux/kernel.h> 25 #include <linux/types.h> 26 #include <linux/i2c.h> 27 #include <linux/delay.h> 28 #include <linux/videodev2.h> 29 #include <linux/spinlock.h> 30 #include <media/v4l2-subdev.h> 31 #include <media/v4l2-device.h> 32 #include <linux/v4l2-mediabus.h> 33 #include <media/media-entity.h> 34 #include <media/v4l2-ctrls.h> 35 36 #include "../include/linux/atomisp_platform.h" 37 38 #define OV2722_NAME "ov2722" 39 40 #define OV2722_POWER_UP_RETRY_NUM 5 41 42 /* Defines for register writes and register array processing */ 43 #define I2C_MSG_LENGTH 0x2 44 #define I2C_RETRY_COUNT 5 45 46 #define OV2722_FOCAL_LENGTH_NUM 278 /*2.78mm*/ 47 #define OV2722_FOCAL_LENGTH_DEM 100 48 #define OV2722_F_NUMBER_DEFAULT_NUM 26 49 #define OV2722_F_NUMBER_DEM 10 50 51 #define MAX_FMTS 1 52 53 /* 54 * focal length bits definition: 55 * bits 31-16: numerator, bits 15-0: denominator 56 */ 57 #define OV2722_FOCAL_LENGTH_DEFAULT 0x1160064 58 59 /* 60 * current f-number bits definition: 61 * bits 31-16: numerator, bits 15-0: denominator 62 */ 63 #define OV2722_F_NUMBER_DEFAULT 0x1a000a 64 65 /* 66 * f-number range bits definition: 67 * bits 31-24: max f-number numerator 68 * bits 23-16: max f-number denominator 69 * bits 15-8: min f-number numerator 70 * bits 7-0: min f-number denominator 71 */ 72 #define OV2722_F_NUMBER_RANGE 0x1a0a1a0a 73 #define OV2720_ID 0x2720 74 #define OV2722_ID 0x2722 75 76 #define OV2722_FINE_INTG_TIME_MIN 0 77 #define OV2722_FINE_INTG_TIME_MAX_MARGIN 0 78 #define OV2722_COARSE_INTG_TIME_MIN 1 79 #define OV2722_COARSE_INTG_TIME_MAX_MARGIN 4 80 81 /* 82 * OV2722 System control registers 83 */ 84 #define OV2722_SW_SLEEP 0x0100 85 #define OV2722_SW_RESET 0x0103 86 #define OV2722_SW_STREAM 0x0100 87 88 #define OV2722_SC_CMMN_CHIP_ID_H 0x300A 89 #define OV2722_SC_CMMN_CHIP_ID_L 0x300B 90 #define OV2722_SC_CMMN_SCCB_ID 0x300C 91 #define OV2722_SC_CMMN_SUB_ID 0x302A /* process, version*/ 92 93 #define OV2722_SC_CMMN_PAD_OEN0 0x3000 94 #define OV2722_SC_CMMN_PAD_OEN1 0x3001 95 #define OV2722_SC_CMMN_PAD_OEN2 0x3002 96 #define OV2722_SC_CMMN_PAD_OUT0 0x3008 97 #define OV2722_SC_CMMN_PAD_OUT1 0x3009 98 #define OV2722_SC_CMMN_PAD_OUT2 0x300D 99 #define OV2722_SC_CMMN_PAD_SEL0 0x300E 100 #define OV2722_SC_CMMN_PAD_SEL1 0x300F 101 #define OV2722_SC_CMMN_PAD_SEL2 0x3010 102 103 #define OV2722_SC_CMMN_PAD_PK 0x3011 104 #define OV2722_SC_CMMN_A_PWC_PK_O_13 0x3013 105 #define OV2722_SC_CMMN_A_PWC_PK_O_14 0x3014 106 107 #define OV2722_SC_CMMN_CLKRST0 0x301A 108 #define OV2722_SC_CMMN_CLKRST1 0x301B 109 #define OV2722_SC_CMMN_CLKRST2 0x301C 110 #define OV2722_SC_CMMN_CLKRST3 0x301D 111 #define OV2722_SC_CMMN_CLKRST4 0x301E 112 #define OV2722_SC_CMMN_CLKRST5 0x3005 113 #define OV2722_SC_CMMN_PCLK_DIV_CTRL 0x3007 114 #define OV2722_SC_CMMN_CLOCK_SEL 0x3020 115 #define OV2722_SC_SOC_CLKRST5 0x3040 116 117 #define OV2722_SC_CMMN_PLL_CTRL0 0x3034 118 #define OV2722_SC_CMMN_PLL_CTRL1 0x3035 119 #define OV2722_SC_CMMN_PLL_CTRL2 0x3039 120 #define OV2722_SC_CMMN_PLL_CTRL3 0x3037 121 #define OV2722_SC_CMMN_PLL_MULTIPLIER 0x3036 122 #define OV2722_SC_CMMN_PLL_DEBUG_OPT 0x3038 123 #define OV2722_SC_CMMN_PLLS_CTRL0 0x303A 124 #define OV2722_SC_CMMN_PLLS_CTRL1 0x303B 125 #define OV2722_SC_CMMN_PLLS_CTRL2 0x303C 126 #define OV2722_SC_CMMN_PLLS_CTRL3 0x303D 127 128 #define OV2722_SC_CMMN_MIPI_PHY_16 0x3016 129 #define OV2722_SC_CMMN_MIPI_PHY_17 0x3017 130 #define OV2722_SC_CMMN_MIPI_SC_CTRL_18 0x3018 131 #define OV2722_SC_CMMN_MIPI_SC_CTRL_19 0x3019 132 #define OV2722_SC_CMMN_MIPI_SC_CTRL_21 0x3021 133 #define OV2722_SC_CMMN_MIPI_SC_CTRL_22 0x3022 134 135 #define OV2722_AEC_PK_EXPO_H 0x3500 136 #define OV2722_AEC_PK_EXPO_M 0x3501 137 #define OV2722_AEC_PK_EXPO_L 0x3502 138 #define OV2722_AEC_MANUAL_CTRL 0x3503 139 #define OV2722_AGC_ADJ_H 0x3508 140 #define OV2722_AGC_ADJ_L 0x3509 141 #define OV2722_VTS_DIFF_H 0x350c 142 #define OV2722_VTS_DIFF_L 0x350d 143 #define OV2722_GROUP_ACCESS 0x3208 144 #define OV2722_HTS_H 0x380c 145 #define OV2722_HTS_L 0x380d 146 #define OV2722_VTS_H 0x380e 147 #define OV2722_VTS_L 0x380f 148 149 #define OV2722_MWB_GAIN_R_H 0x5186 150 #define OV2722_MWB_GAIN_R_L 0x5187 151 #define OV2722_MWB_GAIN_G_H 0x5188 152 #define OV2722_MWB_GAIN_G_L 0x5189 153 #define OV2722_MWB_GAIN_B_H 0x518a 154 #define OV2722_MWB_GAIN_B_L 0x518b 155 156 #define OV2722_H_CROP_START_H 0x3800 157 #define OV2722_H_CROP_START_L 0x3801 158 #define OV2722_V_CROP_START_H 0x3802 159 #define OV2722_V_CROP_START_L 0x3803 160 #define OV2722_H_CROP_END_H 0x3804 161 #define OV2722_H_CROP_END_L 0x3805 162 #define OV2722_V_CROP_END_H 0x3806 163 #define OV2722_V_CROP_END_L 0x3807 164 #define OV2722_H_OUTSIZE_H 0x3808 165 #define OV2722_H_OUTSIZE_L 0x3809 166 #define OV2722_V_OUTSIZE_H 0x380a 167 #define OV2722_V_OUTSIZE_L 0x380b 168 169 #define OV2722_START_STREAMING 0x01 170 #define OV2722_STOP_STREAMING 0x00 171 172 struct regval_list { 173 u16 reg_num; 174 u8 value; 175 }; 176 177 struct ov2722_resolution { 178 u8 *desc; 179 const struct ov2722_reg *regs; 180 int res; 181 int width; 182 int height; 183 int fps; 184 int pix_clk_freq; 185 u32 skip_frames; 186 u16 pixels_per_line; 187 u16 lines_per_frame; 188 u8 bin_factor_x; 189 u8 bin_factor_y; 190 u8 bin_mode; 191 bool used; 192 int mipi_freq; 193 }; 194 195 struct ov2722_format { 196 u8 *desc; 197 u32 pixelformat; 198 struct ov2722_reg *regs; 199 }; 200 201 /* 202 * ov2722 device structure. 203 */ 204 struct ov2722_device { 205 struct v4l2_subdev sd; 206 struct media_pad pad; 207 struct v4l2_mbus_framefmt format; 208 struct mutex input_lock; 209 210 struct camera_sensor_platform_data *platform_data; 211 int vt_pix_clk_freq_mhz; 212 int fmt_idx; 213 int run_mode; 214 u16 pixels_per_line; 215 u16 lines_per_frame; 216 u8 res; 217 u8 type; 218 219 struct v4l2_ctrl_handler ctrl_handler; 220 struct v4l2_ctrl *link_freq; 221 }; 222 223 enum ov2722_tok_type { 224 OV2722_8BIT = 0x0001, 225 OV2722_16BIT = 0x0002, 226 OV2722_32BIT = 0x0004, 227 OV2722_TOK_TERM = 0xf000, /* terminating token for reg list */ 228 OV2722_TOK_DELAY = 0xfe00, /* delay token for reg list */ 229 OV2722_TOK_MASK = 0xfff0 230 }; 231 232 /** 233 * struct ov2722_reg - MI sensor register format 234 * @type: type of the register 235 * @reg: 16-bit offset to register 236 * @val: 8/16/32-bit register value 237 * 238 * Define a structure for sensor register initialization values 239 */ 240 struct ov2722_reg { 241 enum ov2722_tok_type type; 242 u16 reg; 243 u32 val; /* @set value for read/mod/write, @mask */ 244 }; 245 246 #define to_ov2722_sensor(x) container_of(x, struct ov2722_device, sd) 247 248 #define OV2722_MAX_WRITE_BUF_SIZE 30 249 250 struct ov2722_write_buffer { 251 u16 addr; 252 u8 data[OV2722_MAX_WRITE_BUF_SIZE]; 253 }; 254 255 struct ov2722_write_ctrl { 256 int index; 257 struct ov2722_write_buffer buffer; 258 }; 259 260 static const struct i2c_device_id ov2722_id[] = { 261 {OV2722_NAME, 0}, 262 {} 263 }; 264 265 /* 266 * Register settings for various resolution 267 */ 268 static struct ov2722_reg const ov2722_QVGA_30fps[] = { 269 {OV2722_8BIT, 0x3718, 0x10}, 270 {OV2722_8BIT, 0x3702, 0x0c}, 271 {OV2722_8BIT, 0x373a, 0x1c}, 272 {OV2722_8BIT, 0x3715, 0x01}, 273 {OV2722_8BIT, 0x3703, 0x0c}, 274 {OV2722_8BIT, 0x3705, 0x06}, 275 {OV2722_8BIT, 0x3730, 0x0e}, 276 {OV2722_8BIT, 0x3704, 0x1c}, 277 {OV2722_8BIT, 0x3f06, 0x00}, 278 {OV2722_8BIT, 0x371c, 0x00}, 279 {OV2722_8BIT, 0x371d, 0x46}, 280 {OV2722_8BIT, 0x371e, 0x00}, 281 {OV2722_8BIT, 0x371f, 0x63}, 282 {OV2722_8BIT, 0x3708, 0x61}, 283 {OV2722_8BIT, 0x3709, 0x12}, 284 {OV2722_8BIT, 0x3800, 0x01}, 285 {OV2722_8BIT, 0x3801, 0x42}, /* H crop start: 322 */ 286 {OV2722_8BIT, 0x3802, 0x00}, 287 {OV2722_8BIT, 0x3803, 0x20}, /* V crop start: 32 */ 288 {OV2722_8BIT, 0x3804, 0x06}, 289 {OV2722_8BIT, 0x3805, 0x95}, /* H crop end: 1685 */ 290 {OV2722_8BIT, 0x3806, 0x04}, 291 {OV2722_8BIT, 0x3807, 0x27}, /* V crop end: 1063 */ 292 {OV2722_8BIT, 0x3808, 0x01}, 293 {OV2722_8BIT, 0x3809, 0x50}, /* H output size: 336 */ 294 {OV2722_8BIT, 0x380a, 0x01}, 295 {OV2722_8BIT, 0x380b, 0x00}, /* V output size: 256 */ 296 297 /* H blank timing */ 298 {OV2722_8BIT, 0x380c, 0x08}, 299 {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ 300 {OV2722_8BIT, 0x380e, 0x04}, 301 {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ 302 {OV2722_8BIT, 0x3810, 0x00}, 303 {OV2722_8BIT, 0x3811, 0x04}, /* H window offset: 5 */ 304 {OV2722_8BIT, 0x3812, 0x00}, 305 {OV2722_8BIT, 0x3813, 0x01}, /* V window offset: 2 */ 306 {OV2722_8BIT, 0x3820, 0xc0}, 307 {OV2722_8BIT, 0x3821, 0x06}, /* flip isp*/ 308 {OV2722_8BIT, 0x3814, 0x71}, 309 {OV2722_8BIT, 0x3815, 0x71}, 310 {OV2722_8BIT, 0x3612, 0x49}, 311 {OV2722_8BIT, 0x3618, 0x00}, 312 {OV2722_8BIT, 0x3a08, 0x01}, 313 {OV2722_8BIT, 0x3a09, 0xc3}, 314 {OV2722_8BIT, 0x3a0a, 0x01}, 315 {OV2722_8BIT, 0x3a0b, 0x77}, 316 {OV2722_8BIT, 0x3a0d, 0x00}, 317 {OV2722_8BIT, 0x3a0e, 0x00}, 318 {OV2722_8BIT, 0x4520, 0x09}, 319 {OV2722_8BIT, 0x4837, 0x1b}, 320 {OV2722_8BIT, 0x3000, 0xff}, 321 {OV2722_8BIT, 0x3001, 0xff}, 322 {OV2722_8BIT, 0x3002, 0xf0}, 323 {OV2722_8BIT, 0x3600, 0x08}, 324 {OV2722_8BIT, 0x3621, 0xc0}, 325 {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ 326 {OV2722_8BIT, 0x3633, 0x63}, 327 {OV2722_8BIT, 0x3634, 0x24}, 328 {OV2722_8BIT, 0x3f01, 0x0c}, 329 {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ 330 {OV2722_8BIT, 0x3614, 0xf0}, 331 {OV2722_8BIT, 0x3630, 0x2d}, 332 {OV2722_8BIT, 0x370b, 0x62}, 333 {OV2722_8BIT, 0x3706, 0x61}, 334 {OV2722_8BIT, 0x4000, 0x02}, 335 {OV2722_8BIT, 0x4002, 0xc5}, 336 {OV2722_8BIT, 0x4005, 0x08}, 337 {OV2722_8BIT, 0x404f, 0x84}, 338 {OV2722_8BIT, 0x4051, 0x00}, 339 {OV2722_8BIT, 0x5000, 0xff}, 340 {OV2722_8BIT, 0x3a18, 0x00}, 341 {OV2722_8BIT, 0x3a19, 0x80}, 342 {OV2722_8BIT, 0x4521, 0x00}, 343 {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ 344 {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ 345 {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ 346 {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ 347 {OV2722_8BIT, 0x370c, 0x0c}, 348 {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ 349 {OV2722_8BIT, 0x3035, 0x00}, 350 {OV2722_8BIT, 0x3036, 0x26}, 351 {OV2722_8BIT, 0x3037, 0xa1}, 352 {OV2722_8BIT, 0x303e, 0x19}, 353 {OV2722_8BIT, 0x3038, 0x06}, 354 {OV2722_8BIT, 0x3018, 0x04}, 355 356 /* Added for power optimization */ 357 {OV2722_8BIT, 0x3000, 0x00}, 358 {OV2722_8BIT, 0x3001, 0x00}, 359 {OV2722_8BIT, 0x3002, 0x00}, 360 {OV2722_8BIT, 0x3a0f, 0x40}, 361 {OV2722_8BIT, 0x3a10, 0x38}, 362 {OV2722_8BIT, 0x3a1b, 0x48}, 363 {OV2722_8BIT, 0x3a1e, 0x30}, 364 {OV2722_8BIT, 0x3a11, 0x90}, 365 {OV2722_8BIT, 0x3a1f, 0x10}, 366 {OV2722_8BIT, 0x3011, 0x22}, 367 {OV2722_8BIT, 0x3a00, 0x58}, 368 {OV2722_8BIT, 0x3503, 0x17}, 369 {OV2722_8BIT, 0x3500, 0x00}, 370 {OV2722_8BIT, 0x3501, 0x46}, 371 {OV2722_8BIT, 0x3502, 0x00}, 372 {OV2722_8BIT, 0x3508, 0x00}, 373 {OV2722_8BIT, 0x3509, 0x10}, 374 {OV2722_TOK_TERM, 0, 0}, 375 376 }; 377 378 static struct ov2722_reg const ov2722_480P_30fps[] = { 379 {OV2722_8BIT, 0x3718, 0x10}, 380 {OV2722_8BIT, 0x3702, 0x18}, 381 {OV2722_8BIT, 0x373a, 0x3c}, 382 {OV2722_8BIT, 0x3715, 0x01}, 383 {OV2722_8BIT, 0x3703, 0x1d}, 384 {OV2722_8BIT, 0x3705, 0x12}, 385 {OV2722_8BIT, 0x3730, 0x1f}, 386 {OV2722_8BIT, 0x3704, 0x3f}, 387 {OV2722_8BIT, 0x3f06, 0x1d}, 388 {OV2722_8BIT, 0x371c, 0x00}, 389 {OV2722_8BIT, 0x371d, 0x83}, 390 {OV2722_8BIT, 0x371e, 0x00}, 391 {OV2722_8BIT, 0x371f, 0xbd}, 392 {OV2722_8BIT, 0x3708, 0x63}, 393 {OV2722_8BIT, 0x3709, 0x52}, 394 {OV2722_8BIT, 0x3800, 0x00}, 395 {OV2722_8BIT, 0x3801, 0xf2}, /* H crop start: 322 - 80 = 242*/ 396 {OV2722_8BIT, 0x3802, 0x00}, 397 {OV2722_8BIT, 0x3803, 0x20}, /* V crop start: 32*/ 398 {OV2722_8BIT, 0x3804, 0x06}, 399 {OV2722_8BIT, 0x3805, 0xBB}, /* H crop end: 1643 + 80 = 1723*/ 400 {OV2722_8BIT, 0x3806, 0x04}, 401 {OV2722_8BIT, 0x3807, 0x03}, /* V crop end: 1027*/ 402 {OV2722_8BIT, 0x3808, 0x02}, 403 {OV2722_8BIT, 0x3809, 0xE0}, /* H output size: 656 +80 = 736*/ 404 {OV2722_8BIT, 0x380a, 0x01}, 405 {OV2722_8BIT, 0x380b, 0xF0}, /* V output size: 496 */ 406 407 /* H blank timing */ 408 {OV2722_8BIT, 0x380c, 0x08}, 409 {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ 410 {OV2722_8BIT, 0x380e, 0x04}, 411 {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ 412 {OV2722_8BIT, 0x3810, 0x00}, 413 {OV2722_8BIT, 0x3811, 0x04}, /* H window offset: 5 */ 414 {OV2722_8BIT, 0x3812, 0x00}, 415 {OV2722_8BIT, 0x3813, 0x01}, /* V window offset: 2 */ 416 {OV2722_8BIT, 0x3820, 0x80}, 417 {OV2722_8BIT, 0x3821, 0x06}, /* flip isp*/ 418 {OV2722_8BIT, 0x3814, 0x31}, 419 {OV2722_8BIT, 0x3815, 0x31}, 420 {OV2722_8BIT, 0x3612, 0x4b}, 421 {OV2722_8BIT, 0x3618, 0x04}, 422 {OV2722_8BIT, 0x3a08, 0x02}, 423 {OV2722_8BIT, 0x3a09, 0x67}, 424 {OV2722_8BIT, 0x3a0a, 0x02}, 425 {OV2722_8BIT, 0x3a0b, 0x00}, 426 {OV2722_8BIT, 0x3a0d, 0x00}, 427 {OV2722_8BIT, 0x3a0e, 0x00}, 428 {OV2722_8BIT, 0x4520, 0x0a}, 429 {OV2722_8BIT, 0x4837, 0x1b}, 430 {OV2722_8BIT, 0x3000, 0xff}, 431 {OV2722_8BIT, 0x3001, 0xff}, 432 {OV2722_8BIT, 0x3002, 0xf0}, 433 {OV2722_8BIT, 0x3600, 0x08}, 434 {OV2722_8BIT, 0x3621, 0xc0}, 435 {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ 436 {OV2722_8BIT, 0x3633, 0x63}, 437 {OV2722_8BIT, 0x3634, 0x24}, 438 {OV2722_8BIT, 0x3f01, 0x0c}, 439 {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ 440 {OV2722_8BIT, 0x3614, 0xf0}, 441 {OV2722_8BIT, 0x3630, 0x2d}, 442 {OV2722_8BIT, 0x370b, 0x62}, 443 {OV2722_8BIT, 0x3706, 0x61}, 444 {OV2722_8BIT, 0x4000, 0x02}, 445 {OV2722_8BIT, 0x4002, 0xc5}, 446 {OV2722_8BIT, 0x4005, 0x08}, 447 {OV2722_8BIT, 0x404f, 0x84}, 448 {OV2722_8BIT, 0x4051, 0x00}, 449 {OV2722_8BIT, 0x5000, 0xff}, 450 {OV2722_8BIT, 0x3a18, 0x00}, 451 {OV2722_8BIT, 0x3a19, 0x80}, 452 {OV2722_8BIT, 0x4521, 0x00}, 453 {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ 454 {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ 455 {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ 456 {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ 457 {OV2722_8BIT, 0x370c, 0x0c}, 458 {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ 459 {OV2722_8BIT, 0x3035, 0x00}, 460 {OV2722_8BIT, 0x3036, 0x26}, 461 {OV2722_8BIT, 0x3037, 0xa1}, 462 {OV2722_8BIT, 0x303e, 0x19}, 463 {OV2722_8BIT, 0x3038, 0x06}, 464 {OV2722_8BIT, 0x3018, 0x04}, 465 466 /* Added for power optimization */ 467 {OV2722_8BIT, 0x3000, 0x00}, 468 {OV2722_8BIT, 0x3001, 0x00}, 469 {OV2722_8BIT, 0x3002, 0x00}, 470 {OV2722_8BIT, 0x3a0f, 0x40}, 471 {OV2722_8BIT, 0x3a10, 0x38}, 472 {OV2722_8BIT, 0x3a1b, 0x48}, 473 {OV2722_8BIT, 0x3a1e, 0x30}, 474 {OV2722_8BIT, 0x3a11, 0x90}, 475 {OV2722_8BIT, 0x3a1f, 0x10}, 476 {OV2722_8BIT, 0x3011, 0x22}, 477 {OV2722_8BIT, 0x3a00, 0x58}, 478 {OV2722_8BIT, 0x3503, 0x17}, 479 {OV2722_8BIT, 0x3500, 0x00}, 480 {OV2722_8BIT, 0x3501, 0x46}, 481 {OV2722_8BIT, 0x3502, 0x00}, 482 {OV2722_8BIT, 0x3508, 0x00}, 483 {OV2722_8BIT, 0x3509, 0x10}, 484 {OV2722_TOK_TERM, 0, 0}, 485 }; 486 487 static struct ov2722_reg const ov2722_VGA_30fps[] = { 488 {OV2722_8BIT, 0x3718, 0x10}, 489 {OV2722_8BIT, 0x3702, 0x18}, 490 {OV2722_8BIT, 0x373a, 0x3c}, 491 {OV2722_8BIT, 0x3715, 0x01}, 492 {OV2722_8BIT, 0x3703, 0x1d}, 493 {OV2722_8BIT, 0x3705, 0x12}, 494 {OV2722_8BIT, 0x3730, 0x1f}, 495 {OV2722_8BIT, 0x3704, 0x3f}, 496 {OV2722_8BIT, 0x3f06, 0x1d}, 497 {OV2722_8BIT, 0x371c, 0x00}, 498 {OV2722_8BIT, 0x371d, 0x83}, 499 {OV2722_8BIT, 0x371e, 0x00}, 500 {OV2722_8BIT, 0x371f, 0xbd}, 501 {OV2722_8BIT, 0x3708, 0x63}, 502 {OV2722_8BIT, 0x3709, 0x52}, 503 {OV2722_8BIT, 0x3800, 0x01}, 504 {OV2722_8BIT, 0x3801, 0x42}, /* H crop start: 322 */ 505 {OV2722_8BIT, 0x3802, 0x00}, 506 {OV2722_8BIT, 0x3803, 0x20}, /* V crop start: 32*/ 507 {OV2722_8BIT, 0x3804, 0x06}, 508 {OV2722_8BIT, 0x3805, 0x6B}, /* H crop end: 1643*/ 509 {OV2722_8BIT, 0x3806, 0x04}, 510 {OV2722_8BIT, 0x3807, 0x03}, /* V crop end: 1027*/ 511 {OV2722_8BIT, 0x3808, 0x02}, 512 {OV2722_8BIT, 0x3809, 0x90}, /* H output size: 656 */ 513 {OV2722_8BIT, 0x380a, 0x01}, 514 {OV2722_8BIT, 0x380b, 0xF0}, /* V output size: 496 */ 515 516 /* H blank timing */ 517 {OV2722_8BIT, 0x380c, 0x08}, 518 {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ 519 {OV2722_8BIT, 0x380e, 0x04}, 520 {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ 521 {OV2722_8BIT, 0x3810, 0x00}, 522 {OV2722_8BIT, 0x3811, 0x04}, /* H window offset: 5 */ 523 {OV2722_8BIT, 0x3812, 0x00}, 524 {OV2722_8BIT, 0x3813, 0x01}, /* V window offset: 2 */ 525 {OV2722_8BIT, 0x3820, 0x80}, 526 {OV2722_8BIT, 0x3821, 0x06}, /* flip isp*/ 527 {OV2722_8BIT, 0x3814, 0x31}, 528 {OV2722_8BIT, 0x3815, 0x31}, 529 {OV2722_8BIT, 0x3612, 0x4b}, 530 {OV2722_8BIT, 0x3618, 0x04}, 531 {OV2722_8BIT, 0x3a08, 0x02}, 532 {OV2722_8BIT, 0x3a09, 0x67}, 533 {OV2722_8BIT, 0x3a0a, 0x02}, 534 {OV2722_8BIT, 0x3a0b, 0x00}, 535 {OV2722_8BIT, 0x3a0d, 0x00}, 536 {OV2722_8BIT, 0x3a0e, 0x00}, 537 {OV2722_8BIT, 0x4520, 0x0a}, 538 {OV2722_8BIT, 0x4837, 0x29}, 539 {OV2722_8BIT, 0x3000, 0xff}, 540 {OV2722_8BIT, 0x3001, 0xff}, 541 {OV2722_8BIT, 0x3002, 0xf0}, 542 {OV2722_8BIT, 0x3600, 0x08}, 543 {OV2722_8BIT, 0x3621, 0xc0}, 544 {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ 545 {OV2722_8BIT, 0x3633, 0x63}, 546 {OV2722_8BIT, 0x3634, 0x24}, 547 {OV2722_8BIT, 0x3f01, 0x0c}, 548 {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ 549 {OV2722_8BIT, 0x3614, 0xf0}, 550 {OV2722_8BIT, 0x3630, 0x2d}, 551 {OV2722_8BIT, 0x370b, 0x62}, 552 {OV2722_8BIT, 0x3706, 0x61}, 553 {OV2722_8BIT, 0x4000, 0x02}, 554 {OV2722_8BIT, 0x4002, 0xc5}, 555 {OV2722_8BIT, 0x4005, 0x08}, 556 {OV2722_8BIT, 0x404f, 0x84}, 557 {OV2722_8BIT, 0x4051, 0x00}, 558 {OV2722_8BIT, 0x5000, 0xff}, 559 {OV2722_8BIT, 0x3a18, 0x00}, 560 {OV2722_8BIT, 0x3a19, 0x80}, 561 {OV2722_8BIT, 0x4521, 0x00}, 562 {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ 563 {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ 564 {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ 565 {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ 566 {OV2722_8BIT, 0x370c, 0x0c}, 567 {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ 568 {OV2722_8BIT, 0x3035, 0x00}, 569 {OV2722_8BIT, 0x3036, 0x26}, 570 {OV2722_8BIT, 0x3037, 0xa1}, 571 {OV2722_8BIT, 0x303e, 0x19}, 572 {OV2722_8BIT, 0x3038, 0x06}, 573 {OV2722_8BIT, 0x3018, 0x04}, 574 575 /* Added for power optimization */ 576 {OV2722_8BIT, 0x3000, 0x00}, 577 {OV2722_8BIT, 0x3001, 0x00}, 578 {OV2722_8BIT, 0x3002, 0x00}, 579 {OV2722_8BIT, 0x3a0f, 0x40}, 580 {OV2722_8BIT, 0x3a10, 0x38}, 581 {OV2722_8BIT, 0x3a1b, 0x48}, 582 {OV2722_8BIT, 0x3a1e, 0x30}, 583 {OV2722_8BIT, 0x3a11, 0x90}, 584 {OV2722_8BIT, 0x3a1f, 0x10}, 585 {OV2722_8BIT, 0x3011, 0x22}, 586 {OV2722_8BIT, 0x3a00, 0x58}, 587 {OV2722_8BIT, 0x3503, 0x17}, 588 {OV2722_8BIT, 0x3500, 0x00}, 589 {OV2722_8BIT, 0x3501, 0x46}, 590 {OV2722_8BIT, 0x3502, 0x00}, 591 {OV2722_8BIT, 0x3508, 0x00}, 592 {OV2722_8BIT, 0x3509, 0x10}, 593 {OV2722_TOK_TERM, 0, 0}, 594 }; 595 596 static struct ov2722_reg const ov2722_1632_1092_30fps[] = { 597 {OV2722_8BIT, 0x3021, 0x03}, /* For stand wait for 598 a whole frame complete.(vblank) */ 599 {OV2722_8BIT, 0x3718, 0x10}, 600 {OV2722_8BIT, 0x3702, 0x24}, 601 {OV2722_8BIT, 0x373a, 0x60}, 602 {OV2722_8BIT, 0x3715, 0x01}, 603 {OV2722_8BIT, 0x3703, 0x2e}, 604 {OV2722_8BIT, 0x3705, 0x10}, 605 {OV2722_8BIT, 0x3730, 0x30}, 606 {OV2722_8BIT, 0x3704, 0x62}, 607 {OV2722_8BIT, 0x3f06, 0x3a}, 608 {OV2722_8BIT, 0x371c, 0x00}, 609 {OV2722_8BIT, 0x371d, 0xc4}, 610 {OV2722_8BIT, 0x371e, 0x01}, 611 {OV2722_8BIT, 0x371f, 0x0d}, 612 {OV2722_8BIT, 0x3708, 0x61}, 613 {OV2722_8BIT, 0x3709, 0x12}, 614 {OV2722_8BIT, 0x3800, 0x00}, 615 {OV2722_8BIT, 0x3801, 0x9E}, /* H crop start: 158 */ 616 {OV2722_8BIT, 0x3802, 0x00}, 617 {OV2722_8BIT, 0x3803, 0x01}, /* V crop start: 1 */ 618 {OV2722_8BIT, 0x3804, 0x07}, 619 {OV2722_8BIT, 0x3805, 0x05}, /* H crop end: 1797 */ 620 {OV2722_8BIT, 0x3806, 0x04}, 621 {OV2722_8BIT, 0x3807, 0x45}, /* V crop end: 1093 */ 622 623 {OV2722_8BIT, 0x3808, 0x06}, 624 {OV2722_8BIT, 0x3809, 0x60}, /* H output size: 1632 */ 625 {OV2722_8BIT, 0x380a, 0x04}, 626 {OV2722_8BIT, 0x380b, 0x44}, /* V output size: 1092 */ 627 {OV2722_8BIT, 0x380c, 0x08}, 628 {OV2722_8BIT, 0x380d, 0xd4}, /* H timing: 2260 */ 629 {OV2722_8BIT, 0x380e, 0x04}, 630 {OV2722_8BIT, 0x380f, 0xdc}, /* V timing: 1244 */ 631 {OV2722_8BIT, 0x3810, 0x00}, 632 {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ 633 {OV2722_8BIT, 0x3812, 0x00}, 634 {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ 635 {OV2722_8BIT, 0x3820, 0x80}, 636 {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ 637 {OV2722_8BIT, 0x3814, 0x11}, 638 {OV2722_8BIT, 0x3815, 0x11}, 639 {OV2722_8BIT, 0x3612, 0x0b}, 640 {OV2722_8BIT, 0x3618, 0x04}, 641 {OV2722_8BIT, 0x3a08, 0x01}, 642 {OV2722_8BIT, 0x3a09, 0x50}, 643 {OV2722_8BIT, 0x3a0a, 0x01}, 644 {OV2722_8BIT, 0x3a0b, 0x18}, 645 {OV2722_8BIT, 0x3a0d, 0x03}, 646 {OV2722_8BIT, 0x3a0e, 0x03}, 647 {OV2722_8BIT, 0x4520, 0x00}, 648 {OV2722_8BIT, 0x4837, 0x1b}, 649 {OV2722_8BIT, 0x3600, 0x08}, 650 {OV2722_8BIT, 0x3621, 0xc0}, 651 {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ 652 {OV2722_8BIT, 0x3633, 0x23}, 653 {OV2722_8BIT, 0x3634, 0x54}, 654 {OV2722_8BIT, 0x3f01, 0x0c}, 655 {OV2722_8BIT, 0x5001, 0xc1}, 656 {OV2722_8BIT, 0x3614, 0xf0}, 657 {OV2722_8BIT, 0x3630, 0x2d}, 658 {OV2722_8BIT, 0x370b, 0x62}, 659 {OV2722_8BIT, 0x3706, 0x61}, 660 {OV2722_8BIT, 0x4000, 0x02}, 661 {OV2722_8BIT, 0x4002, 0xc5}, 662 {OV2722_8BIT, 0x4005, 0x08}, 663 {OV2722_8BIT, 0x404f, 0x84}, 664 {OV2722_8BIT, 0x4051, 0x00}, 665 {OV2722_8BIT, 0x5000, 0xcf}, /* manual 3a */ 666 {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ 667 {OV2722_8BIT, 0x3a18, 0x00}, 668 {OV2722_8BIT, 0x3a19, 0x80}, 669 {OV2722_8BIT, 0x4521, 0x00}, 670 {OV2722_8BIT, 0x5183, 0xb0}, 671 {OV2722_8BIT, 0x5184, 0xb0}, 672 {OV2722_8BIT, 0x5185, 0xb0}, 673 {OV2722_8BIT, 0x370c, 0x0c}, 674 {OV2722_8BIT, 0x3035, 0x00}, 675 {OV2722_8BIT, 0x3036, 0x2c}, /* 422.4 MHz */ 676 {OV2722_8BIT, 0x3037, 0xa1}, 677 {OV2722_8BIT, 0x303e, 0x19}, 678 {OV2722_8BIT, 0x3038, 0x06}, 679 {OV2722_8BIT, 0x3018, 0x04}, 680 {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ 681 {OV2722_8BIT, 0x3001, 0x00}, 682 {OV2722_8BIT, 0x3002, 0x00}, 683 {OV2722_8BIT, 0x3a0f, 0x40}, 684 {OV2722_8BIT, 0x3a10, 0x38}, 685 {OV2722_8BIT, 0x3a1b, 0x48}, 686 {OV2722_8BIT, 0x3a1e, 0x30}, 687 {OV2722_8BIT, 0x3a11, 0x90}, 688 {OV2722_8BIT, 0x3a1f, 0x10}, 689 {OV2722_8BIT, 0x3503, 0x17}, /* manual 3a */ 690 {OV2722_8BIT, 0x3500, 0x00}, 691 {OV2722_8BIT, 0x3501, 0x3F}, 692 {OV2722_8BIT, 0x3502, 0x00}, 693 {OV2722_8BIT, 0x3508, 0x00}, 694 {OV2722_8BIT, 0x3509, 0x00}, 695 {OV2722_TOK_TERM, 0, 0} 696 }; 697 698 static struct ov2722_reg const ov2722_1452_1092_30fps[] = { 699 {OV2722_8BIT, 0x3021, 0x03}, /* For stand wait for 700 a whole frame complete.(vblank) */ 701 {OV2722_8BIT, 0x3718, 0x10}, 702 {OV2722_8BIT, 0x3702, 0x24}, 703 {OV2722_8BIT, 0x373a, 0x60}, 704 {OV2722_8BIT, 0x3715, 0x01}, 705 {OV2722_8BIT, 0x3703, 0x2e}, 706 {OV2722_8BIT, 0x3705, 0x10}, 707 {OV2722_8BIT, 0x3730, 0x30}, 708 {OV2722_8BIT, 0x3704, 0x62}, 709 {OV2722_8BIT, 0x3f06, 0x3a}, 710 {OV2722_8BIT, 0x371c, 0x00}, 711 {OV2722_8BIT, 0x371d, 0xc4}, 712 {OV2722_8BIT, 0x371e, 0x01}, 713 {OV2722_8BIT, 0x371f, 0x0d}, 714 {OV2722_8BIT, 0x3708, 0x61}, 715 {OV2722_8BIT, 0x3709, 0x12}, 716 {OV2722_8BIT, 0x3800, 0x00}, 717 {OV2722_8BIT, 0x3801, 0xF8}, /* H crop start: 248 */ 718 {OV2722_8BIT, 0x3802, 0x00}, 719 {OV2722_8BIT, 0x3803, 0x01}, /* V crop start: 1 */ 720 {OV2722_8BIT, 0x3804, 0x06}, 721 {OV2722_8BIT, 0x3805, 0xab}, /* H crop end: 1707 */ 722 {OV2722_8BIT, 0x3806, 0x04}, 723 {OV2722_8BIT, 0x3807, 0x45}, /* V crop end: 1093 */ 724 {OV2722_8BIT, 0x3808, 0x05}, 725 {OV2722_8BIT, 0x3809, 0xac}, /* H output size: 1452 */ 726 {OV2722_8BIT, 0x380a, 0x04}, 727 {OV2722_8BIT, 0x380b, 0x44}, /* V output size: 1092 */ 728 {OV2722_8BIT, 0x380c, 0x08}, 729 {OV2722_8BIT, 0x380d, 0xd4}, /* H timing: 2260 */ 730 {OV2722_8BIT, 0x380e, 0x04}, 731 {OV2722_8BIT, 0x380f, 0xdc}, /* V timing: 1244 */ 732 {OV2722_8BIT, 0x3810, 0x00}, 733 {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ 734 {OV2722_8BIT, 0x3812, 0x00}, 735 {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ 736 {OV2722_8BIT, 0x3820, 0x80}, 737 {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ 738 {OV2722_8BIT, 0x3814, 0x11}, 739 {OV2722_8BIT, 0x3815, 0x11}, 740 {OV2722_8BIT, 0x3612, 0x0b}, 741 {OV2722_8BIT, 0x3618, 0x04}, 742 {OV2722_8BIT, 0x3a08, 0x01}, 743 {OV2722_8BIT, 0x3a09, 0x50}, 744 {OV2722_8BIT, 0x3a0a, 0x01}, 745 {OV2722_8BIT, 0x3a0b, 0x18}, 746 {OV2722_8BIT, 0x3a0d, 0x03}, 747 {OV2722_8BIT, 0x3a0e, 0x03}, 748 {OV2722_8BIT, 0x4520, 0x00}, 749 {OV2722_8BIT, 0x4837, 0x1b}, 750 {OV2722_8BIT, 0x3600, 0x08}, 751 {OV2722_8BIT, 0x3621, 0xc0}, 752 {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ 753 {OV2722_8BIT, 0x3633, 0x23}, 754 {OV2722_8BIT, 0x3634, 0x54}, 755 {OV2722_8BIT, 0x3f01, 0x0c}, 756 {OV2722_8BIT, 0x5001, 0xc1}, 757 {OV2722_8BIT, 0x3614, 0xf0}, 758 {OV2722_8BIT, 0x3630, 0x2d}, 759 {OV2722_8BIT, 0x370b, 0x62}, 760 {OV2722_8BIT, 0x3706, 0x61}, 761 {OV2722_8BIT, 0x4000, 0x02}, 762 {OV2722_8BIT, 0x4002, 0xc5}, 763 {OV2722_8BIT, 0x4005, 0x08}, 764 {OV2722_8BIT, 0x404f, 0x84}, 765 {OV2722_8BIT, 0x4051, 0x00}, 766 {OV2722_8BIT, 0x5000, 0xcf}, /* manual 3a */ 767 {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ 768 {OV2722_8BIT, 0x3a18, 0x00}, 769 {OV2722_8BIT, 0x3a19, 0x80}, 770 {OV2722_8BIT, 0x4521, 0x00}, 771 {OV2722_8BIT, 0x5183, 0xb0}, 772 {OV2722_8BIT, 0x5184, 0xb0}, 773 {OV2722_8BIT, 0x5185, 0xb0}, 774 {OV2722_8BIT, 0x370c, 0x0c}, 775 {OV2722_8BIT, 0x3035, 0x00}, 776 {OV2722_8BIT, 0x3036, 0x2c}, /* 422.4 MHz */ 777 {OV2722_8BIT, 0x3037, 0xa1}, 778 {OV2722_8BIT, 0x303e, 0x19}, 779 {OV2722_8BIT, 0x3038, 0x06}, 780 {OV2722_8BIT, 0x3018, 0x04}, 781 {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ 782 {OV2722_8BIT, 0x3001, 0x00}, 783 {OV2722_8BIT, 0x3002, 0x00}, 784 {OV2722_8BIT, 0x3a0f, 0x40}, 785 {OV2722_8BIT, 0x3a10, 0x38}, 786 {OV2722_8BIT, 0x3a1b, 0x48}, 787 {OV2722_8BIT, 0x3a1e, 0x30}, 788 {OV2722_8BIT, 0x3a11, 0x90}, 789 {OV2722_8BIT, 0x3a1f, 0x10}, 790 {OV2722_8BIT, 0x3503, 0x17}, /* manual 3a */ 791 {OV2722_8BIT, 0x3500, 0x00}, 792 {OV2722_8BIT, 0x3501, 0x3F}, 793 {OV2722_8BIT, 0x3502, 0x00}, 794 {OV2722_8BIT, 0x3508, 0x00}, 795 {OV2722_8BIT, 0x3509, 0x00}, 796 {OV2722_TOK_TERM, 0, 0} 797 }; 798 static struct ov2722_reg const ov2722_1M3_30fps[] = { 799 {OV2722_8BIT, 0x3718, 0x10}, 800 {OV2722_8BIT, 0x3702, 0x24}, 801 {OV2722_8BIT, 0x373a, 0x60}, 802 {OV2722_8BIT, 0x3715, 0x01}, 803 {OV2722_8BIT, 0x3703, 0x2e}, 804 {OV2722_8BIT, 0x3705, 0x10}, 805 {OV2722_8BIT, 0x3730, 0x30}, 806 {OV2722_8BIT, 0x3704, 0x62}, 807 {OV2722_8BIT, 0x3f06, 0x3a}, 808 {OV2722_8BIT, 0x371c, 0x00}, 809 {OV2722_8BIT, 0x371d, 0xc4}, 810 {OV2722_8BIT, 0x371e, 0x01}, 811 {OV2722_8BIT, 0x371f, 0x0d}, 812 {OV2722_8BIT, 0x3708, 0x61}, 813 {OV2722_8BIT, 0x3709, 0x12}, 814 {OV2722_8BIT, 0x3800, 0x01}, 815 {OV2722_8BIT, 0x3801, 0x4a}, /* H crop start: 330 */ 816 {OV2722_8BIT, 0x3802, 0x00}, 817 {OV2722_8BIT, 0x3803, 0x03}, /* V crop start: 3 */ 818 {OV2722_8BIT, 0x3804, 0x06}, 819 {OV2722_8BIT, 0x3805, 0xe1}, /* H crop end: 1761 */ 820 {OV2722_8BIT, 0x3806, 0x04}, 821 {OV2722_8BIT, 0x3807, 0x47}, /* V crop end: 1095 */ 822 {OV2722_8BIT, 0x3808, 0x05}, 823 {OV2722_8BIT, 0x3809, 0x88}, /* H output size: 1416 */ 824 {OV2722_8BIT, 0x380a, 0x04}, 825 {OV2722_8BIT, 0x380b, 0x0a}, /* V output size: 1034 */ 826 827 /* H blank timing */ 828 {OV2722_8BIT, 0x380c, 0x08}, 829 {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ 830 {OV2722_8BIT, 0x380e, 0x04}, 831 {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ 832 {OV2722_8BIT, 0x3810, 0x00}, 833 {OV2722_8BIT, 0x3811, 0x05}, /* H window offset: 5 */ 834 {OV2722_8BIT, 0x3812, 0x00}, 835 {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ 836 {OV2722_8BIT, 0x3820, 0x80}, 837 {OV2722_8BIT, 0x3821, 0x06}, /* flip isp */ 838 {OV2722_8BIT, 0x3814, 0x11}, 839 {OV2722_8BIT, 0x3815, 0x11}, 840 {OV2722_8BIT, 0x3612, 0x0b}, 841 {OV2722_8BIT, 0x3618, 0x04}, 842 {OV2722_8BIT, 0x3a08, 0x01}, 843 {OV2722_8BIT, 0x3a09, 0x50}, 844 {OV2722_8BIT, 0x3a0a, 0x01}, 845 {OV2722_8BIT, 0x3a0b, 0x18}, 846 {OV2722_8BIT, 0x3a0d, 0x03}, 847 {OV2722_8BIT, 0x3a0e, 0x03}, 848 {OV2722_8BIT, 0x4520, 0x00}, 849 {OV2722_8BIT, 0x4837, 0x1b}, 850 {OV2722_8BIT, 0x3000, 0xff}, 851 {OV2722_8BIT, 0x3001, 0xff}, 852 {OV2722_8BIT, 0x3002, 0xf0}, 853 {OV2722_8BIT, 0x3600, 0x08}, 854 {OV2722_8BIT, 0x3621, 0xc0}, 855 {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ 856 {OV2722_8BIT, 0x3633, 0x23}, 857 {OV2722_8BIT, 0x3634, 0x54}, 858 {OV2722_8BIT, 0x3f01, 0x0c}, 859 {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ 860 {OV2722_8BIT, 0x3614, 0xf0}, 861 {OV2722_8BIT, 0x3630, 0x2d}, 862 {OV2722_8BIT, 0x370b, 0x62}, 863 {OV2722_8BIT, 0x3706, 0x61}, 864 {OV2722_8BIT, 0x4000, 0x02}, 865 {OV2722_8BIT, 0x4002, 0xc5}, 866 {OV2722_8BIT, 0x4005, 0x08}, 867 {OV2722_8BIT, 0x404f, 0x84}, 868 {OV2722_8BIT, 0x4051, 0x00}, 869 {OV2722_8BIT, 0x5000, 0xcf}, 870 {OV2722_8BIT, 0x3a18, 0x00}, 871 {OV2722_8BIT, 0x3a19, 0x80}, 872 {OV2722_8BIT, 0x4521, 0x00}, 873 {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ 874 {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ 875 {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ 876 {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ 877 {OV2722_8BIT, 0x370c, 0x0c}, 878 {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ 879 {OV2722_8BIT, 0x3035, 0x00}, 880 {OV2722_8BIT, 0x3036, 0x26}, 881 {OV2722_8BIT, 0x3037, 0xa1}, 882 {OV2722_8BIT, 0x303e, 0x19}, 883 {OV2722_8BIT, 0x3038, 0x06}, 884 {OV2722_8BIT, 0x3018, 0x04}, 885 886 /* Added for power optimization */ 887 {OV2722_8BIT, 0x3000, 0x00}, 888 {OV2722_8BIT, 0x3001, 0x00}, 889 {OV2722_8BIT, 0x3002, 0x00}, 890 {OV2722_8BIT, 0x3a0f, 0x40}, 891 {OV2722_8BIT, 0x3a10, 0x38}, 892 {OV2722_8BIT, 0x3a1b, 0x48}, 893 {OV2722_8BIT, 0x3a1e, 0x30}, 894 {OV2722_8BIT, 0x3a11, 0x90}, 895 {OV2722_8BIT, 0x3a1f, 0x10}, 896 {OV2722_8BIT, 0x3503, 0x17}, 897 {OV2722_8BIT, 0x3500, 0x00}, 898 {OV2722_8BIT, 0x3501, 0x46}, 899 {OV2722_8BIT, 0x3502, 0x00}, 900 {OV2722_8BIT, 0x3508, 0x00}, 901 {OV2722_8BIT, 0x3509, 0x10}, 902 {OV2722_TOK_TERM, 0, 0}, 903 }; 904 905 static struct ov2722_reg const ov2722_1080p_30fps[] = { 906 {OV2722_8BIT, 0x3021, 0x03}, /* For stand wait for a whole 907 frame complete.(vblank) */ 908 {OV2722_8BIT, 0x3718, 0x10}, 909 {OV2722_8BIT, 0x3702, 0x24}, 910 {OV2722_8BIT, 0x373a, 0x60}, 911 {OV2722_8BIT, 0x3715, 0x01}, 912 {OV2722_8BIT, 0x3703, 0x2e}, 913 {OV2722_8BIT, 0x3705, 0x2b}, 914 {OV2722_8BIT, 0x3730, 0x30}, 915 {OV2722_8BIT, 0x3704, 0x62}, 916 {OV2722_8BIT, 0x3f06, 0x3a}, 917 {OV2722_8BIT, 0x371c, 0x00}, 918 {OV2722_8BIT, 0x371d, 0xc4}, 919 {OV2722_8BIT, 0x371e, 0x01}, 920 {OV2722_8BIT, 0x371f, 0x28}, 921 {OV2722_8BIT, 0x3708, 0x61}, 922 {OV2722_8BIT, 0x3709, 0x12}, 923 {OV2722_8BIT, 0x3800, 0x00}, 924 {OV2722_8BIT, 0x3801, 0x08}, /* H crop start: 8 */ 925 {OV2722_8BIT, 0x3802, 0x00}, 926 {OV2722_8BIT, 0x3803, 0x01}, /* V crop start: 1 */ 927 {OV2722_8BIT, 0x3804, 0x07}, 928 {OV2722_8BIT, 0x3805, 0x9b}, /* H crop end: 1947 */ 929 {OV2722_8BIT, 0x3806, 0x04}, 930 {OV2722_8BIT, 0x3807, 0x45}, /* V crop end: 1093 */ 931 {OV2722_8BIT, 0x3808, 0x07}, 932 {OV2722_8BIT, 0x3809, 0x8c}, /* H output size: 1932 */ 933 {OV2722_8BIT, 0x380a, 0x04}, 934 {OV2722_8BIT, 0x380b, 0x44}, /* V output size: 1092 */ 935 {OV2722_8BIT, 0x380c, 0x08}, 936 {OV2722_8BIT, 0x380d, 0x14}, /* H timing: 2068 */ 937 {OV2722_8BIT, 0x380e, 0x04}, 938 {OV2722_8BIT, 0x380f, 0x5a}, /* V timing: 1114 */ 939 {OV2722_8BIT, 0x3810, 0x00}, 940 {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ 941 {OV2722_8BIT, 0x3812, 0x00}, 942 {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ 943 {OV2722_8BIT, 0x3820, 0x80}, 944 {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ 945 {OV2722_8BIT, 0x3814, 0x11}, 946 {OV2722_8BIT, 0x3815, 0x11}, 947 {OV2722_8BIT, 0x3612, 0x4b}, 948 {OV2722_8BIT, 0x3618, 0x04}, 949 {OV2722_8BIT, 0x3a08, 0x01}, 950 {OV2722_8BIT, 0x3a09, 0x50}, 951 {OV2722_8BIT, 0x3a0a, 0x01}, 952 {OV2722_8BIT, 0x3a0b, 0x18}, 953 {OV2722_8BIT, 0x3a0d, 0x03}, 954 {OV2722_8BIT, 0x3a0e, 0x03}, 955 {OV2722_8BIT, 0x4520, 0x00}, 956 {OV2722_8BIT, 0x4837, 0x1b}, 957 {OV2722_8BIT, 0x3000, 0xff}, 958 {OV2722_8BIT, 0x3001, 0xff}, 959 {OV2722_8BIT, 0x3002, 0xf0}, 960 {OV2722_8BIT, 0x3600, 0x08}, 961 {OV2722_8BIT, 0x3621, 0xc0}, 962 {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ 963 {OV2722_8BIT, 0x3633, 0x63}, 964 {OV2722_8BIT, 0x3634, 0x24}, 965 {OV2722_8BIT, 0x3f01, 0x0c}, 966 {OV2722_8BIT, 0x5001, 0xc1}, 967 {OV2722_8BIT, 0x3614, 0xf0}, 968 {OV2722_8BIT, 0x3630, 0x2d}, 969 {OV2722_8BIT, 0x370b, 0x62}, 970 {OV2722_8BIT, 0x3706, 0x61}, 971 {OV2722_8BIT, 0x4000, 0x02}, 972 {OV2722_8BIT, 0x4002, 0xc5}, 973 {OV2722_8BIT, 0x4005, 0x08}, 974 {OV2722_8BIT, 0x404f, 0x84}, 975 {OV2722_8BIT, 0x4051, 0x00}, 976 {OV2722_8BIT, 0x5000, 0xcd}, /* manual 3a */ 977 {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ 978 {OV2722_8BIT, 0x3a18, 0x00}, 979 {OV2722_8BIT, 0x3a19, 0x80}, 980 {OV2722_8BIT, 0x3503, 0x17}, 981 {OV2722_8BIT, 0x4521, 0x00}, 982 {OV2722_8BIT, 0x5183, 0xb0}, 983 {OV2722_8BIT, 0x5184, 0xb0}, 984 {OV2722_8BIT, 0x5185, 0xb0}, 985 {OV2722_8BIT, 0x370c, 0x0c}, 986 {OV2722_8BIT, 0x3035, 0x00}, 987 {OV2722_8BIT, 0x3036, 0x24}, /* 345.6 MHz */ 988 {OV2722_8BIT, 0x3037, 0xa1}, 989 {OV2722_8BIT, 0x303e, 0x19}, 990 {OV2722_8BIT, 0x3038, 0x06}, 991 {OV2722_8BIT, 0x3018, 0x04}, 992 {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ 993 {OV2722_8BIT, 0x3001, 0x00}, 994 {OV2722_8BIT, 0x3002, 0x00}, 995 {OV2722_8BIT, 0x3a0f, 0x40}, 996 {OV2722_8BIT, 0x3a10, 0x38}, 997 {OV2722_8BIT, 0x3a1b, 0x48}, 998 {OV2722_8BIT, 0x3a1e, 0x30}, 999 {OV2722_8BIT, 0x3a11, 0x90}, 1000 {OV2722_8BIT, 0x3a1f, 0x10}, 1001 {OV2722_8BIT, 0x3011, 0x22}, 1002 {OV2722_8BIT, 0x3500, 0x00}, 1003 {OV2722_8BIT, 0x3501, 0x3F}, 1004 {OV2722_8BIT, 0x3502, 0x00}, 1005 {OV2722_8BIT, 0x3508, 0x00}, 1006 {OV2722_8BIT, 0x3509, 0x00}, 1007 {OV2722_TOK_TERM, 0, 0} 1008 }; 1009 1010 static struct ov2722_reg const ov2722_720p_30fps[] = { 1011 {OV2722_8BIT, 0x3021, 0x03}, 1012 {OV2722_8BIT, 0x3718, 0x10}, 1013 {OV2722_8BIT, 0x3702, 0x24}, 1014 {OV2722_8BIT, 0x373a, 0x60}, 1015 {OV2722_8BIT, 0x3715, 0x01}, 1016 {OV2722_8BIT, 0x3703, 0x2e}, 1017 {OV2722_8BIT, 0x3705, 0x10}, 1018 {OV2722_8BIT, 0x3730, 0x30}, 1019 {OV2722_8BIT, 0x3704, 0x62}, 1020 {OV2722_8BIT, 0x3f06, 0x3a}, 1021 {OV2722_8BIT, 0x371c, 0x00}, 1022 {OV2722_8BIT, 0x371d, 0xc4}, 1023 {OV2722_8BIT, 0x371e, 0x01}, 1024 {OV2722_8BIT, 0x371f, 0x0d}, 1025 {OV2722_8BIT, 0x3708, 0x61}, 1026 {OV2722_8BIT, 0x3709, 0x12}, 1027 {OV2722_8BIT, 0x3800, 0x01}, 1028 {OV2722_8BIT, 0x3801, 0x40}, /* H crop start: 320 */ 1029 {OV2722_8BIT, 0x3802, 0x00}, 1030 {OV2722_8BIT, 0x3803, 0xb1}, /* V crop start: 177 */ 1031 {OV2722_8BIT, 0x3804, 0x06}, 1032 {OV2722_8BIT, 0x3805, 0x55}, /* H crop end: 1621 */ 1033 {OV2722_8BIT, 0x3806, 0x03}, 1034 {OV2722_8BIT, 0x3807, 0x95}, /* V crop end: 918 */ 1035 {OV2722_8BIT, 0x3808, 0x05}, 1036 {OV2722_8BIT, 0x3809, 0x10}, /* H output size: 0x0788==1928 */ 1037 {OV2722_8BIT, 0x380a, 0x02}, 1038 {OV2722_8BIT, 0x380b, 0xe0}, /* output size: 0x02DE==734 */ 1039 {OV2722_8BIT, 0x380c, 0x08}, 1040 {OV2722_8BIT, 0x380d, 0x00}, /* H timing: 2048 */ 1041 {OV2722_8BIT, 0x380e, 0x04}, 1042 {OV2722_8BIT, 0x380f, 0xa3}, /* V timing: 1187 */ 1043 {OV2722_8BIT, 0x3810, 0x00}, 1044 {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ 1045 {OV2722_8BIT, 0x3812, 0x00}, 1046 {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ 1047 {OV2722_8BIT, 0x3820, 0x80}, 1048 {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ 1049 {OV2722_8BIT, 0x3814, 0x11}, 1050 {OV2722_8BIT, 0x3815, 0x11}, 1051 {OV2722_8BIT, 0x3612, 0x0b}, 1052 {OV2722_8BIT, 0x3618, 0x04}, 1053 {OV2722_8BIT, 0x3a08, 0x01}, 1054 {OV2722_8BIT, 0x3a09, 0x50}, 1055 {OV2722_8BIT, 0x3a0a, 0x01}, 1056 {OV2722_8BIT, 0x3a0b, 0x18}, 1057 {OV2722_8BIT, 0x3a0d, 0x03}, 1058 {OV2722_8BIT, 0x3a0e, 0x03}, 1059 {OV2722_8BIT, 0x4520, 0x00}, 1060 {OV2722_8BIT, 0x4837, 0x1b}, 1061 {OV2722_8BIT, 0x3600, 0x08}, 1062 {OV2722_8BIT, 0x3621, 0xc0}, 1063 {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ 1064 {OV2722_8BIT, 0x3633, 0x23}, 1065 {OV2722_8BIT, 0x3634, 0x54}, 1066 {OV2722_8BIT, 0x3f01, 0x0c}, 1067 {OV2722_8BIT, 0x5001, 0xc1}, 1068 {OV2722_8BIT, 0x3614, 0xf0}, 1069 {OV2722_8BIT, 0x3630, 0x2d}, 1070 {OV2722_8BIT, 0x370b, 0x62}, 1071 {OV2722_8BIT, 0x3706, 0x61}, 1072 {OV2722_8BIT, 0x4000, 0x02}, 1073 {OV2722_8BIT, 0x4002, 0xc5}, 1074 {OV2722_8BIT, 0x4005, 0x08}, 1075 {OV2722_8BIT, 0x404f, 0x84}, 1076 {OV2722_8BIT, 0x4051, 0x00}, 1077 {OV2722_8BIT, 0x5000, 0xcf}, /* manual 3a */ 1078 {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ 1079 {OV2722_8BIT, 0x3a18, 0x00}, 1080 {OV2722_8BIT, 0x3a19, 0x80}, 1081 {OV2722_8BIT, 0x4521, 0x00}, 1082 {OV2722_8BIT, 0x5183, 0xb0}, 1083 {OV2722_8BIT, 0x5184, 0xb0}, 1084 {OV2722_8BIT, 0x5185, 0xb0}, 1085 {OV2722_8BIT, 0x370c, 0x0c}, 1086 {OV2722_8BIT, 0x3035, 0x00}, 1087 {OV2722_8BIT, 0x3036, 0x26}, /* {0x3036, 0x2c}, //422.4 MHz */ 1088 {OV2722_8BIT, 0x3037, 0xa1}, 1089 {OV2722_8BIT, 0x303e, 0x19}, 1090 {OV2722_8BIT, 0x3038, 0x06}, 1091 {OV2722_8BIT, 0x3018, 0x04}, 1092 {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ 1093 {OV2722_8BIT, 0x3001, 0x00}, 1094 {OV2722_8BIT, 0x3002, 0x00}, 1095 {OV2722_8BIT, 0x3a0f, 0x40}, 1096 {OV2722_8BIT, 0x3a10, 0x38}, 1097 {OV2722_8BIT, 0x3a1b, 0x48}, 1098 {OV2722_8BIT, 0x3a1e, 0x30}, 1099 {OV2722_8BIT, 0x3a11, 0x90}, 1100 {OV2722_8BIT, 0x3a1f, 0x10}, 1101 {OV2722_8BIT, 0x3503, 0x17}, /* manual 3a */ 1102 {OV2722_8BIT, 0x3500, 0x00}, 1103 {OV2722_8BIT, 0x3501, 0x3F}, 1104 {OV2722_8BIT, 0x3502, 0x00}, 1105 {OV2722_8BIT, 0x3508, 0x00}, 1106 {OV2722_8BIT, 0x3509, 0x00}, 1107 {OV2722_TOK_TERM, 0, 0}, 1108 }; 1109 1110 struct ov2722_resolution ov2722_res_preview[] = { 1111 { 1112 .desc = "ov2722_1632_1092_30fps", 1113 .width = 1632, 1114 .height = 1092, 1115 .fps = 30, 1116 .pix_clk_freq = 85, 1117 .used = 0, 1118 .pixels_per_line = 2260, 1119 .lines_per_frame = 1244, 1120 .bin_factor_x = 1, 1121 .bin_factor_y = 1, 1122 .bin_mode = 0, 1123 .skip_frames = 3, 1124 .regs = ov2722_1632_1092_30fps, 1125 .mipi_freq = 422400, 1126 }, 1127 { 1128 .desc = "ov2722_1452_1092_30fps", 1129 .width = 1452, 1130 .height = 1092, 1131 .fps = 30, 1132 .pix_clk_freq = 85, 1133 .used = 0, 1134 .pixels_per_line = 2260, 1135 .lines_per_frame = 1244, 1136 .bin_factor_x = 1, 1137 .bin_factor_y = 1, 1138 .bin_mode = 0, 1139 .skip_frames = 3, 1140 .regs = ov2722_1452_1092_30fps, 1141 .mipi_freq = 422400, 1142 }, 1143 { 1144 .desc = "ov2722_1080P_30fps", 1145 .width = 1932, 1146 .height = 1092, 1147 .pix_clk_freq = 69, 1148 .fps = 30, 1149 .used = 0, 1150 .pixels_per_line = 2068, 1151 .lines_per_frame = 1114, 1152 .bin_factor_x = 1, 1153 .bin_factor_y = 1, 1154 .bin_mode = 0, 1155 .skip_frames = 3, 1156 .regs = ov2722_1080p_30fps, 1157 .mipi_freq = 345600, 1158 }, 1159 }; 1160 #define N_RES_PREVIEW (ARRAY_SIZE(ov2722_res_preview)) 1161 1162 struct ov2722_resolution ov2722_res_still[] = { 1163 { 1164 .desc = "ov2722_480P_30fps", 1165 .width = 1632, 1166 .height = 1092, 1167 .fps = 30, 1168 .pix_clk_freq = 85, 1169 .used = 0, 1170 .pixels_per_line = 2260, 1171 .lines_per_frame = 1244, 1172 .bin_factor_x = 1, 1173 .bin_factor_y = 1, 1174 .bin_mode = 0, 1175 .skip_frames = 3, 1176 .regs = ov2722_1632_1092_30fps, 1177 .mipi_freq = 422400, 1178 }, 1179 { 1180 .desc = "ov2722_1452_1092_30fps", 1181 .width = 1452, 1182 .height = 1092, 1183 .fps = 30, 1184 .pix_clk_freq = 85, 1185 .used = 0, 1186 .pixels_per_line = 2260, 1187 .lines_per_frame = 1244, 1188 .bin_factor_x = 1, 1189 .bin_factor_y = 1, 1190 .bin_mode = 0, 1191 .skip_frames = 3, 1192 .regs = ov2722_1452_1092_30fps, 1193 .mipi_freq = 422400, 1194 }, 1195 { 1196 .desc = "ov2722_1080P_30fps", 1197 .width = 1932, 1198 .height = 1092, 1199 .pix_clk_freq = 69, 1200 .fps = 30, 1201 .used = 0, 1202 .pixels_per_line = 2068, 1203 .lines_per_frame = 1114, 1204 .bin_factor_x = 1, 1205 .bin_factor_y = 1, 1206 .bin_mode = 0, 1207 .skip_frames = 3, 1208 .regs = ov2722_1080p_30fps, 1209 .mipi_freq = 345600, 1210 }, 1211 }; 1212 #define N_RES_STILL (ARRAY_SIZE(ov2722_res_still)) 1213 1214 struct ov2722_resolution ov2722_res_video[] = { 1215 { 1216 .desc = "ov2722_QVGA_30fps", 1217 .width = 336, 1218 .height = 256, 1219 .fps = 30, 1220 .pix_clk_freq = 73, 1221 .used = 0, 1222 .pixels_per_line = 2048, 1223 .lines_per_frame = 1184, 1224 .bin_factor_x = 1, 1225 .bin_factor_y = 1, 1226 .bin_mode = 0, 1227 .skip_frames = 3, 1228 .regs = ov2722_QVGA_30fps, 1229 .mipi_freq = 364800, 1230 }, 1231 { 1232 .desc = "ov2722_480P_30fps", 1233 .width = 736, 1234 .height = 496, 1235 .fps = 30, 1236 .pix_clk_freq = 73, 1237 .used = 0, 1238 .pixels_per_line = 2048, 1239 .lines_per_frame = 1184, 1240 .bin_factor_x = 1, 1241 .bin_factor_y = 1, 1242 .bin_mode = 0, 1243 .skip_frames = 3, 1244 .regs = ov2722_480P_30fps, 1245 }, 1246 { 1247 .desc = "ov2722_1080P_30fps", 1248 .width = 1932, 1249 .height = 1092, 1250 .pix_clk_freq = 69, 1251 .fps = 30, 1252 .used = 0, 1253 .pixels_per_line = 2068, 1254 .lines_per_frame = 1114, 1255 .bin_factor_x = 1, 1256 .bin_factor_y = 1, 1257 .bin_mode = 0, 1258 .skip_frames = 3, 1259 .regs = ov2722_1080p_30fps, 1260 .mipi_freq = 345600, 1261 }, 1262 }; 1263 #define N_RES_VIDEO (ARRAY_SIZE(ov2722_res_video)) 1264 1265 static struct ov2722_resolution *ov2722_res = ov2722_res_preview; 1266 static unsigned long N_RES = N_RES_PREVIEW; 1267 #endif 1268