1 /* 2 * Support for the Omnivision OV8858 camera sensor. 3 * 4 * Copyright (c) 2014 Intel Corporation. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License version 8 * 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 18 * 02110-1301, USA. 19 * 20 */ 21 22 #ifndef __OV8858_H__ 23 #define __OV8858_H__ 24 #include "../include/linux/atomisp_platform.h" 25 #include <media/v4l2-ctrls.h> 26 27 #define I2C_MSG_LENGTH 0x2 28 29 /* 30 * This should be added into include/linux/videodev2.h 31 * NOTE: This is most likely not used anywhere. 32 */ 33 #define V4L2_IDENT_OV8858 V4L2_IDENT_UNKNOWN 34 35 /* 36 * Indexes for VCM driver lists 37 */ 38 #define OV8858_ID_DEFAULT 0 39 #define OV8858_SUNNY 1 40 41 #define OV8858_OTP_START_ADDR 0x7010 42 #define OV8858_OTP_END_ADDR 0x7186 43 44 /* 45 * ov8858 System control registers 46 */ 47 48 #define OV8858_OTP_LOAD_CTRL 0x3D81 49 #define OV8858_OTP_MODE_CTRL 0x3D84 50 #define OV8858_OTP_START_ADDR_REG 0x3D88 51 #define OV8858_OTP_END_ADDR_REG 0x3D8A 52 #define OV8858_OTP_ISP_CTRL2 0x5002 53 54 #define OV8858_OTP_MODE_MANUAL BIT(6) 55 #define OV8858_OTP_MODE_PROGRAM_DISABLE BIT(7) 56 #define OV8858_OTP_LOAD_ENABLE BIT(0) 57 #define OV8858_OTP_DPC_ENABLE BIT(3) 58 59 #define OV8858_PLL1_PREDIV0 0x030A 60 #define OV8858_PLL1_PREDIV 0x0300 61 #define OV8858_PLL1_MULTIPLIER 0x0301 62 #define OV8858_PLL1_SYS_PRE_DIV 0x0305 63 #define OV8858_PLL1_SYS_DIVIDER 0x0306 64 65 #define OV8858_PLL1_PREDIV0_MASK BIT(0) 66 #define OV8858_PLL1_PREDIV_MASK (BIT(0) | BIT(1) | BIT(2)) 67 #define OV8858_PLL1_MULTIPLIER_MASK 0x01FF 68 #define OV8858_PLL1_SYS_PRE_DIV_MASK (BIT(0) | BIT(1)) 69 #define OV8858_PLL1_SYS_DIVIDER_MASK BIT(0) 70 71 #define OV8858_PLL2_PREDIV0 0x0312 72 #define OV8858_PLL2_PREDIV 0x030B 73 #define OV8858_PLL2_MULTIPLIER 0x030C 74 #define OV8858_PLL2_DAC_DIVIDER 0x0312 75 #define OV8858_PLL2_SYS_PRE_DIV 0x030F 76 #define OV8858_PLL2_SYS_DIVIDER 0x030E 77 78 #define OV8858_PLL2_PREDIV0_MASK BIT(4) 79 #define OV8858_PLL2_PREDIV_MASK (BIT(0) | BIT(1) | BIT(2)) 80 #define OV8858_PLL2_MULTIPLIER_MASK 0x01FF 81 #define OV8858_PLL2_DAC_DIVIDER_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 82 #define OV8858_PLL2_SYS_PRE_DIV_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 83 #define OV8858_PLL2_SYS_DIVIDER_MASK (BIT(0) | BIT(1) | BIT(2)) 84 85 #define OV8858_PLL_SCLKSEL1 0x3032 86 #define OV8858_PLL_SCLKSEL2 0x3033 87 #define OV8858_SRB_HOST_INPUT_DIS 0x3106 88 89 #define OV8858_PLL_SCLKSEL1_MASK BIT(7) 90 #define OV8858_PLL_SCLKSEL2_MASK BIT(1) 91 92 #define OV8858_SYS_PRE_DIV_OFFSET 2 93 #define OV8858_SYS_PRE_DIV_MASK (BIT(2) | BIT(3)) 94 #define OV8858_SCLK_PDIV_OFFSET 4 95 #define OV8858_SCLK_PDIV_MASK (BIT(4) | BIT(5) | BIT(6) | BIT(7)) 96 97 #define OV8858_TIMING_HTS 0x380C 98 #define OV8858_TIMING_VTS 0x380E 99 100 #define OV8858_HORIZONTAL_START_H 0x3800 101 #define OV8858_VERTICAL_START_H 0x3802 102 #define OV8858_HORIZONTAL_END_H 0x3804 103 #define OV8858_VERTICAL_END_H 0x3806 104 #define OV8858_HORIZONTAL_OUTPUT_SIZE_H 0x3808 105 #define OV8858_VERTICAL_OUTPUT_SIZE_H 0x380A 106 107 #define OV8858_GROUP_ACCESS 0x3208 108 #define OV8858_GROUP_ZERO 0x00 109 #define OV8858_GROUP_ACCESS_HOLD_START 0x00 110 #define OV8858_GROUP_ACCESS_HOLD_END 0x10 111 #define OV8858_GROUP_ACCESS_DELAY_LAUNCH 0xA0 112 #define OV8858_GROUP_ACCESS_QUICK_LAUNCH 0xE0 113 114 #define OV_SUBDEV_PREFIX "ov" 115 #define OV_ID_DEFAULT 0x0000 116 #define OV8858_NAME "ov8858" 117 #define OV8858_CHIP_ID 0x8858 118 119 #define OV8858_LONG_EXPO 0x3500 120 #define OV8858_LONG_GAIN 0x3508 121 #define OV8858_LONG_DIGI_GAIN 0x350A 122 #define OV8858_SHORT_GAIN 0x350C 123 #define OV8858_SHORT_DIGI_GAIN 0x350E 124 125 #define OV8858_FORMAT1 0x3820 126 #define OV8858_FORMAT2 0x3821 127 128 #define OV8858_FLIP_ENABLE 0x06 129 130 #define OV8858_MWB_RED_GAIN_H 0x5032 131 #define OV8858_MWB_GREEN_GAIN_H 0x5034 132 #define OV8858_MWB_BLUE_GAIN_H 0x5036 133 #define OV8858_MWB_GAIN_MAX 0x0FFF 134 135 #define OV8858_CHIP_ID_HIGH 0x300B 136 #define OV8858_CHIP_ID_LOW 0x300C 137 #define OV8858_STREAM_MODE 0x0100 138 139 #define OV8858_FOCAL_LENGTH_NUM 294 /* 2.94mm */ 140 #define OV8858_FOCAL_LENGTH_DEM 100 141 #define OV8858_F_NUMBER_DEFAULT_NUM 24 /* 2.4 */ 142 #define OV8858_F_NUMBER_DEM 10 143 144 #define OV8858_H_INC_ODD 0x3814 145 #define OV8858_H_INC_EVEN 0x3815 146 #define OV8858_V_INC_ODD 0x382A 147 #define OV8858_V_INC_EVEN 0x382B 148 149 #define OV8858_READ_MODE_BINNING_ON 0x0400 /* ToDo: Check this */ 150 #define OV8858_READ_MODE_BINNING_OFF 0x00 /* ToDo: Check this */ 151 #define OV8858_BIN_FACTOR_MAX 2 152 #define OV8858_INTEGRATION_TIME_MARGIN 14 153 154 #define OV8858_MAX_VTS_VALUE 0xFFFF 155 #define OV8858_MAX_EXPOSURE_VALUE \ 156 (OV8858_MAX_VTS_VALUE - OV8858_INTEGRATION_TIME_MARGIN) 157 #define OV8858_MAX_GAIN_VALUE 0x07FF 158 159 #define OV8858_MAX_FOCUS_POS 1023 160 161 #define OV8858_TEST_PATTERN_REG 0x5E00 162 163 struct ov8858_vcm { 164 int (*power_up)(struct v4l2_subdev *sd); 165 int (*power_down)(struct v4l2_subdev *sd); 166 int (*init)(struct v4l2_subdev *sd); 167 int (*t_focus_abs)(struct v4l2_subdev *sd, s32 value); 168 int (*t_focus_rel)(struct v4l2_subdev *sd, s32 value); 169 int (*q_focus_status)(struct v4l2_subdev *sd, s32 *value); 170 int (*q_focus_abs)(struct v4l2_subdev *sd, s32 *value); 171 int (*t_vcm_slew)(struct v4l2_subdev *sd, s32 value); 172 int (*t_vcm_timing)(struct v4l2_subdev *sd, s32 value); 173 }; 174 175 /* 176 * Defines for register writes and register array processing 177 * */ 178 #define OV8858_BYTE_MAX 32 179 #define OV8858_SHORT_MAX 16 180 #define OV8858_TOK_MASK 0xFFF0 181 182 #define MAX_FPS_OPTIONS_SUPPORTED 3 183 184 #define OV8858_DEPTH_COMP_CONST 2200 185 #define OV8858_DEPTH_VTS_CONST 2573 186 187 enum ov8858_tok_type { 188 OV8858_8BIT = 0x0001, 189 OV8858_16BIT = 0x0002, 190 OV8858_TOK_TERM = 0xF000, /* terminating token for reg list */ 191 OV8858_TOK_DELAY = 0xFE00 /* delay token for reg list */ 192 }; 193 194 /* 195 * If register address or register width is not 32 bit width, 196 * user needs to convert it manually 197 */ 198 struct s_register_setting { 199 u32 reg; 200 u32 val; 201 }; 202 203 /** 204 * struct ov8858_reg - MI sensor register format 205 * @type: type of the register 206 * @reg: 16-bit offset to register 207 * @val: 8/16/32-bit register value 208 * 209 * Define a structure for sensor register initialization values 210 */ 211 struct ov8858_reg { 212 enum ov8858_tok_type type; 213 u16 sreg; 214 u32 val; /* @set value for read/mod/write, @mask */ 215 }; 216 217 struct ov8858_fps_setting { 218 int fps; 219 unsigned short pixels_per_line; 220 unsigned short lines_per_frame; 221 const struct ov8858_reg *regs; /* regs that the fps setting needs */ 222 }; 223 224 struct ov8858_resolution { 225 u8 *desc; 226 const struct ov8858_reg *regs; 227 int res; 228 int width; 229 int height; 230 bool used; 231 u8 bin_factor_x; 232 u8 bin_factor_y; 233 unsigned short skip_frames; 234 const struct ov8858_fps_setting fps_options[MAX_FPS_OPTIONS_SUPPORTED]; 235 }; 236 237 /* 238 * ov8858 device structure 239 * */ 240 struct ov8858_device { 241 struct v4l2_subdev sd; 242 struct media_pad pad; 243 struct v4l2_mbus_framefmt format; 244 245 struct camera_sensor_platform_data *platform_data; 246 struct mutex input_lock; /* serialize sensor's ioctl */ 247 int fmt_idx; 248 int streaming; 249 int vt_pix_clk_freq_mhz; 250 int fps_index; 251 u16 sensor_id; /* Sensor id from registers */ 252 u16 i2c_id; /* Sensor id from i2c_device_id */ 253 int exposure; 254 int gain; 255 u16 digital_gain; 256 u16 pixels_per_line; 257 u16 lines_per_frame; 258 u8 fps; 259 u8 *otp_data; 260 /* Prevent the framerate from being lowered in low light scenes. */ 261 int limit_exposure_flag; 262 bool hflip; 263 bool vflip; 264 265 const struct ov8858_reg *regs; 266 struct ov8858_vcm *vcm_driver; 267 const struct ov8858_resolution *curr_res_table; 268 unsigned long entries_curr_table; 269 270 struct v4l2_ctrl_handler ctrl_handler; 271 struct v4l2_ctrl *run_mode; 272 }; 273 274 #define to_ov8858_sensor(x) container_of(x, struct ov8858_device, sd) 275 276 #define OV8858_MAX_WRITE_BUF_SIZE 32 277 struct ov8858_write_buffer { 278 u16 addr; 279 u8 data[OV8858_MAX_WRITE_BUF_SIZE]; 280 }; 281 282 struct ov8858_write_ctrl { 283 int index; 284 struct ov8858_write_buffer buffer; 285 }; 286 287 static const struct ov8858_reg ov8858_soft_standby[] = { 288 {OV8858_8BIT, 0x0100, 0x00}, 289 {OV8858_TOK_TERM, 0, 0} 290 }; 291 292 static const struct ov8858_reg ov8858_streaming[] = { 293 {OV8858_8BIT, 0x0100, 0x01}, 294 {OV8858_TOK_TERM, 0, 0} 295 }; 296 297 static const struct ov8858_reg ov8858_param_hold[] = { 298 {OV8858_8BIT, OV8858_GROUP_ACCESS, 299 OV8858_GROUP_ZERO | OV8858_GROUP_ACCESS_HOLD_START}, 300 {OV8858_TOK_TERM, 0, 0} 301 }; 302 303 static const struct ov8858_reg ov8858_param_update[] = { 304 {OV8858_8BIT, OV8858_GROUP_ACCESS, 305 OV8858_GROUP_ZERO | OV8858_GROUP_ACCESS_HOLD_END}, 306 {OV8858_8BIT, OV8858_GROUP_ACCESS, 307 OV8858_GROUP_ZERO | OV8858_GROUP_ACCESS_DELAY_LAUNCH}, 308 {OV8858_TOK_TERM, 0, 0} 309 }; 310 311 extern int dw9718_vcm_power_up(struct v4l2_subdev *sd); 312 extern int dw9718_vcm_power_down(struct v4l2_subdev *sd); 313 extern int dw9718_vcm_init(struct v4l2_subdev *sd); 314 extern int dw9718_t_focus_abs(struct v4l2_subdev *sd, s32 value); 315 extern int dw9718_t_focus_rel(struct v4l2_subdev *sd, s32 value); 316 extern int dw9718_q_focus_status(struct v4l2_subdev *sd, s32 *value); 317 extern int dw9718_q_focus_abs(struct v4l2_subdev *sd, s32 *value); 318 extern int dw9718_t_vcm_slew(struct v4l2_subdev *sd, s32 value); 319 extern int dw9718_t_vcm_timing(struct v4l2_subdev *sd, s32 value); 320 321 extern int vcm_power_up(struct v4l2_subdev *sd); 322 extern int vcm_power_down(struct v4l2_subdev *sd); 323 324 static struct ov8858_vcm ov8858_vcms[] = { 325 [OV8858_SUNNY] = { 326 .power_up = dw9718_vcm_power_up, 327 .power_down = dw9718_vcm_power_down, 328 .init = dw9718_vcm_init, 329 .t_focus_abs = dw9718_t_focus_abs, 330 .t_focus_rel = dw9718_t_focus_rel, 331 .q_focus_status = dw9718_q_focus_status, 332 .q_focus_abs = dw9718_q_focus_abs, 333 .t_vcm_slew = dw9718_t_vcm_slew, 334 .t_vcm_timing = dw9718_t_vcm_timing, 335 }, 336 [OV8858_ID_DEFAULT] = { 337 .power_up = NULL, 338 .power_down = NULL, 339 }, 340 }; 341 342 343 #define OV8858_RES_WIDTH_MAX 3280 344 #define OV8858_RES_HEIGHT_MAX 2464 345 346 static struct ov8858_reg ov8858_BasicSettings[] = { 347 {OV8858_8BIT, 0x0103, 0x01}, /* software_reset */ 348 {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ 349 /* PLL settings */ 350 {OV8858_8BIT, 0x0300, 0x05}, /* pll1_pre_div = /4 */ 351 {OV8858_8BIT, 0x0302, 0xAF}, /* pll1_multiplier = 175 */ 352 {OV8858_8BIT, 0x0303, 0x00}, /* pll1_divm = /(1 + 0) */ 353 {OV8858_8BIT, 0x0304, 0x03}, /* pll1_div_mipi = /8 */ 354 {OV8858_8BIT, 0x030B, 0x02}, /* pll2_pre_div = /2 */ 355 {OV8858_8BIT, 0x030D, 0x4E}, /* pll2_r_divp = 78 */ 356 {OV8858_8BIT, 0x030E, 0x00}, /* pll2_r_divs = /1 */ 357 {OV8858_8BIT, 0x030F, 0x04}, /* pll2_r_divsp = /(1 + 4) */ 358 /* pll2_pre_div0 = /1, pll2_r_divdac = /(1 + 1) */ 359 {OV8858_8BIT, 0x0312, 0x01}, 360 {OV8858_8BIT, 0x031E, 0x0C}, /* pll1_no_lat = 1, mipi_bitsel_man = 0 */ 361 362 /* PAD OEN2, VSYNC out enable=0x80, disable=0x00 */ 363 {OV8858_8BIT, 0x3002, 0x80}, 364 /* PAD OUT2, VSYNC pulse direction low-to-high = 1 */ 365 {OV8858_8BIT, 0x3007, 0x01}, 366 /* PAD SEL2, VSYNC out value = 0 */ 367 {OV8858_8BIT, 0x300D, 0x00}, 368 /* PAD OUT2, VSYNC out select = 0 */ 369 {OV8858_8BIT, 0x3010, 0x00}, 370 371 /* Npump clock div = /2, Ppump clock div = /4 */ 372 {OV8858_8BIT, 0x3015, 0x01}, 373 /* 374 * mipi_lane_mode = 1+3, mipi_lvds_sel = 1 = MIPI enable, 375 * r_phy_pd_mipi_man = 0, lane_dis_option = 0 376 */ 377 {OV8858_8BIT, 0x3018, 0x72}, 378 /* Clock switch output = normal, pclk_div = /1 */ 379 {OV8858_8BIT, 0x3020, 0x93}, 380 /* 381 * lvds_mode_o = 0, clock lane disable when pd_mipi = 0, 382 * pd_mipi enable when rst_sync = 1 383 */ 384 {OV8858_8BIT, 0x3022, 0x01}, 385 {OV8858_8BIT, 0x3031, 0x0A}, /* mipi_bit_sel = 10 */ 386 {OV8858_8BIT, 0x3034, 0x00}, /* Unknown */ 387 /* sclk_div = /1, sclk_pre_div = /1, chip debug = 1 */ 388 {OV8858_8BIT, 0x3106, 0x01}, 389 390 {OV8858_8BIT, 0x3305, 0xF1}, /* Unknown */ 391 {OV8858_8BIT, 0x3307, 0x04}, /* Unknown */ 392 {OV8858_8BIT, 0x3308, 0x00}, /* Unknown */ 393 {OV8858_8BIT, 0x3309, 0x28}, /* Unknown */ 394 {OV8858_8BIT, 0x330A, 0x00}, /* Unknown */ 395 {OV8858_8BIT, 0x330B, 0x20}, /* Unknown */ 396 {OV8858_8BIT, 0x330C, 0x00}, /* Unknown */ 397 {OV8858_8BIT, 0x330D, 0x00}, /* Unknown */ 398 {OV8858_8BIT, 0x330E, 0x00}, /* Unknown */ 399 {OV8858_8BIT, 0x330F, 0x40}, /* Unknown */ 400 401 {OV8858_8BIT, 0x3500, 0x00}, /* long exposure = 0x9A20 */ 402 {OV8858_8BIT, 0x3501, 0x9A}, /* long exposure = 0x9A20 */ 403 {OV8858_8BIT, 0x3502, 0x20}, /* long exposure = 0x9A20 */ 404 /* 405 * Digital fraction gain delay option = Delay 1 frame, 406 * Gain change delay option = Delay 1 frame, 407 * Gain delay option = Delay 1 frame, 408 * Gain manual as sensor gain = Input gain as real gain format, 409 * Exposure delay option (must be 0 = Delay 1 frame, 410 * Exposure change delay option (must be 0) = Delay 1 frame 411 */ 412 {OV8858_8BIT, 0x3503, 0x00}, 413 {OV8858_8BIT, 0x3505, 0x80}, /* gain conversation option */ 414 /* 415 * [10:7] are integer gain, [6:0] are fraction gain. For example: 416 * 0x80 is 1x gain, 0x100 is 2x gain, 0x1C0 is 3.5x gain 417 */ 418 {OV8858_8BIT, 0x3508, 0x02}, /* long gain = 0x0200 */ 419 {OV8858_8BIT, 0x3509, 0x00}, /* long gain = 0x0200 */ 420 {OV8858_8BIT, 0x350C, 0x00}, /* short gain = 0x0080 */ 421 {OV8858_8BIT, 0x350D, 0x80}, /* short gain = 0x0080 */ 422 {OV8858_8BIT, 0x3510, 0x00}, /* short exposure = 0x000200 */ 423 {OV8858_8BIT, 0x3511, 0x02}, /* short exposure = 0x000200 */ 424 {OV8858_8BIT, 0x3512, 0x00}, /* short exposure = 0x000200 */ 425 426 {OV8858_8BIT, 0x3600, 0x00}, /* Unknown */ 427 {OV8858_8BIT, 0x3601, 0x00}, /* Unknown */ 428 {OV8858_8BIT, 0x3602, 0x00}, /* Unknown */ 429 {OV8858_8BIT, 0x3603, 0x00}, /* Unknown */ 430 {OV8858_8BIT, 0x3604, 0x22}, /* Unknown */ 431 {OV8858_8BIT, 0x3605, 0x30}, /* Unknown */ 432 {OV8858_8BIT, 0x3606, 0x00}, /* Unknown */ 433 {OV8858_8BIT, 0x3607, 0x20}, /* Unknown */ 434 {OV8858_8BIT, 0x3608, 0x11}, /* Unknown */ 435 {OV8858_8BIT, 0x3609, 0x28}, /* Unknown */ 436 {OV8858_8BIT, 0x360A, 0x00}, /* Unknown */ 437 {OV8858_8BIT, 0x360B, 0x06}, /* Unknown */ 438 {OV8858_8BIT, 0x360C, 0xDC}, /* Unknown */ 439 {OV8858_8BIT, 0x360D, 0x40}, /* Unknown */ 440 {OV8858_8BIT, 0x360E, 0x0C}, /* Unknown */ 441 {OV8858_8BIT, 0x360F, 0x20}, /* Unknown */ 442 {OV8858_8BIT, 0x3610, 0x07}, /* Unknown */ 443 {OV8858_8BIT, 0x3611, 0x20}, /* Unknown */ 444 {OV8858_8BIT, 0x3612, 0x88}, /* Unknown */ 445 {OV8858_8BIT, 0x3613, 0x80}, /* Unknown */ 446 {OV8858_8BIT, 0x3614, 0x58}, /* Unknown */ 447 {OV8858_8BIT, 0x3615, 0x00}, /* Unknown */ 448 {OV8858_8BIT, 0x3616, 0x4A}, /* Unknown */ 449 {OV8858_8BIT, 0x3617, 0x90}, /* Unknown */ 450 {OV8858_8BIT, 0x3618, 0x56}, /* Unknown */ 451 {OV8858_8BIT, 0x3619, 0x70}, /* Unknown */ 452 {OV8858_8BIT, 0x361A, 0x99}, /* Unknown */ 453 {OV8858_8BIT, 0x361B, 0x00}, /* Unknown */ 454 {OV8858_8BIT, 0x361C, 0x07}, /* Unknown */ 455 {OV8858_8BIT, 0x361D, 0x00}, /* Unknown */ 456 {OV8858_8BIT, 0x361E, 0x00}, /* Unknown */ 457 {OV8858_8BIT, 0x361F, 0x00}, /* Unknown */ 458 {OV8858_8BIT, 0x3633, 0x0C}, /* Unknown */ 459 {OV8858_8BIT, 0x3634, 0x0C}, /* Unknown */ 460 {OV8858_8BIT, 0x3635, 0x0C}, /* Unknown */ 461 {OV8858_8BIT, 0x3636, 0x0C}, /* Unknown */ 462 {OV8858_8BIT, 0x3638, 0xFF}, /* Unknown */ 463 {OV8858_8BIT, 0x3645, 0x13}, /* Unknown */ 464 {OV8858_8BIT, 0x3646, 0x83}, /* Unknown */ 465 {OV8858_8BIT, 0x364A, 0x07}, /* Unknown */ 466 467 {OV8858_8BIT, 0x3700, 0x30}, /* Unknown */ 468 {OV8858_8BIT, 0x3701, 0x18}, /* Unknown */ 469 {OV8858_8BIT, 0x3702, 0x50}, /* Unknown */ 470 {OV8858_8BIT, 0x3703, 0x32}, /* Unknown */ 471 {OV8858_8BIT, 0x3704, 0x28}, /* Unknown */ 472 {OV8858_8BIT, 0x3705, 0x00}, /* Unknown */ 473 {OV8858_8BIT, 0x3706, 0x6A}, /* Unknown */ 474 {OV8858_8BIT, 0x3707, 0x08}, /* Unknown */ 475 {OV8858_8BIT, 0x3708, 0x48}, /* Unknown */ 476 {OV8858_8BIT, 0x3709, 0x66}, /* Unknown */ 477 {OV8858_8BIT, 0x370A, 0x01}, /* Unknown */ 478 {OV8858_8BIT, 0x370B, 0x6A}, /* Unknown */ 479 {OV8858_8BIT, 0x370C, 0x07}, /* Unknown */ 480 {OV8858_8BIT, 0x3712, 0x44}, /* Unknown */ 481 {OV8858_8BIT, 0x3714, 0x24}, /* Unknown */ 482 {OV8858_8BIT, 0x3718, 0x14}, /* Unknown */ 483 {OV8858_8BIT, 0x3719, 0x31}, /* Unknown */ 484 {OV8858_8BIT, 0x371E, 0x31}, /* Unknown */ 485 {OV8858_8BIT, 0x371F, 0x7F}, /* Unknown */ 486 {OV8858_8BIT, 0x3720, 0x0A}, /* Unknown */ 487 {OV8858_8BIT, 0x3721, 0x0A}, /* Unknown */ 488 {OV8858_8BIT, 0x3724, 0x0C}, /* Unknown */ 489 {OV8858_8BIT, 0x3725, 0x02}, /* Unknown */ 490 {OV8858_8BIT, 0x3726, 0x0C}, /* Unknown */ 491 {OV8858_8BIT, 0x3728, 0x0A}, /* Unknown */ 492 {OV8858_8BIT, 0x3729, 0x03}, /* Unknown */ 493 {OV8858_8BIT, 0x372A, 0x06}, /* Unknown */ 494 {OV8858_8BIT, 0x372B, 0xA6}, /* Unknown */ 495 {OV8858_8BIT, 0x372C, 0xA6}, /* Unknown */ 496 {OV8858_8BIT, 0x372D, 0xA6}, /* Unknown */ 497 {OV8858_8BIT, 0x372E, 0x0C}, /* Unknown */ 498 {OV8858_8BIT, 0x372F, 0x20}, /* Unknown */ 499 {OV8858_8BIT, 0x3730, 0x02}, /* Unknown */ 500 {OV8858_8BIT, 0x3731, 0x0C}, /* Unknown */ 501 {OV8858_8BIT, 0x3732, 0x28}, /* Unknown */ 502 {OV8858_8BIT, 0x3733, 0x10}, /* Unknown */ 503 {OV8858_8BIT, 0x3734, 0x40}, /* Unknown */ 504 {OV8858_8BIT, 0x3736, 0x30}, /* Unknown */ 505 {OV8858_8BIT, 0x373A, 0x0A}, /* Unknown */ 506 {OV8858_8BIT, 0x373B, 0x0B}, /* Unknown */ 507 {OV8858_8BIT, 0x373C, 0x14}, /* Unknown */ 508 {OV8858_8BIT, 0x373E, 0x06}, /* Unknown */ 509 {OV8858_8BIT, 0x3755, 0x10}, /* Unknown */ 510 {OV8858_8BIT, 0x3758, 0x00}, /* Unknown */ 511 {OV8858_8BIT, 0x3759, 0x4C}, /* Unknown */ 512 {OV8858_8BIT, 0x375A, 0x0C}, /* Unknown */ 513 {OV8858_8BIT, 0x375B, 0x26}, /* Unknown */ 514 {OV8858_8BIT, 0x375C, 0x20}, /* Unknown */ 515 {OV8858_8BIT, 0x375D, 0x04}, /* Unknown */ 516 {OV8858_8BIT, 0x375E, 0x00}, /* Unknown */ 517 {OV8858_8BIT, 0x375F, 0x28}, /* Unknown */ 518 {OV8858_8BIT, 0x3760, 0x00}, /* Unknown */ 519 {OV8858_8BIT, 0x3761, 0x00}, /* Unknown */ 520 {OV8858_8BIT, 0x3762, 0x00}, /* Unknown */ 521 {OV8858_8BIT, 0x3763, 0x00}, /* Unknown */ 522 {OV8858_8BIT, 0x3766, 0xFF}, /* Unknown */ 523 {OV8858_8BIT, 0x3768, 0x22}, /* Unknown */ 524 {OV8858_8BIT, 0x3769, 0x44}, /* Unknown */ 525 {OV8858_8BIT, 0x376A, 0x44}, /* Unknown */ 526 {OV8858_8BIT, 0x376B, 0x00}, /* Unknown */ 527 {OV8858_8BIT, 0x376F, 0x01}, /* Unknown */ 528 {OV8858_8BIT, 0x3772, 0x46}, /* Unknown */ 529 {OV8858_8BIT, 0x3773, 0x04}, /* Unknown */ 530 {OV8858_8BIT, 0x3774, 0x2C}, /* Unknown */ 531 {OV8858_8BIT, 0x3775, 0x13}, /* Unknown */ 532 {OV8858_8BIT, 0x3776, 0x08}, /* Unknown */ 533 {OV8858_8BIT, 0x3777, 0x00}, /* Unknown */ 534 {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ 535 {OV8858_8BIT, 0x37A0, 0x88}, /* Unknown */ 536 {OV8858_8BIT, 0x37A1, 0x7A}, /* Unknown */ 537 {OV8858_8BIT, 0x37A2, 0x7A}, /* Unknown */ 538 {OV8858_8BIT, 0x37A3, 0x00}, /* Unknown */ 539 {OV8858_8BIT, 0x37A4, 0x00}, /* Unknown */ 540 {OV8858_8BIT, 0x37A5, 0x00}, /* Unknown */ 541 {OV8858_8BIT, 0x37A6, 0x00}, /* Unknown */ 542 {OV8858_8BIT, 0x37A7, 0x88}, /* Unknown */ 543 {OV8858_8BIT, 0x37A8, 0x98}, /* Unknown */ 544 {OV8858_8BIT, 0x37A9, 0x98}, /* Unknown */ 545 {OV8858_8BIT, 0x37AA, 0x88}, /* Unknown */ 546 {OV8858_8BIT, 0x37AB, 0x5C}, /* Unknown */ 547 {OV8858_8BIT, 0x37AC, 0x5C}, /* Unknown */ 548 {OV8858_8BIT, 0x37AD, 0x55}, /* Unknown */ 549 {OV8858_8BIT, 0x37AE, 0x19}, /* Unknown */ 550 {OV8858_8BIT, 0x37AF, 0x19}, /* Unknown */ 551 {OV8858_8BIT, 0x37B0, 0x00}, /* Unknown */ 552 {OV8858_8BIT, 0x37B1, 0x00}, /* Unknown */ 553 {OV8858_8BIT, 0x37B2, 0x00}, /* Unknown */ 554 {OV8858_8BIT, 0x37B3, 0x84}, /* Unknown */ 555 {OV8858_8BIT, 0x37B4, 0x84}, /* Unknown */ 556 {OV8858_8BIT, 0x37B5, 0x66}, /* Unknown */ 557 {OV8858_8BIT, 0x37B6, 0x00}, /* Unknown */ 558 {OV8858_8BIT, 0x37B7, 0x00}, /* Unknown */ 559 {OV8858_8BIT, 0x37B8, 0x00}, /* Unknown */ 560 {OV8858_8BIT, 0x37B9, 0xFF}, /* Unknown */ 561 562 {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ 563 {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low */ 564 {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ 565 {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ 566 {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ 567 {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ 568 {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ 569 {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ 570 {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high */ 571 {OV8858_8BIT, 0x3809, 0xC0}, /* h_output_size low */ 572 {OV8858_8BIT, 0x380A, 0x09}, /* v_output_size high */ 573 {OV8858_8BIT, 0x380B, 0x90}, /* v_output_size low */ 574 {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ 575 {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ 576 {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ 577 {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ 578 {OV8858_8BIT, 0x3810, 0x00}, /* h_win offset high */ 579 {OV8858_8BIT, 0x3811, 0x04}, /* h_win offset low */ 580 {OV8858_8BIT, 0x3812, 0x00}, /* v_win offset high */ 581 {OV8858_8BIT, 0x3813, 0x02}, /* v_win offset low */ 582 {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ 583 {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ 584 {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ 585 {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ 586 {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ 587 {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ 588 589 {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ 590 {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ 591 {OV8858_8BIT, 0x3837, 0x18}, /* Unknown */ 592 {OV8858_8BIT, 0x3841, 0xFF}, /* AUTO_SIZE_CTRL */ 593 {OV8858_8BIT, 0x3846, 0x48}, /* Unknown */ 594 595 {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ 596 {OV8858_8BIT, 0x3D8C, 0x73}, /* OTP_SETTING_STT_ADDRESS */ 597 {OV8858_8BIT, 0x3D8D, 0xDE}, /* OTP_SETTING_STT_ADDRESS */ 598 {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ 599 {OV8858_8BIT, 0x3F0A, 0x80}, /* PSRAM control register */ 600 601 {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ 602 {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */ 603 {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ 604 {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ 605 {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ 606 {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ 607 {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ 608 {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ 609 {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ 610 {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ 611 {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ 612 {OV8858_8BIT, 0x4022, 0x0B}, /* Anchor left end = 0x0BC3 */ 613 {OV8858_8BIT, 0x4023, 0xC3}, /* Anchor left end = 0x0BC3 */ 614 {OV8858_8BIT, 0x4024, 0x0C}, /* Anchor right start = 0x0C36 */ 615 {OV8858_8BIT, 0x4025, 0x36}, /* Anchor right start = 0x0C36 */ 616 {OV8858_8BIT, 0x4026, 0x0C}, /* Anchor right end = 0x0C37 */ 617 {OV8858_8BIT, 0x4027, 0x37}, /* Anchor right end = 0x0C37 */ 618 {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ 619 {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ 620 {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ 621 {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */ 622 {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ 623 {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ 624 {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */ 625 {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ 626 627 {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ 628 {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ 629 {OV8858_8BIT, 0x4300, 0xFF}, /* clip_max[11:4] = 0xFFF */ 630 {OV8858_8BIT, 0x4301, 0x00}, /* clip_min[11:4] = 0 */ 631 {OV8858_8BIT, 0x4302, 0x0F}, /* clip_min/max[3:0] */ 632 {OV8858_8BIT, 0x4307, 0x01}, /* Unknown */ 633 {OV8858_8BIT, 0x4316, 0x00}, /* CTRL16 = default */ 634 {OV8858_8BIT, 0x4503, 0x18}, /* Unknown */ 635 {OV8858_8BIT, 0x4500, 0x38}, /* Unknown */ 636 {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ 637 {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ 638 /* wkup_dly = Mark1 wakeup delay/2^10 = 0x25 */ 639 {OV8858_8BIT, 0x4808, 0x25}, 640 {OV8858_8BIT, 0x4816, 0x52}, /* Embedded data type*/ 641 {OV8858_8BIT, 0x481F, 0x32}, /* clk_prepare_min = 0x32 */ 642 {OV8858_8BIT, 0x4825, 0x3A}, /* lpx_p_min = 0x3A */ 643 {OV8858_8BIT, 0x4826, 0x40}, /* hs_prepare_min = 0x40 */ 644 {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ 645 {OV8858_8BIT, 0x4850, 0x10}, /* LANE SEL01 */ 646 {OV8858_8BIT, 0x4851, 0x32}, /* LANE SEL02 */ 647 648 {OV8858_8BIT, 0x4B00, 0x2A}, /* Unknown */ 649 {OV8858_8BIT, 0x4B0D, 0x00}, /* Unknown */ 650 {OV8858_8BIT, 0x4D00, 0x04}, /* TPM_CTRL_REG */ 651 {OV8858_8BIT, 0x4D01, 0x18}, /* TPM_CTRL_REG */ 652 {OV8858_8BIT, 0x4D02, 0xC3}, /* TPM_CTRL_REG */ 653 {OV8858_8BIT, 0x4D03, 0xFF}, /* TPM_CTRL_REG */ 654 {OV8858_8BIT, 0x4D04, 0xFF}, /* TPM_CTRL_REG */ 655 {OV8858_8BIT, 0x4D05, 0xFF}, /* TPM_CTRL_REG */ 656 657 /* 658 * Lens correction (LENC) function enable = 0 659 * Slave sensor AWB Gain function enable = 1 660 * Slave sensor AWB Statistics function enable = 1 661 * Master sensor AWB Gain function enable = 1 662 * Master sensor AWB Statistics function enable = 1 663 * Black DPC function enable = 1 664 * White DPC function enable =1 665 */ 666 {OV8858_8BIT, 0x5000, 0x7E}, 667 {OV8858_8BIT, 0x5001, 0x01}, /* BLC function enable = 1 */ 668 /* 669 * Horizontal scale function enable = 0 670 * WBMATCH bypass mode = Select slave sensor's gain 671 * WBMATCH function enable = 0 672 * Master MWB gain support RGBC = 0 673 * OTP_DPC function enable = 1 674 * Manual mode of VarioPixel function enable = 0 675 * Manual enable of VarioPixel function enable = 0 676 * Use VSYNC to latch ISP modules's function enable signals = 0 677 */ 678 {OV8858_8BIT, 0x5002, 0x08}, 679 /* 680 * Bypass all ISP modules after BLC module = 0 681 * DPC_DBC buffer control enable = 1 682 * WBMATCH VSYNC selection = Select master sensor's VSYNC fall 683 * Select master AWB gain to embed line = AWB gain before manual mode 684 * Enable BLC's input flip_i signal = 0 685 */ 686 {OV8858_8BIT, 0x5003, 0x20}, 687 {OV8858_8BIT, 0x5041, 0x1D}, /* ISP CTRL41 - embedded data=on */ 688 {OV8858_8BIT, 0x5046, 0x12}, /* ISP CTRL46 = default */ 689 /* 690 * Tail enable = 1 691 * Saturate cross cluster enable = 1 692 * Remove cross cluster enable = 1 693 * Enable to remove connected defect pixels in same channel = 1 694 * Enable to remove connected defect pixels in different channel = 1 695 * Smooth enable, use average G for recovery = 1 696 * Black/white sensor mode enable = 0 697 * Manual mode enable = 0 698 */ 699 {OV8858_8BIT, 0x5780, 0xFC}, 700 {OV8858_8BIT, 0x5784, 0x0C}, /* DPC CTRL04 */ 701 {OV8858_8BIT, 0x5787, 0x40}, /* DPC CTRL07 */ 702 {OV8858_8BIT, 0x5788, 0x08}, /* DPC CTRL08 */ 703 {OV8858_8BIT, 0x578A, 0x02}, /* DPC CTRL0A */ 704 {OV8858_8BIT, 0x578B, 0x01}, /* DPC CTRL0B */ 705 {OV8858_8BIT, 0x578C, 0x01}, /* DPC CTRL0C */ 706 {OV8858_8BIT, 0x578E, 0x02}, /* DPC CTRL0E */ 707 {OV8858_8BIT, 0x578F, 0x01}, /* DPC CTRL0F */ 708 {OV8858_8BIT, 0x5790, 0x01}, /* DPC CTRL10 */ 709 {OV8858_8BIT, 0x5901, 0x00}, /* VAP CTRL01 = default */ 710 /* WINC CTRL08 = embedded data in 1st line*/ 711 {OV8858_8BIT, 0x5A08, 0x00}, 712 {OV8858_8BIT, 0x5B00, 0x02}, /* OTP CTRL00 */ 713 {OV8858_8BIT, 0x5B01, 0x10}, /* OTP CTRL01 */ 714 {OV8858_8BIT, 0x5B02, 0x03}, /* OTP CTRL02 */ 715 {OV8858_8BIT, 0x5B03, 0xCF}, /* OTP CTRL03 */ 716 {OV8858_8BIT, 0x5B05, 0x6C}, /* OTP CTRL05 = default */ 717 {OV8858_8BIT, 0x5E00, 0x00}, /* PRE CTRL00 = default */ 718 {OV8858_8BIT, 0x5E01, 0x41}, /* PRE_CTRL01 = default */ 719 720 {OV8858_TOK_TERM, 0, 0} 721 }; 722 723 /*****************************STILL********************************/ 724 725 static const struct ov8858_reg ov8858_8M[] = { 726 {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ 727 {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ 728 {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ 729 {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low 12 */ 730 {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ 731 {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ 732 {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ 733 {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low 3283 */ 734 {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ 735 {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ 736 {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high 3280 x 2464 */ 737 {OV8858_8BIT, 0x3809, 0xD0}, /* h_output_size low */ 738 {OV8858_8BIT, 0x380A, 0x09}, /* v_output_size high */ 739 {OV8858_8BIT, 0x380B, 0xa0}, /* v_output_size low */ 740 {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ 741 {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ 742 {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ 743 {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ 744 {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ 745 {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ 746 {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ 747 {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ 748 {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ 749 {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ 750 {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ 751 {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ 752 {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ 753 {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ 754 {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ 755 {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */ 756 {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ 757 {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ 758 {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ 759 {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ 760 {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ 761 {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ 762 {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ 763 {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ 764 {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ 765 {OV8858_8BIT, 0x4022, 0x0B}, /* Anchor left end = 0x0BC3 */ 766 {OV8858_8BIT, 0x4023, 0xC3}, /* Anchor left end = 0x0BC3 */ 767 {OV8858_8BIT, 0x4024, 0x0C}, /* Anchor right start = 0x0C36 */ 768 {OV8858_8BIT, 0x4025, 0x36}, /* Anchor right start = 0x0C36 */ 769 {OV8858_8BIT, 0x4026, 0x0C}, /* Anchor right end = 0x0C37 */ 770 {OV8858_8BIT, 0x4027, 0x37}, /* Anchor right end = 0x0C37 */ 771 {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ 772 {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ 773 {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ 774 {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */ 775 {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ 776 {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ 777 {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */ 778 {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ 779 {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ 780 {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ 781 {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ 782 {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ 783 {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ 784 {OV8858_TOK_TERM, 0, 0} 785 }; 786 787 static const struct ov8858_reg ov8858_3276x1848[] = { 788 {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ 789 {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ 790 {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ 791 {OV8858_8BIT, 0x3801, 0x10}, /* h_crop_start low 0c->10*/ 792 {OV8858_8BIT, 0x3802, 0x01}, /* v_crop_start high */ 793 {OV8858_8BIT, 0x3803, 0x42}, /* v_crop_start low 3e->42*/ 794 {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ 795 {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ 796 {OV8858_8BIT, 0x3806, 0x08}, /* v_crop_end high */ 797 {OV8858_8BIT, 0x3807, 0x71}, /* v_crop_end low */ 798 {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high 3276 x 1848 */ 799 {OV8858_8BIT, 0x3809, 0xCC}, /* h_output_size low d0->cc*/ 800 {OV8858_8BIT, 0x380A, 0x07}, /* v_output_size high */ 801 {OV8858_8BIT, 0x380B, 0x38}, /* v_output_size low 3c->38*/ 802 {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ 803 {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ 804 {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ 805 {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ 806 {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ 807 {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ 808 {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ 809 {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ 810 {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ 811 {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ 812 {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ 813 {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ 814 {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ 815 {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ 816 {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ 817 {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */ 818 {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ 819 {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ 820 {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ 821 {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ 822 {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ 823 {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ 824 {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ 825 {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ 826 {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ 827 {OV8858_8BIT, 0x4022, 0x0B}, /* Anchor left end = 0x0BC3 */ 828 {OV8858_8BIT, 0x4023, 0xC3}, /* Anchor left end = 0x0BC3 */ 829 {OV8858_8BIT, 0x4024, 0x0C}, /* Anchor right start = 0x0C36 */ 830 {OV8858_8BIT, 0x4025, 0x36}, /* Anchor right start = 0x0C36 */ 831 {OV8858_8BIT, 0x4026, 0x0C}, /* Anchor right end = 0x0C37 */ 832 {OV8858_8BIT, 0x4027, 0x37}, /* Anchor right end = 0x0C37 */ 833 {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ 834 {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ 835 {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ 836 {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */ 837 {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ 838 {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ 839 {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */ 840 {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ 841 {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ 842 {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ 843 {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ 844 {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ 845 {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ 846 {OV8858_TOK_TERM, 0, 0} 847 }; 848 849 static const struct ov8858_reg ov8858_6M[] = { 850 {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ 851 {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ 852 {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ 853 {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low */ 854 {OV8858_8BIT, 0x3802, 0x01}, /* v_crop_start high */ 855 {OV8858_8BIT, 0x3803, 0x3E}, /* v_crop_start low */ 856 {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ 857 {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ 858 {OV8858_8BIT, 0x3806, 0x08}, /* v_crop_end high */ 859 {OV8858_8BIT, 0x3807, 0x71}, /* v_crop_end low */ 860 {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high 3280 x 1852 */ 861 {OV8858_8BIT, 0x3809, 0xD0}, /* h_output_size low */ 862 {OV8858_8BIT, 0x380A, 0x07}, /* v_output_size high */ 863 {OV8858_8BIT, 0x380B, 0x3C}, /* v_output_size low */ 864 {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ 865 {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ 866 {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ 867 {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ 868 {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ 869 {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ 870 {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ 871 {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ 872 {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ 873 {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ 874 {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ 875 {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ 876 {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ 877 {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ 878 {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ 879 {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */ 880 {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ 881 {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ 882 {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ 883 {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ 884 {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ 885 {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ 886 {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ 887 {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ 888 {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ 889 {OV8858_8BIT, 0x4022, 0x0B}, /* Anchor left end = 0x0BC3 */ 890 {OV8858_8BIT, 0x4023, 0xC3}, /* Anchor left end = 0x0BC3 */ 891 {OV8858_8BIT, 0x4024, 0x0C}, /* Anchor right start = 0x0C36 */ 892 {OV8858_8BIT, 0x4025, 0x36}, /* Anchor right start = 0x0C36 */ 893 {OV8858_8BIT, 0x4026, 0x0C}, /* Anchor right end = 0x0C37 */ 894 {OV8858_8BIT, 0x4027, 0x37}, /* Anchor right end = 0x0C37 */ 895 {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ 896 {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ 897 {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ 898 {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */ 899 {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ 900 {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ 901 {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */ 902 {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ 903 {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ 904 {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ 905 {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ 906 {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ 907 {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ 908 {OV8858_TOK_TERM, 0, 0} 909 }; 910 911 static const struct ov8858_reg ov8858_1080P_60[] = { 912 {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ 913 {OV8858_8BIT, 0x3778, 0x17}, /* Unknown */ 914 {OV8858_8BIT, 0x3800, 0x02}, /* h_crop_start high */ 915 {OV8858_8BIT, 0x3801, 0x26}, /* h_crop_start low */ 916 {OV8858_8BIT, 0x3802, 0x02}, /* v_crop_start high */ 917 {OV8858_8BIT, 0x3803, 0x8C}, /* v_crop_start low */ 918 {OV8858_8BIT, 0x3804, 0x0A}, /* h_crop_end high */ 919 {OV8858_8BIT, 0x3805, 0x9D}, /* h_crop_end low */ 920 {OV8858_8BIT, 0x3806, 0x07}, /* v_crop_end high */ 921 {OV8858_8BIT, 0x3807, 0x0A}, /* v_crop_end low */ 922 {OV8858_8BIT, 0x3808, 0x07}, /* h_output_size high*/ 923 {OV8858_8BIT, 0x3809, 0x90}, /* h_output_size low */ 924 {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ 925 {OV8858_8BIT, 0x380B, 0x48}, /* v_output_size low */ 926 {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ 927 {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ 928 {OV8858_8BIT, 0x380E, 0x04}, /* vertical timing size high */ 929 {OV8858_8BIT, 0x380F, 0xEC}, /* vertical timing size low */ 930 {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ 931 {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ 932 {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ 933 {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ 934 {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ 935 {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ 936 {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ 937 {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ 938 {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ 939 {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ 940 {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ 941 {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */ 942 {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ 943 {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ 944 {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ 945 {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ 946 {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ 947 {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ 948 {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ 949 {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ 950 {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ 951 {OV8858_8BIT, 0x4022, 0x07}, /* Anchor left end = 0x072D */ 952 {OV8858_8BIT, 0x4023, 0x2D}, /* Anchor left end = 0x072D */ 953 {OV8858_8BIT, 0x4024, 0x07}, /* Anchor right start = 0x079E */ 954 {OV8858_8BIT, 0x4025, 0x9E}, /* Anchor right start = 0x079E */ 955 {OV8858_8BIT, 0x4026, 0x07}, /* Anchor right end = 0x079F */ 956 {OV8858_8BIT, 0x4027, 0x9F}, /* Anchor right end = 0x079F */ 957 {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ 958 {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ 959 {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ 960 {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */ 961 {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ 962 {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ 963 {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */ 964 {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ 965 {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ 966 {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ 967 {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ 968 {OV8858_8BIT, 0x4601, 0xef}, /* Unknown */ 969 {OV8858_8BIT, 0x4837, 0x16}, /* pclk_period = 0x16 */ 970 {OV8858_TOK_TERM, 0, 0} 971 }; 972 973 static const struct ov8858_reg ov8858_1080P_30[] = { 974 {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ 975 {OV8858_8BIT, 0x3778, 0x17}, /* Unknown */ 976 {OV8858_8BIT, 0x3800, 0x02}, /* h_crop_start high */ 977 {OV8858_8BIT, 0x3801, 0x26}, /* h_crop_start low */ 978 {OV8858_8BIT, 0x3802, 0x02}, /* v_crop_start high */ 979 {OV8858_8BIT, 0x3803, 0x8C}, /* v_crop_start low */ 980 {OV8858_8BIT, 0x3804, 0x0A}, /* h_crop_end high */ 981 {OV8858_8BIT, 0x3805, 0x9D}, /* h_crop_end low */ 982 {OV8858_8BIT, 0x3806, 0x07}, /* v_crop_end high */ 983 {OV8858_8BIT, 0x3807, 0x0A}, /* v_crop_end low */ 984 {OV8858_8BIT, 0x3808, 0x07}, /* h_output_size high*/ 985 {OV8858_8BIT, 0x3809, 0x90}, /* h_output_size low */ 986 {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ 987 {OV8858_8BIT, 0x380B, 0x48}, /* v_output_size low */ 988 {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ 989 {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ 990 {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ 991 {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ 992 {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ 993 {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ 994 {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ 995 {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ 996 {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ 997 {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ 998 {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ 999 {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ 1000 {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ 1001 {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ 1002 {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ 1003 {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */ 1004 {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ 1005 {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ 1006 {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ 1007 {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ 1008 {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ 1009 {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ 1010 {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ 1011 {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ 1012 {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ 1013 {OV8858_8BIT, 0x4022, 0x07}, /* Anchor left end = 0x072D */ 1014 {OV8858_8BIT, 0x4023, 0x2D}, /* Anchor left end = 0x072D */ 1015 {OV8858_8BIT, 0x4024, 0x07}, /* Anchor right start = 0x079E */ 1016 {OV8858_8BIT, 0x4025, 0x9E}, /* Anchor right start = 0x079E */ 1017 {OV8858_8BIT, 0x4026, 0x07}, /* Anchor right end = 0x079F */ 1018 {OV8858_8BIT, 0x4027, 0x9F}, /* Anchor right end = 0x079F */ 1019 {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ 1020 {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ 1021 {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ 1022 {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */ 1023 {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ 1024 {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ 1025 {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */ 1026 {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ 1027 {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ 1028 {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ 1029 {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ 1030 {OV8858_8BIT, 0x4601, 0xef}, /* Unknown */ 1031 {OV8858_8BIT, 0x4837, 0x16}, /* pclk_period = 0x16 */ 1032 {OV8858_TOK_TERM, 0, 0} 1033 }; 1034 1035 static const struct ov8858_reg ov8858_1640x1232[] = { 1036 {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ 1037 {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ 1038 {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ 1039 {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low 12 */ 1040 {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ 1041 {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ 1042 {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high 3283 */ 1043 {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ 1044 {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ 1045 {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ 1046 {OV8858_8BIT, 0x3808, 0x06}, /* h_output_size high 1640 x 1232 */ 1047 {OV8858_8BIT, 0x3809, 0x68}, /* h_output_size low */ 1048 {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ 1049 {OV8858_8BIT, 0x380B, 0xD0}, /* v_output_size low */ 1050 {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ 1051 {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ 1052 {OV8858_8BIT, 0x380E, 0x09}, /* vertical timing size high */ 1053 {OV8858_8BIT, 0x380F, 0xAA}, /* vertical timing size low */ 1054 {OV8858_8BIT, 0x3814, 0x03}, /* h_odd_inc */ 1055 {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ 1056 {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ 1057 {OV8858_8BIT, 0x3821, 0x67}, /* format2 */ 1058 {OV8858_8BIT, 0x382A, 0x03}, /* v_odd_inc */ 1059 {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ 1060 {OV8858_8BIT, 0x3830, 0x08}, /* Unknown */ 1061 {OV8858_8BIT, 0x3836, 0x02}, /* Unknown */ 1062 {OV8858_8BIT, 0x3D85, 0x16}, /* OTP_REG85 */ 1063 {OV8858_8BIT, 0x3F08, 0x08}, /* PSRAM control register */ 1064 {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ 1065 {OV8858_8BIT, 0x4001, 0x10}, /* BLC CTRL01 */ 1066 {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ 1067 {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ 1068 {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ 1069 {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ 1070 {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ 1071 {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ 1072 {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ 1073 {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ 1074 {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ 1075 {OV8858_8BIT, 0x4022, 0x04}, /* Anchor left end = 0x04B9 */ 1076 {OV8858_8BIT, 0x4023, 0xB9}, /* Anchor left end = 0x04B9 */ 1077 {OV8858_8BIT, 0x4024, 0x05}, /* Anchor right start = 0x052A */ 1078 {OV8858_8BIT, 0x4025, 0x2A}, /* Anchor right start = 0x052A */ 1079 {OV8858_8BIT, 0x4026, 0x05}, /* Anchor right end = 0x052B */ 1080 {OV8858_8BIT, 0x4027, 0x2B}, /* Anchor right end = 0x052B */ 1081 {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ 1082 {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ 1083 {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ 1084 {OV8858_8BIT, 0x402B, 0x04}, /* Top black line number = 8 */ 1085 {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ 1086 {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ 1087 {OV8858_8BIT, 0x402E, 0x08}, /* Bottom black line start = 8 */ 1088 {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ 1089 {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ 1090 {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ 1091 {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ 1092 {OV8858_8BIT, 0x4601, 0xCB}, /* Unknown */ 1093 {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ 1094 {OV8858_TOK_TERM, 0, 0} 1095 }; 1096 1097 static const struct ov8858_reg ov8858_1640x1096[] = { 1098 {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ 1099 {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ 1100 {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ 1101 {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low 12 */ 1102 {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ 1103 {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ 1104 {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high 3283 */ 1105 {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ 1106 {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ 1107 {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ 1108 {OV8858_8BIT, 0x3808, 0x06}, /* h_output_size high 1640 x 1096 */ 1109 {OV8858_8BIT, 0x3809, 0x68}, /* h_output_size low */ 1110 {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ 1111 {OV8858_8BIT, 0x380B, 0x48}, /* v_output_size low */ 1112 {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ 1113 {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ 1114 {OV8858_8BIT, 0x380E, 0x09}, /* vertical timing size high */ 1115 {OV8858_8BIT, 0x380F, 0xAA}, /* vertical timing size low */ 1116 {OV8858_8BIT, 0x3814, 0x03}, /* h_odd_inc */ 1117 {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ 1118 {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ 1119 {OV8858_8BIT, 0x3821, 0x67}, /* format2 */ 1120 {OV8858_8BIT, 0x382A, 0x03}, /* v_odd_inc */ 1121 {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ 1122 {OV8858_8BIT, 0x3830, 0x08}, /* Unknown */ 1123 {OV8858_8BIT, 0x3836, 0x02}, /* Unknown */ 1124 {OV8858_8BIT, 0x3D85, 0x16}, /* OTP_REG85 */ 1125 {OV8858_8BIT, 0x3F08, 0x08}, /* PSRAM control register */ 1126 {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ 1127 {OV8858_8BIT, 0x4001, 0x10}, /* BLC CTRL01 */ 1128 {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ 1129 {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ 1130 {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ 1131 {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ 1132 {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ 1133 {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ 1134 {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ 1135 {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ 1136 {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ 1137 {OV8858_8BIT, 0x4022, 0x04}, /* Anchor left end = 0x04B9 */ 1138 {OV8858_8BIT, 0x4023, 0xB9}, /* Anchor left end = 0x04B9 */ 1139 {OV8858_8BIT, 0x4024, 0x05}, /* Anchor right start = 0x052A */ 1140 {OV8858_8BIT, 0x4025, 0x2A}, /* Anchor right start = 0x052A */ 1141 {OV8858_8BIT, 0x4026, 0x05}, /* Anchor right end = 0x052B */ 1142 {OV8858_8BIT, 0x4027, 0x2B}, /* Anchor right end = 0x052B */ 1143 {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ 1144 {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ 1145 {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ 1146 {OV8858_8BIT, 0x402B, 0x04}, /* Top black line number = 8 */ 1147 {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ 1148 {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ 1149 {OV8858_8BIT, 0x402E, 0x08}, /* Bottom black line start = 8 */ 1150 {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ 1151 {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ 1152 {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ 1153 {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ 1154 {OV8858_8BIT, 0x4601, 0xCB}, /* Unknown */ 1155 {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ 1156 {OV8858_TOK_TERM, 0, 0} 1157 }; 1158 1159 1160 static const struct ov8858_reg ov8858_1640x926[] = { 1161 {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ 1162 {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ 1163 {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ 1164 {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low */ 1165 {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ 1166 {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ 1167 {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ 1168 {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ 1169 {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ 1170 {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ 1171 {OV8858_8BIT, 0x3808, 0x06}, /* h_output_size high 1640 x 926 */ 1172 {OV8858_8BIT, 0x3809, 0x68}, /* h_output_size low */ 1173 {OV8858_8BIT, 0x380A, 0x03}, /* v_output_size high */ 1174 {OV8858_8BIT, 0x380B, 0x9E}, /* v_output_size low */ 1175 {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ 1176 {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ 1177 {OV8858_8BIT, 0x380E, 0x09}, /* vertical timing size high */ 1178 {OV8858_8BIT, 0x380F, 0xAA}, /* vertical timing size low */ 1179 {OV8858_8BIT, 0x3814, 0x03}, /* h_odd_inc */ 1180 {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ 1181 {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ 1182 {OV8858_8BIT, 0x3821, 0x67}, /* format2 */ 1183 {OV8858_8BIT, 0x382A, 0x03}, /* v_odd_inc */ 1184 {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ 1185 {OV8858_8BIT, 0x3830, 0x08}, /* Unknown */ 1186 {OV8858_8BIT, 0x3836, 0x02}, /* Unknown */ 1187 {OV8858_8BIT, 0x3D85, 0x16}, /* OTP_REG85 */ 1188 {OV8858_8BIT, 0x3F08, 0x08}, /* PSRAM control register */ 1189 {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ 1190 {OV8858_8BIT, 0x4001, 0x10}, /* BLC CTRL01 */ 1191 {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ 1192 {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ 1193 {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ 1194 {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ 1195 {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ 1196 {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ 1197 {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ 1198 {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ 1199 {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ 1200 {OV8858_8BIT, 0x4022, 0x04}, /* Anchor left end = 0x04B9 */ 1201 {OV8858_8BIT, 0x4023, 0xB9}, /* Anchor left end = 0x04B9 */ 1202 {OV8858_8BIT, 0x4024, 0x05}, /* Anchor right start = 0x052A */ 1203 {OV8858_8BIT, 0x4025, 0x2A}, /* Anchor right start = 0x052A */ 1204 {OV8858_8BIT, 0x4026, 0x05}, /* Anchor right end = 0x052B */ 1205 {OV8858_8BIT, 0x4027, 0x2B}, /* Anchor right end = 0x052B */ 1206 {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ 1207 {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ 1208 {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ 1209 {OV8858_8BIT, 0x402B, 0x04}, /* Top black line number = 8 */ 1210 {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ 1211 {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ 1212 {OV8858_8BIT, 0x402E, 0x08}, /* Bottom black line start = 8 */ 1213 {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ 1214 {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ 1215 {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ 1216 {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ 1217 {OV8858_8BIT, 0x4601, 0xCB}, /* Unknown */ 1218 {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ 1219 {OV8858_TOK_TERM, 0, 0} 1220 }; 1221 1222 static struct ov8858_resolution ov8858_res_preview[] = { 1223 { 1224 .desc = "ov8858_1640x926_PREVIEW", 1225 .width = 1640, 1226 .height = 926, 1227 .used = 0, 1228 .regs = ov8858_1640x926, 1229 .bin_factor_x = 0, 1230 .bin_factor_y = 0, 1231 .skip_frames = 0, 1232 .fps_options = { 1233 { 1234 .fps = 30, 1235 .pixels_per_line = 3880, 1236 .lines_per_frame = 2573, 1237 }, 1238 { 1239 } 1240 }, 1241 }, 1242 { 1243 .desc = "ov8858_1640x1232_PREVIEW", 1244 .width = 1640, 1245 .height = 1232, 1246 .used = 0, 1247 .regs = ov8858_1640x1232, 1248 .bin_factor_x = 0, 1249 .bin_factor_y = 0, 1250 .skip_frames = 0, 1251 .fps_options = { 1252 { 1253 .fps = 30, 1254 .pixels_per_line = 3880, 1255 .lines_per_frame = 2573, 1256 }, 1257 { 1258 } 1259 }, 1260 }, 1261 { 1262 .desc = "ov8858_3276x1848_PREVIEW", 1263 .width = 3276, 1264 .height = 1848, 1265 .used = 0, 1266 .regs = ov8858_3276x1848, 1267 .bin_factor_x = 0, 1268 .bin_factor_y = 0, 1269 .skip_frames = 0, 1270 .fps_options = { 1271 { 1272 .fps = 30, 1273 .pixels_per_line = 3880, 1274 .lines_per_frame = 2573, 1275 }, 1276 { 1277 } 1278 }, 1279 }, 1280 { 1281 .desc = "ov8858_8M_PREVIEW", 1282 .width = 3280, 1283 .height = 2464, 1284 .used = 0, 1285 .regs = ov8858_8M, 1286 .bin_factor_x = 0, 1287 .bin_factor_y = 0, 1288 .skip_frames = 0, 1289 .fps_options = { 1290 { 1291 .fps = 30, 1292 .pixels_per_line = 3880, 1293 .lines_per_frame = 2573, 1294 }, 1295 { 1296 } 1297 }, 1298 }, 1299 }; 1300 1301 static struct ov8858_resolution ov8858_res_still[] = { 1302 { 1303 .desc = "ov8858_1640x1232_STILL", 1304 .width = 1640, 1305 .height = 1232, 1306 .used = 0, 1307 .regs = ov8858_1640x1232, 1308 .bin_factor_x = 0, 1309 .bin_factor_y = 0, 1310 .skip_frames = 0, 1311 .fps_options = { 1312 { 1313 .fps = 30, 1314 .pixels_per_line = 3880, 1315 .lines_per_frame = 2573, 1316 }, 1317 { 1318 } 1319 }, 1320 }, 1321 { 1322 .desc = "ov8858_1640x926_STILL", 1323 .width = 1640, 1324 .height = 926, 1325 .used = 0, 1326 .regs = ov8858_1640x926, 1327 .bin_factor_x = 0, 1328 .bin_factor_y = 0, 1329 .skip_frames = 1, 1330 .fps_options = { 1331 { 1332 .fps = 30, 1333 .pixels_per_line = 3880, 1334 .lines_per_frame = 2573, 1335 }, 1336 { 1337 } 1338 }, 1339 }, 1340 { 1341 .desc = "ov8858_3276X1848_STILL", 1342 .width = 3276, 1343 .height = 1848, 1344 .used = 0, 1345 .regs = ov8858_3276x1848, 1346 .bin_factor_x = 0, 1347 .bin_factor_y = 0, 1348 .skip_frames = 1, 1349 .fps_options = { 1350 { 1351 .fps = 30, 1352 .pixels_per_line = 3880, 1353 .lines_per_frame = 2573, 1354 }, 1355 { 1356 } 1357 }, 1358 }, 1359 { 1360 .desc = "ov8858_8M_STILL", 1361 .width = 3280, 1362 .height = 2464, 1363 .used = 0, 1364 .regs = ov8858_8M, 1365 .bin_factor_x = 0, 1366 .bin_factor_y = 0, 1367 .skip_frames = 1, 1368 .fps_options = { 1369 { 1370 /* Pixel clock: 149.76MHZ */ 1371 .fps = 10, 1372 .pixels_per_line = 3880, 1373 .lines_per_frame = 3859, 1374 }, 1375 { 1376 } 1377 }, 1378 }, 1379 }; 1380 1381 static struct ov8858_resolution ov8858_res_video[] = { 1382 { 1383 .desc = "ov8858_1640x926_VIDEO", 1384 .width = 1640, 1385 .height = 926, 1386 .used = 0, 1387 .regs = ov8858_1640x926, 1388 .bin_factor_x = 0, 1389 .bin_factor_y = 0, 1390 .skip_frames = 1, 1391 .fps_options = { 1392 { 1393 .fps = 30, 1394 .pixels_per_line = 3880, 1395 .lines_per_frame = 2573, 1396 }, 1397 { 1398 } 1399 }, 1400 }, 1401 { 1402 .desc = "ov8858_1640x1232_VIDEO", 1403 .width = 1640, 1404 .height = 1232, 1405 .used = 0, 1406 .regs = ov8858_1640x1232, 1407 .bin_factor_x = 0, 1408 .bin_factor_y = 0, 1409 .skip_frames = 1, 1410 .fps_options = { 1411 { 1412 .fps = 30, 1413 .pixels_per_line = 3880, 1414 .lines_per_frame = 2573, 1415 }, 1416 { 1417 } 1418 }, 1419 }, 1420 { 1421 .desc = "ov8858_1640x1096_VIDEO", 1422 .width = 1640, 1423 .height = 1096, 1424 .used = 0, 1425 .regs = ov8858_1640x1096, 1426 .bin_factor_x = 0, 1427 .bin_factor_y = 0, 1428 .skip_frames = 1, 1429 .fps_options = { 1430 { 1431 .fps = 30, 1432 .pixels_per_line = 3880, 1433 .lines_per_frame = 2573, 1434 }, 1435 { 1436 } 1437 }, 1438 }, 1439 { 1440 .desc = "ov8858_6M_VIDEO", 1441 .width = 3280, 1442 .height = 1852, 1443 .used = 0, 1444 .regs = ov8858_6M, 1445 .bin_factor_x = 0, 1446 .bin_factor_y = 0, 1447 .skip_frames = 1, 1448 .fps_options = { 1449 { 1450 .fps = 30, 1451 .pixels_per_line = 3880, 1452 .lines_per_frame = 2573, 1453 }, 1454 { 1455 } 1456 }, 1457 }, 1458 { 1459 .desc = "ov8858_8M_VIDEO", 1460 .width = 3280, 1461 .height = 2464, 1462 .used = 0, 1463 .regs = ov8858_8M, 1464 .bin_factor_x = 0, 1465 .bin_factor_y = 0, 1466 .skip_frames = 1, 1467 .fps_options = { 1468 { 1469 .fps = 30, 1470 .pixels_per_line = 3880, 1471 .lines_per_frame = 2573, 1472 }, 1473 { 1474 } 1475 }, 1476 }, 1477 }; 1478 1479 #endif /* __OV8858_H__ */ 1480