1 /*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34 #include <linux/phy.h>
35 #include <linux/delay.h>
36 #include <linux/netdevice.h>
37 #include <linux/smp.h>
38 #include <linux/ethtool.h>
39 #include <linux/module.h>
40 #include <linux/etherdevice.h>
41 #include <linux/skbuff.h>
42 #include <linux/jiffies.h>
43 #include <linux/interrupt.h>
44 #include <linux/platform_device.h>
45
46 #include <asm/mipsregs.h>
47 /*
48 * fmn.h - For FMN credit configuration and registering fmn_handler.
49 * FMN is communication mechanism that allows processing agents within
50 * XLR/XLS to communicate each other.
51 */
52 #include <asm/netlogic/xlr/fmn.h>
53
54 #include "platform_net.h"
55 #include "xlr_net.h"
56
57 /*
58 * The readl/writel implementation byteswaps on XLR/XLS, so
59 * we need to use __raw_ IO to read the NAE registers
60 * because they are in the big-endian MMIO area on the SoC.
61 */
xlr_nae_wreg(u32 __iomem * base,unsigned int reg,u32 val)62 static inline void xlr_nae_wreg(u32 __iomem *base, unsigned int reg, u32 val)
63 {
64 __raw_writel(val, base + reg);
65 }
66
xlr_nae_rdreg(u32 __iomem * base,unsigned int reg)67 static inline u32 xlr_nae_rdreg(u32 __iomem *base, unsigned int reg)
68 {
69 return __raw_readl(base + reg);
70 }
71
xlr_reg_update(u32 * base_addr,u32 off,u32 val,u32 mask)72 static inline void xlr_reg_update(u32 *base_addr, u32 off, u32 val, u32 mask)
73 {
74 u32 tmp;
75
76 tmp = xlr_nae_rdreg(base_addr, off);
77 xlr_nae_wreg(base_addr, off, (tmp & ~mask) | (val & mask));
78 }
79
80 #define MAC_SKB_BACK_PTR_SIZE SMP_CACHE_BYTES
81
send_to_rfr_fifo(struct xlr_net_priv * priv,void * addr)82 static int send_to_rfr_fifo(struct xlr_net_priv *priv, void *addr)
83 {
84 struct nlm_fmn_msg msg;
85 int ret = 0, num_try = 0, stnid;
86 unsigned long paddr, mflags;
87
88 paddr = virt_to_bus(addr);
89 msg.msg0 = (u64)paddr & 0xffffffffe0ULL;
90 msg.msg1 = 0;
91 msg.msg2 = 0;
92 msg.msg3 = 0;
93 stnid = priv->nd->rfr_station;
94 do {
95 mflags = nlm_cop2_enable_irqsave();
96 ret = nlm_fmn_send(1, 0, stnid, &msg);
97 nlm_cop2_disable_irqrestore(mflags);
98 if (ret == 0)
99 return 0;
100 } while (++num_try < 10000);
101
102 netdev_err(priv->ndev, "Send to RFR failed in RX path\n");
103 return ret;
104 }
105
xlr_alloc_skb(void)106 static inline unsigned char *xlr_alloc_skb(void)
107 {
108 struct sk_buff *skb;
109 int buf_len = sizeof(struct sk_buff *);
110 unsigned char *skb_data;
111
112 /* skb->data is cache aligned */
113 skb = alloc_skb(XLR_RX_BUF_SIZE, GFP_ATOMIC);
114 if (!skb)
115 return NULL;
116 skb_data = skb->data;
117 skb_put(skb, MAC_SKB_BACK_PTR_SIZE);
118 skb_pull(skb, MAC_SKB_BACK_PTR_SIZE);
119 memcpy(skb_data, &skb, buf_len);
120
121 return skb->data;
122 }
123
xlr_net_fmn_handler(int bkt,int src_stnid,int size,int code,struct nlm_fmn_msg * msg,void * arg)124 static void xlr_net_fmn_handler(int bkt, int src_stnid, int size, int code,
125 struct nlm_fmn_msg *msg, void *arg)
126 {
127 struct sk_buff *skb;
128 void *skb_data = NULL;
129 struct net_device *ndev;
130 struct xlr_net_priv *priv;
131 u32 port, length;
132 unsigned char *addr;
133 struct xlr_adapter *adapter = arg;
134
135 length = (msg->msg0 >> 40) & 0x3fff;
136 if (length == 0) {
137 addr = bus_to_virt(msg->msg0 & 0xffffffffffULL);
138 addr = addr - MAC_SKB_BACK_PTR_SIZE;
139 skb = (struct sk_buff *)(*(unsigned long *)addr);
140 dev_kfree_skb_any((struct sk_buff *)addr);
141 } else {
142 addr = (unsigned char *)
143 bus_to_virt(msg->msg0 & 0xffffffffe0ULL);
144 length = length - BYTE_OFFSET - MAC_CRC_LEN;
145 port = ((int)msg->msg0) & 0x0f;
146 addr = addr - MAC_SKB_BACK_PTR_SIZE;
147 skb = (struct sk_buff *)(*(unsigned long *)addr);
148 skb->dev = adapter->netdev[port];
149 if (!skb->dev)
150 return;
151 ndev = skb->dev;
152 priv = netdev_priv(ndev);
153
154 /* 16 byte IP header align */
155 skb_reserve(skb, BYTE_OFFSET);
156 skb_put(skb, length);
157 skb->protocol = eth_type_trans(skb, skb->dev);
158 netif_rx(skb);
159 /* Fill rx ring */
160 skb_data = xlr_alloc_skb();
161 if (skb_data)
162 send_to_rfr_fifo(priv, skb_data);
163 }
164 }
165
xlr_get_phydev(struct xlr_net_priv * priv)166 static struct phy_device *xlr_get_phydev(struct xlr_net_priv *priv)
167 {
168 return mdiobus_get_phy(priv->mii_bus, priv->phy_addr);
169 }
170
171 /*
172 * Ethtool operation
173 */
xlr_get_link_ksettings(struct net_device * ndev,struct ethtool_link_ksettings * ecmd)174 static int xlr_get_link_ksettings(struct net_device *ndev,
175 struct ethtool_link_ksettings *ecmd)
176 {
177 struct xlr_net_priv *priv = netdev_priv(ndev);
178 struct phy_device *phydev = xlr_get_phydev(priv);
179
180 if (!phydev)
181 return -ENODEV;
182
183 phy_ethtool_ksettings_get(phydev, ecmd);
184
185 return 0;
186 }
187
xlr_set_link_ksettings(struct net_device * ndev,const struct ethtool_link_ksettings * ecmd)188 static int xlr_set_link_ksettings(struct net_device *ndev,
189 const struct ethtool_link_ksettings *ecmd)
190 {
191 struct xlr_net_priv *priv = netdev_priv(ndev);
192 struct phy_device *phydev = xlr_get_phydev(priv);
193
194 if (!phydev)
195 return -ENODEV;
196 return phy_ethtool_ksettings_set(phydev, ecmd);
197 }
198
199 static const struct ethtool_ops xlr_ethtool_ops = {
200 .get_link_ksettings = xlr_get_link_ksettings,
201 .set_link_ksettings = xlr_set_link_ksettings,
202 };
203
204 /*
205 * Net operations
206 */
xlr_net_fill_rx_ring(struct net_device * ndev)207 static int xlr_net_fill_rx_ring(struct net_device *ndev)
208 {
209 void *skb_data;
210 struct xlr_net_priv *priv = netdev_priv(ndev);
211 int i;
212
213 for (i = 0; i < MAX_FRIN_SPILL / 4; i++) {
214 skb_data = xlr_alloc_skb();
215 if (!skb_data) {
216 netdev_err(ndev, "SKB allocation failed\n");
217 return -ENOMEM;
218 }
219 send_to_rfr_fifo(priv, skb_data);
220 }
221 netdev_info(ndev, "Rx ring setup done\n");
222 return 0;
223 }
224
xlr_net_open(struct net_device * ndev)225 static int xlr_net_open(struct net_device *ndev)
226 {
227 u32 err;
228 struct xlr_net_priv *priv = netdev_priv(ndev);
229 struct phy_device *phydev = xlr_get_phydev(priv);
230
231 /* schedule a link state check */
232 phy_start(phydev);
233
234 err = phy_start_aneg(phydev);
235 if (err) {
236 pr_err("Autoneg failed\n");
237 return err;
238 }
239 /* Setup the speed from PHY to internal reg*/
240 xlr_set_gmac_speed(priv);
241
242 netif_tx_start_all_queues(ndev);
243
244 return 0;
245 }
246
xlr_net_stop(struct net_device * ndev)247 static int xlr_net_stop(struct net_device *ndev)
248 {
249 struct xlr_net_priv *priv = netdev_priv(ndev);
250 struct phy_device *phydev = xlr_get_phydev(priv);
251
252 phy_stop(phydev);
253 netif_tx_stop_all_queues(ndev);
254 return 0;
255 }
256
xlr_make_tx_desc(struct nlm_fmn_msg * msg,unsigned long addr,struct sk_buff * skb)257 static void xlr_make_tx_desc(struct nlm_fmn_msg *msg, unsigned long addr,
258 struct sk_buff *skb)
259 {
260 unsigned long physkb = virt_to_phys(skb);
261 int cpu_core = nlm_core_id();
262 int fr_stn_id = cpu_core * 8 + XLR_FB_STN; /* FB to 6th bucket */
263
264 msg->msg0 = (((u64)1 << 63) | /* End of packet descriptor */
265 ((u64)127 << 54) | /* No Free back */
266 (u64)skb->len << 40 | /* Length of data */
267 ((u64)addr));
268 msg->msg1 = (((u64)1 << 63) |
269 ((u64)fr_stn_id << 54) | /* Free back id */
270 (u64)0 << 40 | /* Set len to 0 */
271 ((u64)physkb & 0xffffffff)); /* 32bit address */
272 msg->msg2 = 0;
273 msg->msg3 = 0;
274 }
275
xlr_net_start_xmit(struct sk_buff * skb,struct net_device * ndev)276 static netdev_tx_t xlr_net_start_xmit(struct sk_buff *skb,
277 struct net_device *ndev)
278 {
279 struct nlm_fmn_msg msg;
280 struct xlr_net_priv *priv = netdev_priv(ndev);
281 int ret;
282 u32 flags;
283
284 xlr_make_tx_desc(&msg, virt_to_phys(skb->data), skb);
285 flags = nlm_cop2_enable_irqsave();
286 ret = nlm_fmn_send(2, 0, priv->tx_stnid, &msg);
287 nlm_cop2_disable_irqrestore(flags);
288 if (ret)
289 dev_kfree_skb_any(skb);
290 return NETDEV_TX_OK;
291 }
292
xlr_net_select_queue(struct net_device * ndev,struct sk_buff * skb,void * accel_priv,select_queue_fallback_t fallback)293 static u16 xlr_net_select_queue(struct net_device *ndev, struct sk_buff *skb,
294 void *accel_priv,
295 select_queue_fallback_t fallback)
296 {
297 return (u16)smp_processor_id();
298 }
299
xlr_hw_set_mac_addr(struct net_device * ndev)300 static void xlr_hw_set_mac_addr(struct net_device *ndev)
301 {
302 struct xlr_net_priv *priv = netdev_priv(ndev);
303
304 /* set mac station address */
305 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0,
306 ((ndev->dev_addr[5] << 24) | (ndev->dev_addr[4] << 16) |
307 (ndev->dev_addr[3] << 8) | (ndev->dev_addr[2])));
308 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0 + 1,
309 ((ndev->dev_addr[1] << 24) | (ndev->dev_addr[0] << 16)));
310
311 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2, 0xffffffff);
312 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2 + 1, 0xffffffff);
313 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3, 0xffffffff);
314 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3 + 1, 0xffffffff);
315
316 xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG,
317 (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
318 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
319 (1 << O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID));
320
321 if (priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII ||
322 priv->nd->phy_interface == PHY_INTERFACE_MODE_SGMII)
323 xlr_reg_update(priv->base_addr, R_IPG_IFG, MAC_B2B_IPG, 0x7f);
324 }
325
xlr_net_set_mac_addr(struct net_device * ndev,void * data)326 static int xlr_net_set_mac_addr(struct net_device *ndev, void *data)
327 {
328 int err;
329
330 err = eth_mac_addr(ndev, data);
331 if (err)
332 return err;
333 xlr_hw_set_mac_addr(ndev);
334 return 0;
335 }
336
xlr_set_rx_mode(struct net_device * ndev)337 static void xlr_set_rx_mode(struct net_device *ndev)
338 {
339 struct xlr_net_priv *priv = netdev_priv(ndev);
340 u32 regval;
341
342 regval = xlr_nae_rdreg(priv->base_addr, R_MAC_FILTER_CONFIG);
343
344 if (ndev->flags & IFF_PROMISC) {
345 regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
346 (1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
347 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
348 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN);
349 } else {
350 regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
351 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN));
352 }
353
354 xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, regval);
355 }
356
xlr_stats(struct net_device * ndev,struct rtnl_link_stats64 * stats)357 static void xlr_stats(struct net_device *ndev, struct rtnl_link_stats64 *stats)
358 {
359 struct xlr_net_priv *priv = netdev_priv(ndev);
360
361 stats->rx_packets = xlr_nae_rdreg(priv->base_addr, RX_PACKET_COUNTER);
362 stats->tx_packets = xlr_nae_rdreg(priv->base_addr, TX_PACKET_COUNTER);
363 stats->rx_bytes = xlr_nae_rdreg(priv->base_addr, RX_BYTE_COUNTER);
364 stats->tx_bytes = xlr_nae_rdreg(priv->base_addr, TX_BYTE_COUNTER);
365 stats->tx_errors = xlr_nae_rdreg(priv->base_addr, TX_FCS_ERROR_COUNTER);
366 stats->rx_dropped = xlr_nae_rdreg(priv->base_addr,
367 RX_DROP_PACKET_COUNTER);
368 stats->tx_dropped = xlr_nae_rdreg(priv->base_addr,
369 TX_DROP_FRAME_COUNTER);
370
371 stats->multicast = xlr_nae_rdreg(priv->base_addr,
372 RX_MULTICAST_PACKET_COUNTER);
373 stats->collisions = xlr_nae_rdreg(priv->base_addr,
374 TX_TOTAL_COLLISION_COUNTER);
375
376 stats->rx_length_errors = xlr_nae_rdreg(priv->base_addr,
377 RX_FRAME_LENGTH_ERROR_COUNTER);
378 stats->rx_over_errors = xlr_nae_rdreg(priv->base_addr,
379 RX_DROP_PACKET_COUNTER);
380 stats->rx_crc_errors = xlr_nae_rdreg(priv->base_addr,
381 RX_FCS_ERROR_COUNTER);
382 stats->rx_frame_errors = xlr_nae_rdreg(priv->base_addr,
383 RX_ALIGNMENT_ERROR_COUNTER);
384
385 stats->rx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
386 RX_DROP_PACKET_COUNTER);
387 stats->rx_missed_errors = xlr_nae_rdreg(priv->base_addr,
388 RX_CARRIER_SENSE_ERROR_COUNTER);
389
390 stats->rx_errors = (stats->rx_over_errors + stats->rx_crc_errors +
391 stats->rx_frame_errors + stats->rx_fifo_errors +
392 stats->rx_missed_errors);
393
394 stats->tx_aborted_errors = xlr_nae_rdreg(priv->base_addr,
395 TX_EXCESSIVE_COLLISION_PACKET_COUNTER);
396 stats->tx_carrier_errors = xlr_nae_rdreg(priv->base_addr,
397 TX_DROP_FRAME_COUNTER);
398 stats->tx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
399 TX_DROP_FRAME_COUNTER);
400 }
401
402 static const struct net_device_ops xlr_netdev_ops = {
403 .ndo_open = xlr_net_open,
404 .ndo_stop = xlr_net_stop,
405 .ndo_start_xmit = xlr_net_start_xmit,
406 .ndo_select_queue = xlr_net_select_queue,
407 .ndo_set_mac_address = xlr_net_set_mac_addr,
408 .ndo_set_rx_mode = xlr_set_rx_mode,
409 .ndo_get_stats64 = xlr_stats,
410 };
411
412 /*
413 * Gmac init
414 */
xlr_config_spill(struct xlr_net_priv * priv,int reg_start_0,int reg_start_1,int reg_size,int size)415 static void *xlr_config_spill(struct xlr_net_priv *priv, int reg_start_0,
416 int reg_start_1, int reg_size, int size)
417 {
418 void *spill;
419 u32 *base;
420 unsigned long phys_addr;
421 u32 spill_size;
422
423 base = priv->base_addr;
424 spill_size = size;
425 spill = kmalloc(spill_size + SMP_CACHE_BYTES, GFP_ATOMIC);
426 if (!spill) {
427 pr_err("Unable to allocate memory for spill area!\n");
428 return ZERO_SIZE_PTR;
429 }
430
431 spill = PTR_ALIGN(spill, SMP_CACHE_BYTES);
432 phys_addr = virt_to_phys(spill);
433 dev_dbg(&priv->ndev->dev, "Allocated spill %d bytes at %lx\n",
434 size, phys_addr);
435 xlr_nae_wreg(base, reg_start_0, (phys_addr >> 5) & 0xffffffff);
436 xlr_nae_wreg(base, reg_start_1, ((u64)phys_addr >> 37) & 0x07);
437 xlr_nae_wreg(base, reg_size, spill_size);
438
439 return spill;
440 }
441
442 /*
443 * Configure the 6 FIFO's that are used by the network accelarator to
444 * communicate with the rest of the XLx device. 4 of the FIFO's are for
445 * packets from NA --> cpu (called Class FIFO's) and 2 are for feeding
446 * the NA with free descriptors.
447 */
xlr_config_fifo_spill_area(struct xlr_net_priv * priv)448 static void xlr_config_fifo_spill_area(struct xlr_net_priv *priv)
449 {
450 priv->frin_spill = xlr_config_spill(priv,
451 R_REG_FRIN_SPILL_MEM_START_0,
452 R_REG_FRIN_SPILL_MEM_START_1,
453 R_REG_FRIN_SPILL_MEM_SIZE,
454 MAX_FRIN_SPILL *
455 sizeof(u64));
456 priv->frout_spill = xlr_config_spill(priv,
457 R_FROUT_SPILL_MEM_START_0,
458 R_FROUT_SPILL_MEM_START_1,
459 R_FROUT_SPILL_MEM_SIZE,
460 MAX_FROUT_SPILL *
461 sizeof(u64));
462 priv->class_0_spill = xlr_config_spill(priv,
463 R_CLASS0_SPILL_MEM_START_0,
464 R_CLASS0_SPILL_MEM_START_1,
465 R_CLASS0_SPILL_MEM_SIZE,
466 MAX_CLASS_0_SPILL *
467 sizeof(u64));
468 priv->class_1_spill = xlr_config_spill(priv,
469 R_CLASS1_SPILL_MEM_START_0,
470 R_CLASS1_SPILL_MEM_START_1,
471 R_CLASS1_SPILL_MEM_SIZE,
472 MAX_CLASS_1_SPILL *
473 sizeof(u64));
474 priv->class_2_spill = xlr_config_spill(priv,
475 R_CLASS2_SPILL_MEM_START_0,
476 R_CLASS2_SPILL_MEM_START_1,
477 R_CLASS2_SPILL_MEM_SIZE,
478 MAX_CLASS_2_SPILL *
479 sizeof(u64));
480 priv->class_3_spill = xlr_config_spill(priv,
481 R_CLASS3_SPILL_MEM_START_0,
482 R_CLASS3_SPILL_MEM_START_1,
483 R_CLASS3_SPILL_MEM_SIZE,
484 MAX_CLASS_3_SPILL *
485 sizeof(u64));
486 }
487
488 /*
489 * Configure PDE to Round-Robin distribution of packets to the
490 * available cpu
491 */
xlr_config_pde(struct xlr_net_priv * priv)492 static void xlr_config_pde(struct xlr_net_priv *priv)
493 {
494 int i = 0;
495 u64 bkt_map = 0;
496
497 /* Each core has 8 buckets(station) */
498 for (i = 0; i < hweight32(priv->nd->cpu_mask); i++)
499 bkt_map |= (0xff << (i * 8));
500
501 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0, (bkt_map & 0xffffffff));
502 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0 + 1,
503 ((bkt_map >> 32) & 0xffffffff));
504
505 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1, (bkt_map & 0xffffffff));
506 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1 + 1,
507 ((bkt_map >> 32) & 0xffffffff));
508
509 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2, (bkt_map & 0xffffffff));
510 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2 + 1,
511 ((bkt_map >> 32) & 0xffffffff));
512
513 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3, (bkt_map & 0xffffffff));
514 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3 + 1,
515 ((bkt_map >> 32) & 0xffffffff));
516 }
517
518 /*
519 * Setup the Message ring credits, bucket size and other
520 * common configuration
521 */
xlr_config_common(struct xlr_net_priv * priv)522 static int xlr_config_common(struct xlr_net_priv *priv)
523 {
524 struct xlr_fmn_info *gmac = priv->nd->gmac_fmn_info;
525 int start_stn_id = gmac->start_stn_id;
526 int end_stn_id = gmac->end_stn_id;
527 int *bucket_size = priv->nd->bucket_size;
528 int i, j, err;
529
530 /* Setting non-core MsgBktSize(0x321 - 0x325) */
531 for (i = start_stn_id; i <= end_stn_id; i++) {
532 xlr_nae_wreg(priv->base_addr,
533 R_GMAC_RFR0_BUCKET_SIZE + i - start_stn_id,
534 bucket_size[i]);
535 }
536
537 /*
538 * Setting non-core Credit counter register
539 * Distributing Gmac's credit to CPU's
540 */
541 for (i = 0; i < 8; i++) {
542 for (j = 0; j < 8; j++)
543 xlr_nae_wreg(priv->base_addr,
544 (R_CC_CPU0_0 + (i * 8)) + j,
545 gmac->credit_config[(i * 8) + j]);
546 }
547
548 xlr_nae_wreg(priv->base_addr, R_MSG_TX_THRESHOLD, 3);
549 xlr_nae_wreg(priv->base_addr, R_DMACR0, 0xffffffff);
550 xlr_nae_wreg(priv->base_addr, R_DMACR1, 0xffffffff);
551 xlr_nae_wreg(priv->base_addr, R_DMACR2, 0xffffffff);
552 xlr_nae_wreg(priv->base_addr, R_DMACR3, 0xffffffff);
553 xlr_nae_wreg(priv->base_addr, R_FREEQCARVE, 0);
554
555 err = xlr_net_fill_rx_ring(priv->ndev);
556 if (err)
557 return err;
558 nlm_register_fmn_handler(start_stn_id, end_stn_id, xlr_net_fmn_handler,
559 priv->adapter);
560 return 0;
561 }
562
xlr_config_translate_table(struct xlr_net_priv * priv)563 static void xlr_config_translate_table(struct xlr_net_priv *priv)
564 {
565 u32 cpu_mask;
566 u32 val;
567 int bkts[32]; /* one bucket is assumed for each cpu */
568 int b1, b2, c1, c2, i, j, k;
569 int use_bkt;
570
571 use_bkt = 0;
572 cpu_mask = priv->nd->cpu_mask;
573
574 pr_info("Using %s-based distribution\n",
575 (use_bkt) ? "bucket" : "class");
576 j = 0;
577 for (i = 0; i < 32; i++) {
578 if ((1 << i) & cpu_mask) {
579 /* for each cpu, mark the 4+threadid bucket */
580 bkts[j] = ((i / 4) * 8) + (i % 4);
581 j++;
582 }
583 }
584
585 /*configure the 128 * 9 Translation table to send to available buckets*/
586 k = 0;
587 c1 = 3;
588 c2 = 0;
589 for (i = 0; i < 64; i++) {
590 /*
591 * On use_bkt set the b0, b1 are used, else
592 * the 4 classes are used, here implemented
593 * a logic to distribute the packets to the
594 * buckets equally or based on the class
595 */
596 c1 = (c1 + 1) & 3;
597 c2 = (c1 + 1) & 3;
598 b1 = bkts[k];
599 k = (k + 1) % j;
600 b2 = bkts[k];
601 k = (k + 1) % j;
602
603 val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) |
604 (c2 << 7) | (b2 << 1) | (use_bkt << 0));
605 dev_dbg(&priv->ndev->dev, "Table[%d] b1=%d b2=%d c1=%d c2=%d\n",
606 i, b1, b2, c1, c2);
607 xlr_nae_wreg(priv->base_addr, R_TRANSLATETABLE + i, val);
608 c1 = c2;
609 }
610 }
611
xlr_config_parser(struct xlr_net_priv * priv)612 static void xlr_config_parser(struct xlr_net_priv *priv)
613 {
614 u32 val;
615
616 /* Mark it as ETHERNET type */
617 xlr_nae_wreg(priv->base_addr, R_L2TYPE_0, 0x01);
618
619 /* Use 7bit CRChash for flow classification with 127 as CRC polynomial*/
620 xlr_nae_wreg(priv->base_addr, R_PARSERCONFIGREG,
621 ((0x7f << 8) | (1 << 1)));
622
623 /* configure the parser : L2 Type is configured in the bootloader */
624 /* extract IP: src, dest protocol */
625 xlr_nae_wreg(priv->base_addr, R_L3CTABLE,
626 (9 << 20) | (1 << 19) | (1 << 18) | (0x01 << 16) |
627 (0x0800 << 0));
628 xlr_nae_wreg(priv->base_addr, R_L3CTABLE + 1,
629 (9 << 25) | (1 << 21) | (12 << 14) | (4 << 10) |
630 (16 << 4) | 4);
631
632 /* Configure to extract SRC port and Dest port for TCP and UDP pkts */
633 xlr_nae_wreg(priv->base_addr, R_L4CTABLE, 6);
634 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 2, 17);
635 val = ((0 << 21) | (2 << 17) | (2 << 11) | (2 << 7));
636 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 1, val);
637 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 3, val);
638
639 xlr_config_translate_table(priv);
640 }
641
xlr_phy_write(u32 * base_addr,int phy_addr,int regnum,u16 val)642 static int xlr_phy_write(u32 *base_addr, int phy_addr, int regnum, u16 val)
643 {
644 unsigned long timeout, stoptime, checktime;
645 int timedout;
646
647 /* 100ms timeout*/
648 timeout = msecs_to_jiffies(100);
649 stoptime = jiffies + timeout;
650 timedout = 0;
651
652 xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS, (phy_addr << 8) | regnum);
653
654 /* Write the data which starts the write cycle */
655 xlr_nae_wreg(base_addr, R_MII_MGMT_WRITE_DATA, (u32)val);
656
657 /* poll for the read cycle to complete */
658 while (!timedout) {
659 checktime = jiffies;
660 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
661 break;
662 timedout = time_after(checktime, stoptime);
663 }
664 if (timedout) {
665 pr_info("Phy device write err: device busy");
666 return -EBUSY;
667 }
668
669 return 0;
670 }
671
xlr_phy_read(u32 * base_addr,int phy_addr,int regnum)672 static int xlr_phy_read(u32 *base_addr, int phy_addr, int regnum)
673 {
674 unsigned long timeout, stoptime, checktime;
675 int timedout;
676
677 /* 100ms timeout*/
678 timeout = msecs_to_jiffies(100);
679 stoptime = jiffies + timeout;
680 timedout = 0;
681
682 /* setup the phy reg to be used */
683 xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS,
684 (phy_addr << 8) | (regnum << 0));
685
686 /* Issue the read command */
687 xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND,
688 (1 << O_MII_MGMT_COMMAND__rstat));
689
690 /* poll for the read cycle to complete */
691 while (!timedout) {
692 checktime = jiffies;
693 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
694 break;
695 timedout = time_after(checktime, stoptime);
696 }
697 if (timedout) {
698 pr_info("Phy device read err: device busy");
699 return -EBUSY;
700 }
701
702 /* clear the read cycle */
703 xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND, 0);
704
705 /* Read the data */
706 return xlr_nae_rdreg(base_addr, R_MII_MGMT_STATUS);
707 }
708
xlr_mii_write(struct mii_bus * bus,int phy_addr,int regnum,u16 val)709 static int xlr_mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 val)
710 {
711 struct xlr_net_priv *priv = bus->priv;
712 int ret;
713
714 ret = xlr_phy_write(priv->mii_addr, phy_addr, regnum, val);
715 dev_dbg(&priv->ndev->dev, "mii_write phy %d : %d <- %x [%x]\n",
716 phy_addr, regnum, val, ret);
717 return ret;
718 }
719
xlr_mii_read(struct mii_bus * bus,int phy_addr,int regnum)720 static int xlr_mii_read(struct mii_bus *bus, int phy_addr, int regnum)
721 {
722 struct xlr_net_priv *priv = bus->priv;
723 int ret;
724
725 ret = xlr_phy_read(priv->mii_addr, phy_addr, regnum);
726 dev_dbg(&priv->ndev->dev, "mii_read phy %d : %d [%x]\n",
727 phy_addr, regnum, ret);
728 return ret;
729 }
730
731 /*
732 * XLR ports are RGMII. XLS ports are SGMII mostly except the port0,
733 * which can be configured either SGMII or RGMII, considered SGMII
734 * by default, if board setup to RGMII the port_type need to set
735 * accordingly.Serdes and PCS layer need to configured for SGMII
736 */
xlr_sgmii_init(struct xlr_net_priv * priv)737 static void xlr_sgmii_init(struct xlr_net_priv *priv)
738 {
739 int phy;
740
741 xlr_phy_write(priv->serdes_addr, 26, 0, 0x6DB0);
742 xlr_phy_write(priv->serdes_addr, 26, 1, 0xFFFF);
743 xlr_phy_write(priv->serdes_addr, 26, 2, 0xB6D0);
744 xlr_phy_write(priv->serdes_addr, 26, 3, 0x00FF);
745 xlr_phy_write(priv->serdes_addr, 26, 4, 0x0000);
746 xlr_phy_write(priv->serdes_addr, 26, 5, 0x0000);
747 xlr_phy_write(priv->serdes_addr, 26, 6, 0x0005);
748 xlr_phy_write(priv->serdes_addr, 26, 7, 0x0001);
749 xlr_phy_write(priv->serdes_addr, 26, 8, 0x0000);
750 xlr_phy_write(priv->serdes_addr, 26, 9, 0x0000);
751 xlr_phy_write(priv->serdes_addr, 26, 10, 0x0000);
752
753 /* program GPIO values for serdes init parameters */
754 xlr_nae_wreg(priv->gpio_addr, 0x20, 0x7e6802);
755 xlr_nae_wreg(priv->gpio_addr, 0x10, 0x7104);
756
757 xlr_nae_wreg(priv->gpio_addr, 0x22, 0x7e6802);
758 xlr_nae_wreg(priv->gpio_addr, 0x21, 0x7104);
759
760 /* enable autoneg - more magic */
761 phy = priv->phy_addr % 4 + 27;
762 xlr_phy_write(priv->pcs_addr, phy, 0, 0x1000);
763 xlr_phy_write(priv->pcs_addr, phy, 0, 0x0200);
764 }
765
xlr_set_gmac_speed(struct xlr_net_priv * priv)766 void xlr_set_gmac_speed(struct xlr_net_priv *priv)
767 {
768 struct phy_device *phydev = xlr_get_phydev(priv);
769 int speed;
770
771 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
772 xlr_sgmii_init(priv);
773
774 if (phydev->speed != priv->phy_speed) {
775 speed = phydev->speed;
776 if (speed == SPEED_1000) {
777 /* Set interface to Byte mode */
778 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
779 priv->phy_speed = speed;
780 } else if (speed == SPEED_100 || speed == SPEED_10) {
781 /* Set interface to Nibble mode */
782 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7117);
783 priv->phy_speed = speed;
784 }
785 /* Set SGMII speed in Interface control reg */
786 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
787 if (speed == SPEED_10)
788 xlr_nae_wreg(priv->base_addr,
789 R_INTERFACE_CONTROL,
790 SGMII_SPEED_10);
791 if (speed == SPEED_100)
792 xlr_nae_wreg(priv->base_addr,
793 R_INTERFACE_CONTROL,
794 SGMII_SPEED_100);
795 if (speed == SPEED_1000)
796 xlr_nae_wreg(priv->base_addr,
797 R_INTERFACE_CONTROL,
798 SGMII_SPEED_1000);
799 }
800 if (speed == SPEED_10)
801 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x2);
802 if (speed == SPEED_100)
803 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x1);
804 if (speed == SPEED_1000)
805 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x0);
806 }
807 pr_info("gmac%d : %dMbps\n", priv->port_id, priv->phy_speed);
808 }
809
xlr_gmac_link_adjust(struct net_device * ndev)810 static void xlr_gmac_link_adjust(struct net_device *ndev)
811 {
812 struct xlr_net_priv *priv = netdev_priv(ndev);
813 struct phy_device *phydev = xlr_get_phydev(priv);
814 u32 intreg;
815
816 intreg = xlr_nae_rdreg(priv->base_addr, R_INTREG);
817 if (phydev->link) {
818 if (phydev->speed != priv->phy_speed) {
819 xlr_set_gmac_speed(priv);
820 pr_info("gmac%d : Link up\n", priv->port_id);
821 }
822 } else {
823 xlr_set_gmac_speed(priv);
824 pr_info("gmac%d : Link down\n", priv->port_id);
825 }
826 }
827
xlr_mii_probe(struct xlr_net_priv * priv)828 static int xlr_mii_probe(struct xlr_net_priv *priv)
829 {
830 struct phy_device *phydev = xlr_get_phydev(priv);
831
832 if (!phydev) {
833 pr_err("no PHY found on phy_addr %d\n", priv->phy_addr);
834 return -ENODEV;
835 }
836
837 /* Attach MAC to PHY */
838 phydev = phy_connect(priv->ndev, phydev_name(phydev),
839 xlr_gmac_link_adjust, priv->nd->phy_interface);
840
841 if (IS_ERR(phydev)) {
842 pr_err("could not attach PHY\n");
843 return PTR_ERR(phydev);
844 }
845 phydev->supported &= (ADVERTISED_10baseT_Full
846 | ADVERTISED_10baseT_Half
847 | ADVERTISED_100baseT_Full
848 | ADVERTISED_100baseT_Half
849 | ADVERTISED_1000baseT_Full
850 | ADVERTISED_Autoneg
851 | ADVERTISED_MII);
852
853 phydev->advertising = phydev->supported;
854 phy_attached_info(phydev);
855 return 0;
856 }
857
xlr_setup_mdio(struct xlr_net_priv * priv,struct platform_device * pdev)858 static int xlr_setup_mdio(struct xlr_net_priv *priv,
859 struct platform_device *pdev)
860 {
861 int err;
862
863 priv->mii_bus = mdiobus_alloc();
864 if (!priv->mii_bus) {
865 pr_err("mdiobus alloc failed\n");
866 return -ENOMEM;
867 }
868
869 priv->mii_bus->priv = priv;
870 priv->mii_bus->name = "xlr-mdio";
871 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
872 priv->mii_bus->name, priv->port_id);
873 priv->mii_bus->read = xlr_mii_read;
874 priv->mii_bus->write = xlr_mii_write;
875 priv->mii_bus->parent = &pdev->dev;
876
877 /* Scan only the enabled address */
878 priv->mii_bus->phy_mask = ~(1 << priv->phy_addr);
879
880 /* setting clock divisor to 54 */
881 xlr_nae_wreg(priv->base_addr, R_MII_MGMT_CONFIG, 0x7);
882
883 err = mdiobus_register(priv->mii_bus);
884 if (err) {
885 mdiobus_free(priv->mii_bus);
886 pr_err("mdio bus registration failed\n");
887 return err;
888 }
889
890 pr_info("Registered mdio bus id : %s\n", priv->mii_bus->id);
891 err = xlr_mii_probe(priv);
892 if (err) {
893 mdiobus_free(priv->mii_bus);
894 return err;
895 }
896 return 0;
897 }
898
xlr_port_enable(struct xlr_net_priv * priv)899 static void xlr_port_enable(struct xlr_net_priv *priv)
900 {
901 u32 prid = (read_c0_prid() & 0xf000);
902
903 /* Setup MAC_CONFIG reg if (xls & rgmii) */
904 if ((prid == 0x8000 || prid == 0x4000 || prid == 0xc000) &&
905 priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII)
906 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
907 (1 << O_RX_CONTROL__RGMII),
908 (1 << O_RX_CONTROL__RGMII));
909
910 /* Rx Tx enable */
911 xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
912 ((1 << O_MAC_CONFIG_1__rxen) |
913 (1 << O_MAC_CONFIG_1__txen) |
914 (1 << O_MAC_CONFIG_1__rxfc) |
915 (1 << O_MAC_CONFIG_1__txfc)),
916 ((1 << O_MAC_CONFIG_1__rxen) |
917 (1 << O_MAC_CONFIG_1__txen) |
918 (1 << O_MAC_CONFIG_1__rxfc) |
919 (1 << O_MAC_CONFIG_1__txfc)));
920
921 /* Setup tx control reg */
922 xlr_reg_update(priv->base_addr, R_TX_CONTROL,
923 ((1 << O_TX_CONTROL__TXENABLE) |
924 (512 << O_TX_CONTROL__TXTHRESHOLD)), 0x3fff);
925
926 /* Setup rx control reg */
927 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
928 1 << O_RX_CONTROL__RXENABLE,
929 1 << O_RX_CONTROL__RXENABLE);
930 }
931
xlr_port_disable(struct xlr_net_priv * priv)932 static void xlr_port_disable(struct xlr_net_priv *priv)
933 {
934 /* Setup MAC_CONFIG reg */
935 /* Rx Tx disable*/
936 xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
937 ((1 << O_MAC_CONFIG_1__rxen) |
938 (1 << O_MAC_CONFIG_1__txen) |
939 (1 << O_MAC_CONFIG_1__rxfc) |
940 (1 << O_MAC_CONFIG_1__txfc)), 0x0);
941
942 /* Setup tx control reg */
943 xlr_reg_update(priv->base_addr, R_TX_CONTROL,
944 ((1 << O_TX_CONTROL__TXENABLE) |
945 (512 << O_TX_CONTROL__TXTHRESHOLD)), 0);
946
947 /* Setup rx control reg */
948 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
949 1 << O_RX_CONTROL__RXENABLE, 0);
950 }
951
952 /*
953 * Initialization of gmac
954 */
xlr_gmac_init(struct xlr_net_priv * priv,struct platform_device * pdev)955 static int xlr_gmac_init(struct xlr_net_priv *priv,
956 struct platform_device *pdev)
957 {
958 int ret;
959
960 pr_info("Initializing the gmac%d\n", priv->port_id);
961
962 xlr_port_disable(priv);
963
964 xlr_nae_wreg(priv->base_addr, R_DESC_PACK_CTRL,
965 (1 << O_DESC_PACK_CTRL__MAXENTRY) |
966 (BYTE_OFFSET << O_DESC_PACK_CTRL__BYTEOFFSET) |
967 (1600 << O_DESC_PACK_CTRL__REGULARSIZE));
968
969 ret = xlr_setup_mdio(priv, pdev);
970 if (ret)
971 return ret;
972 xlr_port_enable(priv);
973
974 /* Enable Full-duplex/1000Mbps/CRC */
975 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
976 /* speed 2.5Mhz */
977 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x02);
978 /* Setup Interrupt mask reg */
979 xlr_nae_wreg(priv->base_addr, R_INTMASK, (1 << O_INTMASK__TXILLEGAL) |
980 (1 << O_INTMASK__MDINT) | (1 << O_INTMASK__TXFETCHERROR) |
981 (1 << O_INTMASK__P2PSPILLECC) | (1 << O_INTMASK__TAGFULL) |
982 (1 << O_INTMASK__UNDERRUN) | (1 << O_INTMASK__ABORT));
983
984 /* Clear all stats */
985 xlr_reg_update(priv->base_addr, R_STATCTRL, 0, 1 << O_STATCTRL__CLRCNT);
986 xlr_reg_update(priv->base_addr, R_STATCTRL, 1 << 2, 1 << 2);
987 return 0;
988 }
989
xlr_net_probe(struct platform_device * pdev)990 static int xlr_net_probe(struct platform_device *pdev)
991 {
992 struct xlr_net_priv *priv = NULL;
993 struct net_device *ndev;
994 struct resource *res;
995 struct xlr_adapter *adapter;
996 int err, port;
997
998 pr_info("XLR/XLS Ethernet Driver controller %d\n", pdev->id);
999 /*
1000 * Allocate our adapter data structure and attach it to the device.
1001 */
1002 adapter = (struct xlr_adapter *)
1003 devm_kzalloc(&pdev->dev, sizeof(*adapter), GFP_KERNEL);
1004 if (!adapter)
1005 return -ENOMEM;
1006
1007 /*
1008 * XLR and XLS have 1 and 2 NAE controller respectively
1009 * Each controller has 4 gmac ports, mapping each controller
1010 * under one parent device, 4 gmac ports under one device.
1011 */
1012 for (port = 0; port < pdev->num_resources / 2; port++) {
1013 ndev = alloc_etherdev_mq(sizeof(struct xlr_net_priv), 32);
1014 if (!ndev) {
1015 dev_err(&pdev->dev,
1016 "Allocation of Ethernet device failed\n");
1017 return -ENOMEM;
1018 }
1019
1020 priv = netdev_priv(ndev);
1021 priv->pdev = pdev;
1022 priv->ndev = ndev;
1023 priv->port_id = (pdev->id * 4) + port;
1024 priv->nd = (struct xlr_net_data *)pdev->dev.platform_data;
1025 res = platform_get_resource(pdev, IORESOURCE_MEM, port);
1026 priv->base_addr = devm_ioremap_resource(&pdev->dev, res);
1027 if (IS_ERR(priv->base_addr)) {
1028 err = PTR_ERR(priv->base_addr);
1029 goto err_gmac;
1030 }
1031 priv->adapter = adapter;
1032 adapter->netdev[port] = ndev;
1033
1034 res = platform_get_resource(pdev, IORESOURCE_IRQ, port);
1035 if (!res) {
1036 dev_err(&pdev->dev, "No irq resource for MAC %d\n",
1037 priv->port_id);
1038 err = -ENODEV;
1039 goto err_gmac;
1040 }
1041
1042 ndev->irq = res->start;
1043
1044 priv->phy_addr = priv->nd->phy_addr[port];
1045 priv->tx_stnid = priv->nd->tx_stnid[port];
1046 priv->mii_addr = priv->nd->mii_addr;
1047 priv->serdes_addr = priv->nd->serdes_addr;
1048 priv->pcs_addr = priv->nd->pcs_addr;
1049 priv->gpio_addr = priv->nd->gpio_addr;
1050
1051 ndev->netdev_ops = &xlr_netdev_ops;
1052 ndev->watchdog_timeo = HZ;
1053
1054 /* Setup Mac address and Rx mode */
1055 eth_hw_addr_random(ndev);
1056 xlr_hw_set_mac_addr(ndev);
1057 xlr_set_rx_mode(ndev);
1058
1059 priv->num_rx_desc += MAX_NUM_DESC_SPILL;
1060 ndev->ethtool_ops = &xlr_ethtool_ops;
1061 SET_NETDEV_DEV(ndev, &pdev->dev);
1062
1063 xlr_config_fifo_spill_area(priv);
1064 /* Configure PDE to Round-Robin pkt distribution */
1065 xlr_config_pde(priv);
1066 xlr_config_parser(priv);
1067
1068 /* Call init with respect to port */
1069 if (strcmp(res->name, "gmac") == 0) {
1070 err = xlr_gmac_init(priv, pdev);
1071 if (err) {
1072 dev_err(&pdev->dev, "gmac%d init failed\n",
1073 priv->port_id);
1074 goto err_gmac;
1075 }
1076 }
1077
1078 if (priv->port_id == 0 || priv->port_id == 4) {
1079 err = xlr_config_common(priv);
1080 if (err)
1081 goto err_netdev;
1082 }
1083
1084 err = register_netdev(ndev);
1085 if (err) {
1086 dev_err(&pdev->dev,
1087 "Registering netdev failed for gmac%d\n",
1088 priv->port_id);
1089 goto err_netdev;
1090 }
1091 platform_set_drvdata(pdev, priv);
1092 }
1093
1094 return 0;
1095
1096 err_netdev:
1097 mdiobus_free(priv->mii_bus);
1098 err_gmac:
1099 free_netdev(ndev);
1100 return err;
1101 }
1102
xlr_net_remove(struct platform_device * pdev)1103 static int xlr_net_remove(struct platform_device *pdev)
1104 {
1105 struct xlr_net_priv *priv = platform_get_drvdata(pdev);
1106
1107 unregister_netdev(priv->ndev);
1108 mdiobus_unregister(priv->mii_bus);
1109 mdiobus_free(priv->mii_bus);
1110 free_netdev(priv->ndev);
1111 return 0;
1112 }
1113
1114 static struct platform_driver xlr_net_driver = {
1115 .probe = xlr_net_probe,
1116 .remove = xlr_net_remove,
1117 .driver = {
1118 .name = "xlr-net",
1119 },
1120 };
1121
1122 module_platform_driver(xlr_net_driver);
1123
1124 MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
1125 MODULE_DESCRIPTION("Ethernet driver for Netlogic XLR/XLS");
1126 MODULE_LICENSE("Dual BSD/GPL");
1127 MODULE_ALIAS("platform:xlr-net");
1128