1 /*
2 * abstraction of the spi interface of HopeRf rf69 radio module
3 *
4 * Copyright (C) 2016 Wolf-Entwicklungen
5 * Marcus Wolf <linux@wolf-entwicklungen.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 /* enable prosa debug info */
19 #undef DEBUG
20 /* enable print of values on reg access */
21 #undef DEBUG_VALUES
22 /* enable print of values on fifo access */
23 #undef DEBUG_FIFO_ACCESS
24
25 #include <linux/types.h>
26 #include <linux/spi/spi.h>
27
28 #include "rf69.h"
29 #include "rf69_registers.h"
30
31 #define F_OSC 32000000 /* in Hz */
32 #define FIFO_SIZE 66 /* in byte */
33
34 /*-------------------------------------------------------------------------*/
35
36 #define READ_REG(x) rf69_read_reg (spi, x)
37 #define WRITE_REG(x,y) rf69_write_reg(spi, x, y)
38
39 /*-------------------------------------------------------------------------*/
40
rf69_set_mode(struct spi_device * spi,enum mode mode)41 int rf69_set_mode(struct spi_device *spi, enum mode mode)
42 {
43 #ifdef DEBUG
44 dev_dbg(&spi->dev, "set: mode");
45 #endif
46
47 switch (mode) {
48 case transmit: return WRITE_REG(REG_OPMODE, (READ_REG(REG_OPMODE) & ~MASK_OPMODE_MODE) | OPMODE_MODE_TRANSMIT);
49 case receive: return WRITE_REG(REG_OPMODE, (READ_REG(REG_OPMODE) & ~MASK_OPMODE_MODE) | OPMODE_MODE_RECEIVE);
50 case synthesizer: return WRITE_REG(REG_OPMODE, (READ_REG(REG_OPMODE) & ~MASK_OPMODE_MODE) | OPMODE_MODE_SYNTHESIZER);
51 case standby: return WRITE_REG(REG_OPMODE, (READ_REG(REG_OPMODE) & ~MASK_OPMODE_MODE) | OPMODE_MODE_STANDBY);
52 case mode_sleep: return WRITE_REG(REG_OPMODE, (READ_REG(REG_OPMODE) & ~MASK_OPMODE_MODE) | OPMODE_MODE_SLEEP);
53 default:
54 dev_dbg(&spi->dev, "set: illegal input param");
55 return -EINVAL;
56 }
57
58 // we are using packet mode, so this check is not really needed
59 // but waiting for mode ready is necessary when going from sleep because the FIFO may not be immediately available from previous mode
60 //while (_mode == RF69_MODE_SLEEP && (READ_REG(REG_IRQFLAGS1) & RF_IRQFLAGS1_MODEREADY) == 0x00); // Wait for ModeReady
61
62 }
63
rf69_set_data_mode(struct spi_device * spi,enum dataMode dataMode)64 int rf69_set_data_mode(struct spi_device *spi, enum dataMode dataMode)
65 {
66 #ifdef DEBUG
67 dev_dbg(&spi->dev, "set: data mode");
68 #endif
69
70 switch (dataMode) {
71 case packet: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODE) | DATAMODUL_MODE_PACKET);
72 case continuous: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODE) | DATAMODUL_MODE_CONTINUOUS);
73 case continuousNoSync: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODE) | DATAMODUL_MODE_CONTINUOUS_NOSYNC);
74 default:
75 dev_dbg(&spi->dev, "set: illegal input param");
76 return -EINVAL;
77 }
78 }
79
rf69_set_modulation(struct spi_device * spi,enum modulation modulation)80 int rf69_set_modulation(struct spi_device *spi, enum modulation modulation)
81 {
82 #ifdef DEBUG
83 dev_dbg(&spi->dev, "set: modulation");
84 #endif
85
86 switch (modulation) {
87 case OOK: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_TYPE) | DATAMODUL_MODULATION_TYPE_OOK);
88 case FSK: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_TYPE) | DATAMODUL_MODULATION_TYPE_FSK);
89 default:
90 dev_dbg(&spi->dev, "set: illegal input param");
91 return -EINVAL;
92 }
93 }
94
rf69_get_modulation(struct spi_device * spi)95 enum modulation rf69_get_modulation(struct spi_device *spi)
96 {
97 u8 currentValue;
98
99 #ifdef DEBUG
100 dev_dbg(&spi->dev, "get: mode");
101 #endif
102
103 currentValue = READ_REG(REG_DATAMODUL);
104
105 switch (currentValue & MASK_DATAMODUL_MODULATION_TYPE >> 3) { // TODO improvement: change 3 to define
106 case DATAMODUL_MODULATION_TYPE_OOK: return OOK;
107 case DATAMODUL_MODULATION_TYPE_FSK: return FSK;
108 default: return undefined;
109 }
110 }
111
rf69_set_modulation_shaping(struct spi_device * spi,enum modShaping modShaping)112 int rf69_set_modulation_shaping(struct spi_device *spi, enum modShaping modShaping)
113 {
114 #ifdef DEBUG
115 dev_dbg(&spi->dev, "set: mod shaping");
116 #endif
117
118 if (rf69_get_modulation(spi) == FSK) {
119 switch (modShaping) {
120 case shapingOff: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_SHAPE) | DATAMODUL_MODULATION_SHAPE_NONE);
121 case shaping1_0: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_SHAPE) | DATAMODUL_MODULATION_SHAPE_1_0);
122 case shaping0_5: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_SHAPE) | DATAMODUL_MODULATION_SHAPE_0_3);
123 case shaping0_3: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_SHAPE) | DATAMODUL_MODULATION_SHAPE_0_5);
124 default:
125 dev_dbg(&spi->dev, "set: illegal input param");
126 return -EINVAL;
127 }
128 } else {
129 switch (modShaping) {
130 case shapingOff: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_SHAPE) | DATAMODUL_MODULATION_SHAPE_NONE);
131 case shapingBR: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_SHAPE) | DATAMODUL_MODULATION_SHAPE_BR);
132 case shaping2BR: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_SHAPE) | DATAMODUL_MODULATION_SHAPE_2BR);
133 default:
134 dev_dbg(&spi->dev, "set: illegal input param");
135 return -EINVAL;
136 }
137 }
138 }
139
rf69_set_bit_rate(struct spi_device * spi,u16 bitRate)140 int rf69_set_bit_rate(struct spi_device *spi, u16 bitRate)
141 {
142 int retval;
143 u32 bitRate_min;
144 u32 bitRate_reg;
145 u8 msb;
146 u8 lsb;
147
148 #ifdef DEBUG
149 dev_dbg(&spi->dev, "set: bit rate");
150 #endif
151
152 // check input value
153 bitRate_min = F_OSC / 8388608; // 8388608 = 2^23;
154 if (bitRate < bitRate_min) {
155 dev_dbg(&spi->dev, "setBitRate: illegal input param");
156 return -EINVAL;
157 }
158
159 // calculate reg settings
160 bitRate_reg = (F_OSC / bitRate);
161
162 msb = (bitRate_reg&0xff00) >> 8;
163 lsb = (bitRate_reg&0xff);
164
165 // transmit to RF 69
166 retval = WRITE_REG(REG_BITRATE_MSB, msb);
167 if (retval) return retval;
168 retval = WRITE_REG(REG_BITRATE_LSB, lsb);
169 if (retval) return retval;
170
171 return 0;
172 }
173
rf69_set_deviation(struct spi_device * spi,u32 deviation)174 int rf69_set_deviation(struct spi_device *spi, u32 deviation)
175 {
176 int retval;
177 // u32 f_max; TODO: Abh�ngigkeit von Bitrate beachten!!
178 u64 f_reg;
179 u64 f_step;
180 u8 msb;
181 u8 lsb;
182 u64 factor = 1000000; // to improve precision of calculation
183
184 #ifdef DEBUG
185 dev_dbg(&spi->dev, "set: deviation");
186 #endif
187
188 if (deviation < 600 || deviation > 500000) { //TODO: Abh�ngigkeit von Bitrate beachten!!
189 dev_dbg(&spi->dev, "set_deviation: illegal input param");
190 return -EINVAL;
191 }
192
193 // calculat f step
194 f_step = F_OSC * factor;
195 do_div(f_step, 524288); // 524288 = 2^19
196
197 // calculate register settings
198 f_reg = deviation * factor;
199 do_div(f_reg , f_step);
200
201 msb = (f_reg&0xff00) >> 8;
202 lsb = (f_reg&0xff);
203
204 // check msb
205 if (msb & ~FDEVMASB_MASK) {
206 dev_dbg(&spi->dev, "set_deviation: err in calc of msb");
207 return -EINVAL;
208 }
209
210 // write to chip
211 retval = WRITE_REG(REG_FDEV_MSB, msb);
212 if (retval) return retval;
213 retval = WRITE_REG(REG_FDEV_LSB, lsb);
214 if (retval) return retval;
215
216 return 0;
217 }
218
rf69_set_frequency(struct spi_device * spi,u32 frequency)219 int rf69_set_frequency(struct spi_device *spi, u32 frequency)
220 {
221 int retval;
222 u32 f_max;
223 u64 f_reg;
224 u64 f_step;
225 u8 msb;
226 u8 mid;
227 u8 lsb;
228 u64 factor = 1000000; // to improve precision of calculation
229
230 #ifdef DEBUG
231 dev_dbg(&spi->dev, "set: frequency");
232 #endif
233
234 // calculat f step
235 f_step = F_OSC * factor;
236 do_div(f_step, 524288); // 524288 = 2^19
237
238 // check input value
239 f_max = div_u64(f_step * 8388608, factor);
240 if (frequency > f_max) {
241 dev_dbg(&spi->dev, "setFrequency: illegal input param");
242 return -EINVAL;
243 }
244
245 // calculate reg settings
246 f_reg = frequency * factor;
247 do_div(f_reg , f_step);
248
249 msb = (f_reg&0xff0000) >> 16;
250 mid = (f_reg&0xff00) >> 8;
251 lsb = (f_reg&0xff);
252
253 // write to chip
254 retval = WRITE_REG(REG_FRF_MSB, msb);
255 if (retval) return retval;
256 retval = WRITE_REG(REG_FRF_MID, mid);
257 if (retval) return retval;
258 retval = WRITE_REG(REG_FRF_LSB, lsb);
259 if (retval) return retval;
260
261 return 0;
262 }
263
rf69_set_amplifier_0(struct spi_device * spi,enum optionOnOff optionOnOff)264 int rf69_set_amplifier_0(struct spi_device *spi, enum optionOnOff optionOnOff)
265 {
266 #ifdef DEBUG
267 dev_dbg(&spi->dev, "set: amp #0");
268 #endif
269
270 switch(optionOnOff) {
271 case optionOn: return WRITE_REG(REG_PALEVEL, (READ_REG(REG_PALEVEL) | MASK_PALEVEL_PA0) );
272 case optionOff: return WRITE_REG(REG_PALEVEL, (READ_REG(REG_PALEVEL) & ~MASK_PALEVEL_PA0) );
273 default:
274 dev_dbg(&spi->dev, "set: illegal input param");
275 return -EINVAL;
276 }
277 }
278
rf69_set_amplifier_1(struct spi_device * spi,enum optionOnOff optionOnOff)279 int rf69_set_amplifier_1(struct spi_device *spi, enum optionOnOff optionOnOff)
280 {
281 #ifdef DEBUG
282 dev_dbg(&spi->dev, "set: amp #1");
283 #endif
284
285 switch(optionOnOff) {
286 case optionOn: return WRITE_REG(REG_PALEVEL, (READ_REG(REG_PALEVEL) | MASK_PALEVEL_PA1) );
287 case optionOff: return WRITE_REG(REG_PALEVEL, (READ_REG(REG_PALEVEL) & ~MASK_PALEVEL_PA1) );
288 default:
289 dev_dbg(&spi->dev, "set: illegal input param");
290 return -EINVAL;
291 }
292 }
293
rf69_set_amplifier_2(struct spi_device * spi,enum optionOnOff optionOnOff)294 int rf69_set_amplifier_2(struct spi_device *spi, enum optionOnOff optionOnOff)
295 {
296 #ifdef DEBUG
297 dev_dbg(&spi->dev, "set: amp #2");
298 #endif
299
300 switch(optionOnOff) {
301 case optionOn: return WRITE_REG(REG_PALEVEL, (READ_REG(REG_PALEVEL) | MASK_PALEVEL_PA2) );
302 case optionOff: return WRITE_REG(REG_PALEVEL, (READ_REG(REG_PALEVEL) & ~MASK_PALEVEL_PA2) );
303 default:
304 dev_dbg(&spi->dev, "set: illegal input param");
305 return -EINVAL;
306 }
307 }
308
rf69_set_output_power_level(struct spi_device * spi,u8 powerLevel)309 int rf69_set_output_power_level(struct spi_device *spi, u8 powerLevel)
310 {
311 #ifdef DEBUG
312 dev_dbg(&spi->dev, "set: power level");
313 #endif
314
315 powerLevel +=18; // TODO Abh�ngigkeit von PA0,1,2 setting
316
317 // check input value
318 if (powerLevel > 0x1f) {
319 dev_dbg(&spi->dev, "set: illegal input param");
320 return -EINVAL;
321 }
322
323 // write value
324 return WRITE_REG(REG_PALEVEL, (READ_REG(REG_PALEVEL) & ~MASK_PALEVEL_OUTPUT_POWER) | powerLevel);
325 }
326
rf69_set_pa_ramp(struct spi_device * spi,enum paRamp paRamp)327 int rf69_set_pa_ramp(struct spi_device *spi, enum paRamp paRamp)
328 {
329 #ifdef DEBUG
330 dev_dbg(&spi->dev, "set: pa ramp");
331 #endif
332
333 switch(paRamp) {
334 case ramp3400: return WRITE_REG(REG_PARAMP, PARAMP_3400);
335 case ramp2000: return WRITE_REG(REG_PARAMP, PARAMP_2000);
336 case ramp1000: return WRITE_REG(REG_PARAMP, PARAMP_1000);
337 case ramp500: return WRITE_REG(REG_PARAMP, PARAMP_500);
338 case ramp250: return WRITE_REG(REG_PARAMP, PARAMP_250);
339 case ramp125: return WRITE_REG(REG_PARAMP, PARAMP_125);
340 case ramp100: return WRITE_REG(REG_PARAMP, PARAMP_100);
341 case ramp62: return WRITE_REG(REG_PARAMP, PARAMP_62);
342 case ramp50: return WRITE_REG(REG_PARAMP, PARAMP_50);
343 case ramp40: return WRITE_REG(REG_PARAMP, PARAMP_40);
344 case ramp31: return WRITE_REG(REG_PARAMP, PARAMP_31);
345 case ramp25: return WRITE_REG(REG_PARAMP, PARAMP_25);
346 case ramp20: return WRITE_REG(REG_PARAMP, PARAMP_20);
347 case ramp15: return WRITE_REG(REG_PARAMP, PARAMP_15);
348 case ramp12: return WRITE_REG(REG_PARAMP, PARAMP_12);
349 case ramp10: return WRITE_REG(REG_PARAMP, PARAMP_10);
350 default:
351 dev_dbg(&spi->dev, "set: illegal input param");
352 return -EINVAL;
353 }
354 }
355
rf69_set_antenna_impedance(struct spi_device * spi,enum antennaImpedance antennaImpedance)356 int rf69_set_antenna_impedance(struct spi_device *spi, enum antennaImpedance antennaImpedance)
357 {
358 #ifdef DEBUG
359 dev_dbg(&spi->dev, "set: antenna impedance");
360 #endif
361
362 switch(antennaImpedance) {
363 case fiftyOhm: return WRITE_REG(REG_LNA, (READ_REG(REG_LNA) & ~MASK_LNA_ZIN) );
364 case twohundretOhm: return WRITE_REG(REG_LNA, (READ_REG(REG_LNA) | MASK_LNA_ZIN) );
365 default:
366 dev_dbg(&spi->dev, "set: illegal input param");
367 return -EINVAL;
368 }
369 }
370
rf69_set_lna_gain(struct spi_device * spi,enum lnaGain lnaGain)371 int rf69_set_lna_gain(struct spi_device *spi, enum lnaGain lnaGain)
372 {
373 #ifdef DEBUG
374 dev_dbg(&spi->dev, "set: lna gain");
375 #endif
376
377 switch(lnaGain) {
378 case automatic: return WRITE_REG(REG_LNA, ( (READ_REG(REG_LNA) & ~MASK_LNA_GAIN) & LNA_GAIN_AUTO) );
379 case max: return WRITE_REG(REG_LNA, ( (READ_REG(REG_LNA) & ~MASK_LNA_GAIN) & LNA_GAIN_MAX) );
380 case maxMinus6: return WRITE_REG(REG_LNA, ( (READ_REG(REG_LNA) & ~MASK_LNA_GAIN) & LNA_GAIN_MAX_MINUS_6) );
381 case maxMinus12: return WRITE_REG(REG_LNA, ( (READ_REG(REG_LNA) & ~MASK_LNA_GAIN) & LNA_GAIN_MAX_MINUS_12) );
382 case maxMinus24: return WRITE_REG(REG_LNA, ( (READ_REG(REG_LNA) & ~MASK_LNA_GAIN) & LNA_GAIN_MAX_MINUS_24) );
383 case maxMinus36: return WRITE_REG(REG_LNA, ( (READ_REG(REG_LNA) & ~MASK_LNA_GAIN) & LNA_GAIN_MAX_MINUS_36) );
384 case maxMinus48: return WRITE_REG(REG_LNA, ( (READ_REG(REG_LNA) & ~MASK_LNA_GAIN) & LNA_GAIN_MAX_MINUS_48) );
385 default:
386 dev_dbg(&spi->dev, "set: illegal input param");
387 return -EINVAL;
388 }
389 }
390
rf69_get_lna_gain(struct spi_device * spi)391 enum lnaGain rf69_get_lna_gain(struct spi_device *spi)
392 {
393 u8 currentValue;
394
395 #ifdef DEBUG
396 dev_dbg(&spi->dev, "get: lna gain");
397 #endif
398
399 currentValue = READ_REG(REG_LNA);
400
401 switch (currentValue & MASK_LNA_CURRENT_GAIN >> 3) { // improvement: change 3 to define
402 case LNA_GAIN_AUTO: return automatic;
403 case LNA_GAIN_MAX: return max;
404 case LNA_GAIN_MAX_MINUS_6: return maxMinus6;
405 case LNA_GAIN_MAX_MINUS_12: return maxMinus12;
406 case LNA_GAIN_MAX_MINUS_24: return maxMinus24;
407 case LNA_GAIN_MAX_MINUS_36: return maxMinus36;
408 case LNA_GAIN_MAX_MINUS_48: return maxMinus48;
409 default: return undefined;
410 }
411 }
412
rf69_set_dc_cut_off_frequency_intern(struct spi_device * spi,u8 reg,enum dccPercent dccPercent)413 int rf69_set_dc_cut_off_frequency_intern(struct spi_device *spi ,u8 reg, enum dccPercent dccPercent)
414 {
415 switch (dccPercent) {
416 case dcc16Percent: return WRITE_REG(reg, ( (READ_REG(reg) & ~MASK_BW_DCC_FREQ) | BW_DCC_16_PERCENT) );
417 case dcc8Percent: return WRITE_REG(reg, ( (READ_REG(reg) & ~MASK_BW_DCC_FREQ) | BW_DCC_8_PERCENT) );
418 case dcc4Percent: return WRITE_REG(reg, ( (READ_REG(reg) & ~MASK_BW_DCC_FREQ) | BW_DCC_4_PERCENT) );
419 case dcc2Percent: return WRITE_REG(reg, ( (READ_REG(reg) & ~MASK_BW_DCC_FREQ) | BW_DCC_2_PERCENT) );
420 case dcc1Percent: return WRITE_REG(reg, ( (READ_REG(reg) & ~MASK_BW_DCC_FREQ) | BW_DCC_1_PERCENT) );
421 case dcc0_5Percent: return WRITE_REG(reg, ( (READ_REG(reg) & ~MASK_BW_DCC_FREQ) | BW_DCC_0_5_PERCENT) );
422 case dcc0_25Percent: return WRITE_REG(reg, ( (READ_REG(reg) & ~MASK_BW_DCC_FREQ) | BW_DCC_0_25_PERCENT) );
423 case dcc0_125Percent: return WRITE_REG(reg, ( (READ_REG(reg) & ~MASK_BW_DCC_FREQ) | BW_DCC_0_125_PERCENT) );
424 default:
425 dev_dbg(&spi->dev, "set: illegal input param");
426 return -EINVAL;
427 }
428 }
429
rf69_set_dc_cut_off_frequency(struct spi_device * spi,enum dccPercent dccPercent)430 int rf69_set_dc_cut_off_frequency(struct spi_device *spi, enum dccPercent dccPercent)
431 {
432 #ifdef DEBUG
433 dev_dbg(&spi->dev, "set: cut off freq");
434 #endif
435
436 return rf69_set_dc_cut_off_frequency_intern(spi, REG_RXBW, dccPercent);
437 }
438
rf69_set_dc_cut_off_frequency_during_afc(struct spi_device * spi,enum dccPercent dccPercent)439 int rf69_set_dc_cut_off_frequency_during_afc(struct spi_device *spi, enum dccPercent dccPercent)
440 {
441 #ifdef DEBUG
442 dev_dbg(&spi->dev, "set: cut off freq during afc");
443 #endif
444
445 return rf69_set_dc_cut_off_frequency_intern(spi, REG_AFCBW, dccPercent);
446 }
447
rf69_set_bandwidth_intern(struct spi_device * spi,u8 reg,enum mantisse mantisse,u8 exponent)448 static int rf69_set_bandwidth_intern(struct spi_device *spi, u8 reg,
449 enum mantisse mantisse, u8 exponent)
450 {
451 u8 newValue;
452
453 // check value for mantisse and exponent
454 if (exponent > 7) {
455 dev_dbg(&spi->dev, "set: illegal input param");
456 return -EINVAL;
457 }
458
459 if ((mantisse != mantisse16) &&
460 (mantisse != mantisse20) &&
461 (mantisse != mantisse24)) {
462 dev_dbg(&spi->dev, "set: illegal input param");
463 return -EINVAL;
464 }
465
466 // read old value
467 newValue = READ_REG(reg);
468
469 // "delete" mantisse and exponent = just keep the DCC setting
470 newValue = newValue & MASK_BW_DCC_FREQ;
471
472 // add new mantisse
473 switch(mantisse) {
474 case mantisse16: newValue = newValue | BW_MANT_16; break;
475 case mantisse20: newValue = newValue | BW_MANT_20; break;
476 case mantisse24: newValue = newValue | BW_MANT_24; break;
477 }
478
479 // add new exponent
480 newValue = newValue | exponent;
481
482 // write back
483 return WRITE_REG(reg, newValue);
484 }
485
rf69_set_bandwidth(struct spi_device * spi,enum mantisse mantisse,u8 exponent)486 int rf69_set_bandwidth(struct spi_device *spi, enum mantisse mantisse, u8 exponent)
487 {
488 #ifdef DEBUG
489 dev_dbg(&spi->dev, "set: band width");
490 #endif
491
492 return rf69_set_bandwidth_intern(spi, REG_RXBW, mantisse, exponent);
493 }
494
rf69_set_bandwidth_during_afc(struct spi_device * spi,enum mantisse mantisse,u8 exponent)495 int rf69_set_bandwidth_during_afc(struct spi_device *spi, enum mantisse mantisse, u8 exponent)
496 {
497 #ifdef DEBUG
498 dev_dbg(&spi->dev, "set: band width during afc");
499 #endif
500
501 return rf69_set_bandwidth_intern(spi, REG_AFCBW, mantisse, exponent);
502 }
503
rf69_set_ook_threshold_type(struct spi_device * spi,enum thresholdType thresholdType)504 int rf69_set_ook_threshold_type(struct spi_device *spi, enum thresholdType thresholdType)
505 {
506 #ifdef DEBUG
507 dev_dbg(&spi->dev, "set: threshold type");
508 #endif
509
510 switch (thresholdType) {
511 case fixed: return WRITE_REG(REG_OOKPEAK, ( (READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESTYPE) | OOKPEAK_THRESHTYPE_FIXED) );
512 case peak: return WRITE_REG(REG_OOKPEAK, ( (READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESTYPE) | OOKPEAK_THRESHTYPE_PEAK) );
513 case average: return WRITE_REG(REG_OOKPEAK, ( (READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESTYPE) | OOKPEAK_THRESHTYPE_AVERAGE) );
514 default:
515 dev_dbg(&spi->dev, "set: illegal input param");
516 return -EINVAL;
517 }
518 }
519
rf69_set_ook_threshold_step(struct spi_device * spi,enum thresholdStep thresholdStep)520 int rf69_set_ook_threshold_step(struct spi_device *spi, enum thresholdStep thresholdStep)
521 {
522 #ifdef DEBUG
523 dev_dbg(&spi->dev, "set: threshold step");
524 #endif
525
526 switch (thresholdStep) {
527 case step_0_5db: return WRITE_REG(REG_OOKPEAK, ( (READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESSTEP) | OOKPEAK_THRESHSTEP_0_5_DB) );
528 case step_1_0db: return WRITE_REG(REG_OOKPEAK, ( (READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESSTEP) | OOKPEAK_THRESHSTEP_1_0_DB) );
529 case step_1_5db: return WRITE_REG(REG_OOKPEAK, ( (READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESSTEP) | OOKPEAK_THRESHSTEP_1_5_DB) );
530 case step_2_0db: return WRITE_REG(REG_OOKPEAK, ( (READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESSTEP) | OOKPEAK_THRESHSTEP_2_0_DB) );
531 case step_3_0db: return WRITE_REG(REG_OOKPEAK, ( (READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESSTEP) | OOKPEAK_THRESHSTEP_3_0_DB) );
532 case step_4_0db: return WRITE_REG(REG_OOKPEAK, ( (READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESSTEP) | OOKPEAK_THRESHSTEP_4_0_DB) );
533 case step_5_0db: return WRITE_REG(REG_OOKPEAK, ( (READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESSTEP) | OOKPEAK_THRESHSTEP_5_0_DB) );
534 case step_6_0db: return WRITE_REG(REG_OOKPEAK, ( (READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESSTEP) | OOKPEAK_THRESHSTEP_6_0_DB) );
535 default:
536 dev_dbg(&spi->dev, "set: illegal input param");
537 return -EINVAL;
538 }
539 }
540
rf69_set_ook_threshold_dec(struct spi_device * spi,enum thresholdDecrement thresholdDecrement)541 int rf69_set_ook_threshold_dec(struct spi_device *spi, enum thresholdDecrement thresholdDecrement)
542 {
543 #ifdef DEBUG
544 dev_dbg(&spi->dev, "set: threshold decrement");
545 #endif
546
547 switch (thresholdDecrement) {
548 case dec_every8th: return WRITE_REG(REG_OOKPEAK, ( (READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESDEC) | OOKPEAK_THRESHDEC_EVERY_8TH) );
549 case dec_every4th: return WRITE_REG(REG_OOKPEAK, ( (READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESDEC) | OOKPEAK_THRESHDEC_EVERY_4TH) );
550 case dec_every2nd: return WRITE_REG(REG_OOKPEAK, ( (READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESDEC) | OOKPEAK_THRESHDEC_EVERY_2ND) );
551 case dec_once: return WRITE_REG(REG_OOKPEAK, ( (READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESDEC) | OOKPEAK_THRESHDEC_ONCE) );
552 case dec_twice: return WRITE_REG(REG_OOKPEAK, ( (READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESDEC) | OOKPEAK_THRESHDEC_TWICE) );
553 case dec_4times: return WRITE_REG(REG_OOKPEAK, ( (READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESDEC) | OOKPEAK_THRESHDEC_4_TIMES) );
554 case dec_8times: return WRITE_REG(REG_OOKPEAK, ( (READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESDEC) | OOKPEAK_THRESHDEC_8_TIMES) );
555 case dec_16times: return WRITE_REG(REG_OOKPEAK, ( (READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESDEC) | OOKPEAK_THRESHDEC_16_TIMES) );
556 default:
557 dev_dbg(&spi->dev, "set: illegal input param");
558 return -EINVAL;
559 }
560 }
561
rf69_set_dio_mapping(struct spi_device * spi,u8 DIONumber,u8 value)562 int rf69_set_dio_mapping(struct spi_device *spi, u8 DIONumber, u8 value)
563 {
564 u8 mask;
565 u8 shift;
566 u8 regaddr;
567 u8 regValue;
568
569 #ifdef DEBUG
570 dev_dbg(&spi->dev, "set: DIO mapping");
571 #endif
572
573 switch (DIONumber) {
574 case 0: mask=MASK_DIO0; shift=SHIFT_DIO0; regaddr=REG_DIOMAPPING1; break;
575 case 1: mask=MASK_DIO1; shift=SHIFT_DIO1; regaddr=REG_DIOMAPPING1; break;
576 case 2: mask=MASK_DIO2; shift=SHIFT_DIO2; regaddr=REG_DIOMAPPING1; break;
577 case 3: mask=MASK_DIO3; shift=SHIFT_DIO3; regaddr=REG_DIOMAPPING1; break;
578 case 4: mask=MASK_DIO4; shift=SHIFT_DIO4; regaddr=REG_DIOMAPPING2; break;
579 case 5: mask=MASK_DIO5; shift=SHIFT_DIO5; regaddr=REG_DIOMAPPING2; break;
580 default:
581 dev_dbg(&spi->dev, "set: illegal input param");
582 return -EINVAL;
583 }
584
585 // read reg
586 regValue=READ_REG(regaddr);
587 // delete old value
588 regValue = regValue & ~mask;
589 // add new value
590 regValue = regValue | value << shift;
591 // write back
592 return WRITE_REG(regaddr,regValue);
593 }
594
rf69_get_flag(struct spi_device * spi,enum flag flag)595 bool rf69_get_flag(struct spi_device *spi, enum flag flag)
596 {
597 #ifdef DEBUG
598 dev_dbg(&spi->dev, "get: flag");
599 #endif
600
601 switch(flag) {
602 case modeSwitchCompleted: return (READ_REG(REG_IRQFLAGS1) & MASK_IRQFLAGS1_MODE_READY);
603 case readyToReceive: return (READ_REG(REG_IRQFLAGS1) & MASK_IRQFLAGS1_RX_READY);
604 case readyToSend: return (READ_REG(REG_IRQFLAGS1) & MASK_IRQFLAGS1_TX_READY);
605 case pllLocked: return (READ_REG(REG_IRQFLAGS1) & MASK_IRQFLAGS1_PLL_LOCK);
606 case rssiExceededThreshold: return (READ_REG(REG_IRQFLAGS1) & MASK_IRQFLAGS1_RSSI);
607 case timeout: return (READ_REG(REG_IRQFLAGS1) & MASK_IRQFLAGS1_TIMEOUT);
608 case automode: return (READ_REG(REG_IRQFLAGS1) & MASK_IRQFLAGS1_AUTOMODE);
609 case syncAddressMatch: return (READ_REG(REG_IRQFLAGS1) & MASK_IRQFLAGS1_SYNC_ADDRESS_MATCH);
610 case fifoFull: return (READ_REG(REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_FULL);
611 /* case fifoNotEmpty: return (READ_REG(REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_NOT_EMPTY); */
612 case fifoEmpty: return !(READ_REG(REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_NOT_EMPTY);
613 case fifoLevelBelowThreshold: return (READ_REG(REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_LEVEL);
614 case fifoOverrun: return (READ_REG(REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_OVERRUN);
615 case packetSent: return (READ_REG(REG_IRQFLAGS2) & MASK_IRQFLAGS2_PACKET_SENT);
616 case payloadReady: return (READ_REG(REG_IRQFLAGS2) & MASK_IRQFLAGS2_PAYLOAD_READY);
617 case crcOk: return (READ_REG(REG_IRQFLAGS2) & MASK_IRQFLAGS2_CRC_OK);
618 case batteryLow: return (READ_REG(REG_IRQFLAGS2) & MASK_IRQFLAGS2_LOW_BAT);
619 default: return false;
620 }
621 }
622
rf69_reset_flag(struct spi_device * spi,enum flag flag)623 int rf69_reset_flag(struct spi_device *spi, enum flag flag)
624 {
625 #ifdef DEBUG
626 dev_dbg(&spi->dev, "reset: flag");
627 #endif
628
629 switch(flag) {
630 case rssiExceededThreshold: return WRITE_REG(REG_IRQFLAGS1, MASK_IRQFLAGS1_RSSI);
631 case syncAddressMatch: return WRITE_REG(REG_IRQFLAGS1, MASK_IRQFLAGS1_SYNC_ADDRESS_MATCH);
632 case fifoOverrun: return WRITE_REG(REG_IRQFLAGS2, MASK_IRQFLAGS2_FIFO_OVERRUN);
633 default:
634 dev_dbg(&spi->dev, "set: illegal input param");
635 return -EINVAL;
636 }
637 }
638
rf69_set_rssi_threshold(struct spi_device * spi,u8 threshold)639 int rf69_set_rssi_threshold(struct spi_device *spi, u8 threshold)
640 {
641 #ifdef DEBUG
642 dev_dbg(&spi->dev, "set: rssi threshold");
643 #endif
644
645 /* no value check needed - u8 exactly matches register size */
646
647 return WRITE_REG(REG_RSSITHRESH, threshold);
648 }
649
rf69_set_rx_start_timeout(struct spi_device * spi,u8 timeout)650 int rf69_set_rx_start_timeout(struct spi_device *spi, u8 timeout)
651 {
652 #ifdef DEBUG
653 dev_dbg(&spi->dev, "set: start timeout");
654 #endif
655
656 /* no value check needed - u8 exactly matches register size */
657
658 return WRITE_REG(REG_RXTIMEOUT1, timeout);
659 }
660
rf69_set_rssi_timeout(struct spi_device * spi,u8 timeout)661 int rf69_set_rssi_timeout(struct spi_device *spi, u8 timeout)
662 {
663 #ifdef DEBUG
664 dev_dbg(&spi->dev, "set: rssi timeout");
665 #endif
666
667 /* no value check needed - u8 exactly matches register size */
668
669 return WRITE_REG(REG_RXTIMEOUT2, timeout);
670 }
671
rf69_set_preamble_length(struct spi_device * spi,u16 preambleLength)672 int rf69_set_preamble_length(struct spi_device *spi, u16 preambleLength)
673 {
674 int retval;
675 u8 msb, lsb;
676
677 #ifdef DEBUG
678 dev_dbg(&spi->dev, "set: preamble length");
679 #endif
680
681 /* no value check needed - u16 exactly matches register size */
682
683 /* calculate reg settings */
684 msb = (preambleLength&0xff00) >> 8;
685 lsb = (preambleLength&0xff);
686
687 /* transmit to chip */
688 retval = WRITE_REG(REG_PREAMBLE_MSB, msb);
689 if (retval) return retval;
690 retval = WRITE_REG(REG_PREAMBLE_LSB, lsb);
691
692 return retval;
693 }
694
rf69_set_sync_enable(struct spi_device * spi,enum optionOnOff optionOnOff)695 int rf69_set_sync_enable(struct spi_device *spi, enum optionOnOff optionOnOff)
696 {
697 #ifdef DEBUG
698 dev_dbg(&spi->dev, "set: sync enable");
699 #endif
700
701 switch(optionOnOff) {
702 case optionOn: return WRITE_REG(REG_SYNC_CONFIG, (READ_REG(REG_SYNC_CONFIG) | MASK_SYNC_CONFIG_SYNC_ON) );
703 case optionOff: return WRITE_REG(REG_SYNC_CONFIG, (READ_REG(REG_SYNC_CONFIG) & ~MASK_SYNC_CONFIG_SYNC_ON) );
704 default:
705 dev_dbg(&spi->dev, "set: illegal input param");
706 return -EINVAL;
707 }
708 }
709
rf69_set_fifo_fill_condition(struct spi_device * spi,enum fifoFillCondition fifoFillCondition)710 int rf69_set_fifo_fill_condition(struct spi_device *spi, enum fifoFillCondition fifoFillCondition)
711 {
712 #ifdef DEBUG
713 dev_dbg(&spi->dev, "set: fifo fill condition");
714 #endif
715
716 switch(fifoFillCondition) {
717 case always: return WRITE_REG(REG_SYNC_CONFIG, (READ_REG(REG_SYNC_CONFIG) | MASK_SYNC_CONFIG_FIFO_FILL_CONDITION) );
718 case afterSyncInterrupt: return WRITE_REG(REG_SYNC_CONFIG, (READ_REG(REG_SYNC_CONFIG) & ~MASK_SYNC_CONFIG_FIFO_FILL_CONDITION) );
719 default:
720 dev_dbg(&spi->dev, "set: illegal input param");
721 return -EINVAL;
722 }
723 }
724
rf69_set_sync_size(struct spi_device * spi,u8 syncSize)725 int rf69_set_sync_size(struct spi_device *spi, u8 syncSize)
726 {
727 #ifdef DEBUG
728 dev_dbg(&spi->dev, "set: sync size");
729 #endif
730
731 // check input value
732 if (syncSize > 0x07) {
733 dev_dbg(&spi->dev, "set: illegal input param");
734 return -EINVAL;
735 }
736
737 // write value
738 return WRITE_REG(REG_SYNC_CONFIG, (READ_REG(REG_SYNC_CONFIG) & ~MASK_SYNC_CONFIG_SYNC_SIZE) | (syncSize << 3) );
739 }
740
rf69_set_sync_tolerance(struct spi_device * spi,u8 syncTolerance)741 int rf69_set_sync_tolerance(struct spi_device *spi, u8 syncTolerance)
742 {
743 #ifdef DEBUG
744 dev_dbg(&spi->dev, "set: sync tolerance");
745 #endif
746
747 // check input value
748 if (syncTolerance > 0x07) {
749 dev_dbg(&spi->dev, "set: illegal input param");
750 return -EINVAL;
751 }
752
753 // write value
754 return WRITE_REG(REG_SYNC_CONFIG, (READ_REG(REG_SYNC_CONFIG) & ~MASK_SYNC_CONFIG_SYNC_SIZE) | syncTolerance);
755 }
756
rf69_set_sync_values(struct spi_device * spi,u8 syncValues[8])757 int rf69_set_sync_values(struct spi_device *spi, u8 syncValues[8])
758 {
759 int retval = 0;
760
761 #ifdef DEBUG
762 dev_dbg(&spi->dev, "set: sync values");
763 #endif
764
765 retval += WRITE_REG(REG_SYNCVALUE1, syncValues[0]);
766 retval += WRITE_REG(REG_SYNCVALUE2, syncValues[1]);
767 retval += WRITE_REG(REG_SYNCVALUE3, syncValues[2]);
768 retval += WRITE_REG(REG_SYNCVALUE4, syncValues[3]);
769 retval += WRITE_REG(REG_SYNCVALUE5, syncValues[4]);
770 retval += WRITE_REG(REG_SYNCVALUE6, syncValues[5]);
771 retval += WRITE_REG(REG_SYNCVALUE7, syncValues[6]);
772 retval += WRITE_REG(REG_SYNCVALUE8, syncValues[7]);
773
774 return retval;
775 }
776
rf69_set_packet_format(struct spi_device * spi,enum packetFormat packetFormat)777 int rf69_set_packet_format(struct spi_device *spi, enum packetFormat packetFormat)
778 {
779 #ifdef DEBUG
780 dev_dbg(&spi->dev, "set: packet format");
781 #endif
782
783 switch(packetFormat) {
784 case packetLengthVar: return WRITE_REG(REG_PACKETCONFIG1, (READ_REG(REG_PACKETCONFIG1) | MASK_PACKETCONFIG1_PAKET_FORMAT_VARIABLE) );
785 case packetLengthFix: return WRITE_REG(REG_PACKETCONFIG1, (READ_REG(REG_PACKETCONFIG1) & ~MASK_PACKETCONFIG1_PAKET_FORMAT_VARIABLE) );
786 default:
787 dev_dbg(&spi->dev, "set: illegal input param");
788 return -EINVAL;
789 }
790 }
791
rf69_set_crc_enable(struct spi_device * spi,enum optionOnOff optionOnOff)792 int rf69_set_crc_enable(struct spi_device *spi, enum optionOnOff optionOnOff)
793 {
794 #ifdef DEBUG
795 dev_dbg(&spi->dev, "set: crc enable");
796 #endif
797
798 switch(optionOnOff) {
799 case optionOn: return WRITE_REG(REG_PACKETCONFIG1, (READ_REG(REG_PACKETCONFIG1) | MASK_PACKETCONFIG1_CRC_ON) );
800 case optionOff: return WRITE_REG(REG_PACKETCONFIG1, (READ_REG(REG_PACKETCONFIG1) & ~MASK_PACKETCONFIG1_CRC_ON) );
801 default:
802 dev_dbg(&spi->dev, "set: illegal input param");
803 return -EINVAL;
804 }
805 }
806
rf69_set_adressFiltering(struct spi_device * spi,enum addressFiltering addressFiltering)807 int rf69_set_adressFiltering(struct spi_device *spi, enum addressFiltering addressFiltering)
808 {
809 #ifdef DEBUG
810 dev_dbg(&spi->dev, "set: address filtering");
811 #endif
812
813 switch (addressFiltering) {
814 case filteringOff: return WRITE_REG(REG_PACKETCONFIG1, ( (READ_REG(REG_PACKETCONFIG1) & ~MASK_PACKETCONFIG1_ADDRESSFILTERING) | PACKETCONFIG1_ADDRESSFILTERING_OFF) );
815 case nodeAddress: return WRITE_REG(REG_PACKETCONFIG1, ( (READ_REG(REG_PACKETCONFIG1) & ~MASK_PACKETCONFIG1_ADDRESSFILTERING) | PACKETCONFIG1_ADDRESSFILTERING_NODE) );
816 case nodeOrBroadcastAddress: return WRITE_REG(REG_PACKETCONFIG1, ( (READ_REG(REG_PACKETCONFIG1) & ~MASK_PACKETCONFIG1_ADDRESSFILTERING) | PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST) );
817 default:
818 dev_dbg(&spi->dev, "set: illegal input param");
819 return -EINVAL;
820 }
821 }
822
rf69_set_payload_length(struct spi_device * spi,u8 payloadLength)823 int rf69_set_payload_length(struct spi_device *spi, u8 payloadLength)
824 {
825 #ifdef DEBUG
826 dev_dbg(&spi->dev, "set: payload length");
827 #endif
828
829 return WRITE_REG(REG_PAYLOAD_LENGTH, payloadLength);
830 }
831
rf69_get_payload_length(struct spi_device * spi)832 u8 rf69_get_payload_length(struct spi_device *spi)
833 {
834 #ifdef DEBUG
835 dev_dbg(&spi->dev, "get: payload length");
836 #endif
837
838 return (u8) READ_REG(REG_PAYLOAD_LENGTH);
839 }
840
rf69_set_node_address(struct spi_device * spi,u8 nodeAddress)841 int rf69_set_node_address(struct spi_device *spi, u8 nodeAddress)
842 {
843 #ifdef DEBUG
844 dev_dbg(&spi->dev, "set: node address");
845 #endif
846
847 return WRITE_REG(REG_NODEADRS, nodeAddress);
848 }
849
rf69_set_broadcast_address(struct spi_device * spi,u8 broadcastAddress)850 int rf69_set_broadcast_address(struct spi_device *spi, u8 broadcastAddress)
851 {
852 #ifdef DEBUG
853 dev_dbg(&spi->dev, "set: broadcast address");
854 #endif
855
856 return WRITE_REG(REG_BROADCASTADRS, broadcastAddress);
857 }
858
rf69_set_tx_start_condition(struct spi_device * spi,enum txStartCondition txStartCondition)859 int rf69_set_tx_start_condition(struct spi_device *spi, enum txStartCondition txStartCondition)
860 {
861 #ifdef DEBUG
862 dev_dbg(&spi->dev, "set: start condition");
863 #endif
864
865 switch(txStartCondition) {
866 case fifoLevel: return WRITE_REG(REG_FIFO_THRESH, (READ_REG(REG_FIFO_THRESH) & ~MASK_FIFO_THRESH_TXSTART) );
867 case fifoNotEmpty: return WRITE_REG(REG_FIFO_THRESH, (READ_REG(REG_FIFO_THRESH) | MASK_FIFO_THRESH_TXSTART) );
868 default:
869 dev_dbg(&spi->dev, "set: illegal input param");
870 return -EINVAL;
871 }
872 }
873
rf69_set_fifo_threshold(struct spi_device * spi,u8 threshold)874 int rf69_set_fifo_threshold(struct spi_device *spi, u8 threshold)
875 {
876 int retval;
877
878 #ifdef DEBUG
879 dev_dbg(&spi->dev, "set: fifo threshold");
880 #endif
881
882 // check input value
883 if (threshold & 0x80) {
884 dev_dbg(&spi->dev, "set: illegal input param");
885 return -EINVAL;
886 }
887
888 // write value
889 retval = WRITE_REG(REG_FIFO_THRESH, (READ_REG(REG_FIFO_THRESH) & ~MASK_FIFO_THRESH_VALUE) | threshold);
890 if (retval)
891 return retval;
892
893 // access the fifo to activate new threshold
894 return rf69_read_fifo (spi, (u8*) &retval, 1); // retval used as buffer
895 }
896
rf69_set_dagc(struct spi_device * spi,enum dagc dagc)897 int rf69_set_dagc(struct spi_device *spi, enum dagc dagc)
898 {
899 #ifdef DEBUG
900 dev_dbg(&spi->dev, "set: dagc");
901 #endif
902
903 switch(dagc) {
904 case normalMode: return WRITE_REG(REG_TESTDAGC, DAGC_NORMAL);
905 case improve: return WRITE_REG(REG_TESTDAGC, DAGC_IMPROVED_LOWBETA0);
906 case improve4LowModulationIndex: return WRITE_REG(REG_TESTDAGC, DAGC_IMPROVED_LOWBETA1);
907 default:
908 dev_dbg(&spi->dev, "set: illegal input param");
909 return -EINVAL;
910 }
911 }
912
913 /*-------------------------------------------------------------------------*/
914
rf69_read_fifo(struct spi_device * spi,u8 * buffer,unsigned int size)915 int rf69_read_fifo (struct spi_device *spi, u8 *buffer, unsigned int size)
916 {
917 #ifdef DEBUG_FIFO_ACCESS
918 int i;
919 #endif
920 struct spi_transfer transfer;
921 u8 local_buffer[FIFO_SIZE + 1];
922 int retval;
923
924 if (size > FIFO_SIZE) {
925 #ifdef DEBUG
926 dev_dbg(&spi->dev, "read fifo: passed in buffer bigger then internal buffer \n");
927 #endif
928 return -EMSGSIZE;
929 }
930
931 /* prepare a bidirectional transfer */
932 local_buffer[0] = REG_FIFO;
933 memset(&transfer, 0, sizeof(transfer));
934 transfer.tx_buf = local_buffer;
935 transfer.rx_buf = local_buffer;
936 transfer.len = size+1;
937
938 retval = spi_sync_transfer(spi, &transfer, 1);
939
940 #ifdef DEBUG_FIFO_ACCESS
941 for (i=0; i<size; i++)
942 dev_dbg(&spi->dev, "%d - 0x%x\n", i, local_buffer[i+1]);
943 #endif
944
945 memcpy(buffer, &local_buffer[1], size); // TODO: ohne memcopy w�re sch�ner
946
947 return retval;
948 }
949
rf69_write_fifo(struct spi_device * spi,u8 * buffer,unsigned int size)950 int rf69_write_fifo(struct spi_device *spi, u8 *buffer, unsigned int size)
951 {
952 #ifdef DEBUG_FIFO_ACCESS
953 int i;
954 #endif
955 char spi_address = REG_FIFO | WRITE_BIT;
956 u8 local_buffer[FIFO_SIZE + 1];
957
958 if (size > FIFO_SIZE) {
959 #ifdef DEBUG
960 dev_dbg(&spi->dev, "read fifo: passed in buffer bigger then internal buffer \n");
961 #endif
962 return -EMSGSIZE;
963 }
964
965 local_buffer[0] = spi_address;
966 memcpy(&local_buffer[1], buffer, size); // TODO: ohne memcopy w�re sch�ner
967
968 #ifdef DEBUG_FIFO_ACCESS
969 for (i=0; i<size; i++)
970 dev_dbg(&spi->dev, "0x%x\n",buffer[i]);
971 #endif
972
973 return spi_write (spi, local_buffer, size + 1);
974 }
975
976 /*-------------------------------------------------------------------------*/
977
rf69_read_reg(struct spi_device * spi,u8 addr)978 u8 rf69_read_reg(struct spi_device *spi, u8 addr)
979 {
980 int retval;
981
982 retval = spi_w8r8(spi, addr);
983
984 #ifdef DEBUG_VALUES
985 if (retval < 0)
986 /* should never happen, since we already checked,
987 * that module is connected. Therefore no error
988 * handling, just an optional error message...
989 */
990 dev_dbg(&spi->dev, "read 0x%x FAILED\n",
991 addr);
992 else
993 dev_dbg(&spi->dev, "read 0x%x from reg 0x%x\n",
994 retval,
995 addr);
996 #endif
997
998 return retval;
999 }
1000
rf69_write_reg(struct spi_device * spi,u8 addr,u8 value)1001 int rf69_write_reg(struct spi_device *spi, u8 addr, u8 value)
1002 {
1003 int retval;
1004 char buffer[2];
1005
1006 buffer[0] = addr | WRITE_BIT;
1007 buffer[1] = value;
1008
1009 retval = spi_write(spi, &buffer, 2);
1010
1011 #ifdef DEBUG_VALUES
1012 if (retval < 0)
1013 /* should never happen, since we already checked,
1014 * that module is connected. Therefore no error
1015 * handling, just an optional error message...
1016 */
1017 dev_dbg(&spi->dev, "write 0x%x to 0x%x FAILED\n",
1018 value,
1019 addr);
1020 else
1021 dev_dbg(&spi->dev, "wrote 0x%x to reg 0x%x\n",
1022 value,
1023 addr);
1024 #endif
1025
1026 return retval;
1027 }
1028
1029
1030