1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "wifi.h"
27 #include "core.h"
28 #include "pci.h"
29 #include "base.h"
30 #include "ps.h"
31 #include "efuse.h"
32 #include <linux/interrupt.h>
33 #include <linux/export.h>
34 #include <linux/kmemleak.h>
35 #include <linux/module.h>
36
37 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
38 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
39 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
40 MODULE_LICENSE("GPL");
41 MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
42
43 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
44 INTEL_VENDOR_ID,
45 ATI_VENDOR_ID,
46 AMD_VENDOR_ID,
47 SIS_VENDOR_ID
48 };
49
50 static const u8 ac_to_hwq[] = {
51 VO_QUEUE,
52 VI_QUEUE,
53 BE_QUEUE,
54 BK_QUEUE
55 };
56
_rtl_mac_to_hwqueue(struct ieee80211_hw * hw,struct sk_buff * skb)57 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
58 struct sk_buff *skb)
59 {
60 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
61 __le16 fc = rtl_get_fc(skb);
62 u8 queue_index = skb_get_queue_mapping(skb);
63 struct ieee80211_hdr *hdr;
64
65 if (unlikely(ieee80211_is_beacon(fc)))
66 return BEACON_QUEUE;
67 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
68 return MGNT_QUEUE;
69 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
70 if (ieee80211_is_nullfunc(fc))
71 return HIGH_QUEUE;
72 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
73 hdr = rtl_get_hdr(skb);
74
75 if (is_multicast_ether_addr(hdr->addr1) ||
76 is_broadcast_ether_addr(hdr->addr1))
77 return HIGH_QUEUE;
78 }
79
80 return ac_to_hwq[queue_index];
81 }
82
83 /* Update PCI dependent default settings*/
_rtl_pci_update_default_setting(struct ieee80211_hw * hw)84 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
85 {
86 struct rtl_priv *rtlpriv = rtl_priv(hw);
87 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
88 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
89 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
90 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
91 u8 init_aspm;
92
93 ppsc->reg_rfps_level = 0;
94 ppsc->support_aspm = false;
95
96 /*Update PCI ASPM setting */
97 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
98 switch (rtlpci->const_pci_aspm) {
99 case 0:
100 /*No ASPM */
101 break;
102
103 case 1:
104 /*ASPM dynamically enabled/disable. */
105 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
106 break;
107
108 case 2:
109 /*ASPM with Clock Req dynamically enabled/disable. */
110 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
111 RT_RF_OFF_LEVL_CLK_REQ);
112 break;
113
114 case 3:
115 /* Always enable ASPM and Clock Req
116 * from initialization to halt.
117 */
118 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
119 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
120 RT_RF_OFF_LEVL_CLK_REQ);
121 break;
122
123 case 4:
124 /* Always enable ASPM without Clock Req
125 * from initialization to halt.
126 */
127 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
128 RT_RF_OFF_LEVL_CLK_REQ);
129 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
130 break;
131 }
132
133 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
134
135 /*Update Radio OFF setting */
136 switch (rtlpci->const_hwsw_rfoff_d3) {
137 case 1:
138 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
139 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
140 break;
141
142 case 2:
143 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
144 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
145 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
146 break;
147
148 case 3:
149 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
150 break;
151 }
152
153 /*Set HW definition to determine if it supports ASPM. */
154 switch (rtlpci->const_support_pciaspm) {
155 case 0:{
156 /*Not support ASPM. */
157 bool support_aspm = false;
158
159 ppsc->support_aspm = support_aspm;
160 break;
161 }
162 case 1:{
163 /*Support ASPM. */
164 bool support_aspm = true;
165 bool support_backdoor = true;
166
167 ppsc->support_aspm = support_aspm;
168
169 /*if (priv->oem_id == RT_CID_TOSHIBA &&
170 * !priv->ndis_adapter.amd_l1_patch)
171 * support_backdoor = false;
172 */
173
174 ppsc->support_backdoor = support_backdoor;
175
176 break;
177 }
178 case 2:
179 /*ASPM value set by chipset. */
180 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
181 bool support_aspm = true;
182
183 ppsc->support_aspm = support_aspm;
184 }
185 break;
186 default:
187 pr_err("switch case %#x not processed\n",
188 rtlpci->const_support_pciaspm);
189 break;
190 }
191
192 /* toshiba aspm issue, toshiba will set aspm selfly
193 * so we should not set aspm in driver
194 */
195 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
196 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
197 init_aspm == 0x43)
198 ppsc->support_aspm = false;
199 }
200
_rtl_pci_platform_switch_device_pci_aspm(struct ieee80211_hw * hw,u8 value)201 static bool _rtl_pci_platform_switch_device_pci_aspm(
202 struct ieee80211_hw *hw,
203 u8 value)
204 {
205 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
206 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
207
208 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
209 value |= 0x40;
210
211 pci_write_config_byte(rtlpci->pdev, 0x80, value);
212
213 return false;
214 }
215
216 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
_rtl_pci_switch_clk_req(struct ieee80211_hw * hw,u8 value)217 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
218 {
219 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
220 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
221
222 pci_write_config_byte(rtlpci->pdev, 0x81, value);
223
224 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
225 udelay(100);
226 }
227
228 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
rtl_pci_disable_aspm(struct ieee80211_hw * hw)229 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
230 {
231 struct rtl_priv *rtlpriv = rtl_priv(hw);
232 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
233 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
234 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
235 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
236 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
237 /*Retrieve original configuration settings. */
238 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
239 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.pcibridge_linkctrlreg;
240 u16 aspmlevel = 0;
241 u8 tmp_u1b = 0;
242
243 if (!ppsc->support_aspm)
244 return;
245
246 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
247 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
248 "PCI(Bridge) UNKNOWN\n");
249
250 return;
251 }
252
253 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
254 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
255 _rtl_pci_switch_clk_req(hw, 0x0);
256 }
257
258 /*for promising device will in L0 state after an I/O. */
259 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
260
261 /*Set corresponding value. */
262 aspmlevel |= BIT(0) | BIT(1);
263 linkctrl_reg &= ~aspmlevel;
264 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
265
266 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
267 udelay(50);
268
269 /*4 Disable Pci Bridge ASPM */
270 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
271 pcibridge_linkctrlreg);
272
273 udelay(50);
274 }
275
276 /*
277 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
278 *power saving We should follow the sequence to enable
279 *RTL8192SE first then enable Pci Bridge ASPM
280 *or the system will show bluescreen.
281 */
rtl_pci_enable_aspm(struct ieee80211_hw * hw)282 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
283 {
284 struct rtl_priv *rtlpriv = rtl_priv(hw);
285 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
286 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
287 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
288 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
289 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
290 u16 aspmlevel;
291 u8 u_pcibridge_aspmsetting;
292 u8 u_device_aspmsetting;
293
294 if (!ppsc->support_aspm)
295 return;
296
297 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
298 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
299 "PCI(Bridge) UNKNOWN\n");
300 return;
301 }
302
303 /*4 Enable Pci Bridge ASPM */
304
305 u_pcibridge_aspmsetting =
306 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
307 rtlpci->const_hostpci_aspm_setting;
308
309 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
310 u_pcibridge_aspmsetting &= ~BIT(0);
311
312 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
313 u_pcibridge_aspmsetting);
314
315 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
316 "PlatformEnableASPM(): Write reg[%x] = %x\n",
317 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
318 u_pcibridge_aspmsetting);
319
320 udelay(50);
321
322 /*Get ASPM level (with/without Clock Req) */
323 aspmlevel = rtlpci->const_devicepci_aspm_setting;
324 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
325
326 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
327 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
328
329 u_device_aspmsetting |= aspmlevel;
330
331 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
332
333 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
334 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
335 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
336 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
337 }
338 udelay(100);
339 }
340
rtl_pci_get_amd_l1_patch(struct ieee80211_hw * hw)341 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
342 {
343 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
344
345 bool status = false;
346 u8 offset_e0;
347 unsigned int offset_e4;
348
349 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
350
351 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
352
353 if (offset_e0 == 0xA0) {
354 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
355 if (offset_e4 & BIT(23))
356 status = true;
357 }
358
359 return status;
360 }
361
rtl_pci_check_buddy_priv(struct ieee80211_hw * hw,struct rtl_priv ** buddy_priv)362 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
363 struct rtl_priv **buddy_priv)
364 {
365 struct rtl_priv *rtlpriv = rtl_priv(hw);
366 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
367 bool find_buddy_priv = false;
368 struct rtl_priv *tpriv;
369 struct rtl_pci_priv *tpcipriv = NULL;
370
371 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
372 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list,
373 list) {
374 tpcipriv = (struct rtl_pci_priv *)tpriv->priv;
375 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
376 "pcipriv->ndis_adapter.funcnumber %x\n",
377 pcipriv->ndis_adapter.funcnumber);
378 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
379 "tpcipriv->ndis_adapter.funcnumber %x\n",
380 tpcipriv->ndis_adapter.funcnumber);
381
382 if ((pcipriv->ndis_adapter.busnumber ==
383 tpcipriv->ndis_adapter.busnumber) &&
384 (pcipriv->ndis_adapter.devnumber ==
385 tpcipriv->ndis_adapter.devnumber) &&
386 (pcipriv->ndis_adapter.funcnumber !=
387 tpcipriv->ndis_adapter.funcnumber)) {
388 find_buddy_priv = true;
389 break;
390 }
391 }
392 }
393
394 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
395 "find_buddy_priv %d\n", find_buddy_priv);
396
397 if (find_buddy_priv)
398 *buddy_priv = tpriv;
399
400 return find_buddy_priv;
401 }
402
rtl_pci_get_linkcontrol_field(struct ieee80211_hw * hw)403 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
404 {
405 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
406 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
407 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
408 u8 linkctrl_reg;
409 u8 num4bbytes;
410
411 num4bbytes = (capabilityoffset + 0x10) / 4;
412
413 /*Read Link Control Register */
414 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
415
416 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
417 }
418
rtl_pci_parse_configuration(struct pci_dev * pdev,struct ieee80211_hw * hw)419 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
420 struct ieee80211_hw *hw)
421 {
422 struct rtl_priv *rtlpriv = rtl_priv(hw);
423 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
424
425 u8 tmp;
426 u16 linkctrl_reg;
427
428 /*Link Control Register */
429 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
430 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
431
432 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
433 pcipriv->ndis_adapter.linkctrl_reg);
434
435 pci_read_config_byte(pdev, 0x98, &tmp);
436 tmp |= BIT(4);
437 pci_write_config_byte(pdev, 0x98, tmp);
438
439 tmp = 0x17;
440 pci_write_config_byte(pdev, 0x70f, tmp);
441 }
442
rtl_pci_init_aspm(struct ieee80211_hw * hw)443 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
444 {
445 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
446
447 _rtl_pci_update_default_setting(hw);
448
449 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
450 /*Always enable ASPM & Clock Req. */
451 rtl_pci_enable_aspm(hw);
452 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
453 }
454 }
455
_rtl_pci_io_handler_init(struct device * dev,struct ieee80211_hw * hw)456 static void _rtl_pci_io_handler_init(struct device *dev,
457 struct ieee80211_hw *hw)
458 {
459 struct rtl_priv *rtlpriv = rtl_priv(hw);
460
461 rtlpriv->io.dev = dev;
462
463 rtlpriv->io.write8_async = pci_write8_async;
464 rtlpriv->io.write16_async = pci_write16_async;
465 rtlpriv->io.write32_async = pci_write32_async;
466
467 rtlpriv->io.read8_sync = pci_read8_sync;
468 rtlpriv->io.read16_sync = pci_read16_sync;
469 rtlpriv->io.read32_sync = pci_read32_sync;
470 }
471
_rtl_update_earlymode_info(struct ieee80211_hw * hw,struct sk_buff * skb,struct rtl_tcb_desc * tcb_desc,u8 tid)472 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
473 struct sk_buff *skb,
474 struct rtl_tcb_desc *tcb_desc, u8 tid)
475 {
476 struct rtl_priv *rtlpriv = rtl_priv(hw);
477 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
478 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
479 struct sk_buff *next_skb;
480 u8 additionlen = FCS_LEN;
481
482 /* here open is 4, wep/tkip is 8, aes is 12*/
483 if (info->control.hw_key)
484 additionlen += info->control.hw_key->icv_len;
485
486 /* The most skb num is 6 */
487 tcb_desc->empkt_num = 0;
488 spin_lock_bh(&rtlpriv->locks.waitq_lock);
489 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
490 struct ieee80211_tx_info *next_info;
491
492 next_info = IEEE80211_SKB_CB(next_skb);
493 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
494 tcb_desc->empkt_len[tcb_desc->empkt_num] =
495 next_skb->len + additionlen;
496 tcb_desc->empkt_num++;
497 } else {
498 break;
499 }
500
501 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
502 next_skb))
503 break;
504
505 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
506 break;
507 }
508 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
509
510 return true;
511 }
512
513 /* just for early mode now */
_rtl_pci_tx_chk_waitq(struct ieee80211_hw * hw)514 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
515 {
516 struct rtl_priv *rtlpriv = rtl_priv(hw);
517 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
518 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
519 struct sk_buff *skb = NULL;
520 struct ieee80211_tx_info *info = NULL;
521 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
522 int tid;
523
524 if (!rtlpriv->rtlhal.earlymode_enable)
525 return;
526
527 if (rtlpriv->dm.supp_phymode_switch &&
528 (rtlpriv->easy_concurrent_ctl.switch_in_process ||
529 (rtlpriv->buddy_priv &&
530 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
531 return;
532 /* we just use em for BE/BK/VI/VO */
533 for (tid = 7; tid >= 0; tid--) {
534 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
535 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
536
537 while (!mac->act_scanning &&
538 rtlpriv->psc.rfpwr_state == ERFON) {
539 struct rtl_tcb_desc tcb_desc;
540
541 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
542 spin_lock_bh(&rtlpriv->locks.waitq_lock);
543 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
544 (ring->entries - skb_queue_len(&ring->queue) >
545 rtlhal->max_earlymode_num)) {
546 skb = skb_dequeue(&mac->skb_waitq[tid]);
547 } else {
548 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
549 break;
550 }
551 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
552
553 /* Some macaddr can't do early mode. like
554 * multicast/broadcast/no_qos data
555 */
556 info = IEEE80211_SKB_CB(skb);
557 if (info->flags & IEEE80211_TX_CTL_AMPDU)
558 _rtl_update_earlymode_info(hw, skb,
559 &tcb_desc, tid);
560
561 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
562 }
563 }
564 }
565
_rtl_pci_tx_isr(struct ieee80211_hw * hw,int prio)566 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
567 {
568 struct rtl_priv *rtlpriv = rtl_priv(hw);
569 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
570
571 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
572
573 while (skb_queue_len(&ring->queue)) {
574 struct sk_buff *skb;
575 struct ieee80211_tx_info *info;
576 __le16 fc;
577 u8 tid;
578 u8 *entry;
579
580 if (rtlpriv->use_new_trx_flow)
581 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
582 else
583 entry = (u8 *)(&ring->desc[ring->idx]);
584
585 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
586 return;
587 ring->idx = (ring->idx + 1) % ring->entries;
588
589 skb = __skb_dequeue(&ring->queue);
590 pci_unmap_single(rtlpci->pdev,
591 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, true,
592 HW_DESC_TXBUFF_ADDR),
593 skb->len, PCI_DMA_TODEVICE);
594
595 /* remove early mode header */
596 if (rtlpriv->rtlhal.earlymode_enable)
597 skb_pull(skb, EM_HDR_LEN);
598
599 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
600 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
601 ring->idx,
602 skb_queue_len(&ring->queue),
603 *(u16 *)(skb->data + 22));
604
605 if (prio == TXCMD_QUEUE) {
606 dev_kfree_skb(skb);
607 goto tx_status_ok;
608 }
609
610 /* for sw LPS, just after NULL skb send out, we can
611 * sure AP knows we are sleeping, we should not let
612 * rf sleep
613 */
614 fc = rtl_get_fc(skb);
615 if (ieee80211_is_nullfunc(fc)) {
616 if (ieee80211_has_pm(fc)) {
617 rtlpriv->mac80211.offchan_delay = true;
618 rtlpriv->psc.state_inap = true;
619 } else {
620 rtlpriv->psc.state_inap = false;
621 }
622 }
623 if (ieee80211_is_action(fc)) {
624 struct ieee80211_mgmt *action_frame =
625 (struct ieee80211_mgmt *)skb->data;
626 if (action_frame->u.action.u.ht_smps.action ==
627 WLAN_HT_ACTION_SMPS) {
628 dev_kfree_skb(skb);
629 goto tx_status_ok;
630 }
631 }
632
633 /* update tid tx pkt num */
634 tid = rtl_get_tid(skb);
635 if (tid <= 7)
636 rtlpriv->link_info.tidtx_inperiod[tid]++;
637
638 info = IEEE80211_SKB_CB(skb);
639 ieee80211_tx_info_clear_status(info);
640
641 info->flags |= IEEE80211_TX_STAT_ACK;
642 /*info->status.rates[0].count = 1; */
643
644 ieee80211_tx_status_irqsafe(hw, skb);
645
646 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) {
647 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
648 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n",
649 prio, ring->idx,
650 skb_queue_len(&ring->queue));
651
652 ieee80211_wake_queue(hw, skb_get_queue_mapping (skb));
653 }
654 tx_status_ok:
655 skb = NULL;
656 }
657
658 if (((rtlpriv->link_info.num_rx_inperiod +
659 rtlpriv->link_info.num_tx_inperiod) > 8) ||
660 (rtlpriv->link_info.num_rx_inperiod > 2))
661 rtl_lps_leave(hw);
662 }
663
_rtl_pci_init_one_rxdesc(struct ieee80211_hw * hw,struct sk_buff * new_skb,u8 * entry,int rxring_idx,int desc_idx)664 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
665 struct sk_buff *new_skb, u8 *entry,
666 int rxring_idx, int desc_idx)
667 {
668 struct rtl_priv *rtlpriv = rtl_priv(hw);
669 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
670 u32 bufferaddress;
671 u8 tmp_one = 1;
672 struct sk_buff *skb;
673
674 if (likely(new_skb)) {
675 skb = new_skb;
676 goto remap;
677 }
678 skb = dev_alloc_skb(rtlpci->rxbuffersize);
679 if (!skb)
680 return 0;
681
682 remap:
683 /* just set skb->cb to mapping addr for pci_unmap_single use */
684 *((dma_addr_t *)skb->cb) =
685 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
686 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
687 bufferaddress = *((dma_addr_t *)skb->cb);
688 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress))
689 return 0;
690 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
691 if (rtlpriv->use_new_trx_flow) {
692 /* skb->cb may be 64 bit address */
693 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
694 HW_DESC_RX_PREPARE,
695 (u8 *)(dma_addr_t *)skb->cb);
696 } else {
697 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
698 HW_DESC_RXBUFF_ADDR,
699 (u8 *)&bufferaddress);
700 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
701 HW_DESC_RXPKT_LEN,
702 (u8 *)&rtlpci->rxbuffersize);
703 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
704 HW_DESC_RXOWN,
705 (u8 *)&tmp_one);
706 }
707 return 1;
708 }
709
710 /* inorder to receive 8K AMSDU we have set skb to
711 * 9100bytes in init rx ring, but if this packet is
712 * not a AMSDU, this large packet will be sent to
713 * TCP/IP directly, this cause big packet ping fail
714 * like: "ping -s 65507", so here we will realloc skb
715 * based on the true size of packet, Mac80211
716 * Probably will do it better, but does not yet.
717 *
718 * Some platform will fail when alloc skb sometimes.
719 * in this condition, we will send the old skb to
720 * mac80211 directly, this will not cause any other
721 * issues, but only this packet will be lost by TCP/IP
722 */
_rtl_pci_rx_to_mac80211(struct ieee80211_hw * hw,struct sk_buff * skb,struct ieee80211_rx_status rx_status)723 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
724 struct sk_buff *skb,
725 struct ieee80211_rx_status rx_status)
726 {
727 if (unlikely(!rtl_action_proc(hw, skb, false))) {
728 dev_kfree_skb_any(skb);
729 } else {
730 struct sk_buff *uskb = NULL;
731
732 uskb = dev_alloc_skb(skb->len + 128);
733 if (likely(uskb)) {
734 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
735 sizeof(rx_status));
736 skb_put_data(uskb, skb->data, skb->len);
737 dev_kfree_skb_any(skb);
738 ieee80211_rx_irqsafe(hw, uskb);
739 } else {
740 ieee80211_rx_irqsafe(hw, skb);
741 }
742 }
743 }
744
745 /*hsisr interrupt handler*/
_rtl_pci_hs_interrupt(struct ieee80211_hw * hw)746 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
747 {
748 struct rtl_priv *rtlpriv = rtl_priv(hw);
749 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
750
751 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
752 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
753 rtlpci->sys_irq_mask);
754 }
755
_rtl_pci_rx_interrupt(struct ieee80211_hw * hw)756 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
757 {
758 struct rtl_priv *rtlpriv = rtl_priv(hw);
759 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
760 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
761 struct ieee80211_rx_status rx_status = { 0 };
762 unsigned int count = rtlpci->rxringcount;
763 u8 own;
764 u8 tmp_one;
765 bool unicast = false;
766 u8 hw_queue = 0;
767 unsigned int rx_remained_cnt = 0;
768 struct rtl_stats stats = {
769 .signal = 0,
770 .rate = 0,
771 };
772
773 /*RX NORMAL PKT */
774 while (count--) {
775 struct ieee80211_hdr *hdr;
776 __le16 fc;
777 u16 len;
778 /*rx buffer descriptor */
779 struct rtl_rx_buffer_desc *buffer_desc = NULL;
780 /*if use new trx flow, it means wifi info */
781 struct rtl_rx_desc *pdesc = NULL;
782 /*rx pkt */
783 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
784 rtlpci->rx_ring[rxring_idx].idx];
785 struct sk_buff *new_skb;
786
787 if (rtlpriv->use_new_trx_flow) {
788 if (rx_remained_cnt == 0)
789 rx_remained_cnt =
790 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
791 hw_queue);
792 if (rx_remained_cnt == 0)
793 return;
794 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
795 rtlpci->rx_ring[rxring_idx].idx];
796 pdesc = (struct rtl_rx_desc *)skb->data;
797 } else { /* rx descriptor */
798 pdesc = &rtlpci->rx_ring[rxring_idx].desc[
799 rtlpci->rx_ring[rxring_idx].idx];
800
801 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
802 false,
803 HW_DESC_OWN);
804 if (own) /* wait data to be filled by hardware */
805 return;
806 }
807
808 /* Reaching this point means: data is filled already
809 * AAAAAAttention !!!
810 * We can NOT access 'skb' before 'pci_unmap_single'
811 */
812 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
813 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
814
815 /* get a new skb - if fail, old one will be reused */
816 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
817 if (unlikely(!new_skb))
818 goto no_new;
819 memset(&rx_status, 0, sizeof(rx_status));
820 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
821 &rx_status, (u8 *)pdesc, skb);
822
823 if (rtlpriv->use_new_trx_flow)
824 rtlpriv->cfg->ops->rx_check_dma_ok(hw,
825 (u8 *)buffer_desc,
826 hw_queue);
827
828 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false,
829 HW_DESC_RXPKT_LEN);
830
831 if (skb->end - skb->tail > len) {
832 skb_put(skb, len);
833 if (rtlpriv->use_new_trx_flow)
834 skb_reserve(skb, stats.rx_drvinfo_size +
835 stats.rx_bufshift + 24);
836 else
837 skb_reserve(skb, stats.rx_drvinfo_size +
838 stats.rx_bufshift);
839 } else {
840 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
841 "skb->end - skb->tail = %d, len is %d\n",
842 skb->end - skb->tail, len);
843 dev_kfree_skb_any(skb);
844 goto new_trx_end;
845 }
846 /* handle command packet here */
847 if (rtlpriv->cfg->ops->rx_command_packet &&
848 rtlpriv->cfg->ops->rx_command_packet(hw, &stats, skb)) {
849 dev_kfree_skb_any(skb);
850 goto new_trx_end;
851 }
852
853 /*
854 * NOTICE This can not be use for mac80211,
855 * this is done in mac80211 code,
856 * if done here sec DHCP will fail
857 * skb_trim(skb, skb->len - 4);
858 */
859
860 hdr = rtl_get_hdr(skb);
861 fc = rtl_get_fc(skb);
862
863 if (!stats.crc && !stats.hwerror) {
864 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
865 sizeof(rx_status));
866
867 if (is_broadcast_ether_addr(hdr->addr1)) {
868 ;/*TODO*/
869 } else if (is_multicast_ether_addr(hdr->addr1)) {
870 ;/*TODO*/
871 } else {
872 unicast = true;
873 rtlpriv->stats.rxbytesunicast += skb->len;
874 }
875 rtl_is_special_data(hw, skb, false, true);
876
877 if (ieee80211_is_data(fc)) {
878 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
879 if (unicast)
880 rtlpriv->link_info.num_rx_inperiod++;
881 }
882
883 rtl_collect_scan_list(hw, skb);
884
885 /* static bcn for roaming */
886 rtl_beacon_statistic(hw, skb);
887 rtl_p2p_info(hw, (void *)skb->data, skb->len);
888 /* for sw lps */
889 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
890 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
891 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
892 (rtlpriv->rtlhal.current_bandtype ==
893 BAND_ON_2_4G) &&
894 (ieee80211_is_beacon(fc) ||
895 ieee80211_is_probe_resp(fc))) {
896 dev_kfree_skb_any(skb);
897 } else {
898 rtl_check_beacon_key(hw, (void *)skb->data,
899 skb->len);
900 _rtl_pci_rx_to_mac80211(hw, skb, rx_status);
901 }
902 } else {
903 dev_kfree_skb_any(skb);
904 }
905 new_trx_end:
906 if (rtlpriv->use_new_trx_flow) {
907 rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
908 rtlpci->rx_ring[hw_queue].next_rx_rp %=
909 RTL_PCI_MAX_RX_COUNT;
910
911 rx_remained_cnt--;
912 rtl_write_word(rtlpriv, 0x3B4,
913 rtlpci->rx_ring[hw_queue].next_rx_rp);
914 }
915 if (((rtlpriv->link_info.num_rx_inperiod +
916 rtlpriv->link_info.num_tx_inperiod) > 8) ||
917 (rtlpriv->link_info.num_rx_inperiod > 2))
918 rtl_lps_leave(hw);
919 skb = new_skb;
920 no_new:
921 if (rtlpriv->use_new_trx_flow) {
922 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc,
923 rxring_idx,
924 rtlpci->rx_ring[rxring_idx].idx);
925 } else {
926 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc,
927 rxring_idx,
928 rtlpci->rx_ring[rxring_idx].idx);
929 if (rtlpci->rx_ring[rxring_idx].idx ==
930 rtlpci->rxringcount - 1)
931 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
932 false,
933 HW_DESC_RXERO,
934 (u8 *)&tmp_one);
935 }
936 rtlpci->rx_ring[rxring_idx].idx =
937 (rtlpci->rx_ring[rxring_idx].idx + 1) %
938 rtlpci->rxringcount;
939 }
940 }
941
_rtl_pci_interrupt(int irq,void * dev_id)942 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
943 {
944 struct ieee80211_hw *hw = dev_id;
945 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
946 struct rtl_priv *rtlpriv = rtl_priv(hw);
947 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
948 unsigned long flags;
949 u32 inta = 0;
950 u32 intb = 0;
951 u32 intc = 0;
952 u32 intd = 0;
953 irqreturn_t ret = IRQ_HANDLED;
954
955 if (rtlpci->irq_enabled == 0)
956 return ret;
957
958 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
959 rtlpriv->cfg->ops->disable_interrupt(hw);
960
961 /*read ISR: 4/8bytes */
962 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb, &intc, &intd);
963
964 /*Shared IRQ or HW disappeared */
965 if (!inta || inta == 0xffff)
966 goto done;
967
968 /*<1> beacon related */
969 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
970 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
971 "beacon ok interrupt!\n");
972 }
973
974 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
975 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
976 "beacon err interrupt!\n");
977 }
978
979 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK])
980 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
981
982 if (inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
983 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
984 "prepare beacon for interrupt!\n");
985 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
986 }
987
988 /*<2> Tx related */
989 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
990 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
991
992 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
993 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
994 "Manage ok interrupt!\n");
995 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
996 }
997
998 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
999 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1000 "HIGH_QUEUE ok interrupt!\n");
1001 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
1002 }
1003
1004 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
1005 rtlpriv->link_info.num_tx_inperiod++;
1006
1007 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1008 "BK Tx OK interrupt!\n");
1009 _rtl_pci_tx_isr(hw, BK_QUEUE);
1010 }
1011
1012 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
1013 rtlpriv->link_info.num_tx_inperiod++;
1014
1015 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1016 "BE TX OK interrupt!\n");
1017 _rtl_pci_tx_isr(hw, BE_QUEUE);
1018 }
1019
1020 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
1021 rtlpriv->link_info.num_tx_inperiod++;
1022
1023 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1024 "VI TX OK interrupt!\n");
1025 _rtl_pci_tx_isr(hw, VI_QUEUE);
1026 }
1027
1028 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
1029 rtlpriv->link_info.num_tx_inperiod++;
1030
1031 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1032 "Vo TX OK interrupt!\n");
1033 _rtl_pci_tx_isr(hw, VO_QUEUE);
1034 }
1035
1036 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
1037 if (intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) {
1038 rtlpriv->link_info.num_tx_inperiod++;
1039
1040 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1041 "H2C TX OK interrupt!\n");
1042 _rtl_pci_tx_isr(hw, H2C_QUEUE);
1043 }
1044 }
1045
1046 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
1047 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
1048 rtlpriv->link_info.num_tx_inperiod++;
1049
1050 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1051 "CMD TX OK interrupt!\n");
1052 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
1053 }
1054 }
1055
1056 /*<3> Rx related */
1057 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
1058 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
1059 _rtl_pci_rx_interrupt(hw);
1060 }
1061
1062 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
1063 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1064 "rx descriptor unavailable!\n");
1065 _rtl_pci_rx_interrupt(hw);
1066 }
1067
1068 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
1069 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
1070 _rtl_pci_rx_interrupt(hw);
1071 }
1072
1073 /*<4> fw related*/
1074 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
1075 if (inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
1076 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1077 "firmware interrupt!\n");
1078 queue_delayed_work(rtlpriv->works.rtl_wq,
1079 &rtlpriv->works.fwevt_wq, 0);
1080 }
1081 }
1082
1083 /*<5> hsisr related*/
1084 /* Only 8188EE & 8723BE Supported.
1085 * If Other ICs Come in, System will corrupt,
1086 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR]
1087 * are not initialized
1088 */
1089 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
1090 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1091 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
1092 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1093 "hsisr interrupt!\n");
1094 _rtl_pci_hs_interrupt(hw);
1095 }
1096 }
1097
1098 if (rtlpriv->rtlhal.earlymode_enable)
1099 tasklet_schedule(&rtlpriv->works.irq_tasklet);
1100
1101 done:
1102 rtlpriv->cfg->ops->enable_interrupt(hw);
1103 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1104 return ret;
1105 }
1106
_rtl_pci_irq_tasklet(struct ieee80211_hw * hw)1107 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
1108 {
1109 _rtl_pci_tx_chk_waitq(hw);
1110 }
1111
_rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw * hw)1112 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
1113 {
1114 struct rtl_priv *rtlpriv = rtl_priv(hw);
1115 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1116 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1117 struct rtl8192_tx_ring *ring = NULL;
1118 struct ieee80211_hdr *hdr = NULL;
1119 struct ieee80211_tx_info *info = NULL;
1120 struct sk_buff *pskb = NULL;
1121 struct rtl_tx_desc *pdesc = NULL;
1122 struct rtl_tcb_desc tcb_desc;
1123 /*This is for new trx flow*/
1124 struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
1125 u8 temp_one = 1;
1126 u8 *entry;
1127
1128 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
1129 ring = &rtlpci->tx_ring[BEACON_QUEUE];
1130 pskb = __skb_dequeue(&ring->queue);
1131 if (rtlpriv->use_new_trx_flow)
1132 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1133 else
1134 entry = (u8 *)(&ring->desc[ring->idx]);
1135 if (pskb) {
1136 pci_unmap_single(rtlpci->pdev,
1137 rtlpriv->cfg->ops->get_desc(
1138 hw, (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
1139 pskb->len, PCI_DMA_TODEVICE);
1140 kfree_skb(pskb);
1141 }
1142
1143 /*NB: the beacon data buffer must be 32-bit aligned. */
1144 pskb = ieee80211_beacon_get(hw, mac->vif);
1145 if (!pskb)
1146 return;
1147 hdr = rtl_get_hdr(pskb);
1148 info = IEEE80211_SKB_CB(pskb);
1149 pdesc = &ring->desc[0];
1150 if (rtlpriv->use_new_trx_flow)
1151 pbuffer_desc = &ring->buffer_desc[0];
1152
1153 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1154 (u8 *)pbuffer_desc, info, NULL, pskb,
1155 BEACON_QUEUE, &tcb_desc);
1156
1157 __skb_queue_tail(&ring->queue, pskb);
1158
1159 if (rtlpriv->use_new_trx_flow) {
1160 temp_one = 4;
1161 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
1162 HW_DESC_OWN, (u8 *)&temp_one);
1163 } else {
1164 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1165 &temp_one);
1166 }
1167 }
1168
_rtl_pci_init_trx_var(struct ieee80211_hw * hw)1169 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1170 {
1171 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1172 struct rtl_priv *rtlpriv = rtl_priv(hw);
1173 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1174 u8 i;
1175 u16 desc_num;
1176
1177 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1178 desc_num = TX_DESC_NUM_92E;
1179 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE)
1180 desc_num = TX_DESC_NUM_8822B;
1181 else
1182 desc_num = RT_TXDESC_NUM;
1183
1184 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1185 rtlpci->txringcount[i] = desc_num;
1186
1187 /*
1188 *we just alloc 2 desc for beacon queue,
1189 *because we just need first desc in hw beacon.
1190 */
1191 rtlpci->txringcount[BEACON_QUEUE] = 2;
1192
1193 /*BE queue need more descriptor for performance
1194 *consideration or, No more tx desc will happen,
1195 *and may cause mac80211 mem leakage.
1196 */
1197 if (!rtl_priv(hw)->use_new_trx_flow)
1198 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1199
1200 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1201 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1202 }
1203
_rtl_pci_init_struct(struct ieee80211_hw * hw,struct pci_dev * pdev)1204 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1205 struct pci_dev *pdev)
1206 {
1207 struct rtl_priv *rtlpriv = rtl_priv(hw);
1208 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1209 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1210 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1211
1212 rtlpci->up_first_time = true;
1213 rtlpci->being_init_adapter = false;
1214
1215 rtlhal->hw = hw;
1216 rtlpci->pdev = pdev;
1217
1218 /*Tx/Rx related var */
1219 _rtl_pci_init_trx_var(hw);
1220
1221 /*IBSS*/
1222 mac->beacon_interval = 100;
1223
1224 /*AMPDU*/
1225 mac->min_space_cfg = 0;
1226 mac->max_mss_density = 0;
1227 /*set sane AMPDU defaults */
1228 mac->current_ampdu_density = 7;
1229 mac->current_ampdu_factor = 3;
1230
1231 /*Retry Limit*/
1232 mac->retry_short = 7;
1233 mac->retry_long = 7;
1234
1235 /*QOS*/
1236 rtlpci->acm_method = EACMWAY2_SW;
1237
1238 /*task */
1239 tasklet_init(&rtlpriv->works.irq_tasklet,
1240 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1241 (unsigned long)hw);
1242 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1243 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1244 (unsigned long)hw);
1245 INIT_WORK(&rtlpriv->works.lps_change_work,
1246 rtl_lps_change_work_callback);
1247 }
1248
_rtl_pci_init_tx_ring(struct ieee80211_hw * hw,unsigned int prio,unsigned int entries)1249 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1250 unsigned int prio, unsigned int entries)
1251 {
1252 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1253 struct rtl_priv *rtlpriv = rtl_priv(hw);
1254 struct rtl_tx_buffer_desc *buffer_desc;
1255 struct rtl_tx_desc *desc;
1256 dma_addr_t buffer_desc_dma, desc_dma;
1257 u32 nextdescaddress;
1258 int i;
1259
1260 /* alloc tx buffer desc for new trx flow*/
1261 if (rtlpriv->use_new_trx_flow) {
1262 buffer_desc =
1263 pci_zalloc_consistent(rtlpci->pdev,
1264 sizeof(*buffer_desc) * entries,
1265 &buffer_desc_dma);
1266
1267 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
1268 pr_err("Cannot allocate TX ring (prio = %d)\n",
1269 prio);
1270 return -ENOMEM;
1271 }
1272
1273 rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1274 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1275
1276 rtlpci->tx_ring[prio].cur_tx_rp = 0;
1277 rtlpci->tx_ring[prio].cur_tx_wp = 0;
1278 }
1279
1280 /* alloc dma for this ring */
1281 desc = pci_zalloc_consistent(rtlpci->pdev,
1282 sizeof(*desc) * entries, &desc_dma);
1283
1284 if (!desc || (unsigned long)desc & 0xFF) {
1285 pr_err("Cannot allocate TX ring (prio = %d)\n", prio);
1286 return -ENOMEM;
1287 }
1288
1289 rtlpci->tx_ring[prio].desc = desc;
1290 rtlpci->tx_ring[prio].dma = desc_dma;
1291
1292 rtlpci->tx_ring[prio].idx = 0;
1293 rtlpci->tx_ring[prio].entries = entries;
1294 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1295
1296 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1297 prio, desc);
1298
1299 /* init every desc in this ring */
1300 if (!rtlpriv->use_new_trx_flow) {
1301 for (i = 0; i < entries; i++) {
1302 nextdescaddress = (u32)desc_dma +
1303 ((i + 1) % entries) *
1304 sizeof(*desc);
1305
1306 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
1307 true,
1308 HW_DESC_TX_NEXTDESC_ADDR,
1309 (u8 *)&nextdescaddress);
1310 }
1311 }
1312 return 0;
1313 }
1314
_rtl_pci_init_rx_ring(struct ieee80211_hw * hw,int rxring_idx)1315 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1316 {
1317 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1318 struct rtl_priv *rtlpriv = rtl_priv(hw);
1319 int i;
1320
1321 if (rtlpriv->use_new_trx_flow) {
1322 struct rtl_rx_buffer_desc *entry = NULL;
1323 /* alloc dma for this ring */
1324 rtlpci->rx_ring[rxring_idx].buffer_desc =
1325 pci_zalloc_consistent(rtlpci->pdev,
1326 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1327 rtlpci->rxringcount,
1328 &rtlpci->rx_ring[rxring_idx].dma);
1329 if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1330 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
1331 pr_err("Cannot allocate RX ring\n");
1332 return -ENOMEM;
1333 }
1334
1335 /* init every desc in this ring */
1336 rtlpci->rx_ring[rxring_idx].idx = 0;
1337 for (i = 0; i < rtlpci->rxringcount; i++) {
1338 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
1339 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1340 rxring_idx, i))
1341 return -ENOMEM;
1342 }
1343 } else {
1344 struct rtl_rx_desc *entry = NULL;
1345 u8 tmp_one = 1;
1346 /* alloc dma for this ring */
1347 rtlpci->rx_ring[rxring_idx].desc =
1348 pci_zalloc_consistent(rtlpci->pdev,
1349 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1350 rtlpci->rxringcount,
1351 &rtlpci->rx_ring[rxring_idx].dma);
1352 if (!rtlpci->rx_ring[rxring_idx].desc ||
1353 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
1354 pr_err("Cannot allocate RX ring\n");
1355 return -ENOMEM;
1356 }
1357
1358 /* init every desc in this ring */
1359 rtlpci->rx_ring[rxring_idx].idx = 0;
1360
1361 for (i = 0; i < rtlpci->rxringcount; i++) {
1362 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1363 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1364 rxring_idx, i))
1365 return -ENOMEM;
1366 }
1367
1368 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1369 HW_DESC_RXERO, &tmp_one);
1370 }
1371 return 0;
1372 }
1373
_rtl_pci_free_tx_ring(struct ieee80211_hw * hw,unsigned int prio)1374 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1375 unsigned int prio)
1376 {
1377 struct rtl_priv *rtlpriv = rtl_priv(hw);
1378 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1379 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1380
1381 /* free every desc in this ring */
1382 while (skb_queue_len(&ring->queue)) {
1383 u8 *entry;
1384 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1385
1386 if (rtlpriv->use_new_trx_flow)
1387 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1388 else
1389 entry = (u8 *)(&ring->desc[ring->idx]);
1390
1391 pci_unmap_single(rtlpci->pdev,
1392 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1393 true,
1394 HW_DESC_TXBUFF_ADDR),
1395 skb->len, PCI_DMA_TODEVICE);
1396 kfree_skb(skb);
1397 ring->idx = (ring->idx + 1) % ring->entries;
1398 }
1399
1400 /* free dma of this ring */
1401 pci_free_consistent(rtlpci->pdev,
1402 sizeof(*ring->desc) * ring->entries,
1403 ring->desc, ring->dma);
1404 ring->desc = NULL;
1405 if (rtlpriv->use_new_trx_flow) {
1406 pci_free_consistent(rtlpci->pdev,
1407 sizeof(*ring->buffer_desc) * ring->entries,
1408 ring->buffer_desc, ring->buffer_desc_dma);
1409 ring->buffer_desc = NULL;
1410 }
1411 }
1412
_rtl_pci_free_rx_ring(struct ieee80211_hw * hw,int rxring_idx)1413 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1414 {
1415 struct rtl_priv *rtlpriv = rtl_priv(hw);
1416 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1417 int i;
1418
1419 /* free every desc in this ring */
1420 for (i = 0; i < rtlpci->rxringcount; i++) {
1421 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
1422
1423 if (!skb)
1424 continue;
1425 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
1426 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
1427 kfree_skb(skb);
1428 }
1429
1430 /* free dma of this ring */
1431 if (rtlpriv->use_new_trx_flow) {
1432 pci_free_consistent(rtlpci->pdev,
1433 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1434 rtlpci->rxringcount,
1435 rtlpci->rx_ring[rxring_idx].buffer_desc,
1436 rtlpci->rx_ring[rxring_idx].dma);
1437 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1438 } else {
1439 pci_free_consistent(rtlpci->pdev,
1440 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1441 rtlpci->rxringcount,
1442 rtlpci->rx_ring[rxring_idx].desc,
1443 rtlpci->rx_ring[rxring_idx].dma);
1444 rtlpci->rx_ring[rxring_idx].desc = NULL;
1445 }
1446 }
1447
_rtl_pci_init_trx_ring(struct ieee80211_hw * hw)1448 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1449 {
1450 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1451 int ret;
1452 int i, rxring_idx;
1453
1454 /* rxring_idx 0:RX_MPDU_QUEUE
1455 * rxring_idx 1:RX_CMD_QUEUE
1456 */
1457 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1458 ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1459 if (ret)
1460 return ret;
1461 }
1462
1463 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1464 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]);
1465 if (ret)
1466 goto err_free_rings;
1467 }
1468
1469 return 0;
1470
1471 err_free_rings:
1472 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1473 _rtl_pci_free_rx_ring(hw, rxring_idx);
1474
1475 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1476 if (rtlpci->tx_ring[i].desc ||
1477 rtlpci->tx_ring[i].buffer_desc)
1478 _rtl_pci_free_tx_ring(hw, i);
1479
1480 return 1;
1481 }
1482
_rtl_pci_deinit_trx_ring(struct ieee80211_hw * hw)1483 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1484 {
1485 u32 i, rxring_idx;
1486
1487 /*free rx rings */
1488 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1489 _rtl_pci_free_rx_ring(hw, rxring_idx);
1490
1491 /*free tx rings */
1492 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1493 _rtl_pci_free_tx_ring(hw, i);
1494
1495 return 0;
1496 }
1497
rtl_pci_reset_trx_ring(struct ieee80211_hw * hw)1498 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1499 {
1500 struct rtl_priv *rtlpriv = rtl_priv(hw);
1501 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1502 int i, rxring_idx;
1503 unsigned long flags;
1504 u8 tmp_one = 1;
1505 u32 bufferaddress;
1506 /* rxring_idx 0:RX_MPDU_QUEUE */
1507 /* rxring_idx 1:RX_CMD_QUEUE */
1508 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1509 /* force the rx_ring[RX_MPDU_QUEUE/
1510 * RX_CMD_QUEUE].idx to the first one
1511 * new trx flow, do nothing
1512 */
1513 if (!rtlpriv->use_new_trx_flow &&
1514 rtlpci->rx_ring[rxring_idx].desc) {
1515 struct rtl_rx_desc *entry = NULL;
1516
1517 rtlpci->rx_ring[rxring_idx].idx = 0;
1518 for (i = 0; i < rtlpci->rxringcount; i++) {
1519 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1520 bufferaddress =
1521 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1522 false, HW_DESC_RXBUFF_ADDR);
1523 memset((u8 *)entry, 0,
1524 sizeof(*rtlpci->rx_ring
1525 [rxring_idx].desc));/*clear one entry*/
1526 if (rtlpriv->use_new_trx_flow) {
1527 /* This is deadcode */
1528 rtlpriv->cfg->ops->set_desc(hw,
1529 (u8 *)entry, false,
1530 HW_DESC_RX_PREPARE,
1531 (u8 *)&bufferaddress);
1532 } else {
1533 rtlpriv->cfg->ops->set_desc(hw,
1534 (u8 *)entry, false,
1535 HW_DESC_RXBUFF_ADDR,
1536 (u8 *)&bufferaddress);
1537 rtlpriv->cfg->ops->set_desc(hw,
1538 (u8 *)entry, false,
1539 HW_DESC_RXPKT_LEN,
1540 (u8 *)&rtlpci->rxbuffersize);
1541 rtlpriv->cfg->ops->set_desc(hw,
1542 (u8 *)entry, false,
1543 HW_DESC_RXOWN,
1544 (u8 *)&tmp_one);
1545 }
1546 }
1547 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1548 HW_DESC_RXERO, (u8 *)&tmp_one);
1549 }
1550 rtlpci->rx_ring[rxring_idx].idx = 0;
1551 }
1552
1553 /*
1554 *after reset, release previous pending packet,
1555 *and force the tx idx to the first one
1556 */
1557 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1558 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1559 if (rtlpci->tx_ring[i].desc ||
1560 rtlpci->tx_ring[i].buffer_desc) {
1561 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1562
1563 while (skb_queue_len(&ring->queue)) {
1564 u8 *entry;
1565 struct sk_buff *skb =
1566 __skb_dequeue(&ring->queue);
1567 if (rtlpriv->use_new_trx_flow)
1568 entry = (u8 *)(&ring->buffer_desc
1569 [ring->idx]);
1570 else
1571 entry = (u8 *)(&ring->desc[ring->idx]);
1572
1573 pci_unmap_single(rtlpci->pdev,
1574 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1575 true, HW_DESC_TXBUFF_ADDR),
1576 skb->len, PCI_DMA_TODEVICE);
1577 dev_kfree_skb_irq(skb);
1578 ring->idx = (ring->idx + 1) % ring->entries;
1579 }
1580
1581 if (rtlpriv->use_new_trx_flow) {
1582 rtlpci->tx_ring[i].cur_tx_rp = 0;
1583 rtlpci->tx_ring[i].cur_tx_wp = 0;
1584 }
1585
1586 ring->idx = 0;
1587 ring->entries = rtlpci->txringcount[i];
1588 }
1589 }
1590 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1591
1592 return 0;
1593 }
1594
rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct sk_buff * skb)1595 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1596 struct ieee80211_sta *sta,
1597 struct sk_buff *skb)
1598 {
1599 struct rtl_priv *rtlpriv = rtl_priv(hw);
1600 struct rtl_sta_info *sta_entry = NULL;
1601 u8 tid = rtl_get_tid(skb);
1602 __le16 fc = rtl_get_fc(skb);
1603
1604 if (!sta)
1605 return false;
1606 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1607
1608 if (!rtlpriv->rtlhal.earlymode_enable)
1609 return false;
1610 if (ieee80211_is_nullfunc(fc))
1611 return false;
1612 if (ieee80211_is_qos_nullfunc(fc))
1613 return false;
1614 if (ieee80211_is_pspoll(fc))
1615 return false;
1616 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1617 return false;
1618 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1619 return false;
1620 if (tid > 7)
1621 return false;
1622
1623 /* maybe every tid should be checked */
1624 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1625 return false;
1626
1627 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1628 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1629 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1630
1631 return true;
1632 }
1633
rtl_pci_tx(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct sk_buff * skb,struct rtl_tcb_desc * ptcb_desc)1634 static int rtl_pci_tx(struct ieee80211_hw *hw,
1635 struct ieee80211_sta *sta,
1636 struct sk_buff *skb,
1637 struct rtl_tcb_desc *ptcb_desc)
1638 {
1639 struct rtl_priv *rtlpriv = rtl_priv(hw);
1640 struct rtl_sta_info *sta_entry = NULL;
1641 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1642 struct rtl8192_tx_ring *ring;
1643 struct rtl_tx_desc *pdesc;
1644 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
1645 u16 idx;
1646 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1647 unsigned long flags;
1648 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1649 __le16 fc = rtl_get_fc(skb);
1650 u8 *pda_addr = hdr->addr1;
1651 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1652 /*ssn */
1653 u8 tid = 0;
1654 u16 seq_number = 0;
1655 u8 own;
1656 u8 temp_one = 1;
1657
1658 if (ieee80211_is_mgmt(fc))
1659 rtl_tx_mgmt_proc(hw, skb);
1660
1661 if (rtlpriv->psc.sw_ps_enabled) {
1662 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1663 !ieee80211_has_pm(fc))
1664 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1665 }
1666
1667 rtl_action_proc(hw, skb, true);
1668
1669 if (is_multicast_ether_addr(pda_addr))
1670 rtlpriv->stats.txbytesmulticast += skb->len;
1671 else if (is_broadcast_ether_addr(pda_addr))
1672 rtlpriv->stats.txbytesbroadcast += skb->len;
1673 else
1674 rtlpriv->stats.txbytesunicast += skb->len;
1675
1676 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1677 ring = &rtlpci->tx_ring[hw_queue];
1678 if (hw_queue != BEACON_QUEUE) {
1679 if (rtlpriv->use_new_trx_flow)
1680 idx = ring->cur_tx_wp;
1681 else
1682 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1683 ring->entries;
1684 } else {
1685 idx = 0;
1686 }
1687
1688 pdesc = &ring->desc[idx];
1689 if (rtlpriv->use_new_trx_flow) {
1690 ptx_bd_desc = &ring->buffer_desc[idx];
1691 } else {
1692 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
1693 true, HW_DESC_OWN);
1694
1695 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1696 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1697 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1698 hw_queue, ring->idx, idx,
1699 skb_queue_len(&ring->queue));
1700
1701 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1702 flags);
1703 return skb->len;
1704 }
1705 }
1706
1707 if (rtlpriv->cfg->ops->get_available_desc &&
1708 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
1709 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1710 "get_available_desc fail\n");
1711 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1712 return skb->len;
1713 }
1714
1715 if (ieee80211_is_data_qos(fc)) {
1716 tid = rtl_get_tid(skb);
1717 if (sta) {
1718 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1719 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1720 IEEE80211_SCTL_SEQ) >> 4;
1721 seq_number += 1;
1722
1723 if (!ieee80211_has_morefrags(hdr->frame_control))
1724 sta_entry->tids[tid].seq_number = seq_number;
1725 }
1726 }
1727
1728 if (ieee80211_is_data(fc))
1729 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1730
1731 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1732 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
1733
1734 __skb_queue_tail(&ring->queue, skb);
1735
1736 if (rtlpriv->use_new_trx_flow) {
1737 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1738 HW_DESC_OWN, &hw_queue);
1739 } else {
1740 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1741 HW_DESC_OWN, &temp_one);
1742 }
1743
1744 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1745 hw_queue != BEACON_QUEUE) {
1746 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1747 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1748 hw_queue, ring->idx, idx,
1749 skb_queue_len(&ring->queue));
1750
1751 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1752 }
1753
1754 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1755
1756 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1757
1758 return 0;
1759 }
1760
rtl_pci_flush(struct ieee80211_hw * hw,u32 queues,bool drop)1761 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1762 {
1763 struct rtl_priv *rtlpriv = rtl_priv(hw);
1764 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1765 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1766 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1767 u16 i = 0;
1768 int queue_id;
1769 struct rtl8192_tx_ring *ring;
1770
1771 if (mac->skip_scan)
1772 return;
1773
1774 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1775 u32 queue_len;
1776
1777 if (((queues >> queue_id) & 0x1) == 0) {
1778 queue_id--;
1779 continue;
1780 }
1781 ring = &pcipriv->dev.tx_ring[queue_id];
1782 queue_len = skb_queue_len(&ring->queue);
1783 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1784 queue_id == TXCMD_QUEUE) {
1785 queue_id--;
1786 continue;
1787 } else {
1788 msleep(20);
1789 i++;
1790 }
1791
1792 /* we just wait 1s for all queues */
1793 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1794 is_hal_stop(rtlhal) || i >= 200)
1795 return;
1796 }
1797 }
1798
rtl_pci_deinit(struct ieee80211_hw * hw)1799 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1800 {
1801 struct rtl_priv *rtlpriv = rtl_priv(hw);
1802 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1803
1804 _rtl_pci_deinit_trx_ring(hw);
1805
1806 synchronize_irq(rtlpci->pdev->irq);
1807 tasklet_kill(&rtlpriv->works.irq_tasklet);
1808 cancel_work_sync(&rtlpriv->works.lps_change_work);
1809
1810 flush_workqueue(rtlpriv->works.rtl_wq);
1811 destroy_workqueue(rtlpriv->works.rtl_wq);
1812 }
1813
rtl_pci_init(struct ieee80211_hw * hw,struct pci_dev * pdev)1814 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1815 {
1816 int err;
1817
1818 _rtl_pci_init_struct(hw, pdev);
1819
1820 err = _rtl_pci_init_trx_ring(hw);
1821 if (err) {
1822 pr_err("tx ring initialization failed\n");
1823 return err;
1824 }
1825
1826 return 0;
1827 }
1828
rtl_pci_start(struct ieee80211_hw * hw)1829 static int rtl_pci_start(struct ieee80211_hw *hw)
1830 {
1831 struct rtl_priv *rtlpriv = rtl_priv(hw);
1832 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1833 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1834 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1835 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
1836
1837 int err;
1838
1839 rtl_pci_reset_trx_ring(hw);
1840
1841 rtlpci->driver_is_goingto_unload = false;
1842 if (rtlpriv->cfg->ops->get_btc_status &&
1843 rtlpriv->cfg->ops->get_btc_status()) {
1844 rtlpriv->btcoexist.btc_info.ap_num = 36;
1845 rtlpriv->btcoexist.btc_ops->btc_init_variables(rtlpriv);
1846 rtlpriv->btcoexist.btc_ops->btc_init_hal_vars(rtlpriv);
1847 } else if (rtlpriv->btcoexist.btc_ops) {
1848 rtlpriv->btcoexist.btc_ops->btc_init_variables_wifi_only(
1849 rtlpriv);
1850 }
1851
1852 err = rtlpriv->cfg->ops->hw_init(hw);
1853 if (err) {
1854 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1855 "Failed to config hardware!\n");
1856 return err;
1857 }
1858 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
1859 &rtlmac->retry_long);
1860
1861 rtlpriv->cfg->ops->enable_interrupt(hw);
1862 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1863
1864 rtl_init_rx_config(hw);
1865
1866 /*should be after adapter start and interrupt enable. */
1867 set_hal_start(rtlhal);
1868
1869 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1870
1871 rtlpci->up_first_time = false;
1872
1873 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__);
1874 return 0;
1875 }
1876
rtl_pci_stop(struct ieee80211_hw * hw)1877 static void rtl_pci_stop(struct ieee80211_hw *hw)
1878 {
1879 struct rtl_priv *rtlpriv = rtl_priv(hw);
1880 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1881 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1882 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1883 unsigned long flags;
1884 u8 rf_timeout = 0;
1885
1886 if (rtlpriv->cfg->ops->get_btc_status())
1887 rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv);
1888
1889 if (rtlpriv->btcoexist.btc_ops)
1890 rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv);
1891
1892 /*
1893 *should be before disable interrupt&adapter
1894 *and will do it immediately.
1895 */
1896 set_hal_stop(rtlhal);
1897
1898 rtlpci->driver_is_goingto_unload = true;
1899 rtlpriv->cfg->ops->disable_interrupt(hw);
1900 cancel_work_sync(&rtlpriv->works.lps_change_work);
1901
1902 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1903 while (ppsc->rfchange_inprogress) {
1904 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1905 if (rf_timeout > 100) {
1906 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1907 break;
1908 }
1909 mdelay(1);
1910 rf_timeout++;
1911 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1912 }
1913 ppsc->rfchange_inprogress = true;
1914 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1915
1916 rtlpriv->cfg->ops->hw_disable(hw);
1917 /* some things are not needed if firmware not available */
1918 if (!rtlpriv->max_fw_size)
1919 return;
1920 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1921
1922 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1923 ppsc->rfchange_inprogress = false;
1924 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1925
1926 rtl_pci_enable_aspm(hw);
1927 }
1928
_rtl_pci_find_adapter(struct pci_dev * pdev,struct ieee80211_hw * hw)1929 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1930 struct ieee80211_hw *hw)
1931 {
1932 struct rtl_priv *rtlpriv = rtl_priv(hw);
1933 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1934 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1935 struct pci_dev *bridge_pdev = pdev->bus->self;
1936 u16 venderid;
1937 u16 deviceid;
1938 u8 revisionid;
1939 u16 irqline;
1940 u8 tmp;
1941
1942 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1943 venderid = pdev->vendor;
1944 deviceid = pdev->device;
1945 pci_read_config_byte(pdev, 0x8, &revisionid);
1946 pci_read_config_word(pdev, 0x3C, &irqline);
1947
1948 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1949 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1950 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1951 * the correct driver is r8192e_pci, thus this routine should
1952 * return false.
1953 */
1954 if (deviceid == RTL_PCI_8192SE_DID &&
1955 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1956 return false;
1957
1958 if (deviceid == RTL_PCI_8192_DID ||
1959 deviceid == RTL_PCI_0044_DID ||
1960 deviceid == RTL_PCI_0047_DID ||
1961 deviceid == RTL_PCI_8192SE_DID ||
1962 deviceid == RTL_PCI_8174_DID ||
1963 deviceid == RTL_PCI_8173_DID ||
1964 deviceid == RTL_PCI_8172_DID ||
1965 deviceid == RTL_PCI_8171_DID) {
1966 switch (revisionid) {
1967 case RTL_PCI_REVISION_ID_8192PCIE:
1968 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1969 "8192 PCI-E is found - vid/did=%x/%x\n",
1970 venderid, deviceid);
1971 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1972 return false;
1973 case RTL_PCI_REVISION_ID_8192SE:
1974 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1975 "8192SE is found - vid/did=%x/%x\n",
1976 venderid, deviceid);
1977 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1978 break;
1979 default:
1980 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1981 "Err: Unknown device - vid/did=%x/%x\n",
1982 venderid, deviceid);
1983 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1984 break;
1985 }
1986 } else if (deviceid == RTL_PCI_8723AE_DID) {
1987 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1988 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1989 "8723AE PCI-E is found - vid/did=%x/%x\n",
1990 venderid, deviceid);
1991 } else if (deviceid == RTL_PCI_8192CET_DID ||
1992 deviceid == RTL_PCI_8192CE_DID ||
1993 deviceid == RTL_PCI_8191CE_DID ||
1994 deviceid == RTL_PCI_8188CE_DID) {
1995 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1996 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1997 "8192C PCI-E is found - vid/did=%x/%x\n",
1998 venderid, deviceid);
1999 } else if (deviceid == RTL_PCI_8192DE_DID ||
2000 deviceid == RTL_PCI_8192DE_DID2) {
2001 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
2002 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2003 "8192D PCI-E is found - vid/did=%x/%x\n",
2004 venderid, deviceid);
2005 } else if (deviceid == RTL_PCI_8188EE_DID) {
2006 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
2007 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2008 "Find adapter, Hardware type is 8188EE\n");
2009 } else if (deviceid == RTL_PCI_8723BE_DID) {
2010 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
2011 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2012 "Find adapter, Hardware type is 8723BE\n");
2013 } else if (deviceid == RTL_PCI_8192EE_DID) {
2014 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
2015 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2016 "Find adapter, Hardware type is 8192EE\n");
2017 } else if (deviceid == RTL_PCI_8821AE_DID) {
2018 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
2019 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2020 "Find adapter, Hardware type is 8821AE\n");
2021 } else if (deviceid == RTL_PCI_8812AE_DID) {
2022 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
2023 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2024 "Find adapter, Hardware type is 8812AE\n");
2025 } else if (deviceid == RTL_PCI_8822BE_DID) {
2026 rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE;
2027 rtlhal->bandset = BAND_ON_BOTH;
2028 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2029 "Find adapter, Hardware type is 8822BE\n");
2030 } else {
2031 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2032 "Err: Unknown device - vid/did=%x/%x\n",
2033 venderid, deviceid);
2034
2035 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
2036 }
2037
2038 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
2039 if (revisionid == 0 || revisionid == 1) {
2040 if (revisionid == 0) {
2041 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2042 "Find 92DE MAC0\n");
2043 rtlhal->interfaceindex = 0;
2044 } else if (revisionid == 1) {
2045 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2046 "Find 92DE MAC1\n");
2047 rtlhal->interfaceindex = 1;
2048 }
2049 } else {
2050 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2051 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
2052 venderid, deviceid, revisionid);
2053 rtlhal->interfaceindex = 0;
2054 }
2055 }
2056
2057 switch (rtlhal->hw_type) {
2058 case HARDWARE_TYPE_RTL8192EE:
2059 case HARDWARE_TYPE_RTL8822BE:
2060 /* use new trx flow */
2061 rtlpriv->use_new_trx_flow = true;
2062 break;
2063
2064 default:
2065 rtlpriv->use_new_trx_flow = false;
2066 break;
2067 }
2068
2069 /*find bus info */
2070 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
2071 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
2072 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
2073
2074 /*find bridge info */
2075 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
2076 /* some ARM have no bridge_pdev and will crash here
2077 * so we should check if bridge_pdev is NULL
2078 */
2079 if (bridge_pdev) {
2080 /*find bridge info if available */
2081 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
2082 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
2083 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
2084 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
2085 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2086 "Pci Bridge Vendor is found index: %d\n",
2087 tmp);
2088 break;
2089 }
2090 }
2091 }
2092
2093 if (pcipriv->ndis_adapter.pcibridge_vendor !=
2094 PCI_BRIDGE_VENDOR_UNKNOWN) {
2095 pcipriv->ndis_adapter.pcibridge_busnum =
2096 bridge_pdev->bus->number;
2097 pcipriv->ndis_adapter.pcibridge_devnum =
2098 PCI_SLOT(bridge_pdev->devfn);
2099 pcipriv->ndis_adapter.pcibridge_funcnum =
2100 PCI_FUNC(bridge_pdev->devfn);
2101 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
2102 pci_pcie_cap(bridge_pdev);
2103 pcipriv->ndis_adapter.num4bytes =
2104 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
2105
2106 rtl_pci_get_linkcontrol_field(hw);
2107
2108 if (pcipriv->ndis_adapter.pcibridge_vendor ==
2109 PCI_BRIDGE_VENDOR_AMD) {
2110 pcipriv->ndis_adapter.amd_l1_patch =
2111 rtl_pci_get_amd_l1_patch(hw);
2112 }
2113 }
2114
2115 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2116 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
2117 pcipriv->ndis_adapter.busnumber,
2118 pcipriv->ndis_adapter.devnumber,
2119 pcipriv->ndis_adapter.funcnumber,
2120 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
2121
2122 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2123 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
2124 pcipriv->ndis_adapter.pcibridge_busnum,
2125 pcipriv->ndis_adapter.pcibridge_devnum,
2126 pcipriv->ndis_adapter.pcibridge_funcnum,
2127 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
2128 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
2129 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
2130 pcipriv->ndis_adapter.amd_l1_patch);
2131
2132 rtl_pci_parse_configuration(pdev, hw);
2133 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
2134
2135 return true;
2136 }
2137
rtl_pci_intr_mode_msi(struct ieee80211_hw * hw)2138 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
2139 {
2140 struct rtl_priv *rtlpriv = rtl_priv(hw);
2141 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2142 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2143 int ret;
2144
2145 ret = pci_enable_msi(rtlpci->pdev);
2146 if (ret < 0)
2147 return ret;
2148
2149 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2150 IRQF_SHARED, KBUILD_MODNAME, hw);
2151 if (ret < 0) {
2152 pci_disable_msi(rtlpci->pdev);
2153 return ret;
2154 }
2155
2156 rtlpci->using_msi = true;
2157
2158 RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2159 "MSI Interrupt Mode!\n");
2160 return 0;
2161 }
2162
rtl_pci_intr_mode_legacy(struct ieee80211_hw * hw)2163 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2164 {
2165 struct rtl_priv *rtlpriv = rtl_priv(hw);
2166 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2167 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2168 int ret;
2169
2170 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2171 IRQF_SHARED, KBUILD_MODNAME, hw);
2172 if (ret < 0)
2173 return ret;
2174
2175 rtlpci->using_msi = false;
2176 RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2177 "Pin-based Interrupt Mode!\n");
2178 return 0;
2179 }
2180
rtl_pci_intr_mode_decide(struct ieee80211_hw * hw)2181 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2182 {
2183 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2184 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2185 int ret;
2186
2187 if (rtlpci->msi_support) {
2188 ret = rtl_pci_intr_mode_msi(hw);
2189 if (ret < 0)
2190 ret = rtl_pci_intr_mode_legacy(hw);
2191 } else {
2192 ret = rtl_pci_intr_mode_legacy(hw);
2193 }
2194 return ret;
2195 }
2196
platform_enable_dma64(struct pci_dev * pdev,bool dma64)2197 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64)
2198 {
2199 u8 value;
2200
2201 pci_read_config_byte(pdev, 0x719, &value);
2202
2203 /* 0x719 Bit5 is DMA64 bit fetch. */
2204 if (dma64)
2205 value |= BIT(5);
2206 else
2207 value &= ~BIT(5);
2208
2209 pci_write_config_byte(pdev, 0x719, value);
2210 }
2211
rtl_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)2212 int rtl_pci_probe(struct pci_dev *pdev,
2213 const struct pci_device_id *id)
2214 {
2215 struct ieee80211_hw *hw = NULL;
2216
2217 struct rtl_priv *rtlpriv = NULL;
2218 struct rtl_pci_priv *pcipriv = NULL;
2219 struct rtl_pci *rtlpci;
2220 unsigned long pmem_start, pmem_len, pmem_flags;
2221 int err;
2222
2223 err = rtl_core_module_init();
2224 if (err)
2225 return err;
2226 err = pci_enable_device(pdev);
2227 if (err) {
2228 WARN_ONCE(true, "%s : Cannot enable new PCI device\n",
2229 pci_name(pdev));
2230 return err;
2231 }
2232
2233 if (((struct rtl_hal_cfg *)(id->driver_data))->mod_params->dma64 &&
2234 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2235 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2236 WARN_ONCE(true,
2237 "Unable to obtain 64bit DMA for consistent allocations\n");
2238 err = -ENOMEM;
2239 goto fail1;
2240 }
2241
2242 platform_enable_dma64(pdev, true);
2243 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2244 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
2245 WARN_ONCE(true,
2246 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n");
2247 err = -ENOMEM;
2248 goto fail1;
2249 }
2250
2251 platform_enable_dma64(pdev, false);
2252 }
2253
2254 pci_set_master(pdev);
2255
2256 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2257 sizeof(struct rtl_priv), &rtl_ops);
2258 if (!hw) {
2259 WARN_ONCE(true,
2260 "%s : ieee80211 alloc failed\n", pci_name(pdev));
2261 err = -ENOMEM;
2262 goto fail1;
2263 }
2264
2265 SET_IEEE80211_DEV(hw, &pdev->dev);
2266 pci_set_drvdata(pdev, hw);
2267
2268 rtlpriv = hw->priv;
2269 rtlpriv->hw = hw;
2270 pcipriv = (void *)rtlpriv->priv;
2271 pcipriv->dev.pdev = pdev;
2272 init_completion(&rtlpriv->firmware_loading_complete);
2273 /*proximity init here*/
2274 rtlpriv->proximity.proxim_on = false;
2275
2276 pcipriv = (void *)rtlpriv->priv;
2277 pcipriv->dev.pdev = pdev;
2278
2279 /* init cfg & intf_ops */
2280 rtlpriv->rtlhal.interface = INTF_PCI;
2281 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2282 rtlpriv->intf_ops = &rtl_pci_ops;
2283 rtlpriv->glb_var = &rtl_global_var;
2284
2285 /* MEM map */
2286 err = pci_request_regions(pdev, KBUILD_MODNAME);
2287 if (err) {
2288 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n");
2289 goto fail1;
2290 }
2291
2292 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2293 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2294 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
2295
2296 /*shared mem start */
2297 rtlpriv->io.pci_mem_start =
2298 (unsigned long)pci_iomap(pdev,
2299 rtlpriv->cfg->bar_id, pmem_len);
2300 if (rtlpriv->io.pci_mem_start == 0) {
2301 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n");
2302 err = -ENOMEM;
2303 goto fail2;
2304 }
2305
2306 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2307 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
2308 pmem_start, pmem_len, pmem_flags,
2309 rtlpriv->io.pci_mem_start);
2310
2311 /* Disable Clk Request */
2312 pci_write_config_byte(pdev, 0x81, 0);
2313 /* leave D3 mode */
2314 pci_write_config_byte(pdev, 0x44, 0);
2315 pci_write_config_byte(pdev, 0x04, 0x06);
2316 pci_write_config_byte(pdev, 0x04, 0x07);
2317
2318 /* find adapter */
2319 if (!_rtl_pci_find_adapter(pdev, hw)) {
2320 err = -ENODEV;
2321 goto fail2;
2322 }
2323
2324 /* Init IO handler */
2325 _rtl_pci_io_handler_init(&pdev->dev, hw);
2326
2327 /*like read eeprom and so on */
2328 rtlpriv->cfg->ops->read_eeprom_info(hw);
2329
2330 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2331 pr_err("Can't init_sw_vars\n");
2332 err = -ENODEV;
2333 goto fail3;
2334 }
2335 rtlpriv->cfg->ops->init_sw_leds(hw);
2336
2337 /*aspm */
2338 rtl_pci_init_aspm(hw);
2339
2340 /* Init mac80211 sw */
2341 err = rtl_init_core(hw);
2342 if (err) {
2343 pr_err("Can't allocate sw for mac80211\n");
2344 goto fail3;
2345 }
2346
2347 /* Init PCI sw */
2348 err = rtl_pci_init(hw, pdev);
2349 if (err) {
2350 pr_err("Failed to init PCI\n");
2351 goto fail3;
2352 }
2353
2354 err = ieee80211_register_hw(hw);
2355 if (err) {
2356 pr_err("Can't register mac80211 hw.\n");
2357 err = -ENODEV;
2358 goto fail3;
2359 }
2360 rtlpriv->mac80211.mac80211_registered = 1;
2361
2362 /* add for debug */
2363 rtl_debug_add_one(hw);
2364
2365 /*init rfkill */
2366 rtl_init_rfkill(hw); /* Init PCI sw */
2367
2368 rtlpci = rtl_pcidev(pcipriv);
2369 err = rtl_pci_intr_mode_decide(hw);
2370 if (err) {
2371 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2372 "%s: failed to register IRQ handler\n",
2373 wiphy_name(hw->wiphy));
2374 goto fail3;
2375 }
2376 rtlpci->irq_alloc = 1;
2377
2378 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2379 return 0;
2380
2381 fail3:
2382 pci_set_drvdata(pdev, NULL);
2383 rtl_deinit_core(hw);
2384
2385 fail2:
2386 if (rtlpriv->io.pci_mem_start != 0)
2387 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2388
2389 pci_release_regions(pdev);
2390 complete(&rtlpriv->firmware_loading_complete);
2391
2392 fail1:
2393 if (hw)
2394 ieee80211_free_hw(hw);
2395 pci_disable_device(pdev);
2396
2397 return err;
2398 }
2399
rtl_pci_disconnect(struct pci_dev * pdev)2400 void rtl_pci_disconnect(struct pci_dev *pdev)
2401 {
2402 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2403 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2404 struct rtl_priv *rtlpriv = rtl_priv(hw);
2405 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2406 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2407
2408 /* just in case driver is removed before firmware callback */
2409 wait_for_completion(&rtlpriv->firmware_loading_complete);
2410 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2411
2412 /* remove form debug */
2413 rtl_debug_remove_one(hw);
2414
2415 /*ieee80211_unregister_hw will call ops_stop */
2416 if (rtlmac->mac80211_registered == 1) {
2417 ieee80211_unregister_hw(hw);
2418 rtlmac->mac80211_registered = 0;
2419 } else {
2420 rtl_deinit_deferred_work(hw);
2421 rtlpriv->intf_ops->adapter_stop(hw);
2422 }
2423 rtlpriv->cfg->ops->disable_interrupt(hw);
2424
2425 /*deinit rfkill */
2426 rtl_deinit_rfkill(hw);
2427
2428 rtl_pci_deinit(hw);
2429 rtl_deinit_core(hw);
2430 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2431
2432 if (rtlpci->irq_alloc) {
2433 free_irq(rtlpci->pdev->irq, hw);
2434 rtlpci->irq_alloc = 0;
2435 }
2436
2437 if (rtlpci->using_msi)
2438 pci_disable_msi(rtlpci->pdev);
2439
2440 list_del(&rtlpriv->list);
2441 if (rtlpriv->io.pci_mem_start != 0) {
2442 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2443 pci_release_regions(pdev);
2444 }
2445
2446 pci_disable_device(pdev);
2447
2448 rtl_pci_disable_aspm(hw);
2449
2450 pci_set_drvdata(pdev, NULL);
2451
2452 ieee80211_free_hw(hw);
2453 rtl_core_module_exit();
2454 }
2455
2456 #ifdef CONFIG_PM_SLEEP
2457 /***************************************
2458 * kernel pci power state define:
2459 * PCI_D0 ((pci_power_t __force) 0)
2460 * PCI_D1 ((pci_power_t __force) 1)
2461 * PCI_D2 ((pci_power_t __force) 2)
2462 * PCI_D3hot ((pci_power_t __force) 3)
2463 * PCI_D3cold ((pci_power_t __force) 4)
2464 * PCI_UNKNOWN ((pci_power_t __force) 5)
2465
2466 * This function is called when system
2467 * goes into suspend state mac80211 will
2468 * call rtl_mac_stop() from the mac80211
2469 * suspend function first, So there is
2470 * no need to call hw_disable here.
2471 ****************************************/
rtl_pci_suspend(struct device * dev)2472 int rtl_pci_suspend(struct device *dev)
2473 {
2474 struct pci_dev *pdev = to_pci_dev(dev);
2475 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2476 struct rtl_priv *rtlpriv = rtl_priv(hw);
2477
2478 rtlpriv->cfg->ops->hw_suspend(hw);
2479 rtl_deinit_rfkill(hw);
2480
2481 return 0;
2482 }
2483
rtl_pci_resume(struct device * dev)2484 int rtl_pci_resume(struct device *dev)
2485 {
2486 struct pci_dev *pdev = to_pci_dev(dev);
2487 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2488 struct rtl_priv *rtlpriv = rtl_priv(hw);
2489
2490 rtlpriv->cfg->ops->hw_resume(hw);
2491 rtl_init_rfkill(hw);
2492 return 0;
2493 }
2494 #endif /* CONFIG_PM_SLEEP */
2495
2496 const struct rtl_intf_ops rtl_pci_ops = {
2497 .read_efuse_byte = read_efuse_byte,
2498 .adapter_start = rtl_pci_start,
2499 .adapter_stop = rtl_pci_stop,
2500 .check_buddy_priv = rtl_pci_check_buddy_priv,
2501 .adapter_tx = rtl_pci_tx,
2502 .flush = rtl_pci_flush,
2503 .reset_trx_ring = rtl_pci_reset_trx_ring,
2504 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2505
2506 .disable_aspm = rtl_pci_disable_aspm,
2507 .enable_aspm = rtl_pci_enable_aspm,
2508 };
2509