1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Thunderbolt driver - NHI registers 4 * 5 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com> 6 */ 7 8 #ifndef NHI_REGS_H_ 9 #define NHI_REGS_H_ 10 11 #include <linux/types.h> 12 13 enum ring_flags { 14 RING_FLAG_ISOCH_ENABLE = 1 << 27, /* TX only? */ 15 RING_FLAG_E2E_FLOW_CONTROL = 1 << 28, 16 RING_FLAG_PCI_NO_SNOOP = 1 << 29, 17 RING_FLAG_RAW = 1 << 30, /* ignore EOF/SOF mask, include checksum */ 18 RING_FLAG_ENABLE = 1 << 31, 19 }; 20 21 enum ring_desc_flags { 22 RING_DESC_ISOCH = 0x1, /* TX only? */ 23 RING_DESC_COMPLETED = 0x2, /* set by NHI */ 24 RING_DESC_POSTED = 0x4, /* always set this */ 25 RING_DESC_INTERRUPT = 0x8, /* request an interrupt on completion */ 26 }; 27 28 /** 29 * struct ring_desc - TX/RX ring entry 30 * 31 * For TX set length/eof/sof. 32 * For RX length/eof/sof are set by the NHI. 33 */ 34 struct ring_desc { 35 u64 phys; 36 u32 length:12; 37 u32 eof:4; 38 u32 sof:4; 39 enum ring_desc_flags flags:12; 40 u32 time; /* write zero */ 41 } __packed; 42 43 /* NHI registers in bar 0 */ 44 45 /* 46 * 16 bytes per entry, one entry for every hop (REG_HOP_COUNT) 47 * 00: physical pointer to an array of struct ring_desc 48 * 08: ring tail (set by NHI) 49 * 10: ring head (index of first non posted descriptor) 50 * 12: descriptor count 51 */ 52 #define REG_TX_RING_BASE 0x00000 53 54 /* 55 * 16 bytes per entry, one entry for every hop (REG_HOP_COUNT) 56 * 00: physical pointer to an array of struct ring_desc 57 * 08: ring head (index of first not posted descriptor) 58 * 10: ring tail (set by NHI) 59 * 12: descriptor count 60 * 14: max frame sizes (anything larger than 0x100 has no effect) 61 */ 62 #define REG_RX_RING_BASE 0x08000 63 64 /* 65 * 32 bytes per entry, one entry for every hop (REG_HOP_COUNT) 66 * 00: enum_ring_flags 67 * 04: isoch time stamp ?? (write 0) 68 * ..: unknown 69 */ 70 #define REG_TX_OPTIONS_BASE 0x19800 71 72 /* 73 * 32 bytes per entry, one entry for every hop (REG_HOP_COUNT) 74 * 00: enum ring_flags 75 * If RING_FLAG_E2E_FLOW_CONTROL is set then bits 13-23 must be set to 76 * the corresponding TX hop id. 77 * 04: EOF/SOF mask (ignored for RING_FLAG_RAW rings) 78 * ..: unknown 79 */ 80 #define REG_RX_OPTIONS_BASE 0x29800 81 82 /* 83 * three bitfields: tx, rx, rx overflow 84 * Every bitfield contains one bit for every hop (REG_HOP_COUNT). Registers are 85 * cleared on read. New interrupts are fired only after ALL registers have been 86 * read (even those containing only disabled rings). 87 */ 88 #define REG_RING_NOTIFY_BASE 0x37800 89 #define RING_NOTIFY_REG_COUNT(nhi) ((31 + 3 * nhi->hop_count) / 32) 90 91 /* 92 * two bitfields: rx, tx 93 * Both bitfields contains one bit for every hop (REG_HOP_COUNT). To 94 * enable/disable interrupts set/clear the corresponding bits. 95 */ 96 #define REG_RING_INTERRUPT_BASE 0x38200 97 #define RING_INTERRUPT_REG_COUNT(nhi) ((31 + 2 * nhi->hop_count) / 32) 98 99 /* Interrupt Vector Allocation */ 100 #define REG_INT_VEC_ALLOC_BASE 0x38c40 101 #define REG_INT_VEC_ALLOC_BITS 4 102 #define REG_INT_VEC_ALLOC_MASK GENMASK(3, 0) 103 #define REG_INT_VEC_ALLOC_REGS (32 / REG_INT_VEC_ALLOC_BITS) 104 105 /* The last 11 bits contain the number of hops supported by the NHI port. */ 106 #define REG_HOP_COUNT 0x39640 107 108 #define REG_DMA_MISC 0x39864 109 #define REG_DMA_MISC_INT_AUTO_CLEAR BIT(2) 110 111 #define REG_INMAIL_DATA 0x39900 112 113 #define REG_INMAIL_CMD 0x39904 114 #define REG_INMAIL_CMD_MASK GENMASK(7, 0) 115 #define REG_INMAIL_ERROR BIT(30) 116 #define REG_INMAIL_OP_REQUEST BIT(31) 117 118 #define REG_OUTMAIL_CMD 0x3990c 119 #define REG_OUTMAIL_CMD_OPMODE_SHIFT 8 120 #define REG_OUTMAIL_CMD_OPMODE_MASK GENMASK(11, 8) 121 122 #define REG_FW_STS 0x39944 123 #define REG_FW_STS_NVM_AUTH_DONE BIT(31) 124 #define REG_FW_STS_CIO_RESET_REQ BIT(30) 125 #define REG_FW_STS_ICM_EN_CPU BIT(2) 126 #define REG_FW_STS_ICM_EN_INVERT BIT(1) 127 #define REG_FW_STS_ICM_EN BIT(0) 128 129 #endif 130