1 /*
2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
30 */
31
32
33 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34 #define SUPPORT_SYSRQ
35 #endif
36
37 #include <linux/module.h>
38 #include <linux/ioport.h>
39 #include <linux/init.h>
40 #include <linux/console.h>
41 #include <linux/sysrq.h>
42 #include <linux/device.h>
43 #include <linux/tty.h>
44 #include <linux/tty_flip.h>
45 #include <linux/serial_core.h>
46 #include <linux/serial.h>
47 #include <linux/amba/bus.h>
48 #include <linux/amba/serial.h>
49 #include <linux/clk.h>
50 #include <linux/slab.h>
51 #include <linux/dmaengine.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/scatterlist.h>
54 #include <linux/delay.h>
55 #include <linux/types.h>
56 #include <linux/of.h>
57 #include <linux/of_device.h>
58 #include <linux/pinctrl/consumer.h>
59 #include <linux/sizes.h>
60 #include <linux/io.h>
61 #include <linux/acpi.h>
62
63 #include "amba-pl011.h"
64
65 #define UART_NR 14
66
67 #define SERIAL_AMBA_MAJOR 204
68 #define SERIAL_AMBA_MINOR 64
69 #define SERIAL_AMBA_NR UART_NR
70
71 #define AMBA_ISR_PASS_LIMIT 256
72
73 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
74 #define UART_DUMMY_DR_RX (1 << 16)
75
76 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
77 [REG_DR] = UART01x_DR,
78 [REG_FR] = UART01x_FR,
79 [REG_LCRH_RX] = UART011_LCRH,
80 [REG_LCRH_TX] = UART011_LCRH,
81 [REG_IBRD] = UART011_IBRD,
82 [REG_FBRD] = UART011_FBRD,
83 [REG_CR] = UART011_CR,
84 [REG_IFLS] = UART011_IFLS,
85 [REG_IMSC] = UART011_IMSC,
86 [REG_RIS] = UART011_RIS,
87 [REG_MIS] = UART011_MIS,
88 [REG_ICR] = UART011_ICR,
89 [REG_DMACR] = UART011_DMACR,
90 };
91
92 /* There is by now at least one vendor with differing details, so handle it */
93 struct vendor_data {
94 const u16 *reg_offset;
95 unsigned int ifls;
96 unsigned int fr_busy;
97 unsigned int fr_dsr;
98 unsigned int fr_cts;
99 unsigned int fr_ri;
100 unsigned int inv_fr;
101 bool access_32b;
102 bool oversampling;
103 bool dma_threshold;
104 bool cts_event_workaround;
105 bool always_enabled;
106 bool fixed_options;
107
108 unsigned int (*get_fifosize)(struct amba_device *dev);
109 };
110
get_fifosize_arm(struct amba_device * dev)111 static unsigned int get_fifosize_arm(struct amba_device *dev)
112 {
113 return amba_rev(dev) < 3 ? 16 : 32;
114 }
115
116 static struct vendor_data vendor_arm = {
117 .reg_offset = pl011_std_offsets,
118 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
119 .fr_busy = UART01x_FR_BUSY,
120 .fr_dsr = UART01x_FR_DSR,
121 .fr_cts = UART01x_FR_CTS,
122 .fr_ri = UART011_FR_RI,
123 .oversampling = false,
124 .dma_threshold = false,
125 .cts_event_workaround = false,
126 .always_enabled = false,
127 .fixed_options = false,
128 .get_fifosize = get_fifosize_arm,
129 };
130
131 static const struct vendor_data vendor_sbsa = {
132 .reg_offset = pl011_std_offsets,
133 .fr_busy = UART01x_FR_BUSY,
134 .fr_dsr = UART01x_FR_DSR,
135 .fr_cts = UART01x_FR_CTS,
136 .fr_ri = UART011_FR_RI,
137 .access_32b = true,
138 .oversampling = false,
139 .dma_threshold = false,
140 .cts_event_workaround = false,
141 .always_enabled = true,
142 .fixed_options = true,
143 };
144
145 #ifdef CONFIG_ACPI_SPCR_TABLE
146 static const struct vendor_data vendor_qdt_qdf2400_e44 = {
147 .reg_offset = pl011_std_offsets,
148 .fr_busy = UART011_FR_TXFE,
149 .fr_dsr = UART01x_FR_DSR,
150 .fr_cts = UART01x_FR_CTS,
151 .fr_ri = UART011_FR_RI,
152 .inv_fr = UART011_FR_TXFE,
153 .access_32b = true,
154 .oversampling = false,
155 .dma_threshold = false,
156 .cts_event_workaround = false,
157 .always_enabled = true,
158 .fixed_options = true,
159 };
160 #endif
161
162 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
163 [REG_DR] = UART01x_DR,
164 [REG_ST_DMAWM] = ST_UART011_DMAWM,
165 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
166 [REG_FR] = UART01x_FR,
167 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
168 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
169 [REG_IBRD] = UART011_IBRD,
170 [REG_FBRD] = UART011_FBRD,
171 [REG_CR] = UART011_CR,
172 [REG_IFLS] = UART011_IFLS,
173 [REG_IMSC] = UART011_IMSC,
174 [REG_RIS] = UART011_RIS,
175 [REG_MIS] = UART011_MIS,
176 [REG_ICR] = UART011_ICR,
177 [REG_DMACR] = UART011_DMACR,
178 [REG_ST_XFCR] = ST_UART011_XFCR,
179 [REG_ST_XON1] = ST_UART011_XON1,
180 [REG_ST_XON2] = ST_UART011_XON2,
181 [REG_ST_XOFF1] = ST_UART011_XOFF1,
182 [REG_ST_XOFF2] = ST_UART011_XOFF2,
183 [REG_ST_ITCR] = ST_UART011_ITCR,
184 [REG_ST_ITIP] = ST_UART011_ITIP,
185 [REG_ST_ABCR] = ST_UART011_ABCR,
186 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
187 };
188
get_fifosize_st(struct amba_device * dev)189 static unsigned int get_fifosize_st(struct amba_device *dev)
190 {
191 return 64;
192 }
193
194 static struct vendor_data vendor_st = {
195 .reg_offset = pl011_st_offsets,
196 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
197 .fr_busy = UART01x_FR_BUSY,
198 .fr_dsr = UART01x_FR_DSR,
199 .fr_cts = UART01x_FR_CTS,
200 .fr_ri = UART011_FR_RI,
201 .oversampling = true,
202 .dma_threshold = true,
203 .cts_event_workaround = true,
204 .always_enabled = false,
205 .fixed_options = false,
206 .get_fifosize = get_fifosize_st,
207 };
208
209 static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = {
210 [REG_DR] = ZX_UART011_DR,
211 [REG_FR] = ZX_UART011_FR,
212 [REG_LCRH_RX] = ZX_UART011_LCRH,
213 [REG_LCRH_TX] = ZX_UART011_LCRH,
214 [REG_IBRD] = ZX_UART011_IBRD,
215 [REG_FBRD] = ZX_UART011_FBRD,
216 [REG_CR] = ZX_UART011_CR,
217 [REG_IFLS] = ZX_UART011_IFLS,
218 [REG_IMSC] = ZX_UART011_IMSC,
219 [REG_RIS] = ZX_UART011_RIS,
220 [REG_MIS] = ZX_UART011_MIS,
221 [REG_ICR] = ZX_UART011_ICR,
222 [REG_DMACR] = ZX_UART011_DMACR,
223 };
224
get_fifosize_zte(struct amba_device * dev)225 static unsigned int get_fifosize_zte(struct amba_device *dev)
226 {
227 return 16;
228 }
229
230 static struct vendor_data vendor_zte = {
231 .reg_offset = pl011_zte_offsets,
232 .access_32b = true,
233 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
234 .fr_busy = ZX_UART01x_FR_BUSY,
235 .fr_dsr = ZX_UART01x_FR_DSR,
236 .fr_cts = ZX_UART01x_FR_CTS,
237 .fr_ri = ZX_UART011_FR_RI,
238 .get_fifosize = get_fifosize_zte,
239 };
240
241 /* Deals with DMA transactions */
242
243 struct pl011_sgbuf {
244 struct scatterlist sg;
245 char *buf;
246 };
247
248 struct pl011_dmarx_data {
249 struct dma_chan *chan;
250 struct completion complete;
251 bool use_buf_b;
252 struct pl011_sgbuf sgbuf_a;
253 struct pl011_sgbuf sgbuf_b;
254 dma_cookie_t cookie;
255 bool running;
256 struct timer_list timer;
257 unsigned int last_residue;
258 unsigned long last_jiffies;
259 bool auto_poll_rate;
260 unsigned int poll_rate;
261 unsigned int poll_timeout;
262 };
263
264 struct pl011_dmatx_data {
265 struct dma_chan *chan;
266 struct scatterlist sg;
267 char *buf;
268 bool queued;
269 };
270
271 /*
272 * We wrap our port structure around the generic uart_port.
273 */
274 struct uart_amba_port {
275 struct uart_port port;
276 const u16 *reg_offset;
277 struct clk *clk;
278 const struct vendor_data *vendor;
279 unsigned int dmacr; /* dma control reg */
280 unsigned int im; /* interrupt mask */
281 unsigned int old_status;
282 unsigned int fifosize; /* vendor-specific */
283 unsigned int old_cr; /* state during shutdown */
284 bool autorts;
285 unsigned int fixed_baud; /* vendor-set fixed baud rate */
286 char type[12];
287 #ifdef CONFIG_DMA_ENGINE
288 /* DMA stuff */
289 bool using_tx_dma;
290 bool using_rx_dma;
291 struct pl011_dmarx_data dmarx;
292 struct pl011_dmatx_data dmatx;
293 bool dma_probed;
294 #endif
295 };
296
pl011_reg_to_offset(const struct uart_amba_port * uap,unsigned int reg)297 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
298 unsigned int reg)
299 {
300 return uap->reg_offset[reg];
301 }
302
pl011_read(const struct uart_amba_port * uap,unsigned int reg)303 static unsigned int pl011_read(const struct uart_amba_port *uap,
304 unsigned int reg)
305 {
306 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
307
308 return (uap->port.iotype == UPIO_MEM32) ?
309 readl_relaxed(addr) : readw_relaxed(addr);
310 }
311
pl011_write(unsigned int val,const struct uart_amba_port * uap,unsigned int reg)312 static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
313 unsigned int reg)
314 {
315 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
316
317 if (uap->port.iotype == UPIO_MEM32)
318 writel_relaxed(val, addr);
319 else
320 writew_relaxed(val, addr);
321 }
322
323 /*
324 * Reads up to 256 characters from the FIFO or until it's empty and
325 * inserts them into the TTY layer. Returns the number of characters
326 * read from the FIFO.
327 */
pl011_fifo_to_tty(struct uart_amba_port * uap)328 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
329 {
330 u16 status;
331 unsigned int ch, flag, max_count = 256;
332 int fifotaken = 0;
333
334 while (max_count--) {
335 status = pl011_read(uap, REG_FR);
336 if (status & UART01x_FR_RXFE)
337 break;
338
339 /* Take chars from the FIFO and update status */
340 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
341 flag = TTY_NORMAL;
342 uap->port.icount.rx++;
343 fifotaken++;
344
345 if (unlikely(ch & UART_DR_ERROR)) {
346 if (ch & UART011_DR_BE) {
347 ch &= ~(UART011_DR_FE | UART011_DR_PE);
348 uap->port.icount.brk++;
349 if (uart_handle_break(&uap->port))
350 continue;
351 } else if (ch & UART011_DR_PE)
352 uap->port.icount.parity++;
353 else if (ch & UART011_DR_FE)
354 uap->port.icount.frame++;
355 if (ch & UART011_DR_OE)
356 uap->port.icount.overrun++;
357
358 ch &= uap->port.read_status_mask;
359
360 if (ch & UART011_DR_BE)
361 flag = TTY_BREAK;
362 else if (ch & UART011_DR_PE)
363 flag = TTY_PARITY;
364 else if (ch & UART011_DR_FE)
365 flag = TTY_FRAME;
366 }
367
368 if (uart_handle_sysrq_char(&uap->port, ch & 255))
369 continue;
370
371 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
372 }
373
374 return fifotaken;
375 }
376
377
378 /*
379 * All the DMA operation mode stuff goes inside this ifdef.
380 * This assumes that you have a generic DMA device interface,
381 * no custom DMA interfaces are supported.
382 */
383 #ifdef CONFIG_DMA_ENGINE
384
385 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
386
pl011_sgbuf_init(struct dma_chan * chan,struct pl011_sgbuf * sg,enum dma_data_direction dir)387 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
388 enum dma_data_direction dir)
389 {
390 dma_addr_t dma_addr;
391
392 sg->buf = dma_alloc_coherent(chan->device->dev,
393 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
394 if (!sg->buf)
395 return -ENOMEM;
396
397 sg_init_table(&sg->sg, 1);
398 sg_set_page(&sg->sg, phys_to_page(dma_addr),
399 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
400 sg_dma_address(&sg->sg) = dma_addr;
401 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
402
403 return 0;
404 }
405
pl011_sgbuf_free(struct dma_chan * chan,struct pl011_sgbuf * sg,enum dma_data_direction dir)406 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
407 enum dma_data_direction dir)
408 {
409 if (sg->buf) {
410 dma_free_coherent(chan->device->dev,
411 PL011_DMA_BUFFER_SIZE, sg->buf,
412 sg_dma_address(&sg->sg));
413 }
414 }
415
pl011_dma_probe(struct uart_amba_port * uap)416 static void pl011_dma_probe(struct uart_amba_port *uap)
417 {
418 /* DMA is the sole user of the platform data right now */
419 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
420 struct device *dev = uap->port.dev;
421 struct dma_slave_config tx_conf = {
422 .dst_addr = uap->port.mapbase +
423 pl011_reg_to_offset(uap, REG_DR),
424 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
425 .direction = DMA_MEM_TO_DEV,
426 .dst_maxburst = uap->fifosize >> 1,
427 .device_fc = false,
428 };
429 struct dma_chan *chan;
430 dma_cap_mask_t mask;
431
432 uap->dma_probed = true;
433 chan = dma_request_slave_channel_reason(dev, "tx");
434 if (IS_ERR(chan)) {
435 if (PTR_ERR(chan) == -EPROBE_DEFER) {
436 uap->dma_probed = false;
437 return;
438 }
439
440 /* We need platform data */
441 if (!plat || !plat->dma_filter) {
442 dev_info(uap->port.dev, "no DMA platform data\n");
443 return;
444 }
445
446 /* Try to acquire a generic DMA engine slave TX channel */
447 dma_cap_zero(mask);
448 dma_cap_set(DMA_SLAVE, mask);
449
450 chan = dma_request_channel(mask, plat->dma_filter,
451 plat->dma_tx_param);
452 if (!chan) {
453 dev_err(uap->port.dev, "no TX DMA channel!\n");
454 return;
455 }
456 }
457
458 dmaengine_slave_config(chan, &tx_conf);
459 uap->dmatx.chan = chan;
460
461 dev_info(uap->port.dev, "DMA channel TX %s\n",
462 dma_chan_name(uap->dmatx.chan));
463
464 /* Optionally make use of an RX channel as well */
465 chan = dma_request_slave_channel(dev, "rx");
466
467 if (!chan && plat && plat->dma_rx_param) {
468 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
469
470 if (!chan) {
471 dev_err(uap->port.dev, "no RX DMA channel!\n");
472 return;
473 }
474 }
475
476 if (chan) {
477 struct dma_slave_config rx_conf = {
478 .src_addr = uap->port.mapbase +
479 pl011_reg_to_offset(uap, REG_DR),
480 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
481 .direction = DMA_DEV_TO_MEM,
482 .src_maxburst = uap->fifosize >> 2,
483 .device_fc = false,
484 };
485 struct dma_slave_caps caps;
486
487 /*
488 * Some DMA controllers provide information on their capabilities.
489 * If the controller does, check for suitable residue processing
490 * otherwise assime all is well.
491 */
492 if (0 == dma_get_slave_caps(chan, &caps)) {
493 if (caps.residue_granularity ==
494 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
495 dma_release_channel(chan);
496 dev_info(uap->port.dev,
497 "RX DMA disabled - no residue processing\n");
498 return;
499 }
500 }
501 dmaengine_slave_config(chan, &rx_conf);
502 uap->dmarx.chan = chan;
503
504 uap->dmarx.auto_poll_rate = false;
505 if (plat && plat->dma_rx_poll_enable) {
506 /* Set poll rate if specified. */
507 if (plat->dma_rx_poll_rate) {
508 uap->dmarx.auto_poll_rate = false;
509 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
510 } else {
511 /*
512 * 100 ms defaults to poll rate if not
513 * specified. This will be adjusted with
514 * the baud rate at set_termios.
515 */
516 uap->dmarx.auto_poll_rate = true;
517 uap->dmarx.poll_rate = 100;
518 }
519 /* 3 secs defaults poll_timeout if not specified. */
520 if (plat->dma_rx_poll_timeout)
521 uap->dmarx.poll_timeout =
522 plat->dma_rx_poll_timeout;
523 else
524 uap->dmarx.poll_timeout = 3000;
525 } else if (!plat && dev->of_node) {
526 uap->dmarx.auto_poll_rate = of_property_read_bool(
527 dev->of_node, "auto-poll");
528 if (uap->dmarx.auto_poll_rate) {
529 u32 x;
530
531 if (0 == of_property_read_u32(dev->of_node,
532 "poll-rate-ms", &x))
533 uap->dmarx.poll_rate = x;
534 else
535 uap->dmarx.poll_rate = 100;
536 if (0 == of_property_read_u32(dev->of_node,
537 "poll-timeout-ms", &x))
538 uap->dmarx.poll_timeout = x;
539 else
540 uap->dmarx.poll_timeout = 3000;
541 }
542 }
543 dev_info(uap->port.dev, "DMA channel RX %s\n",
544 dma_chan_name(uap->dmarx.chan));
545 }
546 }
547
pl011_dma_remove(struct uart_amba_port * uap)548 static void pl011_dma_remove(struct uart_amba_port *uap)
549 {
550 if (uap->dmatx.chan)
551 dma_release_channel(uap->dmatx.chan);
552 if (uap->dmarx.chan)
553 dma_release_channel(uap->dmarx.chan);
554 }
555
556 /* Forward declare these for the refill routine */
557 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
558 static void pl011_start_tx_pio(struct uart_amba_port *uap);
559
560 /*
561 * The current DMA TX buffer has been sent.
562 * Try to queue up another DMA buffer.
563 */
pl011_dma_tx_callback(void * data)564 static void pl011_dma_tx_callback(void *data)
565 {
566 struct uart_amba_port *uap = data;
567 struct pl011_dmatx_data *dmatx = &uap->dmatx;
568 unsigned long flags;
569 u16 dmacr;
570
571 spin_lock_irqsave(&uap->port.lock, flags);
572 if (uap->dmatx.queued)
573 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
574 DMA_TO_DEVICE);
575
576 dmacr = uap->dmacr;
577 uap->dmacr = dmacr & ~UART011_TXDMAE;
578 pl011_write(uap->dmacr, uap, REG_DMACR);
579
580 /*
581 * If TX DMA was disabled, it means that we've stopped the DMA for
582 * some reason (eg, XOFF received, or we want to send an X-char.)
583 *
584 * Note: we need to be careful here of a potential race between DMA
585 * and the rest of the driver - if the driver disables TX DMA while
586 * a TX buffer completing, we must update the tx queued status to
587 * get further refills (hence we check dmacr).
588 */
589 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
590 uart_circ_empty(&uap->port.state->xmit)) {
591 uap->dmatx.queued = false;
592 spin_unlock_irqrestore(&uap->port.lock, flags);
593 return;
594 }
595
596 if (pl011_dma_tx_refill(uap) <= 0)
597 /*
598 * We didn't queue a DMA buffer for some reason, but we
599 * have data pending to be sent. Re-enable the TX IRQ.
600 */
601 pl011_start_tx_pio(uap);
602
603 spin_unlock_irqrestore(&uap->port.lock, flags);
604 }
605
606 /*
607 * Try to refill the TX DMA buffer.
608 * Locking: called with port lock held and IRQs disabled.
609 * Returns:
610 * 1 if we queued up a TX DMA buffer.
611 * 0 if we didn't want to handle this by DMA
612 * <0 on error
613 */
pl011_dma_tx_refill(struct uart_amba_port * uap)614 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
615 {
616 struct pl011_dmatx_data *dmatx = &uap->dmatx;
617 struct dma_chan *chan = dmatx->chan;
618 struct dma_device *dma_dev = chan->device;
619 struct dma_async_tx_descriptor *desc;
620 struct circ_buf *xmit = &uap->port.state->xmit;
621 unsigned int count;
622
623 /*
624 * Try to avoid the overhead involved in using DMA if the
625 * transaction fits in the first half of the FIFO, by using
626 * the standard interrupt handling. This ensures that we
627 * issue a uart_write_wakeup() at the appropriate time.
628 */
629 count = uart_circ_chars_pending(xmit);
630 if (count < (uap->fifosize >> 1)) {
631 uap->dmatx.queued = false;
632 return 0;
633 }
634
635 /*
636 * Bodge: don't send the last character by DMA, as this
637 * will prevent XON from notifying us to restart DMA.
638 */
639 count -= 1;
640
641 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
642 if (count > PL011_DMA_BUFFER_SIZE)
643 count = PL011_DMA_BUFFER_SIZE;
644
645 if (xmit->tail < xmit->head)
646 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
647 else {
648 size_t first = UART_XMIT_SIZE - xmit->tail;
649 size_t second;
650
651 if (first > count)
652 first = count;
653 second = count - first;
654
655 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
656 if (second)
657 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
658 }
659
660 dmatx->sg.length = count;
661
662 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
663 uap->dmatx.queued = false;
664 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
665 return -EBUSY;
666 }
667
668 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
669 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
670 if (!desc) {
671 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
672 uap->dmatx.queued = false;
673 /*
674 * If DMA cannot be used right now, we complete this
675 * transaction via IRQ and let the TTY layer retry.
676 */
677 dev_dbg(uap->port.dev, "TX DMA busy\n");
678 return -EBUSY;
679 }
680
681 /* Some data to go along to the callback */
682 desc->callback = pl011_dma_tx_callback;
683 desc->callback_param = uap;
684
685 /* All errors should happen at prepare time */
686 dmaengine_submit(desc);
687
688 /* Fire the DMA transaction */
689 dma_dev->device_issue_pending(chan);
690
691 uap->dmacr |= UART011_TXDMAE;
692 pl011_write(uap->dmacr, uap, REG_DMACR);
693 uap->dmatx.queued = true;
694
695 /*
696 * Now we know that DMA will fire, so advance the ring buffer
697 * with the stuff we just dispatched.
698 */
699 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
700 uap->port.icount.tx += count;
701
702 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
703 uart_write_wakeup(&uap->port);
704
705 return 1;
706 }
707
708 /*
709 * We received a transmit interrupt without a pending X-char but with
710 * pending characters.
711 * Locking: called with port lock held and IRQs disabled.
712 * Returns:
713 * false if we want to use PIO to transmit
714 * true if we queued a DMA buffer
715 */
pl011_dma_tx_irq(struct uart_amba_port * uap)716 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
717 {
718 if (!uap->using_tx_dma)
719 return false;
720
721 /*
722 * If we already have a TX buffer queued, but received a
723 * TX interrupt, it will be because we've just sent an X-char.
724 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
725 */
726 if (uap->dmatx.queued) {
727 uap->dmacr |= UART011_TXDMAE;
728 pl011_write(uap->dmacr, uap, REG_DMACR);
729 uap->im &= ~UART011_TXIM;
730 pl011_write(uap->im, uap, REG_IMSC);
731 return true;
732 }
733
734 /*
735 * We don't have a TX buffer queued, so try to queue one.
736 * If we successfully queued a buffer, mask the TX IRQ.
737 */
738 if (pl011_dma_tx_refill(uap) > 0) {
739 uap->im &= ~UART011_TXIM;
740 pl011_write(uap->im, uap, REG_IMSC);
741 return true;
742 }
743 return false;
744 }
745
746 /*
747 * Stop the DMA transmit (eg, due to received XOFF).
748 * Locking: called with port lock held and IRQs disabled.
749 */
pl011_dma_tx_stop(struct uart_amba_port * uap)750 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
751 {
752 if (uap->dmatx.queued) {
753 uap->dmacr &= ~UART011_TXDMAE;
754 pl011_write(uap->dmacr, uap, REG_DMACR);
755 }
756 }
757
758 /*
759 * Try to start a DMA transmit, or in the case of an XON/OFF
760 * character queued for send, try to get that character out ASAP.
761 * Locking: called with port lock held and IRQs disabled.
762 * Returns:
763 * false if we want the TX IRQ to be enabled
764 * true if we have a buffer queued
765 */
pl011_dma_tx_start(struct uart_amba_port * uap)766 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
767 {
768 u16 dmacr;
769
770 if (!uap->using_tx_dma)
771 return false;
772
773 if (!uap->port.x_char) {
774 /* no X-char, try to push chars out in DMA mode */
775 bool ret = true;
776
777 if (!uap->dmatx.queued) {
778 if (pl011_dma_tx_refill(uap) > 0) {
779 uap->im &= ~UART011_TXIM;
780 pl011_write(uap->im, uap, REG_IMSC);
781 } else
782 ret = false;
783 } else if (!(uap->dmacr & UART011_TXDMAE)) {
784 uap->dmacr |= UART011_TXDMAE;
785 pl011_write(uap->dmacr, uap, REG_DMACR);
786 }
787 return ret;
788 }
789
790 /*
791 * We have an X-char to send. Disable DMA to prevent it loading
792 * the TX fifo, and then see if we can stuff it into the FIFO.
793 */
794 dmacr = uap->dmacr;
795 uap->dmacr &= ~UART011_TXDMAE;
796 pl011_write(uap->dmacr, uap, REG_DMACR);
797
798 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
799 /*
800 * No space in the FIFO, so enable the transmit interrupt
801 * so we know when there is space. Note that once we've
802 * loaded the character, we should just re-enable DMA.
803 */
804 return false;
805 }
806
807 pl011_write(uap->port.x_char, uap, REG_DR);
808 uap->port.icount.tx++;
809 uap->port.x_char = 0;
810
811 /* Success - restore the DMA state */
812 uap->dmacr = dmacr;
813 pl011_write(dmacr, uap, REG_DMACR);
814
815 return true;
816 }
817
818 /*
819 * Flush the transmit buffer.
820 * Locking: called with port lock held and IRQs disabled.
821 */
pl011_dma_flush_buffer(struct uart_port * port)822 static void pl011_dma_flush_buffer(struct uart_port *port)
823 __releases(&uap->port.lock)
824 __acquires(&uap->port.lock)
825 {
826 struct uart_amba_port *uap =
827 container_of(port, struct uart_amba_port, port);
828
829 if (!uap->using_tx_dma)
830 return;
831
832 dmaengine_terminate_async(uap->dmatx.chan);
833
834 if (uap->dmatx.queued) {
835 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
836 DMA_TO_DEVICE);
837 uap->dmatx.queued = false;
838 uap->dmacr &= ~UART011_TXDMAE;
839 pl011_write(uap->dmacr, uap, REG_DMACR);
840 }
841 }
842
843 static void pl011_dma_rx_callback(void *data);
844
pl011_dma_rx_trigger_dma(struct uart_amba_port * uap)845 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
846 {
847 struct dma_chan *rxchan = uap->dmarx.chan;
848 struct pl011_dmarx_data *dmarx = &uap->dmarx;
849 struct dma_async_tx_descriptor *desc;
850 struct pl011_sgbuf *sgbuf;
851
852 if (!rxchan)
853 return -EIO;
854
855 /* Start the RX DMA job */
856 sgbuf = uap->dmarx.use_buf_b ?
857 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
858 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
859 DMA_DEV_TO_MEM,
860 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
861 /*
862 * If the DMA engine is busy and cannot prepare a
863 * channel, no big deal, the driver will fall back
864 * to interrupt mode as a result of this error code.
865 */
866 if (!desc) {
867 uap->dmarx.running = false;
868 dmaengine_terminate_all(rxchan);
869 return -EBUSY;
870 }
871
872 /* Some data to go along to the callback */
873 desc->callback = pl011_dma_rx_callback;
874 desc->callback_param = uap;
875 dmarx->cookie = dmaengine_submit(desc);
876 dma_async_issue_pending(rxchan);
877
878 uap->dmacr |= UART011_RXDMAE;
879 pl011_write(uap->dmacr, uap, REG_DMACR);
880 uap->dmarx.running = true;
881
882 uap->im &= ~UART011_RXIM;
883 pl011_write(uap->im, uap, REG_IMSC);
884
885 return 0;
886 }
887
888 /*
889 * This is called when either the DMA job is complete, or
890 * the FIFO timeout interrupt occurred. This must be called
891 * with the port spinlock uap->port.lock held.
892 */
pl011_dma_rx_chars(struct uart_amba_port * uap,u32 pending,bool use_buf_b,bool readfifo)893 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
894 u32 pending, bool use_buf_b,
895 bool readfifo)
896 {
897 struct tty_port *port = &uap->port.state->port;
898 struct pl011_sgbuf *sgbuf = use_buf_b ?
899 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
900 int dma_count = 0;
901 u32 fifotaken = 0; /* only used for vdbg() */
902
903 struct pl011_dmarx_data *dmarx = &uap->dmarx;
904 int dmataken = 0;
905
906 if (uap->dmarx.poll_rate) {
907 /* The data can be taken by polling */
908 dmataken = sgbuf->sg.length - dmarx->last_residue;
909 /* Recalculate the pending size */
910 if (pending >= dmataken)
911 pending -= dmataken;
912 }
913
914 /* Pick the remain data from the DMA */
915 if (pending) {
916
917 /*
918 * First take all chars in the DMA pipe, then look in the FIFO.
919 * Note that tty_insert_flip_buf() tries to take as many chars
920 * as it can.
921 */
922 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
923 pending);
924
925 uap->port.icount.rx += dma_count;
926 if (dma_count < pending)
927 dev_warn(uap->port.dev,
928 "couldn't insert all characters (TTY is full?)\n");
929 }
930
931 /* Reset the last_residue for Rx DMA poll */
932 if (uap->dmarx.poll_rate)
933 dmarx->last_residue = sgbuf->sg.length;
934
935 /*
936 * Only continue with trying to read the FIFO if all DMA chars have
937 * been taken first.
938 */
939 if (dma_count == pending && readfifo) {
940 /* Clear any error flags */
941 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
942 UART011_FEIS, uap, REG_ICR);
943
944 /*
945 * If we read all the DMA'd characters, and we had an
946 * incomplete buffer, that could be due to an rx error, or
947 * maybe we just timed out. Read any pending chars and check
948 * the error status.
949 *
950 * Error conditions will only occur in the FIFO, these will
951 * trigger an immediate interrupt and stop the DMA job, so we
952 * will always find the error in the FIFO, never in the DMA
953 * buffer.
954 */
955 fifotaken = pl011_fifo_to_tty(uap);
956 }
957
958 spin_unlock(&uap->port.lock);
959 dev_vdbg(uap->port.dev,
960 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
961 dma_count, fifotaken);
962 tty_flip_buffer_push(port);
963 spin_lock(&uap->port.lock);
964 }
965
pl011_dma_rx_irq(struct uart_amba_port * uap)966 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
967 {
968 struct pl011_dmarx_data *dmarx = &uap->dmarx;
969 struct dma_chan *rxchan = dmarx->chan;
970 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
971 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
972 size_t pending;
973 struct dma_tx_state state;
974 enum dma_status dmastat;
975
976 /*
977 * Pause the transfer so we can trust the current counter,
978 * do this before we pause the PL011 block, else we may
979 * overflow the FIFO.
980 */
981 if (dmaengine_pause(rxchan))
982 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
983 dmastat = rxchan->device->device_tx_status(rxchan,
984 dmarx->cookie, &state);
985 if (dmastat != DMA_PAUSED)
986 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
987
988 /* Disable RX DMA - incoming data will wait in the FIFO */
989 uap->dmacr &= ~UART011_RXDMAE;
990 pl011_write(uap->dmacr, uap, REG_DMACR);
991 uap->dmarx.running = false;
992
993 pending = sgbuf->sg.length - state.residue;
994 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
995 /* Then we terminate the transfer - we now know our residue */
996 dmaengine_terminate_all(rxchan);
997
998 /*
999 * This will take the chars we have so far and insert
1000 * into the framework.
1001 */
1002 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
1003
1004 /* Switch buffer & re-trigger DMA job */
1005 dmarx->use_buf_b = !dmarx->use_buf_b;
1006 if (pl011_dma_rx_trigger_dma(uap)) {
1007 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1008 "fall back to interrupt mode\n");
1009 uap->im |= UART011_RXIM;
1010 pl011_write(uap->im, uap, REG_IMSC);
1011 }
1012 }
1013
pl011_dma_rx_callback(void * data)1014 static void pl011_dma_rx_callback(void *data)
1015 {
1016 struct uart_amba_port *uap = data;
1017 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1018 struct dma_chan *rxchan = dmarx->chan;
1019 bool lastbuf = dmarx->use_buf_b;
1020 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
1021 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
1022 size_t pending;
1023 struct dma_tx_state state;
1024 int ret;
1025
1026 /*
1027 * This completion interrupt occurs typically when the
1028 * RX buffer is totally stuffed but no timeout has yet
1029 * occurred. When that happens, we just want the RX
1030 * routine to flush out the secondary DMA buffer while
1031 * we immediately trigger the next DMA job.
1032 */
1033 spin_lock_irq(&uap->port.lock);
1034 /*
1035 * Rx data can be taken by the UART interrupts during
1036 * the DMA irq handler. So we check the residue here.
1037 */
1038 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1039 pending = sgbuf->sg.length - state.residue;
1040 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1041 /* Then we terminate the transfer - we now know our residue */
1042 dmaengine_terminate_all(rxchan);
1043
1044 uap->dmarx.running = false;
1045 dmarx->use_buf_b = !lastbuf;
1046 ret = pl011_dma_rx_trigger_dma(uap);
1047
1048 pl011_dma_rx_chars(uap, pending, lastbuf, false);
1049 spin_unlock_irq(&uap->port.lock);
1050 /*
1051 * Do this check after we picked the DMA chars so we don't
1052 * get some IRQ immediately from RX.
1053 */
1054 if (ret) {
1055 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1056 "fall back to interrupt mode\n");
1057 uap->im |= UART011_RXIM;
1058 pl011_write(uap->im, uap, REG_IMSC);
1059 }
1060 }
1061
1062 /*
1063 * Stop accepting received characters, when we're shutting down or
1064 * suspending this port.
1065 * Locking: called with port lock held and IRQs disabled.
1066 */
pl011_dma_rx_stop(struct uart_amba_port * uap)1067 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1068 {
1069 /* FIXME. Just disable the DMA enable */
1070 uap->dmacr &= ~UART011_RXDMAE;
1071 pl011_write(uap->dmacr, uap, REG_DMACR);
1072 }
1073
1074 /*
1075 * Timer handler for Rx DMA polling.
1076 * Every polling, It checks the residue in the dma buffer and transfer
1077 * data to the tty. Also, last_residue is updated for the next polling.
1078 */
pl011_dma_rx_poll(unsigned long args)1079 static void pl011_dma_rx_poll(unsigned long args)
1080 {
1081 struct uart_amba_port *uap = (struct uart_amba_port *)args;
1082 struct tty_port *port = &uap->port.state->port;
1083 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1084 struct dma_chan *rxchan = uap->dmarx.chan;
1085 unsigned long flags = 0;
1086 unsigned int dmataken = 0;
1087 unsigned int size = 0;
1088 struct pl011_sgbuf *sgbuf;
1089 int dma_count;
1090 struct dma_tx_state state;
1091
1092 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
1093 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1094 if (likely(state.residue < dmarx->last_residue)) {
1095 dmataken = sgbuf->sg.length - dmarx->last_residue;
1096 size = dmarx->last_residue - state.residue;
1097 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
1098 size);
1099 if (dma_count == size)
1100 dmarx->last_residue = state.residue;
1101 dmarx->last_jiffies = jiffies;
1102 }
1103 tty_flip_buffer_push(port);
1104
1105 /*
1106 * If no data is received in poll_timeout, the driver will fall back
1107 * to interrupt mode. We will retrigger DMA at the first interrupt.
1108 */
1109 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1110 > uap->dmarx.poll_timeout) {
1111
1112 spin_lock_irqsave(&uap->port.lock, flags);
1113 pl011_dma_rx_stop(uap);
1114 uap->im |= UART011_RXIM;
1115 pl011_write(uap->im, uap, REG_IMSC);
1116 spin_unlock_irqrestore(&uap->port.lock, flags);
1117
1118 uap->dmarx.running = false;
1119 dmaengine_terminate_all(rxchan);
1120 del_timer(&uap->dmarx.timer);
1121 } else {
1122 mod_timer(&uap->dmarx.timer,
1123 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1124 }
1125 }
1126
pl011_dma_startup(struct uart_amba_port * uap)1127 static void pl011_dma_startup(struct uart_amba_port *uap)
1128 {
1129 int ret;
1130
1131 if (!uap->dma_probed)
1132 pl011_dma_probe(uap);
1133
1134 if (!uap->dmatx.chan)
1135 return;
1136
1137 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1138 if (!uap->dmatx.buf) {
1139 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1140 uap->port.fifosize = uap->fifosize;
1141 return;
1142 }
1143
1144 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
1145
1146 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1147 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1148 uap->using_tx_dma = true;
1149
1150 if (!uap->dmarx.chan)
1151 goto skip_rx;
1152
1153 /* Allocate and map DMA RX buffers */
1154 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1155 DMA_FROM_DEVICE);
1156 if (ret) {
1157 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1158 "RX buffer A", ret);
1159 goto skip_rx;
1160 }
1161
1162 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1163 DMA_FROM_DEVICE);
1164 if (ret) {
1165 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1166 "RX buffer B", ret);
1167 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1168 DMA_FROM_DEVICE);
1169 goto skip_rx;
1170 }
1171
1172 uap->using_rx_dma = true;
1173
1174 skip_rx:
1175 /* Turn on DMA error (RX/TX will be enabled on demand) */
1176 uap->dmacr |= UART011_DMAONERR;
1177 pl011_write(uap->dmacr, uap, REG_DMACR);
1178
1179 /*
1180 * ST Micro variants has some specific dma burst threshold
1181 * compensation. Set this to 16 bytes, so burst will only
1182 * be issued above/below 16 bytes.
1183 */
1184 if (uap->vendor->dma_threshold)
1185 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1186 uap, REG_ST_DMAWM);
1187
1188 if (uap->using_rx_dma) {
1189 if (pl011_dma_rx_trigger_dma(uap))
1190 dev_dbg(uap->port.dev, "could not trigger initial "
1191 "RX DMA job, fall back to interrupt mode\n");
1192 if (uap->dmarx.poll_rate) {
1193 init_timer(&(uap->dmarx.timer));
1194 uap->dmarx.timer.function = pl011_dma_rx_poll;
1195 uap->dmarx.timer.data = (unsigned long)uap;
1196 mod_timer(&uap->dmarx.timer,
1197 jiffies +
1198 msecs_to_jiffies(uap->dmarx.poll_rate));
1199 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1200 uap->dmarx.last_jiffies = jiffies;
1201 }
1202 }
1203 }
1204
pl011_dma_shutdown(struct uart_amba_port * uap)1205 static void pl011_dma_shutdown(struct uart_amba_port *uap)
1206 {
1207 if (!(uap->using_tx_dma || uap->using_rx_dma))
1208 return;
1209
1210 /* Disable RX and TX DMA */
1211 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
1212 cpu_relax();
1213
1214 spin_lock_irq(&uap->port.lock);
1215 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1216 pl011_write(uap->dmacr, uap, REG_DMACR);
1217 spin_unlock_irq(&uap->port.lock);
1218
1219 if (uap->using_tx_dma) {
1220 /* In theory, this should already be done by pl011_dma_flush_buffer */
1221 dmaengine_terminate_all(uap->dmatx.chan);
1222 if (uap->dmatx.queued) {
1223 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1224 DMA_TO_DEVICE);
1225 uap->dmatx.queued = false;
1226 }
1227
1228 kfree(uap->dmatx.buf);
1229 uap->using_tx_dma = false;
1230 }
1231
1232 if (uap->using_rx_dma) {
1233 dmaengine_terminate_all(uap->dmarx.chan);
1234 /* Clean up the RX DMA */
1235 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1236 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
1237 if (uap->dmarx.poll_rate)
1238 del_timer_sync(&uap->dmarx.timer);
1239 uap->using_rx_dma = false;
1240 }
1241 }
1242
pl011_dma_rx_available(struct uart_amba_port * uap)1243 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1244 {
1245 return uap->using_rx_dma;
1246 }
1247
pl011_dma_rx_running(struct uart_amba_port * uap)1248 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1249 {
1250 return uap->using_rx_dma && uap->dmarx.running;
1251 }
1252
1253 #else
1254 /* Blank functions if the DMA engine is not available */
pl011_dma_probe(struct uart_amba_port * uap)1255 static inline void pl011_dma_probe(struct uart_amba_port *uap)
1256 {
1257 }
1258
pl011_dma_remove(struct uart_amba_port * uap)1259 static inline void pl011_dma_remove(struct uart_amba_port *uap)
1260 {
1261 }
1262
pl011_dma_startup(struct uart_amba_port * uap)1263 static inline void pl011_dma_startup(struct uart_amba_port *uap)
1264 {
1265 }
1266
pl011_dma_shutdown(struct uart_amba_port * uap)1267 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1268 {
1269 }
1270
pl011_dma_tx_irq(struct uart_amba_port * uap)1271 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1272 {
1273 return false;
1274 }
1275
pl011_dma_tx_stop(struct uart_amba_port * uap)1276 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1277 {
1278 }
1279
pl011_dma_tx_start(struct uart_amba_port * uap)1280 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1281 {
1282 return false;
1283 }
1284
pl011_dma_rx_irq(struct uart_amba_port * uap)1285 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1286 {
1287 }
1288
pl011_dma_rx_stop(struct uart_amba_port * uap)1289 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1290 {
1291 }
1292
pl011_dma_rx_trigger_dma(struct uart_amba_port * uap)1293 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1294 {
1295 return -EIO;
1296 }
1297
pl011_dma_rx_available(struct uart_amba_port * uap)1298 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1299 {
1300 return false;
1301 }
1302
pl011_dma_rx_running(struct uart_amba_port * uap)1303 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1304 {
1305 return false;
1306 }
1307
1308 #define pl011_dma_flush_buffer NULL
1309 #endif
1310
pl011_stop_tx(struct uart_port * port)1311 static void pl011_stop_tx(struct uart_port *port)
1312 {
1313 struct uart_amba_port *uap =
1314 container_of(port, struct uart_amba_port, port);
1315
1316 uap->im &= ~UART011_TXIM;
1317 pl011_write(uap->im, uap, REG_IMSC);
1318 pl011_dma_tx_stop(uap);
1319 }
1320
1321 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1322
1323 /* Start TX with programmed I/O only (no DMA) */
pl011_start_tx_pio(struct uart_amba_port * uap)1324 static void pl011_start_tx_pio(struct uart_amba_port *uap)
1325 {
1326 if (pl011_tx_chars(uap, false)) {
1327 uap->im |= UART011_TXIM;
1328 pl011_write(uap->im, uap, REG_IMSC);
1329 }
1330 }
1331
pl011_start_tx(struct uart_port * port)1332 static void pl011_start_tx(struct uart_port *port)
1333 {
1334 struct uart_amba_port *uap =
1335 container_of(port, struct uart_amba_port, port);
1336
1337 if (!pl011_dma_tx_start(uap))
1338 pl011_start_tx_pio(uap);
1339 }
1340
pl011_stop_rx(struct uart_port * port)1341 static void pl011_stop_rx(struct uart_port *port)
1342 {
1343 struct uart_amba_port *uap =
1344 container_of(port, struct uart_amba_port, port);
1345
1346 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1347 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1348 pl011_write(uap->im, uap, REG_IMSC);
1349
1350 pl011_dma_rx_stop(uap);
1351 }
1352
pl011_enable_ms(struct uart_port * port)1353 static void pl011_enable_ms(struct uart_port *port)
1354 {
1355 struct uart_amba_port *uap =
1356 container_of(port, struct uart_amba_port, port);
1357
1358 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1359 pl011_write(uap->im, uap, REG_IMSC);
1360 }
1361
pl011_rx_chars(struct uart_amba_port * uap)1362 static void pl011_rx_chars(struct uart_amba_port *uap)
1363 __releases(&uap->port.lock)
1364 __acquires(&uap->port.lock)
1365 {
1366 pl011_fifo_to_tty(uap);
1367
1368 spin_unlock(&uap->port.lock);
1369 tty_flip_buffer_push(&uap->port.state->port);
1370 /*
1371 * If we were temporarily out of DMA mode for a while,
1372 * attempt to switch back to DMA mode again.
1373 */
1374 if (pl011_dma_rx_available(uap)) {
1375 if (pl011_dma_rx_trigger_dma(uap)) {
1376 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1377 "fall back to interrupt mode again\n");
1378 uap->im |= UART011_RXIM;
1379 pl011_write(uap->im, uap, REG_IMSC);
1380 } else {
1381 #ifdef CONFIG_DMA_ENGINE
1382 /* Start Rx DMA poll */
1383 if (uap->dmarx.poll_rate) {
1384 uap->dmarx.last_jiffies = jiffies;
1385 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1386 mod_timer(&uap->dmarx.timer,
1387 jiffies +
1388 msecs_to_jiffies(uap->dmarx.poll_rate));
1389 }
1390 #endif
1391 }
1392 }
1393 spin_lock(&uap->port.lock);
1394 }
1395
pl011_tx_char(struct uart_amba_port * uap,unsigned char c,bool from_irq)1396 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1397 bool from_irq)
1398 {
1399 if (unlikely(!from_irq) &&
1400 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1401 return false; /* unable to transmit character */
1402
1403 pl011_write(c, uap, REG_DR);
1404 uap->port.icount.tx++;
1405
1406 return true;
1407 }
1408
1409 /* Returns true if tx interrupts have to be (kept) enabled */
pl011_tx_chars(struct uart_amba_port * uap,bool from_irq)1410 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1411 {
1412 struct circ_buf *xmit = &uap->port.state->xmit;
1413 int count = uap->fifosize >> 1;
1414
1415 if (uap->port.x_char) {
1416 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1417 return true;
1418 uap->port.x_char = 0;
1419 --count;
1420 }
1421 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1422 pl011_stop_tx(&uap->port);
1423 return false;
1424 }
1425
1426 /* If we are using DMA mode, try to send some characters. */
1427 if (pl011_dma_tx_irq(uap))
1428 return true;
1429
1430 do {
1431 if (likely(from_irq) && count-- == 0)
1432 break;
1433
1434 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1435 break;
1436
1437 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1438 } while (!uart_circ_empty(xmit));
1439
1440 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1441 uart_write_wakeup(&uap->port);
1442
1443 if (uart_circ_empty(xmit)) {
1444 pl011_stop_tx(&uap->port);
1445 return false;
1446 }
1447 return true;
1448 }
1449
pl011_modem_status(struct uart_amba_port * uap)1450 static void pl011_modem_status(struct uart_amba_port *uap)
1451 {
1452 unsigned int status, delta;
1453
1454 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1455
1456 delta = status ^ uap->old_status;
1457 uap->old_status = status;
1458
1459 if (!delta)
1460 return;
1461
1462 if (delta & UART01x_FR_DCD)
1463 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1464
1465 if (delta & uap->vendor->fr_dsr)
1466 uap->port.icount.dsr++;
1467
1468 if (delta & uap->vendor->fr_cts)
1469 uart_handle_cts_change(&uap->port,
1470 status & uap->vendor->fr_cts);
1471
1472 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1473 }
1474
check_apply_cts_event_workaround(struct uart_amba_port * uap)1475 static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1476 {
1477 unsigned int dummy_read;
1478
1479 if (!uap->vendor->cts_event_workaround)
1480 return;
1481
1482 /* workaround to make sure that all bits are unlocked.. */
1483 pl011_write(0x00, uap, REG_ICR);
1484
1485 /*
1486 * WA: introduce 26ns(1 uart clk) delay before W1C;
1487 * single apb access will incur 2 pclk(133.12Mhz) delay,
1488 * so add 2 dummy reads
1489 */
1490 dummy_read = pl011_read(uap, REG_ICR);
1491 dummy_read = pl011_read(uap, REG_ICR);
1492 }
1493
pl011_int(int irq,void * dev_id)1494 static irqreturn_t pl011_int(int irq, void *dev_id)
1495 {
1496 struct uart_amba_port *uap = dev_id;
1497 unsigned long flags;
1498 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1499 u16 imsc;
1500 int handled = 0;
1501
1502 spin_lock_irqsave(&uap->port.lock, flags);
1503 imsc = pl011_read(uap, REG_IMSC);
1504 status = pl011_read(uap, REG_RIS) & imsc;
1505 if (status) {
1506 do {
1507 check_apply_cts_event_workaround(uap);
1508
1509 pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
1510 UART011_RXIS),
1511 uap, REG_ICR);
1512
1513 if (status & (UART011_RTIS|UART011_RXIS)) {
1514 if (pl011_dma_rx_running(uap))
1515 pl011_dma_rx_irq(uap);
1516 else
1517 pl011_rx_chars(uap);
1518 }
1519 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1520 UART011_CTSMIS|UART011_RIMIS))
1521 pl011_modem_status(uap);
1522 if (status & UART011_TXIS)
1523 pl011_tx_chars(uap, true);
1524
1525 if (pass_counter-- == 0)
1526 break;
1527
1528 status = pl011_read(uap, REG_RIS) & imsc;
1529 } while (status != 0);
1530 handled = 1;
1531 }
1532
1533 spin_unlock_irqrestore(&uap->port.lock, flags);
1534
1535 return IRQ_RETVAL(handled);
1536 }
1537
pl011_tx_empty(struct uart_port * port)1538 static unsigned int pl011_tx_empty(struct uart_port *port)
1539 {
1540 struct uart_amba_port *uap =
1541 container_of(port, struct uart_amba_port, port);
1542
1543 /* Allow feature register bits to be inverted to work around errata */
1544 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1545
1546 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1547 0 : TIOCSER_TEMT;
1548 }
1549
pl011_get_mctrl(struct uart_port * port)1550 static unsigned int pl011_get_mctrl(struct uart_port *port)
1551 {
1552 struct uart_amba_port *uap =
1553 container_of(port, struct uart_amba_port, port);
1554 unsigned int result = 0;
1555 unsigned int status = pl011_read(uap, REG_FR);
1556
1557 #define TIOCMBIT(uartbit, tiocmbit) \
1558 if (status & uartbit) \
1559 result |= tiocmbit
1560
1561 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1562 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
1563 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
1564 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
1565 #undef TIOCMBIT
1566 return result;
1567 }
1568
pl011_set_mctrl(struct uart_port * port,unsigned int mctrl)1569 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1570 {
1571 struct uart_amba_port *uap =
1572 container_of(port, struct uart_amba_port, port);
1573 unsigned int cr;
1574
1575 cr = pl011_read(uap, REG_CR);
1576
1577 #define TIOCMBIT(tiocmbit, uartbit) \
1578 if (mctrl & tiocmbit) \
1579 cr |= uartbit; \
1580 else \
1581 cr &= ~uartbit
1582
1583 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1584 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1585 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1586 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1587 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1588
1589 if (uap->autorts) {
1590 /* We need to disable auto-RTS if we want to turn RTS off */
1591 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1592 }
1593 #undef TIOCMBIT
1594
1595 pl011_write(cr, uap, REG_CR);
1596 }
1597
pl011_break_ctl(struct uart_port * port,int break_state)1598 static void pl011_break_ctl(struct uart_port *port, int break_state)
1599 {
1600 struct uart_amba_port *uap =
1601 container_of(port, struct uart_amba_port, port);
1602 unsigned long flags;
1603 unsigned int lcr_h;
1604
1605 spin_lock_irqsave(&uap->port.lock, flags);
1606 lcr_h = pl011_read(uap, REG_LCRH_TX);
1607 if (break_state == -1)
1608 lcr_h |= UART01x_LCRH_BRK;
1609 else
1610 lcr_h &= ~UART01x_LCRH_BRK;
1611 pl011_write(lcr_h, uap, REG_LCRH_TX);
1612 spin_unlock_irqrestore(&uap->port.lock, flags);
1613 }
1614
1615 #ifdef CONFIG_CONSOLE_POLL
1616
pl011_quiesce_irqs(struct uart_port * port)1617 static void pl011_quiesce_irqs(struct uart_port *port)
1618 {
1619 struct uart_amba_port *uap =
1620 container_of(port, struct uart_amba_port, port);
1621
1622 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1623 /*
1624 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1625 * we simply mask it. start_tx() will unmask it.
1626 *
1627 * Note we can race with start_tx(), and if the race happens, the
1628 * polling user might get another interrupt just after we clear it.
1629 * But it should be OK and can happen even w/o the race, e.g.
1630 * controller immediately got some new data and raised the IRQ.
1631 *
1632 * And whoever uses polling routines assumes that it manages the device
1633 * (including tx queue), so we're also fine with start_tx()'s caller
1634 * side.
1635 */
1636 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1637 REG_IMSC);
1638 }
1639
pl011_get_poll_char(struct uart_port * port)1640 static int pl011_get_poll_char(struct uart_port *port)
1641 {
1642 struct uart_amba_port *uap =
1643 container_of(port, struct uart_amba_port, port);
1644 unsigned int status;
1645
1646 /*
1647 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1648 * debugger.
1649 */
1650 pl011_quiesce_irqs(port);
1651
1652 status = pl011_read(uap, REG_FR);
1653 if (status & UART01x_FR_RXFE)
1654 return NO_POLL_CHAR;
1655
1656 return pl011_read(uap, REG_DR);
1657 }
1658
pl011_put_poll_char(struct uart_port * port,unsigned char ch)1659 static void pl011_put_poll_char(struct uart_port *port,
1660 unsigned char ch)
1661 {
1662 struct uart_amba_port *uap =
1663 container_of(port, struct uart_amba_port, port);
1664
1665 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1666 cpu_relax();
1667
1668 pl011_write(ch, uap, REG_DR);
1669 }
1670
1671 #endif /* CONFIG_CONSOLE_POLL */
1672
pl011_hwinit(struct uart_port * port)1673 static int pl011_hwinit(struct uart_port *port)
1674 {
1675 struct uart_amba_port *uap =
1676 container_of(port, struct uart_amba_port, port);
1677 int retval;
1678
1679 /* Optionaly enable pins to be muxed in and configured */
1680 pinctrl_pm_select_default_state(port->dev);
1681
1682 /*
1683 * Try to enable the clock producer.
1684 */
1685 retval = clk_prepare_enable(uap->clk);
1686 if (retval)
1687 return retval;
1688
1689 uap->port.uartclk = clk_get_rate(uap->clk);
1690
1691 /* Clear pending error and receive interrupts */
1692 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1693 UART011_FEIS | UART011_RTIS | UART011_RXIS,
1694 uap, REG_ICR);
1695
1696 /*
1697 * Save interrupts enable mask, and enable RX interrupts in case if
1698 * the interrupt is used for NMI entry.
1699 */
1700 uap->im = pl011_read(uap, REG_IMSC);
1701 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
1702
1703 if (dev_get_platdata(uap->port.dev)) {
1704 struct amba_pl011_data *plat;
1705
1706 plat = dev_get_platdata(uap->port.dev);
1707 if (plat->init)
1708 plat->init();
1709 }
1710 return 0;
1711 }
1712
pl011_split_lcrh(const struct uart_amba_port * uap)1713 static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1714 {
1715 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1716 pl011_reg_to_offset(uap, REG_LCRH_TX);
1717 }
1718
pl011_write_lcr_h(struct uart_amba_port * uap,unsigned int lcr_h)1719 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1720 {
1721 pl011_write(lcr_h, uap, REG_LCRH_RX);
1722 if (pl011_split_lcrh(uap)) {
1723 int i;
1724 /*
1725 * Wait 10 PCLKs before writing LCRH_TX register,
1726 * to get this delay write read only register 10 times
1727 */
1728 for (i = 0; i < 10; ++i)
1729 pl011_write(0xff, uap, REG_MIS);
1730 pl011_write(lcr_h, uap, REG_LCRH_TX);
1731 }
1732 }
1733
pl011_allocate_irq(struct uart_amba_port * uap)1734 static int pl011_allocate_irq(struct uart_amba_port *uap)
1735 {
1736 pl011_write(uap->im, uap, REG_IMSC);
1737
1738 return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1739 }
1740
1741 /*
1742 * Enable interrupts, only timeouts when using DMA
1743 * if initial RX DMA job failed, start in interrupt mode
1744 * as well.
1745 */
pl011_enable_interrupts(struct uart_amba_port * uap)1746 static void pl011_enable_interrupts(struct uart_amba_port *uap)
1747 {
1748 unsigned int i;
1749
1750 spin_lock_irq(&uap->port.lock);
1751
1752 /* Clear out any spuriously appearing RX interrupts */
1753 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
1754
1755 /*
1756 * RXIS is asserted only when the RX FIFO transitions from below
1757 * to above the trigger threshold. If the RX FIFO is already
1758 * full to the threshold this can't happen and RXIS will now be
1759 * stuck off. Drain the RX FIFO explicitly to fix this:
1760 */
1761 for (i = 0; i < uap->fifosize * 2; ++i) {
1762 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
1763 break;
1764
1765 pl011_read(uap, REG_DR);
1766 }
1767
1768 uap->im = UART011_RTIM;
1769 if (!pl011_dma_rx_running(uap))
1770 uap->im |= UART011_RXIM;
1771 pl011_write(uap->im, uap, REG_IMSC);
1772 spin_unlock_irq(&uap->port.lock);
1773 }
1774
pl011_startup(struct uart_port * port)1775 static int pl011_startup(struct uart_port *port)
1776 {
1777 struct uart_amba_port *uap =
1778 container_of(port, struct uart_amba_port, port);
1779 unsigned int cr;
1780 int retval;
1781
1782 retval = pl011_hwinit(port);
1783 if (retval)
1784 goto clk_dis;
1785
1786 retval = pl011_allocate_irq(uap);
1787 if (retval)
1788 goto clk_dis;
1789
1790 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1791
1792 spin_lock_irq(&uap->port.lock);
1793
1794 /* restore RTS and DTR */
1795 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1796 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1797 pl011_write(cr, uap, REG_CR);
1798
1799 spin_unlock_irq(&uap->port.lock);
1800
1801 /*
1802 * initialise the old status of the modem signals
1803 */
1804 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1805
1806 /* Startup DMA */
1807 pl011_dma_startup(uap);
1808
1809 pl011_enable_interrupts(uap);
1810
1811 return 0;
1812
1813 clk_dis:
1814 clk_disable_unprepare(uap->clk);
1815 return retval;
1816 }
1817
sbsa_uart_startup(struct uart_port * port)1818 static int sbsa_uart_startup(struct uart_port *port)
1819 {
1820 struct uart_amba_port *uap =
1821 container_of(port, struct uart_amba_port, port);
1822 int retval;
1823
1824 retval = pl011_hwinit(port);
1825 if (retval)
1826 return retval;
1827
1828 retval = pl011_allocate_irq(uap);
1829 if (retval)
1830 return retval;
1831
1832 /* The SBSA UART does not support any modem status lines. */
1833 uap->old_status = 0;
1834
1835 pl011_enable_interrupts(uap);
1836
1837 return 0;
1838 }
1839
pl011_shutdown_channel(struct uart_amba_port * uap,unsigned int lcrh)1840 static void pl011_shutdown_channel(struct uart_amba_port *uap,
1841 unsigned int lcrh)
1842 {
1843 unsigned long val;
1844
1845 val = pl011_read(uap, lcrh);
1846 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1847 pl011_write(val, uap, lcrh);
1848 }
1849
1850 /*
1851 * disable the port. It should not disable RTS and DTR.
1852 * Also RTS and DTR state should be preserved to restore
1853 * it during startup().
1854 */
pl011_disable_uart(struct uart_amba_port * uap)1855 static void pl011_disable_uart(struct uart_amba_port *uap)
1856 {
1857 unsigned int cr;
1858
1859 uap->autorts = false;
1860 spin_lock_irq(&uap->port.lock);
1861 cr = pl011_read(uap, REG_CR);
1862 uap->old_cr = cr;
1863 cr &= UART011_CR_RTS | UART011_CR_DTR;
1864 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1865 pl011_write(cr, uap, REG_CR);
1866 spin_unlock_irq(&uap->port.lock);
1867
1868 /*
1869 * disable break condition and fifos
1870 */
1871 pl011_shutdown_channel(uap, REG_LCRH_RX);
1872 if (pl011_split_lcrh(uap))
1873 pl011_shutdown_channel(uap, REG_LCRH_TX);
1874 }
1875
pl011_disable_interrupts(struct uart_amba_port * uap)1876 static void pl011_disable_interrupts(struct uart_amba_port *uap)
1877 {
1878 spin_lock_irq(&uap->port.lock);
1879
1880 /* mask all interrupts and clear all pending ones */
1881 uap->im = 0;
1882 pl011_write(uap->im, uap, REG_IMSC);
1883 pl011_write(0xffff, uap, REG_ICR);
1884
1885 spin_unlock_irq(&uap->port.lock);
1886 }
1887
pl011_shutdown(struct uart_port * port)1888 static void pl011_shutdown(struct uart_port *port)
1889 {
1890 struct uart_amba_port *uap =
1891 container_of(port, struct uart_amba_port, port);
1892
1893 pl011_disable_interrupts(uap);
1894
1895 pl011_dma_shutdown(uap);
1896
1897 free_irq(uap->port.irq, uap);
1898
1899 pl011_disable_uart(uap);
1900
1901 /*
1902 * Shut down the clock producer
1903 */
1904 clk_disable_unprepare(uap->clk);
1905 /* Optionally let pins go into sleep states */
1906 pinctrl_pm_select_sleep_state(port->dev);
1907
1908 if (dev_get_platdata(uap->port.dev)) {
1909 struct amba_pl011_data *plat;
1910
1911 plat = dev_get_platdata(uap->port.dev);
1912 if (plat->exit)
1913 plat->exit();
1914 }
1915
1916 if (uap->port.ops->flush_buffer)
1917 uap->port.ops->flush_buffer(port);
1918 }
1919
sbsa_uart_shutdown(struct uart_port * port)1920 static void sbsa_uart_shutdown(struct uart_port *port)
1921 {
1922 struct uart_amba_port *uap =
1923 container_of(port, struct uart_amba_port, port);
1924
1925 pl011_disable_interrupts(uap);
1926
1927 free_irq(uap->port.irq, uap);
1928
1929 if (uap->port.ops->flush_buffer)
1930 uap->port.ops->flush_buffer(port);
1931 }
1932
1933 static void
pl011_setup_status_masks(struct uart_port * port,struct ktermios * termios)1934 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
1935 {
1936 port->read_status_mask = UART011_DR_OE | 255;
1937 if (termios->c_iflag & INPCK)
1938 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1939 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1940 port->read_status_mask |= UART011_DR_BE;
1941
1942 /*
1943 * Characters to ignore
1944 */
1945 port->ignore_status_mask = 0;
1946 if (termios->c_iflag & IGNPAR)
1947 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1948 if (termios->c_iflag & IGNBRK) {
1949 port->ignore_status_mask |= UART011_DR_BE;
1950 /*
1951 * If we're ignoring parity and break indicators,
1952 * ignore overruns too (for real raw support).
1953 */
1954 if (termios->c_iflag & IGNPAR)
1955 port->ignore_status_mask |= UART011_DR_OE;
1956 }
1957
1958 /*
1959 * Ignore all characters if CREAD is not set.
1960 */
1961 if ((termios->c_cflag & CREAD) == 0)
1962 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1963 }
1964
1965 static void
pl011_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)1966 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1967 struct ktermios *old)
1968 {
1969 struct uart_amba_port *uap =
1970 container_of(port, struct uart_amba_port, port);
1971 unsigned int lcr_h, old_cr;
1972 unsigned long flags;
1973 unsigned int baud, quot, clkdiv;
1974
1975 if (uap->vendor->oversampling)
1976 clkdiv = 8;
1977 else
1978 clkdiv = 16;
1979
1980 /*
1981 * Ask the core to calculate the divisor for us.
1982 */
1983 baud = uart_get_baud_rate(port, termios, old, 0,
1984 port->uartclk / clkdiv);
1985 #ifdef CONFIG_DMA_ENGINE
1986 /*
1987 * Adjust RX DMA polling rate with baud rate if not specified.
1988 */
1989 if (uap->dmarx.auto_poll_rate)
1990 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
1991 #endif
1992
1993 if (baud > port->uartclk/16)
1994 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1995 else
1996 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1997
1998 switch (termios->c_cflag & CSIZE) {
1999 case CS5:
2000 lcr_h = UART01x_LCRH_WLEN_5;
2001 break;
2002 case CS6:
2003 lcr_h = UART01x_LCRH_WLEN_6;
2004 break;
2005 case CS7:
2006 lcr_h = UART01x_LCRH_WLEN_7;
2007 break;
2008 default: // CS8
2009 lcr_h = UART01x_LCRH_WLEN_8;
2010 break;
2011 }
2012 if (termios->c_cflag & CSTOPB)
2013 lcr_h |= UART01x_LCRH_STP2;
2014 if (termios->c_cflag & PARENB) {
2015 lcr_h |= UART01x_LCRH_PEN;
2016 if (!(termios->c_cflag & PARODD))
2017 lcr_h |= UART01x_LCRH_EPS;
2018 if (termios->c_cflag & CMSPAR)
2019 lcr_h |= UART011_LCRH_SPS;
2020 }
2021 if (uap->fifosize > 1)
2022 lcr_h |= UART01x_LCRH_FEN;
2023
2024 spin_lock_irqsave(&port->lock, flags);
2025
2026 /*
2027 * Update the per-port timeout.
2028 */
2029 uart_update_timeout(port, termios->c_cflag, baud);
2030
2031 pl011_setup_status_masks(port, termios);
2032
2033 if (UART_ENABLE_MS(port, termios->c_cflag))
2034 pl011_enable_ms(port);
2035
2036 /* first, disable everything */
2037 old_cr = pl011_read(uap, REG_CR);
2038 pl011_write(0, uap, REG_CR);
2039
2040 if (termios->c_cflag & CRTSCTS) {
2041 if (old_cr & UART011_CR_RTS)
2042 old_cr |= UART011_CR_RTSEN;
2043
2044 old_cr |= UART011_CR_CTSEN;
2045 uap->autorts = true;
2046 } else {
2047 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2048 uap->autorts = false;
2049 }
2050
2051 if (uap->vendor->oversampling) {
2052 if (baud > port->uartclk / 16)
2053 old_cr |= ST_UART011_CR_OVSFACT;
2054 else
2055 old_cr &= ~ST_UART011_CR_OVSFACT;
2056 }
2057
2058 /*
2059 * Workaround for the ST Micro oversampling variants to
2060 * increase the bitrate slightly, by lowering the divisor,
2061 * to avoid delayed sampling of start bit at high speeds,
2062 * else we see data corruption.
2063 */
2064 if (uap->vendor->oversampling) {
2065 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
2066 quot -= 1;
2067 else if ((baud > 3250000) && (quot > 2))
2068 quot -= 2;
2069 }
2070 /* Set baud rate */
2071 pl011_write(quot & 0x3f, uap, REG_FBRD);
2072 pl011_write(quot >> 6, uap, REG_IBRD);
2073
2074 /*
2075 * ----------v----------v----------v----------v-----
2076 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
2077 * REG_FBRD & REG_IBRD.
2078 * ----------^----------^----------^----------^-----
2079 */
2080 pl011_write_lcr_h(uap, lcr_h);
2081 pl011_write(old_cr, uap, REG_CR);
2082
2083 spin_unlock_irqrestore(&port->lock, flags);
2084 }
2085
2086 static void
sbsa_uart_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)2087 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2088 struct ktermios *old)
2089 {
2090 struct uart_amba_port *uap =
2091 container_of(port, struct uart_amba_port, port);
2092 unsigned long flags;
2093
2094 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2095
2096 /* The SBSA UART only supports 8n1 without hardware flow control. */
2097 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2098 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2099 termios->c_cflag |= CS8 | CLOCAL;
2100
2101 spin_lock_irqsave(&port->lock, flags);
2102 uart_update_timeout(port, CS8, uap->fixed_baud);
2103 pl011_setup_status_masks(port, termios);
2104 spin_unlock_irqrestore(&port->lock, flags);
2105 }
2106
pl011_type(struct uart_port * port)2107 static const char *pl011_type(struct uart_port *port)
2108 {
2109 struct uart_amba_port *uap =
2110 container_of(port, struct uart_amba_port, port);
2111 return uap->port.type == PORT_AMBA ? uap->type : NULL;
2112 }
2113
2114 /*
2115 * Release the memory region(s) being used by 'port'
2116 */
pl011_release_port(struct uart_port * port)2117 static void pl011_release_port(struct uart_port *port)
2118 {
2119 release_mem_region(port->mapbase, SZ_4K);
2120 }
2121
2122 /*
2123 * Request the memory region(s) being used by 'port'
2124 */
pl011_request_port(struct uart_port * port)2125 static int pl011_request_port(struct uart_port *port)
2126 {
2127 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
2128 != NULL ? 0 : -EBUSY;
2129 }
2130
2131 /*
2132 * Configure/autoconfigure the port.
2133 */
pl011_config_port(struct uart_port * port,int flags)2134 static void pl011_config_port(struct uart_port *port, int flags)
2135 {
2136 if (flags & UART_CONFIG_TYPE) {
2137 port->type = PORT_AMBA;
2138 pl011_request_port(port);
2139 }
2140 }
2141
2142 /*
2143 * verify the new serial_struct (for TIOCSSERIAL).
2144 */
pl011_verify_port(struct uart_port * port,struct serial_struct * ser)2145 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
2146 {
2147 int ret = 0;
2148 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2149 ret = -EINVAL;
2150 if (ser->irq < 0 || ser->irq >= nr_irqs)
2151 ret = -EINVAL;
2152 if (ser->baud_base < 9600)
2153 ret = -EINVAL;
2154 return ret;
2155 }
2156
2157 static const struct uart_ops amba_pl011_pops = {
2158 .tx_empty = pl011_tx_empty,
2159 .set_mctrl = pl011_set_mctrl,
2160 .get_mctrl = pl011_get_mctrl,
2161 .stop_tx = pl011_stop_tx,
2162 .start_tx = pl011_start_tx,
2163 .stop_rx = pl011_stop_rx,
2164 .enable_ms = pl011_enable_ms,
2165 .break_ctl = pl011_break_ctl,
2166 .startup = pl011_startup,
2167 .shutdown = pl011_shutdown,
2168 .flush_buffer = pl011_dma_flush_buffer,
2169 .set_termios = pl011_set_termios,
2170 .type = pl011_type,
2171 .release_port = pl011_release_port,
2172 .request_port = pl011_request_port,
2173 .config_port = pl011_config_port,
2174 .verify_port = pl011_verify_port,
2175 #ifdef CONFIG_CONSOLE_POLL
2176 .poll_init = pl011_hwinit,
2177 .poll_get_char = pl011_get_poll_char,
2178 .poll_put_char = pl011_put_poll_char,
2179 #endif
2180 };
2181
sbsa_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)2182 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2183 {
2184 }
2185
sbsa_uart_get_mctrl(struct uart_port * port)2186 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2187 {
2188 return 0;
2189 }
2190
2191 static const struct uart_ops sbsa_uart_pops = {
2192 .tx_empty = pl011_tx_empty,
2193 .set_mctrl = sbsa_uart_set_mctrl,
2194 .get_mctrl = sbsa_uart_get_mctrl,
2195 .stop_tx = pl011_stop_tx,
2196 .start_tx = pl011_start_tx,
2197 .stop_rx = pl011_stop_rx,
2198 .startup = sbsa_uart_startup,
2199 .shutdown = sbsa_uart_shutdown,
2200 .set_termios = sbsa_uart_set_termios,
2201 .type = pl011_type,
2202 .release_port = pl011_release_port,
2203 .request_port = pl011_request_port,
2204 .config_port = pl011_config_port,
2205 .verify_port = pl011_verify_port,
2206 #ifdef CONFIG_CONSOLE_POLL
2207 .poll_init = pl011_hwinit,
2208 .poll_get_char = pl011_get_poll_char,
2209 .poll_put_char = pl011_put_poll_char,
2210 #endif
2211 };
2212
2213 static struct uart_amba_port *amba_ports[UART_NR];
2214
2215 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2216
pl011_console_putchar(struct uart_port * port,int ch)2217 static void pl011_console_putchar(struct uart_port *port, int ch)
2218 {
2219 struct uart_amba_port *uap =
2220 container_of(port, struct uart_amba_port, port);
2221
2222 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2223 cpu_relax();
2224 pl011_write(ch, uap, REG_DR);
2225 }
2226
2227 static void
pl011_console_write(struct console * co,const char * s,unsigned int count)2228 pl011_console_write(struct console *co, const char *s, unsigned int count)
2229 {
2230 struct uart_amba_port *uap = amba_ports[co->index];
2231 unsigned int old_cr = 0, new_cr;
2232 unsigned long flags;
2233 int locked = 1;
2234
2235 clk_enable(uap->clk);
2236
2237 local_irq_save(flags);
2238 if (uap->port.sysrq)
2239 locked = 0;
2240 else if (oops_in_progress)
2241 locked = spin_trylock(&uap->port.lock);
2242 else
2243 spin_lock(&uap->port.lock);
2244
2245 /*
2246 * First save the CR then disable the interrupts
2247 */
2248 if (!uap->vendor->always_enabled) {
2249 old_cr = pl011_read(uap, REG_CR);
2250 new_cr = old_cr & ~UART011_CR_CTSEN;
2251 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
2252 pl011_write(new_cr, uap, REG_CR);
2253 }
2254
2255 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2256
2257 /*
2258 * Finally, wait for transmitter to become empty and restore the
2259 * TCR. Allow feature register bits to be inverted to work around
2260 * errata.
2261 */
2262 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2263 & uap->vendor->fr_busy)
2264 cpu_relax();
2265 if (!uap->vendor->always_enabled)
2266 pl011_write(old_cr, uap, REG_CR);
2267
2268 if (locked)
2269 spin_unlock(&uap->port.lock);
2270 local_irq_restore(flags);
2271
2272 clk_disable(uap->clk);
2273 }
2274
2275 static void __init
pl011_console_get_options(struct uart_amba_port * uap,int * baud,int * parity,int * bits)2276 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2277 int *parity, int *bits)
2278 {
2279 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
2280 unsigned int lcr_h, ibrd, fbrd;
2281
2282 lcr_h = pl011_read(uap, REG_LCRH_TX);
2283
2284 *parity = 'n';
2285 if (lcr_h & UART01x_LCRH_PEN) {
2286 if (lcr_h & UART01x_LCRH_EPS)
2287 *parity = 'e';
2288 else
2289 *parity = 'o';
2290 }
2291
2292 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2293 *bits = 7;
2294 else
2295 *bits = 8;
2296
2297 ibrd = pl011_read(uap, REG_IBRD);
2298 fbrd = pl011_read(uap, REG_FBRD);
2299
2300 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2301
2302 if (uap->vendor->oversampling) {
2303 if (pl011_read(uap, REG_CR)
2304 & ST_UART011_CR_OVSFACT)
2305 *baud *= 2;
2306 }
2307 }
2308 }
2309
pl011_console_setup(struct console * co,char * options)2310 static int __init pl011_console_setup(struct console *co, char *options)
2311 {
2312 struct uart_amba_port *uap;
2313 int baud = 38400;
2314 int bits = 8;
2315 int parity = 'n';
2316 int flow = 'n';
2317 int ret;
2318
2319 /*
2320 * Check whether an invalid uart number has been specified, and
2321 * if so, search for the first available port that does have
2322 * console support.
2323 */
2324 if (co->index >= UART_NR)
2325 co->index = 0;
2326 uap = amba_ports[co->index];
2327 if (!uap)
2328 return -ENODEV;
2329
2330 /* Allow pins to be muxed in and configured */
2331 pinctrl_pm_select_default_state(uap->port.dev);
2332
2333 ret = clk_prepare(uap->clk);
2334 if (ret)
2335 return ret;
2336
2337 if (dev_get_platdata(uap->port.dev)) {
2338 struct amba_pl011_data *plat;
2339
2340 plat = dev_get_platdata(uap->port.dev);
2341 if (plat->init)
2342 plat->init();
2343 }
2344
2345 uap->port.uartclk = clk_get_rate(uap->clk);
2346
2347 if (uap->vendor->fixed_options) {
2348 baud = uap->fixed_baud;
2349 } else {
2350 if (options)
2351 uart_parse_options(options,
2352 &baud, &parity, &bits, &flow);
2353 else
2354 pl011_console_get_options(uap, &baud, &parity, &bits);
2355 }
2356
2357 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2358 }
2359
2360 /**
2361 * pl011_console_match - non-standard console matching
2362 * @co: registering console
2363 * @name: name from console command line
2364 * @idx: index from console command line
2365 * @options: ptr to option string from console command line
2366 *
2367 * Only attempts to match console command lines of the form:
2368 * console=pl011,mmio|mmio32,<addr>[,<options>]
2369 * console=pl011,0x<addr>[,<options>]
2370 * This form is used to register an initial earlycon boot console and
2371 * replace it with the amba_console at pl011 driver init.
2372 *
2373 * Performs console setup for a match (as required by interface)
2374 * If no <options> are specified, then assume the h/w is already setup.
2375 *
2376 * Returns 0 if console matches; otherwise non-zero to use default matching
2377 */
pl011_console_match(struct console * co,char * name,int idx,char * options)2378 static int __init pl011_console_match(struct console *co, char *name, int idx,
2379 char *options)
2380 {
2381 unsigned char iotype;
2382 resource_size_t addr;
2383 int i;
2384
2385 /*
2386 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum
2387 * have a distinct console name, so make sure we check for that.
2388 * The actual implementation of the erratum occurs in the probe
2389 * function.
2390 */
2391 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0))
2392 return -ENODEV;
2393
2394 if (uart_parse_earlycon(options, &iotype, &addr, &options))
2395 return -ENODEV;
2396
2397 if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
2398 return -ENODEV;
2399
2400 /* try to match the port specified on the command line */
2401 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2402 struct uart_port *port;
2403
2404 if (!amba_ports[i])
2405 continue;
2406
2407 port = &amba_ports[i]->port;
2408
2409 if (port->mapbase != addr)
2410 continue;
2411
2412 co->index = i;
2413 port->cons = co;
2414 return pl011_console_setup(co, options);
2415 }
2416
2417 return -ENODEV;
2418 }
2419
2420 static struct uart_driver amba_reg;
2421 static struct console amba_console = {
2422 .name = "ttyAMA",
2423 .write = pl011_console_write,
2424 .device = uart_console_device,
2425 .setup = pl011_console_setup,
2426 .match = pl011_console_match,
2427 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2428 .index = -1,
2429 .data = &amba_reg,
2430 };
2431
2432 #define AMBA_CONSOLE (&amba_console)
2433
qdf2400_e44_putc(struct uart_port * port,int c)2434 static void qdf2400_e44_putc(struct uart_port *port, int c)
2435 {
2436 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2437 cpu_relax();
2438 writel(c, port->membase + UART01x_DR);
2439 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))
2440 cpu_relax();
2441 }
2442
qdf2400_e44_early_write(struct console * con,const char * s,unsigned n)2443 static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n)
2444 {
2445 struct earlycon_device *dev = con->data;
2446
2447 uart_console_write(&dev->port, s, n, qdf2400_e44_putc);
2448 }
2449
pl011_putc(struct uart_port * port,int c)2450 static void pl011_putc(struct uart_port *port, int c)
2451 {
2452 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2453 cpu_relax();
2454 if (port->iotype == UPIO_MEM32)
2455 writel(c, port->membase + UART01x_DR);
2456 else
2457 writeb(c, port->membase + UART01x_DR);
2458 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2459 cpu_relax();
2460 }
2461
pl011_early_write(struct console * con,const char * s,unsigned n)2462 static void pl011_early_write(struct console *con, const char *s, unsigned n)
2463 {
2464 struct earlycon_device *dev = con->data;
2465
2466 uart_console_write(&dev->port, s, n, pl011_putc);
2467 }
2468
2469 /*
2470 * On non-ACPI systems, earlycon is enabled by specifying
2471 * "earlycon=pl011,<address>" on the kernel command line.
2472 *
2473 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table,
2474 * by specifying only "earlycon" on the command line. Because it requires
2475 * SPCR, the console starts after ACPI is parsed, which is later than a
2476 * traditional early console.
2477 *
2478 * To get the traditional early console that starts before ACPI is parsed,
2479 * specify the full "earlycon=pl011,<address>" option.
2480 */
pl011_early_console_setup(struct earlycon_device * device,const char * opt)2481 static int __init pl011_early_console_setup(struct earlycon_device *device,
2482 const char *opt)
2483 {
2484 if (!device->port.membase)
2485 return -ENODEV;
2486
2487 device->con->write = pl011_early_write;
2488
2489 return 0;
2490 }
2491 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
2492 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
2493
2494 /*
2495 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by
2496 * Erratum 44, traditional earlycon can be enabled by specifying
2497 * "earlycon=qdf2400_e44,<address>". Any options are ignored.
2498 *
2499 * Alternatively, you can just specify "earlycon", and the early console
2500 * will be enabled with the information from the SPCR table. In this
2501 * case, the SPCR code will detect the need for the E44 work-around,
2502 * and set the console name to "qdf2400_e44".
2503 */
2504 static int __init
qdf2400_e44_early_console_setup(struct earlycon_device * device,const char * opt)2505 qdf2400_e44_early_console_setup(struct earlycon_device *device,
2506 const char *opt)
2507 {
2508 if (!device->port.membase)
2509 return -ENODEV;
2510
2511 device->con->write = qdf2400_e44_early_write;
2512 return 0;
2513 }
2514 EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup);
2515
2516 #else
2517 #define AMBA_CONSOLE NULL
2518 #endif
2519
2520 static struct uart_driver amba_reg = {
2521 .owner = THIS_MODULE,
2522 .driver_name = "ttyAMA",
2523 .dev_name = "ttyAMA",
2524 .major = SERIAL_AMBA_MAJOR,
2525 .minor = SERIAL_AMBA_MINOR,
2526 .nr = UART_NR,
2527 .cons = AMBA_CONSOLE,
2528 };
2529
pl011_probe_dt_alias(int index,struct device * dev)2530 static int pl011_probe_dt_alias(int index, struct device *dev)
2531 {
2532 struct device_node *np;
2533 static bool seen_dev_with_alias = false;
2534 static bool seen_dev_without_alias = false;
2535 int ret = index;
2536
2537 if (!IS_ENABLED(CONFIG_OF))
2538 return ret;
2539
2540 np = dev->of_node;
2541 if (!np)
2542 return ret;
2543
2544 ret = of_alias_get_id(np, "serial");
2545 if (ret < 0) {
2546 seen_dev_without_alias = true;
2547 ret = index;
2548 } else {
2549 seen_dev_with_alias = true;
2550 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2551 dev_warn(dev, "requested serial port %d not available.\n", ret);
2552 ret = index;
2553 }
2554 }
2555
2556 if (seen_dev_with_alias && seen_dev_without_alias)
2557 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2558
2559 return ret;
2560 }
2561
2562 /* unregisters the driver also if no more ports are left */
pl011_unregister_port(struct uart_amba_port * uap)2563 static void pl011_unregister_port(struct uart_amba_port *uap)
2564 {
2565 int i;
2566 bool busy = false;
2567
2568 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2569 if (amba_ports[i] == uap)
2570 amba_ports[i] = NULL;
2571 else if (amba_ports[i])
2572 busy = true;
2573 }
2574 pl011_dma_remove(uap);
2575 if (!busy)
2576 uart_unregister_driver(&amba_reg);
2577 }
2578
pl011_find_free_port(void)2579 static int pl011_find_free_port(void)
2580 {
2581 int i;
2582
2583 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2584 if (amba_ports[i] == NULL)
2585 return i;
2586
2587 return -EBUSY;
2588 }
2589
pl011_setup_port(struct device * dev,struct uart_amba_port * uap,struct resource * mmiobase,int index)2590 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2591 struct resource *mmiobase, int index)
2592 {
2593 void __iomem *base;
2594
2595 base = devm_ioremap_resource(dev, mmiobase);
2596 if (IS_ERR(base))
2597 return PTR_ERR(base);
2598
2599 index = pl011_probe_dt_alias(index, dev);
2600
2601 uap->old_cr = 0;
2602 uap->port.dev = dev;
2603 uap->port.mapbase = mmiobase->start;
2604 uap->port.membase = base;
2605 uap->port.fifosize = uap->fifosize;
2606 uap->port.flags = UPF_BOOT_AUTOCONF;
2607 uap->port.line = index;
2608
2609 amba_ports[index] = uap;
2610
2611 return 0;
2612 }
2613
pl011_register_port(struct uart_amba_port * uap)2614 static int pl011_register_port(struct uart_amba_port *uap)
2615 {
2616 int ret;
2617
2618 /* Ensure interrupts from this UART are masked and cleared */
2619 pl011_write(0, uap, REG_IMSC);
2620 pl011_write(0xffff, uap, REG_ICR);
2621
2622 if (!amba_reg.state) {
2623 ret = uart_register_driver(&amba_reg);
2624 if (ret < 0) {
2625 dev_err(uap->port.dev,
2626 "Failed to register AMBA-PL011 driver\n");
2627 return ret;
2628 }
2629 }
2630
2631 ret = uart_add_one_port(&amba_reg, &uap->port);
2632 if (ret)
2633 pl011_unregister_port(uap);
2634
2635 return ret;
2636 }
2637
pl011_probe(struct amba_device * dev,const struct amba_id * id)2638 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2639 {
2640 struct uart_amba_port *uap;
2641 struct vendor_data *vendor = id->data;
2642 int portnr, ret;
2643
2644 portnr = pl011_find_free_port();
2645 if (portnr < 0)
2646 return portnr;
2647
2648 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2649 GFP_KERNEL);
2650 if (!uap)
2651 return -ENOMEM;
2652
2653 uap->clk = devm_clk_get(&dev->dev, NULL);
2654 if (IS_ERR(uap->clk))
2655 return PTR_ERR(uap->clk);
2656
2657 uap->reg_offset = vendor->reg_offset;
2658 uap->vendor = vendor;
2659 uap->fifosize = vendor->get_fifosize(dev);
2660 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2661 uap->port.irq = dev->irq[0];
2662 uap->port.ops = &amba_pl011_pops;
2663
2664 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2665
2666 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2667 if (ret)
2668 return ret;
2669
2670 amba_set_drvdata(dev, uap);
2671
2672 return pl011_register_port(uap);
2673 }
2674
pl011_remove(struct amba_device * dev)2675 static int pl011_remove(struct amba_device *dev)
2676 {
2677 struct uart_amba_port *uap = amba_get_drvdata(dev);
2678
2679 uart_remove_one_port(&amba_reg, &uap->port);
2680 pl011_unregister_port(uap);
2681 return 0;
2682 }
2683
2684 #ifdef CONFIG_PM_SLEEP
pl011_suspend(struct device * dev)2685 static int pl011_suspend(struct device *dev)
2686 {
2687 struct uart_amba_port *uap = dev_get_drvdata(dev);
2688
2689 if (!uap)
2690 return -EINVAL;
2691
2692 return uart_suspend_port(&amba_reg, &uap->port);
2693 }
2694
pl011_resume(struct device * dev)2695 static int pl011_resume(struct device *dev)
2696 {
2697 struct uart_amba_port *uap = dev_get_drvdata(dev);
2698
2699 if (!uap)
2700 return -EINVAL;
2701
2702 return uart_resume_port(&amba_reg, &uap->port);
2703 }
2704 #endif
2705
2706 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2707
sbsa_uart_probe(struct platform_device * pdev)2708 static int sbsa_uart_probe(struct platform_device *pdev)
2709 {
2710 struct uart_amba_port *uap;
2711 struct resource *r;
2712 int portnr, ret;
2713 int baudrate;
2714
2715 /*
2716 * Check the mandatory baud rate parameter in the DT node early
2717 * so that we can easily exit with the error.
2718 */
2719 if (pdev->dev.of_node) {
2720 struct device_node *np = pdev->dev.of_node;
2721
2722 ret = of_property_read_u32(np, "current-speed", &baudrate);
2723 if (ret)
2724 return ret;
2725 } else {
2726 baudrate = 115200;
2727 }
2728
2729 portnr = pl011_find_free_port();
2730 if (portnr < 0)
2731 return portnr;
2732
2733 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2734 GFP_KERNEL);
2735 if (!uap)
2736 return -ENOMEM;
2737
2738 ret = platform_get_irq(pdev, 0);
2739 if (ret < 0) {
2740 if (ret != -EPROBE_DEFER)
2741 dev_err(&pdev->dev, "cannot obtain irq\n");
2742 return ret;
2743 }
2744 uap->port.irq = ret;
2745
2746 #ifdef CONFIG_ACPI_SPCR_TABLE
2747 if (qdf2400_e44_present) {
2748 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n");
2749 uap->vendor = &vendor_qdt_qdf2400_e44;
2750 } else
2751 #endif
2752 uap->vendor = &vendor_sbsa;
2753
2754 uap->reg_offset = uap->vendor->reg_offset;
2755 uap->fifosize = 32;
2756 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2757 uap->port.ops = &sbsa_uart_pops;
2758 uap->fixed_baud = baudrate;
2759
2760 snprintf(uap->type, sizeof(uap->type), "SBSA");
2761
2762 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2763
2764 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2765 if (ret)
2766 return ret;
2767
2768 platform_set_drvdata(pdev, uap);
2769
2770 return pl011_register_port(uap);
2771 }
2772
sbsa_uart_remove(struct platform_device * pdev)2773 static int sbsa_uart_remove(struct platform_device *pdev)
2774 {
2775 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2776
2777 uart_remove_one_port(&amba_reg, &uap->port);
2778 pl011_unregister_port(uap);
2779 return 0;
2780 }
2781
2782 static const struct of_device_id sbsa_uart_of_match[] = {
2783 { .compatible = "arm,sbsa-uart", },
2784 {},
2785 };
2786 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2787
2788 static const struct acpi_device_id sbsa_uart_acpi_match[] = {
2789 { "ARMH0011", 0 },
2790 {},
2791 };
2792 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2793
2794 static struct platform_driver arm_sbsa_uart_platform_driver = {
2795 .probe = sbsa_uart_probe,
2796 .remove = sbsa_uart_remove,
2797 .driver = {
2798 .name = "sbsa-uart",
2799 .of_match_table = of_match_ptr(sbsa_uart_of_match),
2800 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
2801 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2802 },
2803 };
2804
2805 static const struct amba_id pl011_ids[] = {
2806 {
2807 .id = 0x00041011,
2808 .mask = 0x000fffff,
2809 .data = &vendor_arm,
2810 },
2811 {
2812 .id = 0x00380802,
2813 .mask = 0x00ffffff,
2814 .data = &vendor_st,
2815 },
2816 {
2817 .id = AMBA_LINUX_ID(0x00, 0x1, 0xffe),
2818 .mask = 0x00ffffff,
2819 .data = &vendor_zte,
2820 },
2821 { 0, 0 },
2822 };
2823
2824 MODULE_DEVICE_TABLE(amba, pl011_ids);
2825
2826 static struct amba_driver pl011_driver = {
2827 .drv = {
2828 .name = "uart-pl011",
2829 .pm = &pl011_dev_pm_ops,
2830 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2831 },
2832 .id_table = pl011_ids,
2833 .probe = pl011_probe,
2834 .remove = pl011_remove,
2835 };
2836
pl011_init(void)2837 static int __init pl011_init(void)
2838 {
2839 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2840
2841 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
2842 pr_warn("could not register SBSA UART platform driver\n");
2843 return amba_driver_register(&pl011_driver);
2844 }
2845
pl011_exit(void)2846 static void __exit pl011_exit(void)
2847 {
2848 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
2849 amba_driver_unregister(&pl011_driver);
2850 }
2851
2852 /*
2853 * While this can be a module, if builtin it's most likely the console
2854 * So let's leave module_exit but move module_init to an earlier place
2855 */
2856 arch_initcall(pl011_init);
2857 module_exit(pl011_exit);
2858
2859 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2860 MODULE_DESCRIPTION("ARM AMBA serial port driver");
2861 MODULE_LICENSE("GPL");
2862