1 /*
2 * Driver for Atmel AT91 Serial ports
3 * Copyright (C) 2003 Rick Bronson
4 *
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * DMA support added by Chip Coldwell.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25 #include <linux/tty.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
29 #include <linux/serial.h>
30 #include <linux/clk.h>
31 #include <linux/console.h>
32 #include <linux/sysrq.h>
33 #include <linux/tty_flip.h>
34 #include <linux/platform_device.h>
35 #include <linux/of.h>
36 #include <linux/of_device.h>
37 #include <linux/of_gpio.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmaengine.h>
40 #include <linux/atmel_pdc.h>
41 #include <linux/uaccess.h>
42 #include <linux/platform_data/atmel.h>
43 #include <linux/timer.h>
44 #include <linux/gpio.h>
45 #include <linux/gpio/consumer.h>
46 #include <linux/err.h>
47 #include <linux/irq.h>
48 #include <linux/suspend.h>
49 #include <linux/mm.h>
50
51 #include <asm/io.h>
52 #include <asm/ioctls.h>
53
54 #define PDC_BUFFER_SIZE 512
55 /* Revisit: We should calculate this based on the actual port settings */
56 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
57
58 /* The minium number of data FIFOs should be able to contain */
59 #define ATMEL_MIN_FIFO_SIZE 8
60 /*
61 * These two offsets are substracted from the RX FIFO size to define the RTS
62 * high and low thresholds
63 */
64 #define ATMEL_RTS_HIGH_OFFSET 16
65 #define ATMEL_RTS_LOW_OFFSET 20
66
67 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
68 #define SUPPORT_SYSRQ
69 #endif
70
71 #include <linux/serial_core.h>
72
73 #include "serial_mctrl_gpio.h"
74 #include "atmel_serial.h"
75
76 static void atmel_start_rx(struct uart_port *port);
77 static void atmel_stop_rx(struct uart_port *port);
78
79 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
80
81 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
82 * should coexist with the 8250 driver, such as if we have an external 16C550
83 * UART. */
84 #define SERIAL_ATMEL_MAJOR 204
85 #define MINOR_START 154
86 #define ATMEL_DEVICENAME "ttyAT"
87
88 #else
89
90 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
91 * name, but it is legally reserved for the 8250 driver. */
92 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
93 #define MINOR_START 64
94 #define ATMEL_DEVICENAME "ttyS"
95
96 #endif
97
98 #define ATMEL_ISR_PASS_LIMIT 256
99
100 struct atmel_dma_buffer {
101 unsigned char *buf;
102 dma_addr_t dma_addr;
103 unsigned int dma_size;
104 unsigned int ofs;
105 };
106
107 struct atmel_uart_char {
108 u16 status;
109 u16 ch;
110 };
111
112 /*
113 * Be careful, the real size of the ring buffer is
114 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
115 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
116 * DMA mode.
117 */
118 #define ATMEL_SERIAL_RINGSIZE 1024
119
120 /*
121 * at91: 6 USARTs and one DBGU port (SAM9260)
122 * samx7: 3 USARTs and 5 UARTs
123 */
124 #define ATMEL_MAX_UART 8
125
126 /*
127 * We wrap our port structure around the generic uart_port.
128 */
129 struct atmel_uart_port {
130 struct uart_port uart; /* uart */
131 struct clk *clk; /* uart clock */
132 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
133 u32 backup_imr; /* IMR saved during suspend */
134 int break_active; /* break being received */
135
136 bool use_dma_rx; /* enable DMA receiver */
137 bool use_pdc_rx; /* enable PDC receiver */
138 short pdc_rx_idx; /* current PDC RX buffer */
139 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
140
141 bool use_dma_tx; /* enable DMA transmitter */
142 bool use_pdc_tx; /* enable PDC transmitter */
143 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
144
145 spinlock_t lock_tx; /* port lock */
146 spinlock_t lock_rx; /* port lock */
147 struct dma_chan *chan_tx;
148 struct dma_chan *chan_rx;
149 struct dma_async_tx_descriptor *desc_tx;
150 struct dma_async_tx_descriptor *desc_rx;
151 dma_cookie_t cookie_tx;
152 dma_cookie_t cookie_rx;
153 struct scatterlist sg_tx;
154 struct scatterlist sg_rx;
155 struct tasklet_struct tasklet_rx;
156 struct tasklet_struct tasklet_tx;
157 atomic_t tasklet_shutdown;
158 unsigned int irq_status_prev;
159 unsigned int tx_len;
160
161 struct circ_buf rx_ring;
162
163 struct mctrl_gpios *gpios;
164 unsigned int tx_done_mask;
165 u32 fifo_size;
166 u32 rts_high;
167 u32 rts_low;
168 bool ms_irq_enabled;
169 u32 rtor; /* address of receiver timeout register if it exists */
170 bool has_frac_baudrate;
171 bool has_hw_timer;
172 struct timer_list uart_timer;
173
174 bool suspended;
175 unsigned int pending;
176 unsigned int pending_status;
177 spinlock_t lock_suspended;
178
179 bool hd_start_rx; /* can start RX during half-duplex operation */
180
181 #ifdef CONFIG_PM
182 struct {
183 u32 cr;
184 u32 mr;
185 u32 imr;
186 u32 brgr;
187 u32 rtor;
188 u32 ttgr;
189 u32 fmr;
190 u32 fimr;
191 } cache;
192 #endif
193
194 int (*prepare_rx)(struct uart_port *port);
195 int (*prepare_tx)(struct uart_port *port);
196 void (*schedule_rx)(struct uart_port *port);
197 void (*schedule_tx)(struct uart_port *port);
198 void (*release_rx)(struct uart_port *port);
199 void (*release_tx)(struct uart_port *port);
200 };
201
202 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
203 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
204
205 #ifdef SUPPORT_SYSRQ
206 static struct console atmel_console;
207 #endif
208
209 #if defined(CONFIG_OF)
210 static const struct of_device_id atmel_serial_dt_ids[] = {
211 { .compatible = "atmel,at91rm9200-usart" },
212 { .compatible = "atmel,at91sam9260-usart" },
213 { /* sentinel */ }
214 };
215 #endif
216
217 static inline struct atmel_uart_port *
to_atmel_uart_port(struct uart_port * uart)218 to_atmel_uart_port(struct uart_port *uart)
219 {
220 return container_of(uart, struct atmel_uart_port, uart);
221 }
222
atmel_uart_readl(struct uart_port * port,u32 reg)223 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
224 {
225 return __raw_readl(port->membase + reg);
226 }
227
atmel_uart_writel(struct uart_port * port,u32 reg,u32 value)228 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
229 {
230 __raw_writel(value, port->membase + reg);
231 }
232
atmel_uart_read_char(struct uart_port * port)233 static inline u8 atmel_uart_read_char(struct uart_port *port)
234 {
235 return __raw_readb(port->membase + ATMEL_US_RHR);
236 }
237
atmel_uart_write_char(struct uart_port * port,u8 value)238 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
239 {
240 __raw_writeb(value, port->membase + ATMEL_US_THR);
241 }
242
atmel_uart_is_half_duplex(struct uart_port * port)243 static inline int atmel_uart_is_half_duplex(struct uart_port *port)
244 {
245 return (port->rs485.flags & SER_RS485_ENABLED) &&
246 !(port->rs485.flags & SER_RS485_RX_DURING_TX);
247 }
248
249 #ifdef CONFIG_SERIAL_ATMEL_PDC
atmel_use_pdc_rx(struct uart_port * port)250 static bool atmel_use_pdc_rx(struct uart_port *port)
251 {
252 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
253
254 return atmel_port->use_pdc_rx;
255 }
256
atmel_use_pdc_tx(struct uart_port * port)257 static bool atmel_use_pdc_tx(struct uart_port *port)
258 {
259 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
260
261 return atmel_port->use_pdc_tx;
262 }
263 #else
atmel_use_pdc_rx(struct uart_port * port)264 static bool atmel_use_pdc_rx(struct uart_port *port)
265 {
266 return false;
267 }
268
atmel_use_pdc_tx(struct uart_port * port)269 static bool atmel_use_pdc_tx(struct uart_port *port)
270 {
271 return false;
272 }
273 #endif
274
atmel_use_dma_tx(struct uart_port * port)275 static bool atmel_use_dma_tx(struct uart_port *port)
276 {
277 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
278
279 return atmel_port->use_dma_tx;
280 }
281
atmel_use_dma_rx(struct uart_port * port)282 static bool atmel_use_dma_rx(struct uart_port *port)
283 {
284 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
285
286 return atmel_port->use_dma_rx;
287 }
288
atmel_use_fifo(struct uart_port * port)289 static bool atmel_use_fifo(struct uart_port *port)
290 {
291 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
292
293 return atmel_port->fifo_size;
294 }
295
atmel_tasklet_schedule(struct atmel_uart_port * atmel_port,struct tasklet_struct * t)296 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
297 struct tasklet_struct *t)
298 {
299 if (!atomic_read(&atmel_port->tasklet_shutdown))
300 tasklet_schedule(t);
301 }
302
atmel_get_lines_status(struct uart_port * port)303 static unsigned int atmel_get_lines_status(struct uart_port *port)
304 {
305 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
306 unsigned int status, ret = 0;
307
308 status = atmel_uart_readl(port, ATMEL_US_CSR);
309
310 mctrl_gpio_get(atmel_port->gpios, &ret);
311
312 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
313 UART_GPIO_CTS))) {
314 if (ret & TIOCM_CTS)
315 status &= ~ATMEL_US_CTS;
316 else
317 status |= ATMEL_US_CTS;
318 }
319
320 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
321 UART_GPIO_DSR))) {
322 if (ret & TIOCM_DSR)
323 status &= ~ATMEL_US_DSR;
324 else
325 status |= ATMEL_US_DSR;
326 }
327
328 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
329 UART_GPIO_RI))) {
330 if (ret & TIOCM_RI)
331 status &= ~ATMEL_US_RI;
332 else
333 status |= ATMEL_US_RI;
334 }
335
336 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
337 UART_GPIO_DCD))) {
338 if (ret & TIOCM_CD)
339 status &= ~ATMEL_US_DCD;
340 else
341 status |= ATMEL_US_DCD;
342 }
343
344 return status;
345 }
346
347 /* Enable or disable the rs485 support */
atmel_config_rs485(struct uart_port * port,struct serial_rs485 * rs485conf)348 static int atmel_config_rs485(struct uart_port *port,
349 struct serial_rs485 *rs485conf)
350 {
351 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
352 unsigned int mode;
353
354 /* Disable interrupts */
355 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
356
357 mode = atmel_uart_readl(port, ATMEL_US_MR);
358
359 /* Resetting serial mode to RS232 (0x0) */
360 mode &= ~ATMEL_US_USMODE;
361
362 port->rs485 = *rs485conf;
363
364 if (rs485conf->flags & SER_RS485_ENABLED) {
365 dev_dbg(port->dev, "Setting UART to RS485\n");
366 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
367 atmel_uart_writel(port, ATMEL_US_TTGR,
368 rs485conf->delay_rts_after_send);
369 mode |= ATMEL_US_USMODE_RS485;
370 } else {
371 dev_dbg(port->dev, "Setting UART to RS232\n");
372 if (atmel_use_pdc_tx(port))
373 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
374 ATMEL_US_TXBUFE;
375 else
376 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
377 }
378 atmel_uart_writel(port, ATMEL_US_MR, mode);
379
380 /* Enable interrupts */
381 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
382
383 return 0;
384 }
385
386 /*
387 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
388 */
atmel_tx_empty(struct uart_port * port)389 static u_int atmel_tx_empty(struct uart_port *port)
390 {
391 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
392 TIOCSER_TEMT :
393 0;
394 }
395
396 /*
397 * Set state of the modem control output lines
398 */
atmel_set_mctrl(struct uart_port * port,u_int mctrl)399 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
400 {
401 unsigned int control = 0;
402 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
403 unsigned int rts_paused, rts_ready;
404 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
405
406 /* override mode to RS485 if needed, otherwise keep the current mode */
407 if (port->rs485.flags & SER_RS485_ENABLED) {
408 atmel_uart_writel(port, ATMEL_US_TTGR,
409 port->rs485.delay_rts_after_send);
410 mode &= ~ATMEL_US_USMODE;
411 mode |= ATMEL_US_USMODE_RS485;
412 }
413
414 /* set the RTS line state according to the mode */
415 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
416 /* force RTS line to high level */
417 rts_paused = ATMEL_US_RTSEN;
418
419 /* give the control of the RTS line back to the hardware */
420 rts_ready = ATMEL_US_RTSDIS;
421 } else {
422 /* force RTS line to high level */
423 rts_paused = ATMEL_US_RTSDIS;
424
425 /* force RTS line to low level */
426 rts_ready = ATMEL_US_RTSEN;
427 }
428
429 if (mctrl & TIOCM_RTS)
430 control |= rts_ready;
431 else
432 control |= rts_paused;
433
434 if (mctrl & TIOCM_DTR)
435 control |= ATMEL_US_DTREN;
436 else
437 control |= ATMEL_US_DTRDIS;
438
439 atmel_uart_writel(port, ATMEL_US_CR, control);
440
441 mctrl_gpio_set(atmel_port->gpios, mctrl);
442
443 /* Local loopback mode? */
444 mode &= ~ATMEL_US_CHMODE;
445 if (mctrl & TIOCM_LOOP)
446 mode |= ATMEL_US_CHMODE_LOC_LOOP;
447 else
448 mode |= ATMEL_US_CHMODE_NORMAL;
449
450 atmel_uart_writel(port, ATMEL_US_MR, mode);
451 }
452
453 /*
454 * Get state of the modem control input lines
455 */
atmel_get_mctrl(struct uart_port * port)456 static u_int atmel_get_mctrl(struct uart_port *port)
457 {
458 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
459 unsigned int ret = 0, status;
460
461 status = atmel_uart_readl(port, ATMEL_US_CSR);
462
463 /*
464 * The control signals are active low.
465 */
466 if (!(status & ATMEL_US_DCD))
467 ret |= TIOCM_CD;
468 if (!(status & ATMEL_US_CTS))
469 ret |= TIOCM_CTS;
470 if (!(status & ATMEL_US_DSR))
471 ret |= TIOCM_DSR;
472 if (!(status & ATMEL_US_RI))
473 ret |= TIOCM_RI;
474
475 return mctrl_gpio_get(atmel_port->gpios, &ret);
476 }
477
478 /*
479 * Stop transmitting.
480 */
atmel_stop_tx(struct uart_port * port)481 static void atmel_stop_tx(struct uart_port *port)
482 {
483 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
484
485 if (atmel_use_pdc_tx(port)) {
486 /* disable PDC transmit */
487 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
488 }
489
490 /*
491 * Disable the transmitter.
492 * This is mandatory when DMA is used, otherwise the DMA buffer
493 * is fully transmitted.
494 */
495 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
496
497 /* Disable interrupts */
498 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
499
500 if (atmel_uart_is_half_duplex(port))
501 if (!atomic_read(&atmel_port->tasklet_shutdown))
502 atmel_start_rx(port);
503
504 }
505
506 /*
507 * Start transmitting.
508 */
atmel_start_tx(struct uart_port * port)509 static void atmel_start_tx(struct uart_port *port)
510 {
511 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
512
513 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
514 & ATMEL_PDC_TXTEN))
515 /* The transmitter is already running. Yes, we
516 really need this.*/
517 return;
518
519 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
520 if (atmel_uart_is_half_duplex(port))
521 atmel_stop_rx(port);
522
523 if (atmel_use_pdc_tx(port))
524 /* re-enable PDC transmit */
525 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
526
527 /* Enable interrupts */
528 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
529
530 /* re-enable the transmitter */
531 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
532 }
533
534 /*
535 * start receiving - port is in process of being opened.
536 */
atmel_start_rx(struct uart_port * port)537 static void atmel_start_rx(struct uart_port *port)
538 {
539 /* reset status and receiver */
540 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
541
542 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
543
544 if (atmel_use_pdc_rx(port)) {
545 /* enable PDC controller */
546 atmel_uart_writel(port, ATMEL_US_IER,
547 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
548 port->read_status_mask);
549 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
550 } else {
551 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
552 }
553 }
554
555 /*
556 * Stop receiving - port is in process of being closed.
557 */
atmel_stop_rx(struct uart_port * port)558 static void atmel_stop_rx(struct uart_port *port)
559 {
560 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
561
562 if (atmel_use_pdc_rx(port)) {
563 /* disable PDC receive */
564 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
565 atmel_uart_writel(port, ATMEL_US_IDR,
566 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
567 port->read_status_mask);
568 } else {
569 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
570 }
571 }
572
573 /*
574 * Enable modem status interrupts
575 */
atmel_enable_ms(struct uart_port * port)576 static void atmel_enable_ms(struct uart_port *port)
577 {
578 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
579 uint32_t ier = 0;
580
581 /*
582 * Interrupt should not be enabled twice
583 */
584 if (atmel_port->ms_irq_enabled)
585 return;
586
587 atmel_port->ms_irq_enabled = true;
588
589 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
590 ier |= ATMEL_US_CTSIC;
591
592 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
593 ier |= ATMEL_US_DSRIC;
594
595 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
596 ier |= ATMEL_US_RIIC;
597
598 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
599 ier |= ATMEL_US_DCDIC;
600
601 atmel_uart_writel(port, ATMEL_US_IER, ier);
602
603 mctrl_gpio_enable_ms(atmel_port->gpios);
604 }
605
606 /*
607 * Disable modem status interrupts
608 */
atmel_disable_ms(struct uart_port * port)609 static void atmel_disable_ms(struct uart_port *port)
610 {
611 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
612 uint32_t idr = 0;
613
614 /*
615 * Interrupt should not be disabled twice
616 */
617 if (!atmel_port->ms_irq_enabled)
618 return;
619
620 atmel_port->ms_irq_enabled = false;
621
622 mctrl_gpio_disable_ms(atmel_port->gpios);
623
624 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
625 idr |= ATMEL_US_CTSIC;
626
627 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
628 idr |= ATMEL_US_DSRIC;
629
630 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
631 idr |= ATMEL_US_RIIC;
632
633 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
634 idr |= ATMEL_US_DCDIC;
635
636 atmel_uart_writel(port, ATMEL_US_IDR, idr);
637 }
638
639 /*
640 * Control the transmission of a break signal
641 */
atmel_break_ctl(struct uart_port * port,int break_state)642 static void atmel_break_ctl(struct uart_port *port, int break_state)
643 {
644 if (break_state != 0)
645 /* start break */
646 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
647 else
648 /* stop break */
649 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
650 }
651
652 /*
653 * Stores the incoming character in the ring buffer
654 */
655 static void
atmel_buffer_rx_char(struct uart_port * port,unsigned int status,unsigned int ch)656 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
657 unsigned int ch)
658 {
659 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
660 struct circ_buf *ring = &atmel_port->rx_ring;
661 struct atmel_uart_char *c;
662
663 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
664 /* Buffer overflow, ignore char */
665 return;
666
667 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
668 c->status = status;
669 c->ch = ch;
670
671 /* Make sure the character is stored before we update head. */
672 smp_wmb();
673
674 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
675 }
676
677 /*
678 * Deal with parity, framing and overrun errors.
679 */
atmel_pdc_rxerr(struct uart_port * port,unsigned int status)680 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
681 {
682 /* clear error */
683 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
684
685 if (status & ATMEL_US_RXBRK) {
686 /* ignore side-effect */
687 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
688 port->icount.brk++;
689 }
690 if (status & ATMEL_US_PARE)
691 port->icount.parity++;
692 if (status & ATMEL_US_FRAME)
693 port->icount.frame++;
694 if (status & ATMEL_US_OVRE)
695 port->icount.overrun++;
696 }
697
698 /*
699 * Characters received (called from interrupt handler)
700 */
atmel_rx_chars(struct uart_port * port)701 static void atmel_rx_chars(struct uart_port *port)
702 {
703 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
704 unsigned int status, ch;
705
706 status = atmel_uart_readl(port, ATMEL_US_CSR);
707 while (status & ATMEL_US_RXRDY) {
708 ch = atmel_uart_read_char(port);
709
710 /*
711 * note that the error handling code is
712 * out of the main execution path
713 */
714 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
715 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
716 || atmel_port->break_active)) {
717
718 /* clear error */
719 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
720
721 if (status & ATMEL_US_RXBRK
722 && !atmel_port->break_active) {
723 atmel_port->break_active = 1;
724 atmel_uart_writel(port, ATMEL_US_IER,
725 ATMEL_US_RXBRK);
726 } else {
727 /*
728 * This is either the end-of-break
729 * condition or we've received at
730 * least one character without RXBRK
731 * being set. In both cases, the next
732 * RXBRK will indicate start-of-break.
733 */
734 atmel_uart_writel(port, ATMEL_US_IDR,
735 ATMEL_US_RXBRK);
736 status &= ~ATMEL_US_RXBRK;
737 atmel_port->break_active = 0;
738 }
739 }
740
741 atmel_buffer_rx_char(port, status, ch);
742 status = atmel_uart_readl(port, ATMEL_US_CSR);
743 }
744
745 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
746 }
747
748 /*
749 * Transmit characters (called from tasklet with TXRDY interrupt
750 * disabled)
751 */
atmel_tx_chars(struct uart_port * port)752 static void atmel_tx_chars(struct uart_port *port)
753 {
754 struct circ_buf *xmit = &port->state->xmit;
755 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
756
757 if (port->x_char &&
758 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
759 atmel_uart_write_char(port, port->x_char);
760 port->icount.tx++;
761 port->x_char = 0;
762 }
763 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
764 return;
765
766 while (atmel_uart_readl(port, ATMEL_US_CSR) &
767 atmel_port->tx_done_mask) {
768 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
769 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
770 port->icount.tx++;
771 if (uart_circ_empty(xmit))
772 break;
773 }
774
775 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
776 uart_write_wakeup(port);
777
778 if (!uart_circ_empty(xmit))
779 /* Enable interrupts */
780 atmel_uart_writel(port, ATMEL_US_IER,
781 atmel_port->tx_done_mask);
782 }
783
atmel_complete_tx_dma(void * arg)784 static void atmel_complete_tx_dma(void *arg)
785 {
786 struct atmel_uart_port *atmel_port = arg;
787 struct uart_port *port = &atmel_port->uart;
788 struct circ_buf *xmit = &port->state->xmit;
789 struct dma_chan *chan = atmel_port->chan_tx;
790 unsigned long flags;
791
792 spin_lock_irqsave(&port->lock, flags);
793
794 if (chan)
795 dmaengine_terminate_all(chan);
796 xmit->tail += atmel_port->tx_len;
797 xmit->tail &= UART_XMIT_SIZE - 1;
798
799 port->icount.tx += atmel_port->tx_len;
800
801 spin_lock_irq(&atmel_port->lock_tx);
802 async_tx_ack(atmel_port->desc_tx);
803 atmel_port->cookie_tx = -EINVAL;
804 atmel_port->desc_tx = NULL;
805 spin_unlock_irq(&atmel_port->lock_tx);
806
807 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
808 uart_write_wakeup(port);
809
810 /*
811 * xmit is a circular buffer so, if we have just send data from
812 * xmit->tail to the end of xmit->buf, now we have to transmit the
813 * remaining data from the beginning of xmit->buf to xmit->head.
814 */
815 if (!uart_circ_empty(xmit))
816 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
817 else if (atmel_uart_is_half_duplex(port)) {
818 /*
819 * DMA done, re-enable TXEMPTY and signal that we can stop
820 * TX and start RX for RS485
821 */
822 atmel_port->hd_start_rx = true;
823 atmel_uart_writel(port, ATMEL_US_IER,
824 atmel_port->tx_done_mask);
825 }
826
827 spin_unlock_irqrestore(&port->lock, flags);
828 }
829
atmel_release_tx_dma(struct uart_port * port)830 static void atmel_release_tx_dma(struct uart_port *port)
831 {
832 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
833 struct dma_chan *chan = atmel_port->chan_tx;
834
835 if (chan) {
836 dmaengine_terminate_all(chan);
837 dma_release_channel(chan);
838 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
839 DMA_TO_DEVICE);
840 }
841
842 atmel_port->desc_tx = NULL;
843 atmel_port->chan_tx = NULL;
844 atmel_port->cookie_tx = -EINVAL;
845 }
846
847 /*
848 * Called from tasklet with TXRDY interrupt is disabled.
849 */
atmel_tx_dma(struct uart_port * port)850 static void atmel_tx_dma(struct uart_port *port)
851 {
852 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
853 struct circ_buf *xmit = &port->state->xmit;
854 struct dma_chan *chan = atmel_port->chan_tx;
855 struct dma_async_tx_descriptor *desc;
856 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
857 unsigned int tx_len, part1_len, part2_len, sg_len;
858 dma_addr_t phys_addr;
859
860 /* Make sure we have an idle channel */
861 if (atmel_port->desc_tx != NULL)
862 return;
863
864 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
865 /*
866 * DMA is idle now.
867 * Port xmit buffer is already mapped,
868 * and it is one page... Just adjust
869 * offsets and lengths. Since it is a circular buffer,
870 * we have to transmit till the end, and then the rest.
871 * Take the port lock to get a
872 * consistent xmit buffer state.
873 */
874 tx_len = CIRC_CNT_TO_END(xmit->head,
875 xmit->tail,
876 UART_XMIT_SIZE);
877
878 if (atmel_port->fifo_size) {
879 /* multi data mode */
880 part1_len = (tx_len & ~0x3); /* DWORD access */
881 part2_len = (tx_len & 0x3); /* BYTE access */
882 } else {
883 /* single data (legacy) mode */
884 part1_len = 0;
885 part2_len = tx_len; /* BYTE access only */
886 }
887
888 sg_init_table(sgl, 2);
889 sg_len = 0;
890 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
891 if (part1_len) {
892 sg = &sgl[sg_len++];
893 sg_dma_address(sg) = phys_addr;
894 sg_dma_len(sg) = part1_len;
895
896 phys_addr += part1_len;
897 }
898
899 if (part2_len) {
900 sg = &sgl[sg_len++];
901 sg_dma_address(sg) = phys_addr;
902 sg_dma_len(sg) = part2_len;
903 }
904
905 /*
906 * save tx_len so atmel_complete_tx_dma() will increase
907 * xmit->tail correctly
908 */
909 atmel_port->tx_len = tx_len;
910
911 desc = dmaengine_prep_slave_sg(chan,
912 sgl,
913 sg_len,
914 DMA_MEM_TO_DEV,
915 DMA_PREP_INTERRUPT |
916 DMA_CTRL_ACK);
917 if (!desc) {
918 dev_err(port->dev, "Failed to send via dma!\n");
919 return;
920 }
921
922 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
923
924 atmel_port->desc_tx = desc;
925 desc->callback = atmel_complete_tx_dma;
926 desc->callback_param = atmel_port;
927 atmel_port->cookie_tx = dmaengine_submit(desc);
928 }
929
930 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
931 uart_write_wakeup(port);
932 }
933
atmel_prepare_tx_dma(struct uart_port * port)934 static int atmel_prepare_tx_dma(struct uart_port *port)
935 {
936 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
937 dma_cap_mask_t mask;
938 struct dma_slave_config config;
939 int ret, nent;
940
941 dma_cap_zero(mask);
942 dma_cap_set(DMA_SLAVE, mask);
943
944 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
945 if (atmel_port->chan_tx == NULL)
946 goto chan_err;
947 dev_info(port->dev, "using %s for tx DMA transfers\n",
948 dma_chan_name(atmel_port->chan_tx));
949
950 spin_lock_init(&atmel_port->lock_tx);
951 sg_init_table(&atmel_port->sg_tx, 1);
952 /* UART circular tx buffer is an aligned page. */
953 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
954 sg_set_page(&atmel_port->sg_tx,
955 virt_to_page(port->state->xmit.buf),
956 UART_XMIT_SIZE,
957 offset_in_page(port->state->xmit.buf));
958 nent = dma_map_sg(port->dev,
959 &atmel_port->sg_tx,
960 1,
961 DMA_TO_DEVICE);
962
963 if (!nent) {
964 dev_dbg(port->dev, "need to release resource of dma\n");
965 goto chan_err;
966 } else {
967 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
968 sg_dma_len(&atmel_port->sg_tx),
969 port->state->xmit.buf,
970 &sg_dma_address(&atmel_port->sg_tx));
971 }
972
973 /* Configure the slave DMA */
974 memset(&config, 0, sizeof(config));
975 config.direction = DMA_MEM_TO_DEV;
976 config.dst_addr_width = (atmel_port->fifo_size) ?
977 DMA_SLAVE_BUSWIDTH_4_BYTES :
978 DMA_SLAVE_BUSWIDTH_1_BYTE;
979 config.dst_addr = port->mapbase + ATMEL_US_THR;
980 config.dst_maxburst = 1;
981
982 ret = dmaengine_slave_config(atmel_port->chan_tx,
983 &config);
984 if (ret) {
985 dev_err(port->dev, "DMA tx slave configuration failed\n");
986 goto chan_err;
987 }
988
989 return 0;
990
991 chan_err:
992 dev_err(port->dev, "TX channel not available, switch to pio\n");
993 atmel_port->use_dma_tx = 0;
994 if (atmel_port->chan_tx)
995 atmel_release_tx_dma(port);
996 return -EINVAL;
997 }
998
atmel_complete_rx_dma(void * arg)999 static void atmel_complete_rx_dma(void *arg)
1000 {
1001 struct uart_port *port = arg;
1002 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1003
1004 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1005 }
1006
atmel_release_rx_dma(struct uart_port * port)1007 static void atmel_release_rx_dma(struct uart_port *port)
1008 {
1009 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1010 struct dma_chan *chan = atmel_port->chan_rx;
1011
1012 if (chan) {
1013 dmaengine_terminate_all(chan);
1014 dma_release_channel(chan);
1015 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1016 DMA_FROM_DEVICE);
1017 }
1018
1019 atmel_port->desc_rx = NULL;
1020 atmel_port->chan_rx = NULL;
1021 atmel_port->cookie_rx = -EINVAL;
1022 }
1023
atmel_rx_from_dma(struct uart_port * port)1024 static void atmel_rx_from_dma(struct uart_port *port)
1025 {
1026 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1027 struct tty_port *tport = &port->state->port;
1028 struct circ_buf *ring = &atmel_port->rx_ring;
1029 struct dma_chan *chan = atmel_port->chan_rx;
1030 struct dma_tx_state state;
1031 enum dma_status dmastat;
1032 size_t count;
1033
1034
1035 /* Reset the UART timeout early so that we don't miss one */
1036 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1037 dmastat = dmaengine_tx_status(chan,
1038 atmel_port->cookie_rx,
1039 &state);
1040 /* Restart a new tasklet if DMA status is error */
1041 if (dmastat == DMA_ERROR) {
1042 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1043 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1044 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1045 return;
1046 }
1047
1048 /* CPU claims ownership of RX DMA buffer */
1049 dma_sync_sg_for_cpu(port->dev,
1050 &atmel_port->sg_rx,
1051 1,
1052 DMA_FROM_DEVICE);
1053
1054 /*
1055 * ring->head points to the end of data already written by the DMA.
1056 * ring->tail points to the beginning of data to be read by the
1057 * framework.
1058 * The current transfer size should not be larger than the dma buffer
1059 * length.
1060 */
1061 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1062 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1063 /*
1064 * At this point ring->head may point to the first byte right after the
1065 * last byte of the dma buffer:
1066 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1067 *
1068 * However ring->tail must always points inside the dma buffer:
1069 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1070 *
1071 * Since we use a ring buffer, we have to handle the case
1072 * where head is lower than tail. In such a case, we first read from
1073 * tail to the end of the buffer then reset tail.
1074 */
1075 if (ring->head < ring->tail) {
1076 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1077
1078 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1079 ring->tail = 0;
1080 port->icount.rx += count;
1081 }
1082
1083 /* Finally we read data from tail to head */
1084 if (ring->tail < ring->head) {
1085 count = ring->head - ring->tail;
1086
1087 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1088 /* Wrap ring->head if needed */
1089 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1090 ring->head = 0;
1091 ring->tail = ring->head;
1092 port->icount.rx += count;
1093 }
1094
1095 /* USART retreives ownership of RX DMA buffer */
1096 dma_sync_sg_for_device(port->dev,
1097 &atmel_port->sg_rx,
1098 1,
1099 DMA_FROM_DEVICE);
1100
1101 /*
1102 * Drop the lock here since it might end up calling
1103 * uart_start(), which takes the lock.
1104 */
1105 spin_unlock(&port->lock);
1106 tty_flip_buffer_push(tport);
1107 spin_lock(&port->lock);
1108
1109 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1110 }
1111
atmel_prepare_rx_dma(struct uart_port * port)1112 static int atmel_prepare_rx_dma(struct uart_port *port)
1113 {
1114 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1115 struct dma_async_tx_descriptor *desc;
1116 dma_cap_mask_t mask;
1117 struct dma_slave_config config;
1118 struct circ_buf *ring;
1119 int ret, nent;
1120
1121 ring = &atmel_port->rx_ring;
1122
1123 dma_cap_zero(mask);
1124 dma_cap_set(DMA_CYCLIC, mask);
1125
1126 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1127 if (atmel_port->chan_rx == NULL)
1128 goto chan_err;
1129 dev_info(port->dev, "using %s for rx DMA transfers\n",
1130 dma_chan_name(atmel_port->chan_rx));
1131
1132 spin_lock_init(&atmel_port->lock_rx);
1133 sg_init_table(&atmel_port->sg_rx, 1);
1134 /* UART circular rx buffer is an aligned page. */
1135 BUG_ON(!PAGE_ALIGNED(ring->buf));
1136 sg_set_page(&atmel_port->sg_rx,
1137 virt_to_page(ring->buf),
1138 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1139 offset_in_page(ring->buf));
1140 nent = dma_map_sg(port->dev,
1141 &atmel_port->sg_rx,
1142 1,
1143 DMA_FROM_DEVICE);
1144
1145 if (!nent) {
1146 dev_dbg(port->dev, "need to release resource of dma\n");
1147 goto chan_err;
1148 } else {
1149 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1150 sg_dma_len(&atmel_port->sg_rx),
1151 ring->buf,
1152 &sg_dma_address(&atmel_port->sg_rx));
1153 }
1154
1155 /* Configure the slave DMA */
1156 memset(&config, 0, sizeof(config));
1157 config.direction = DMA_DEV_TO_MEM;
1158 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1159 config.src_addr = port->mapbase + ATMEL_US_RHR;
1160 config.src_maxburst = 1;
1161
1162 ret = dmaengine_slave_config(atmel_port->chan_rx,
1163 &config);
1164 if (ret) {
1165 dev_err(port->dev, "DMA rx slave configuration failed\n");
1166 goto chan_err;
1167 }
1168 /*
1169 * Prepare a cyclic dma transfer, assign 2 descriptors,
1170 * each one is half ring buffer size
1171 */
1172 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1173 sg_dma_address(&atmel_port->sg_rx),
1174 sg_dma_len(&atmel_port->sg_rx),
1175 sg_dma_len(&atmel_port->sg_rx)/2,
1176 DMA_DEV_TO_MEM,
1177 DMA_PREP_INTERRUPT);
1178 if (!desc) {
1179 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1180 goto chan_err;
1181 }
1182 desc->callback = atmel_complete_rx_dma;
1183 desc->callback_param = port;
1184 atmel_port->desc_rx = desc;
1185 atmel_port->cookie_rx = dmaengine_submit(desc);
1186
1187 return 0;
1188
1189 chan_err:
1190 dev_err(port->dev, "RX channel not available, switch to pio\n");
1191 atmel_port->use_dma_rx = 0;
1192 if (atmel_port->chan_rx)
1193 atmel_release_rx_dma(port);
1194 return -EINVAL;
1195 }
1196
atmel_uart_timer_callback(unsigned long data)1197 static void atmel_uart_timer_callback(unsigned long data)
1198 {
1199 struct uart_port *port = (void *)data;
1200 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1201
1202 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1203 tasklet_schedule(&atmel_port->tasklet_rx);
1204 mod_timer(&atmel_port->uart_timer,
1205 jiffies + uart_poll_timeout(port));
1206 }
1207 }
1208
1209 /*
1210 * receive interrupt handler.
1211 */
1212 static void
atmel_handle_receive(struct uart_port * port,unsigned int pending)1213 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1214 {
1215 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1216
1217 if (atmel_use_pdc_rx(port)) {
1218 /*
1219 * PDC receive. Just schedule the tasklet and let it
1220 * figure out the details.
1221 *
1222 * TODO: We're not handling error flags correctly at
1223 * the moment.
1224 */
1225 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1226 atmel_uart_writel(port, ATMEL_US_IDR,
1227 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1228 atmel_tasklet_schedule(atmel_port,
1229 &atmel_port->tasklet_rx);
1230 }
1231
1232 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1233 ATMEL_US_FRAME | ATMEL_US_PARE))
1234 atmel_pdc_rxerr(port, pending);
1235 }
1236
1237 if (atmel_use_dma_rx(port)) {
1238 if (pending & ATMEL_US_TIMEOUT) {
1239 atmel_uart_writel(port, ATMEL_US_IDR,
1240 ATMEL_US_TIMEOUT);
1241 atmel_tasklet_schedule(atmel_port,
1242 &atmel_port->tasklet_rx);
1243 }
1244 }
1245
1246 /* Interrupt receive */
1247 if (pending & ATMEL_US_RXRDY)
1248 atmel_rx_chars(port);
1249 else if (pending & ATMEL_US_RXBRK) {
1250 /*
1251 * End of break detected. If it came along with a
1252 * character, atmel_rx_chars will handle it.
1253 */
1254 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1255 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1256 atmel_port->break_active = 0;
1257 }
1258 }
1259
1260 /*
1261 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1262 */
1263 static void
atmel_handle_transmit(struct uart_port * port,unsigned int pending)1264 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1265 {
1266 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1267
1268 if (pending & atmel_port->tx_done_mask) {
1269 atmel_uart_writel(port, ATMEL_US_IDR,
1270 atmel_port->tx_done_mask);
1271
1272 /* Start RX if flag was set and FIFO is empty */
1273 if (atmel_port->hd_start_rx) {
1274 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1275 & ATMEL_US_TXEMPTY))
1276 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1277
1278 atmel_port->hd_start_rx = false;
1279 atmel_start_rx(port);
1280 }
1281
1282 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1283 }
1284 }
1285
1286 /*
1287 * status flags interrupt handler.
1288 */
1289 static void
atmel_handle_status(struct uart_port * port,unsigned int pending,unsigned int status)1290 atmel_handle_status(struct uart_port *port, unsigned int pending,
1291 unsigned int status)
1292 {
1293 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1294 unsigned int status_change;
1295
1296 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1297 | ATMEL_US_CTSIC)) {
1298 status_change = status ^ atmel_port->irq_status_prev;
1299 atmel_port->irq_status_prev = status;
1300
1301 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1302 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1303 /* TODO: All reads to CSR will clear these interrupts! */
1304 if (status_change & ATMEL_US_RI)
1305 port->icount.rng++;
1306 if (status_change & ATMEL_US_DSR)
1307 port->icount.dsr++;
1308 if (status_change & ATMEL_US_DCD)
1309 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1310 if (status_change & ATMEL_US_CTS)
1311 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1312
1313 wake_up_interruptible(&port->state->port.delta_msr_wait);
1314 }
1315 }
1316 }
1317
1318 /*
1319 * Interrupt handler
1320 */
atmel_interrupt(int irq,void * dev_id)1321 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1322 {
1323 struct uart_port *port = dev_id;
1324 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1325 unsigned int status, pending, mask, pass_counter = 0;
1326
1327 spin_lock(&atmel_port->lock_suspended);
1328
1329 do {
1330 status = atmel_get_lines_status(port);
1331 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1332 pending = status & mask;
1333 if (!pending)
1334 break;
1335
1336 if (atmel_port->suspended) {
1337 atmel_port->pending |= pending;
1338 atmel_port->pending_status = status;
1339 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1340 pm_system_wakeup();
1341 break;
1342 }
1343
1344 atmel_handle_receive(port, pending);
1345 atmel_handle_status(port, pending, status);
1346 atmel_handle_transmit(port, pending);
1347 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1348
1349 spin_unlock(&atmel_port->lock_suspended);
1350
1351 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1352 }
1353
atmel_release_tx_pdc(struct uart_port * port)1354 static void atmel_release_tx_pdc(struct uart_port *port)
1355 {
1356 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1357 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1358
1359 dma_unmap_single(port->dev,
1360 pdc->dma_addr,
1361 pdc->dma_size,
1362 DMA_TO_DEVICE);
1363 }
1364
1365 /*
1366 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1367 */
atmel_tx_pdc(struct uart_port * port)1368 static void atmel_tx_pdc(struct uart_port *port)
1369 {
1370 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1371 struct circ_buf *xmit = &port->state->xmit;
1372 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1373 int count;
1374
1375 /* nothing left to transmit? */
1376 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1377 return;
1378
1379 xmit->tail += pdc->ofs;
1380 xmit->tail &= UART_XMIT_SIZE - 1;
1381
1382 port->icount.tx += pdc->ofs;
1383 pdc->ofs = 0;
1384
1385 /* more to transmit - setup next transfer */
1386
1387 /* disable PDC transmit */
1388 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1389
1390 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1391 dma_sync_single_for_device(port->dev,
1392 pdc->dma_addr,
1393 pdc->dma_size,
1394 DMA_TO_DEVICE);
1395
1396 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1397 pdc->ofs = count;
1398
1399 atmel_uart_writel(port, ATMEL_PDC_TPR,
1400 pdc->dma_addr + xmit->tail);
1401 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1402 /* re-enable PDC transmit */
1403 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1404 /* Enable interrupts */
1405 atmel_uart_writel(port, ATMEL_US_IER,
1406 atmel_port->tx_done_mask);
1407 } else {
1408 if (atmel_uart_is_half_duplex(port)) {
1409 /* DMA done, stop TX, start RX for RS485 */
1410 atmel_start_rx(port);
1411 }
1412 }
1413
1414 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1415 uart_write_wakeup(port);
1416 }
1417
atmel_prepare_tx_pdc(struct uart_port * port)1418 static int atmel_prepare_tx_pdc(struct uart_port *port)
1419 {
1420 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1421 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1422 struct circ_buf *xmit = &port->state->xmit;
1423
1424 pdc->buf = xmit->buf;
1425 pdc->dma_addr = dma_map_single(port->dev,
1426 pdc->buf,
1427 UART_XMIT_SIZE,
1428 DMA_TO_DEVICE);
1429 pdc->dma_size = UART_XMIT_SIZE;
1430 pdc->ofs = 0;
1431
1432 return 0;
1433 }
1434
atmel_rx_from_ring(struct uart_port * port)1435 static void atmel_rx_from_ring(struct uart_port *port)
1436 {
1437 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1438 struct circ_buf *ring = &atmel_port->rx_ring;
1439 unsigned int flg;
1440 unsigned int status;
1441
1442 while (ring->head != ring->tail) {
1443 struct atmel_uart_char c;
1444
1445 /* Make sure c is loaded after head. */
1446 smp_rmb();
1447
1448 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1449
1450 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1451
1452 port->icount.rx++;
1453 status = c.status;
1454 flg = TTY_NORMAL;
1455
1456 /*
1457 * note that the error handling code is
1458 * out of the main execution path
1459 */
1460 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1461 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1462 if (status & ATMEL_US_RXBRK) {
1463 /* ignore side-effect */
1464 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1465
1466 port->icount.brk++;
1467 if (uart_handle_break(port))
1468 continue;
1469 }
1470 if (status & ATMEL_US_PARE)
1471 port->icount.parity++;
1472 if (status & ATMEL_US_FRAME)
1473 port->icount.frame++;
1474 if (status & ATMEL_US_OVRE)
1475 port->icount.overrun++;
1476
1477 status &= port->read_status_mask;
1478
1479 if (status & ATMEL_US_RXBRK)
1480 flg = TTY_BREAK;
1481 else if (status & ATMEL_US_PARE)
1482 flg = TTY_PARITY;
1483 else if (status & ATMEL_US_FRAME)
1484 flg = TTY_FRAME;
1485 }
1486
1487
1488 if (uart_handle_sysrq_char(port, c.ch))
1489 continue;
1490
1491 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1492 }
1493
1494 /*
1495 * Drop the lock here since it might end up calling
1496 * uart_start(), which takes the lock.
1497 */
1498 spin_unlock(&port->lock);
1499 tty_flip_buffer_push(&port->state->port);
1500 spin_lock(&port->lock);
1501 }
1502
atmel_release_rx_pdc(struct uart_port * port)1503 static void atmel_release_rx_pdc(struct uart_port *port)
1504 {
1505 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1506 int i;
1507
1508 for (i = 0; i < 2; i++) {
1509 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1510
1511 dma_unmap_single(port->dev,
1512 pdc->dma_addr,
1513 pdc->dma_size,
1514 DMA_FROM_DEVICE);
1515 kfree(pdc->buf);
1516 }
1517 }
1518
atmel_rx_from_pdc(struct uart_port * port)1519 static void atmel_rx_from_pdc(struct uart_port *port)
1520 {
1521 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1522 struct tty_port *tport = &port->state->port;
1523 struct atmel_dma_buffer *pdc;
1524 int rx_idx = atmel_port->pdc_rx_idx;
1525 unsigned int head;
1526 unsigned int tail;
1527 unsigned int count;
1528
1529 do {
1530 /* Reset the UART timeout early so that we don't miss one */
1531 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1532
1533 pdc = &atmel_port->pdc_rx[rx_idx];
1534 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1535 tail = pdc->ofs;
1536
1537 /* If the PDC has switched buffers, RPR won't contain
1538 * any address within the current buffer. Since head
1539 * is unsigned, we just need a one-way comparison to
1540 * find out.
1541 *
1542 * In this case, we just need to consume the entire
1543 * buffer and resubmit it for DMA. This will clear the
1544 * ENDRX bit as well, so that we can safely re-enable
1545 * all interrupts below.
1546 */
1547 head = min(head, pdc->dma_size);
1548
1549 if (likely(head != tail)) {
1550 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1551 pdc->dma_size, DMA_FROM_DEVICE);
1552
1553 /*
1554 * head will only wrap around when we recycle
1555 * the DMA buffer, and when that happens, we
1556 * explicitly set tail to 0. So head will
1557 * always be greater than tail.
1558 */
1559 count = head - tail;
1560
1561 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1562 count);
1563
1564 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1565 pdc->dma_size, DMA_FROM_DEVICE);
1566
1567 port->icount.rx += count;
1568 pdc->ofs = head;
1569 }
1570
1571 /*
1572 * If the current buffer is full, we need to check if
1573 * the next one contains any additional data.
1574 */
1575 if (head >= pdc->dma_size) {
1576 pdc->ofs = 0;
1577 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1578 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1579
1580 rx_idx = !rx_idx;
1581 atmel_port->pdc_rx_idx = rx_idx;
1582 }
1583 } while (head >= pdc->dma_size);
1584
1585 /*
1586 * Drop the lock here since it might end up calling
1587 * uart_start(), which takes the lock.
1588 */
1589 spin_unlock(&port->lock);
1590 tty_flip_buffer_push(tport);
1591 spin_lock(&port->lock);
1592
1593 atmel_uart_writel(port, ATMEL_US_IER,
1594 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1595 }
1596
atmel_prepare_rx_pdc(struct uart_port * port)1597 static int atmel_prepare_rx_pdc(struct uart_port *port)
1598 {
1599 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1600 int i;
1601
1602 for (i = 0; i < 2; i++) {
1603 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1604
1605 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1606 if (pdc->buf == NULL) {
1607 if (i != 0) {
1608 dma_unmap_single(port->dev,
1609 atmel_port->pdc_rx[0].dma_addr,
1610 PDC_BUFFER_SIZE,
1611 DMA_FROM_DEVICE);
1612 kfree(atmel_port->pdc_rx[0].buf);
1613 }
1614 atmel_port->use_pdc_rx = 0;
1615 return -ENOMEM;
1616 }
1617 pdc->dma_addr = dma_map_single(port->dev,
1618 pdc->buf,
1619 PDC_BUFFER_SIZE,
1620 DMA_FROM_DEVICE);
1621 pdc->dma_size = PDC_BUFFER_SIZE;
1622 pdc->ofs = 0;
1623 }
1624
1625 atmel_port->pdc_rx_idx = 0;
1626
1627 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1628 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1629
1630 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1631 atmel_port->pdc_rx[1].dma_addr);
1632 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1633
1634 return 0;
1635 }
1636
1637 /*
1638 * tasklet handling tty stuff outside the interrupt handler.
1639 */
atmel_tasklet_rx_func(unsigned long data)1640 static void atmel_tasklet_rx_func(unsigned long data)
1641 {
1642 struct uart_port *port = (struct uart_port *)data;
1643 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1644
1645 /* The interrupt handler does not take the lock */
1646 spin_lock(&port->lock);
1647 atmel_port->schedule_rx(port);
1648 spin_unlock(&port->lock);
1649 }
1650
atmel_tasklet_tx_func(unsigned long data)1651 static void atmel_tasklet_tx_func(unsigned long data)
1652 {
1653 struct uart_port *port = (struct uart_port *)data;
1654 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1655
1656 /* The interrupt handler does not take the lock */
1657 spin_lock(&port->lock);
1658 atmel_port->schedule_tx(port);
1659 spin_unlock(&port->lock);
1660 }
1661
atmel_init_property(struct atmel_uart_port * atmel_port,struct platform_device * pdev)1662 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1663 struct platform_device *pdev)
1664 {
1665 struct device_node *np = pdev->dev.of_node;
1666
1667 /* DMA/PDC usage specification */
1668 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1669 if (of_property_read_bool(np, "dmas")) {
1670 atmel_port->use_dma_rx = true;
1671 atmel_port->use_pdc_rx = false;
1672 } else {
1673 atmel_port->use_dma_rx = false;
1674 atmel_port->use_pdc_rx = true;
1675 }
1676 } else {
1677 atmel_port->use_dma_rx = false;
1678 atmel_port->use_pdc_rx = false;
1679 }
1680
1681 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1682 if (of_property_read_bool(np, "dmas")) {
1683 atmel_port->use_dma_tx = true;
1684 atmel_port->use_pdc_tx = false;
1685 } else {
1686 atmel_port->use_dma_tx = false;
1687 atmel_port->use_pdc_tx = true;
1688 }
1689 } else {
1690 atmel_port->use_dma_tx = false;
1691 atmel_port->use_pdc_tx = false;
1692 }
1693 }
1694
atmel_init_rs485(struct uart_port * port,struct platform_device * pdev)1695 static void atmel_init_rs485(struct uart_port *port,
1696 struct platform_device *pdev)
1697 {
1698 struct device_node *np = pdev->dev.of_node;
1699
1700 struct serial_rs485 *rs485conf = &port->rs485;
1701 u32 rs485_delay[2];
1702
1703 /* rs485 properties */
1704 if (of_property_read_u32_array(np, "rs485-rts-delay",
1705 rs485_delay, 2) == 0) {
1706 rs485conf->delay_rts_before_send = rs485_delay[0];
1707 rs485conf->delay_rts_after_send = rs485_delay[1];
1708 rs485conf->flags = 0;
1709 }
1710
1711 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1712 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1713
1714 if (of_get_property(np, "linux,rs485-enabled-at-boot-time", NULL))
1715 rs485conf->flags |= SER_RS485_ENABLED;
1716 }
1717
atmel_set_ops(struct uart_port * port)1718 static void atmel_set_ops(struct uart_port *port)
1719 {
1720 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1721
1722 if (atmel_use_dma_rx(port)) {
1723 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1724 atmel_port->schedule_rx = &atmel_rx_from_dma;
1725 atmel_port->release_rx = &atmel_release_rx_dma;
1726 } else if (atmel_use_pdc_rx(port)) {
1727 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1728 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1729 atmel_port->release_rx = &atmel_release_rx_pdc;
1730 } else {
1731 atmel_port->prepare_rx = NULL;
1732 atmel_port->schedule_rx = &atmel_rx_from_ring;
1733 atmel_port->release_rx = NULL;
1734 }
1735
1736 if (atmel_use_dma_tx(port)) {
1737 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1738 atmel_port->schedule_tx = &atmel_tx_dma;
1739 atmel_port->release_tx = &atmel_release_tx_dma;
1740 } else if (atmel_use_pdc_tx(port)) {
1741 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1742 atmel_port->schedule_tx = &atmel_tx_pdc;
1743 atmel_port->release_tx = &atmel_release_tx_pdc;
1744 } else {
1745 atmel_port->prepare_tx = NULL;
1746 atmel_port->schedule_tx = &atmel_tx_chars;
1747 atmel_port->release_tx = NULL;
1748 }
1749 }
1750
1751 /*
1752 * Get ip name usart or uart
1753 */
atmel_get_ip_name(struct uart_port * port)1754 static void atmel_get_ip_name(struct uart_port *port)
1755 {
1756 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1757 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1758 u32 version;
1759 u32 usart, dbgu_uart, new_uart;
1760 /* ASCII decoding for IP version */
1761 usart = 0x55534152; /* USAR(T) */
1762 dbgu_uart = 0x44424755; /* DBGU */
1763 new_uart = 0x55415254; /* UART */
1764
1765 /*
1766 * Only USART devices from at91sam9260 SOC implement fractional
1767 * baudrate. It is available for all asynchronous modes, with the
1768 * following restriction: the sampling clock's duty cycle is not
1769 * constant.
1770 */
1771 atmel_port->has_frac_baudrate = false;
1772 atmel_port->has_hw_timer = false;
1773
1774 if (name == new_uart) {
1775 dev_dbg(port->dev, "Uart with hw timer");
1776 atmel_port->has_hw_timer = true;
1777 atmel_port->rtor = ATMEL_UA_RTOR;
1778 } else if (name == usart) {
1779 dev_dbg(port->dev, "Usart\n");
1780 atmel_port->has_frac_baudrate = true;
1781 atmel_port->has_hw_timer = true;
1782 atmel_port->rtor = ATMEL_US_RTOR;
1783 } else if (name == dbgu_uart) {
1784 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1785 } else {
1786 /* fallback for older SoCs: use version field */
1787 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1788 switch (version) {
1789 case 0x302:
1790 case 0x10213:
1791 case 0x10302:
1792 dev_dbg(port->dev, "This version is usart\n");
1793 atmel_port->has_frac_baudrate = true;
1794 atmel_port->has_hw_timer = true;
1795 atmel_port->rtor = ATMEL_US_RTOR;
1796 break;
1797 case 0x203:
1798 case 0x10202:
1799 dev_dbg(port->dev, "This version is uart\n");
1800 break;
1801 default:
1802 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1803 }
1804 }
1805 }
1806
1807 /*
1808 * Perform initialization and enable port for reception
1809 */
atmel_startup(struct uart_port * port)1810 static int atmel_startup(struct uart_port *port)
1811 {
1812 struct platform_device *pdev = to_platform_device(port->dev);
1813 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1814 int retval;
1815
1816 /*
1817 * Ensure that no interrupts are enabled otherwise when
1818 * request_irq() is called we could get stuck trying to
1819 * handle an unexpected interrupt
1820 */
1821 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1822 atmel_port->ms_irq_enabled = false;
1823
1824 /*
1825 * Allocate the IRQ
1826 */
1827 retval = request_irq(port->irq, atmel_interrupt,
1828 IRQF_SHARED | IRQF_COND_SUSPEND,
1829 dev_name(&pdev->dev), port);
1830 if (retval) {
1831 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1832 return retval;
1833 }
1834
1835 atomic_set(&atmel_port->tasklet_shutdown, 0);
1836 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1837 (unsigned long)port);
1838 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1839 (unsigned long)port);
1840
1841 /*
1842 * Initialize DMA (if necessary)
1843 */
1844 atmel_init_property(atmel_port, pdev);
1845 atmel_set_ops(port);
1846
1847 if (atmel_port->prepare_rx) {
1848 retval = atmel_port->prepare_rx(port);
1849 if (retval < 0)
1850 atmel_set_ops(port);
1851 }
1852
1853 if (atmel_port->prepare_tx) {
1854 retval = atmel_port->prepare_tx(port);
1855 if (retval < 0)
1856 atmel_set_ops(port);
1857 }
1858
1859 /*
1860 * Enable FIFO when available
1861 */
1862 if (atmel_port->fifo_size) {
1863 unsigned int txrdym = ATMEL_US_ONE_DATA;
1864 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1865 unsigned int fmr;
1866
1867 atmel_uart_writel(port, ATMEL_US_CR,
1868 ATMEL_US_FIFOEN |
1869 ATMEL_US_RXFCLR |
1870 ATMEL_US_TXFLCLR);
1871
1872 if (atmel_use_dma_tx(port))
1873 txrdym = ATMEL_US_FOUR_DATA;
1874
1875 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1876 if (atmel_port->rts_high &&
1877 atmel_port->rts_low)
1878 fmr |= ATMEL_US_FRTSC |
1879 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1880 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1881
1882 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1883 }
1884
1885 /* Save current CSR for comparison in atmel_tasklet_func() */
1886 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1887
1888 /*
1889 * Finally, enable the serial port
1890 */
1891 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1892 /* enable xmit & rcvr */
1893 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1894
1895 setup_timer(&atmel_port->uart_timer,
1896 atmel_uart_timer_callback,
1897 (unsigned long)port);
1898
1899 if (atmel_use_pdc_rx(port)) {
1900 /* set UART timeout */
1901 if (!atmel_port->has_hw_timer) {
1902 mod_timer(&atmel_port->uart_timer,
1903 jiffies + uart_poll_timeout(port));
1904 /* set USART timeout */
1905 } else {
1906 atmel_uart_writel(port, atmel_port->rtor,
1907 PDC_RX_TIMEOUT);
1908 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1909
1910 atmel_uart_writel(port, ATMEL_US_IER,
1911 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1912 }
1913 /* enable PDC controller */
1914 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1915 } else if (atmel_use_dma_rx(port)) {
1916 /* set UART timeout */
1917 if (!atmel_port->has_hw_timer) {
1918 mod_timer(&atmel_port->uart_timer,
1919 jiffies + uart_poll_timeout(port));
1920 /* set USART timeout */
1921 } else {
1922 atmel_uart_writel(port, atmel_port->rtor,
1923 PDC_RX_TIMEOUT);
1924 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1925
1926 atmel_uart_writel(port, ATMEL_US_IER,
1927 ATMEL_US_TIMEOUT);
1928 }
1929 } else {
1930 /* enable receive only */
1931 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1932 }
1933
1934 return 0;
1935 }
1936
1937 /*
1938 * Flush any TX data submitted for DMA. Called when the TX circular
1939 * buffer is reset.
1940 */
atmel_flush_buffer(struct uart_port * port)1941 static void atmel_flush_buffer(struct uart_port *port)
1942 {
1943 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1944
1945 if (atmel_use_pdc_tx(port)) {
1946 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
1947 atmel_port->pdc_tx.ofs = 0;
1948 }
1949 /*
1950 * in uart_flush_buffer(), the xmit circular buffer has just
1951 * been cleared, so we have to reset tx_len accordingly.
1952 */
1953 atmel_port->tx_len = 0;
1954 }
1955
1956 /*
1957 * Disable the port
1958 */
atmel_shutdown(struct uart_port * port)1959 static void atmel_shutdown(struct uart_port *port)
1960 {
1961 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1962
1963 /* Disable modem control lines interrupts */
1964 atmel_disable_ms(port);
1965
1966 /* Disable interrupts at device level */
1967 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1968
1969 /* Prevent spurious interrupts from scheduling the tasklet */
1970 atomic_inc(&atmel_port->tasklet_shutdown);
1971
1972 /*
1973 * Prevent any tasklets being scheduled during
1974 * cleanup
1975 */
1976 del_timer_sync(&atmel_port->uart_timer);
1977
1978 /* Make sure that no interrupt is on the fly */
1979 synchronize_irq(port->irq);
1980
1981 /*
1982 * Clear out any scheduled tasklets before
1983 * we destroy the buffers
1984 */
1985 tasklet_kill(&atmel_port->tasklet_rx);
1986 tasklet_kill(&atmel_port->tasklet_tx);
1987
1988 /*
1989 * Ensure everything is stopped and
1990 * disable port and break condition.
1991 */
1992 atmel_stop_rx(port);
1993 atmel_stop_tx(port);
1994
1995 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1996
1997 /*
1998 * Shut-down the DMA.
1999 */
2000 if (atmel_port->release_rx)
2001 atmel_port->release_rx(port);
2002 if (atmel_port->release_tx)
2003 atmel_port->release_tx(port);
2004
2005 /*
2006 * Reset ring buffer pointers
2007 */
2008 atmel_port->rx_ring.head = 0;
2009 atmel_port->rx_ring.tail = 0;
2010
2011 /*
2012 * Free the interrupts
2013 */
2014 free_irq(port->irq, port);
2015
2016 atmel_flush_buffer(port);
2017 }
2018
2019 /*
2020 * Power / Clock management.
2021 */
atmel_serial_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)2022 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2023 unsigned int oldstate)
2024 {
2025 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2026
2027 switch (state) {
2028 case 0:
2029 /*
2030 * Enable the peripheral clock for this serial port.
2031 * This is called on uart_open() or a resume event.
2032 */
2033 clk_prepare_enable(atmel_port->clk);
2034
2035 /* re-enable interrupts if we disabled some on suspend */
2036 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2037 break;
2038 case 3:
2039 /* Back up the interrupt mask and disable all interrupts */
2040 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2041 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2042
2043 /*
2044 * Disable the peripheral clock for this serial port.
2045 * This is called on uart_close() or a suspend event.
2046 */
2047 clk_disable_unprepare(atmel_port->clk);
2048 break;
2049 default:
2050 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2051 }
2052 }
2053
2054 /*
2055 * Change the port parameters
2056 */
atmel_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)2057 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2058 struct ktermios *old)
2059 {
2060 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2061 unsigned long flags;
2062 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2063
2064 /* save the current mode register */
2065 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2066
2067 /* reset the mode, clock divisor, parity, stop bits and data size */
2068 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2069 ATMEL_US_PAR | ATMEL_US_USMODE);
2070
2071 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2072
2073 /* byte size */
2074 switch (termios->c_cflag & CSIZE) {
2075 case CS5:
2076 mode |= ATMEL_US_CHRL_5;
2077 break;
2078 case CS6:
2079 mode |= ATMEL_US_CHRL_6;
2080 break;
2081 case CS7:
2082 mode |= ATMEL_US_CHRL_7;
2083 break;
2084 default:
2085 mode |= ATMEL_US_CHRL_8;
2086 break;
2087 }
2088
2089 /* stop bits */
2090 if (termios->c_cflag & CSTOPB)
2091 mode |= ATMEL_US_NBSTOP_2;
2092
2093 /* parity */
2094 if (termios->c_cflag & PARENB) {
2095 /* Mark or Space parity */
2096 if (termios->c_cflag & CMSPAR) {
2097 if (termios->c_cflag & PARODD)
2098 mode |= ATMEL_US_PAR_MARK;
2099 else
2100 mode |= ATMEL_US_PAR_SPACE;
2101 } else if (termios->c_cflag & PARODD)
2102 mode |= ATMEL_US_PAR_ODD;
2103 else
2104 mode |= ATMEL_US_PAR_EVEN;
2105 } else
2106 mode |= ATMEL_US_PAR_NONE;
2107
2108 spin_lock_irqsave(&port->lock, flags);
2109
2110 port->read_status_mask = ATMEL_US_OVRE;
2111 if (termios->c_iflag & INPCK)
2112 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2113 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2114 port->read_status_mask |= ATMEL_US_RXBRK;
2115
2116 if (atmel_use_pdc_rx(port))
2117 /* need to enable error interrupts */
2118 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2119
2120 /*
2121 * Characters to ignore
2122 */
2123 port->ignore_status_mask = 0;
2124 if (termios->c_iflag & IGNPAR)
2125 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2126 if (termios->c_iflag & IGNBRK) {
2127 port->ignore_status_mask |= ATMEL_US_RXBRK;
2128 /*
2129 * If we're ignoring parity and break indicators,
2130 * ignore overruns too (for real raw support).
2131 */
2132 if (termios->c_iflag & IGNPAR)
2133 port->ignore_status_mask |= ATMEL_US_OVRE;
2134 }
2135 /* TODO: Ignore all characters if CREAD is set.*/
2136
2137 /* update the per-port timeout */
2138 uart_update_timeout(port, termios->c_cflag, baud);
2139
2140 /*
2141 * save/disable interrupts. The tty layer will ensure that the
2142 * transmitter is empty if requested by the caller, so there's
2143 * no need to wait for it here.
2144 */
2145 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2146 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2147
2148 /* disable receiver and transmitter */
2149 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2150
2151 /* mode */
2152 if (port->rs485.flags & SER_RS485_ENABLED) {
2153 atmel_uart_writel(port, ATMEL_US_TTGR,
2154 port->rs485.delay_rts_after_send);
2155 mode |= ATMEL_US_USMODE_RS485;
2156 } else if (termios->c_cflag & CRTSCTS) {
2157 /* RS232 with hardware handshake (RTS/CTS) */
2158 if (atmel_use_fifo(port) &&
2159 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2160 /*
2161 * with ATMEL_US_USMODE_HWHS set, the controller will
2162 * be able to drive the RTS pin high/low when the RX
2163 * FIFO is above RXFTHRES/below RXFTHRES2.
2164 * It will also disable the transmitter when the CTS
2165 * pin is high.
2166 * This mode is not activated if CTS pin is a GPIO
2167 * because in this case, the transmitter is always
2168 * disabled (there must be an internal pull-up
2169 * responsible for this behaviour).
2170 * If the RTS pin is a GPIO, the controller won't be
2171 * able to drive it according to the FIFO thresholds,
2172 * but it will be handled by the driver.
2173 */
2174 mode |= ATMEL_US_USMODE_HWHS;
2175 } else {
2176 /*
2177 * For platforms without FIFO, the flow control is
2178 * handled by the driver.
2179 */
2180 mode |= ATMEL_US_USMODE_NORMAL;
2181 }
2182 } else {
2183 /* RS232 without hadware handshake */
2184 mode |= ATMEL_US_USMODE_NORMAL;
2185 }
2186
2187 /*
2188 * Set the baud rate:
2189 * Fractional baudrate allows to setup output frequency more
2190 * accurately. This feature is enabled only when using normal mode.
2191 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2192 * Currently, OVER is always set to 0 so we get
2193 * baudrate = selected clock / (16 * (CD + FP / 8))
2194 * then
2195 * 8 CD + FP = selected clock / (2 * baudrate)
2196 */
2197 if (atmel_port->has_frac_baudrate) {
2198 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2199 cd = div >> 3;
2200 fp = div & ATMEL_US_FP_MASK;
2201 } else {
2202 cd = uart_get_divisor(port, baud);
2203 }
2204
2205 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2206 cd /= 8;
2207 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2208 }
2209 quot = cd | fp << ATMEL_US_FP_OFFSET;
2210
2211 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2212
2213 /* set the mode, clock divisor, parity, stop bits and data size */
2214 atmel_uart_writel(port, ATMEL_US_MR, mode);
2215
2216 /*
2217 * when switching the mode, set the RTS line state according to the
2218 * new mode, otherwise keep the former state
2219 */
2220 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2221 unsigned int rts_state;
2222
2223 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2224 /* let the hardware control the RTS line */
2225 rts_state = ATMEL_US_RTSDIS;
2226 } else {
2227 /* force RTS line to low level */
2228 rts_state = ATMEL_US_RTSEN;
2229 }
2230
2231 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2232 }
2233
2234 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2235 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2236
2237 /* restore interrupts */
2238 atmel_uart_writel(port, ATMEL_US_IER, imr);
2239
2240 /* CTS flow-control and modem-status interrupts */
2241 if (UART_ENABLE_MS(port, termios->c_cflag))
2242 atmel_enable_ms(port);
2243 else
2244 atmel_disable_ms(port);
2245
2246 spin_unlock_irqrestore(&port->lock, flags);
2247 }
2248
atmel_set_ldisc(struct uart_port * port,struct ktermios * termios)2249 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2250 {
2251 if (termios->c_line == N_PPS) {
2252 port->flags |= UPF_HARDPPS_CD;
2253 spin_lock_irq(&port->lock);
2254 atmel_enable_ms(port);
2255 spin_unlock_irq(&port->lock);
2256 } else {
2257 port->flags &= ~UPF_HARDPPS_CD;
2258 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2259 spin_lock_irq(&port->lock);
2260 atmel_disable_ms(port);
2261 spin_unlock_irq(&port->lock);
2262 }
2263 }
2264 }
2265
2266 /*
2267 * Return string describing the specified port
2268 */
atmel_type(struct uart_port * port)2269 static const char *atmel_type(struct uart_port *port)
2270 {
2271 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2272 }
2273
2274 /*
2275 * Release the memory region(s) being used by 'port'.
2276 */
atmel_release_port(struct uart_port * port)2277 static void atmel_release_port(struct uart_port *port)
2278 {
2279 struct platform_device *pdev = to_platform_device(port->dev);
2280 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2281
2282 release_mem_region(port->mapbase, size);
2283
2284 if (port->flags & UPF_IOREMAP) {
2285 iounmap(port->membase);
2286 port->membase = NULL;
2287 }
2288 }
2289
2290 /*
2291 * Request the memory region(s) being used by 'port'.
2292 */
atmel_request_port(struct uart_port * port)2293 static int atmel_request_port(struct uart_port *port)
2294 {
2295 struct platform_device *pdev = to_platform_device(port->dev);
2296 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2297
2298 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2299 return -EBUSY;
2300
2301 if (port->flags & UPF_IOREMAP) {
2302 port->membase = ioremap(port->mapbase, size);
2303 if (port->membase == NULL) {
2304 release_mem_region(port->mapbase, size);
2305 return -ENOMEM;
2306 }
2307 }
2308
2309 return 0;
2310 }
2311
2312 /*
2313 * Configure/autoconfigure the port.
2314 */
atmel_config_port(struct uart_port * port,int flags)2315 static void atmel_config_port(struct uart_port *port, int flags)
2316 {
2317 if (flags & UART_CONFIG_TYPE) {
2318 port->type = PORT_ATMEL;
2319 atmel_request_port(port);
2320 }
2321 }
2322
2323 /*
2324 * Verify the new serial_struct (for TIOCSSERIAL).
2325 */
atmel_verify_port(struct uart_port * port,struct serial_struct * ser)2326 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2327 {
2328 int ret = 0;
2329 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2330 ret = -EINVAL;
2331 if (port->irq != ser->irq)
2332 ret = -EINVAL;
2333 if (ser->io_type != SERIAL_IO_MEM)
2334 ret = -EINVAL;
2335 if (port->uartclk / 16 != ser->baud_base)
2336 ret = -EINVAL;
2337 if (port->mapbase != (unsigned long)ser->iomem_base)
2338 ret = -EINVAL;
2339 if (port->iobase != ser->port)
2340 ret = -EINVAL;
2341 if (ser->hub6 != 0)
2342 ret = -EINVAL;
2343 return ret;
2344 }
2345
2346 #ifdef CONFIG_CONSOLE_POLL
atmel_poll_get_char(struct uart_port * port)2347 static int atmel_poll_get_char(struct uart_port *port)
2348 {
2349 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2350 cpu_relax();
2351
2352 return atmel_uart_read_char(port);
2353 }
2354
atmel_poll_put_char(struct uart_port * port,unsigned char ch)2355 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2356 {
2357 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2358 cpu_relax();
2359
2360 atmel_uart_write_char(port, ch);
2361 }
2362 #endif
2363
2364 static const struct uart_ops atmel_pops = {
2365 .tx_empty = atmel_tx_empty,
2366 .set_mctrl = atmel_set_mctrl,
2367 .get_mctrl = atmel_get_mctrl,
2368 .stop_tx = atmel_stop_tx,
2369 .start_tx = atmel_start_tx,
2370 .stop_rx = atmel_stop_rx,
2371 .enable_ms = atmel_enable_ms,
2372 .break_ctl = atmel_break_ctl,
2373 .startup = atmel_startup,
2374 .shutdown = atmel_shutdown,
2375 .flush_buffer = atmel_flush_buffer,
2376 .set_termios = atmel_set_termios,
2377 .set_ldisc = atmel_set_ldisc,
2378 .type = atmel_type,
2379 .release_port = atmel_release_port,
2380 .request_port = atmel_request_port,
2381 .config_port = atmel_config_port,
2382 .verify_port = atmel_verify_port,
2383 .pm = atmel_serial_pm,
2384 #ifdef CONFIG_CONSOLE_POLL
2385 .poll_get_char = atmel_poll_get_char,
2386 .poll_put_char = atmel_poll_put_char,
2387 #endif
2388 };
2389
2390 /*
2391 * Configure the port from the platform device resource info.
2392 */
atmel_init_port(struct atmel_uart_port * atmel_port,struct platform_device * pdev)2393 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2394 struct platform_device *pdev)
2395 {
2396 int ret;
2397 struct uart_port *port = &atmel_port->uart;
2398
2399 atmel_init_property(atmel_port, pdev);
2400 atmel_set_ops(port);
2401
2402 atmel_init_rs485(port, pdev);
2403
2404 port->iotype = UPIO_MEM;
2405 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
2406 port->ops = &atmel_pops;
2407 port->fifosize = 1;
2408 port->dev = &pdev->dev;
2409 port->mapbase = pdev->resource[0].start;
2410 port->irq = pdev->resource[1].start;
2411 port->rs485_config = atmel_config_rs485;
2412 port->membase = NULL;
2413
2414 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2415
2416 /* for console, the clock could already be configured */
2417 if (!atmel_port->clk) {
2418 atmel_port->clk = clk_get(&pdev->dev, "usart");
2419 if (IS_ERR(atmel_port->clk)) {
2420 ret = PTR_ERR(atmel_port->clk);
2421 atmel_port->clk = NULL;
2422 return ret;
2423 }
2424 ret = clk_prepare_enable(atmel_port->clk);
2425 if (ret) {
2426 clk_put(atmel_port->clk);
2427 atmel_port->clk = NULL;
2428 return ret;
2429 }
2430 port->uartclk = clk_get_rate(atmel_port->clk);
2431 clk_disable_unprepare(atmel_port->clk);
2432 /* only enable clock when USART is in use */
2433 }
2434
2435 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2436 if (port->rs485.flags & SER_RS485_ENABLED)
2437 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2438 else if (atmel_use_pdc_tx(port)) {
2439 port->fifosize = PDC_BUFFER_SIZE;
2440 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2441 } else {
2442 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2443 }
2444
2445 return 0;
2446 }
2447
2448 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
atmel_console_putchar(struct uart_port * port,int ch)2449 static void atmel_console_putchar(struct uart_port *port, int ch)
2450 {
2451 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2452 cpu_relax();
2453 atmel_uart_write_char(port, ch);
2454 }
2455
2456 /*
2457 * Interrupts are disabled on entering
2458 */
atmel_console_write(struct console * co,const char * s,u_int count)2459 static void atmel_console_write(struct console *co, const char *s, u_int count)
2460 {
2461 struct uart_port *port = &atmel_ports[co->index].uart;
2462 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2463 unsigned int status, imr;
2464 unsigned int pdc_tx;
2465
2466 /*
2467 * First, save IMR and then disable interrupts
2468 */
2469 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2470 atmel_uart_writel(port, ATMEL_US_IDR,
2471 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2472
2473 /* Store PDC transmit status and disable it */
2474 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2475 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2476
2477 /* Make sure that tx path is actually able to send characters */
2478 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2479
2480 uart_console_write(port, s, count, atmel_console_putchar);
2481
2482 /*
2483 * Finally, wait for transmitter to become empty
2484 * and restore IMR
2485 */
2486 do {
2487 status = atmel_uart_readl(port, ATMEL_US_CSR);
2488 } while (!(status & ATMEL_US_TXRDY));
2489
2490 /* Restore PDC transmit status */
2491 if (pdc_tx)
2492 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2493
2494 /* set interrupts back the way they were */
2495 atmel_uart_writel(port, ATMEL_US_IER, imr);
2496 }
2497
2498 /*
2499 * If the port was already initialised (eg, by a boot loader),
2500 * try to determine the current setup.
2501 */
atmel_console_get_options(struct uart_port * port,int * baud,int * parity,int * bits)2502 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2503 int *parity, int *bits)
2504 {
2505 unsigned int mr, quot;
2506
2507 /*
2508 * If the baud rate generator isn't running, the port wasn't
2509 * initialized by the boot loader.
2510 */
2511 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2512 if (!quot)
2513 return;
2514
2515 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2516 if (mr == ATMEL_US_CHRL_8)
2517 *bits = 8;
2518 else
2519 *bits = 7;
2520
2521 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2522 if (mr == ATMEL_US_PAR_EVEN)
2523 *parity = 'e';
2524 else if (mr == ATMEL_US_PAR_ODD)
2525 *parity = 'o';
2526
2527 /*
2528 * The serial core only rounds down when matching this to a
2529 * supported baud rate. Make sure we don't end up slightly
2530 * lower than one of those, as it would make us fall through
2531 * to a much lower baud rate than we really want.
2532 */
2533 *baud = port->uartclk / (16 * (quot - 1));
2534 }
2535
atmel_console_setup(struct console * co,char * options)2536 static int __init atmel_console_setup(struct console *co, char *options)
2537 {
2538 int ret;
2539 struct uart_port *port = &atmel_ports[co->index].uart;
2540 int baud = 115200;
2541 int bits = 8;
2542 int parity = 'n';
2543 int flow = 'n';
2544
2545 if (port->membase == NULL) {
2546 /* Port not initialized yet - delay setup */
2547 return -ENODEV;
2548 }
2549
2550 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2551 if (ret)
2552 return ret;
2553
2554 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2555 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2556 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2557
2558 if (options)
2559 uart_parse_options(options, &baud, &parity, &bits, &flow);
2560 else
2561 atmel_console_get_options(port, &baud, &parity, &bits);
2562
2563 return uart_set_options(port, co, baud, parity, bits, flow);
2564 }
2565
2566 static struct uart_driver atmel_uart;
2567
2568 static struct console atmel_console = {
2569 .name = ATMEL_DEVICENAME,
2570 .write = atmel_console_write,
2571 .device = uart_console_device,
2572 .setup = atmel_console_setup,
2573 .flags = CON_PRINTBUFFER,
2574 .index = -1,
2575 .data = &atmel_uart,
2576 };
2577
2578 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2579
atmel_is_console_port(struct uart_port * port)2580 static inline bool atmel_is_console_port(struct uart_port *port)
2581 {
2582 return port->cons && port->cons->index == port->line;
2583 }
2584
2585 #else
2586 #define ATMEL_CONSOLE_DEVICE NULL
2587
atmel_is_console_port(struct uart_port * port)2588 static inline bool atmel_is_console_port(struct uart_port *port)
2589 {
2590 return false;
2591 }
2592 #endif
2593
2594 static struct uart_driver atmel_uart = {
2595 .owner = THIS_MODULE,
2596 .driver_name = "atmel_serial",
2597 .dev_name = ATMEL_DEVICENAME,
2598 .major = SERIAL_ATMEL_MAJOR,
2599 .minor = MINOR_START,
2600 .nr = ATMEL_MAX_UART,
2601 .cons = ATMEL_CONSOLE_DEVICE,
2602 };
2603
2604 #ifdef CONFIG_PM
atmel_serial_clk_will_stop(void)2605 static bool atmel_serial_clk_will_stop(void)
2606 {
2607 #ifdef CONFIG_ARCH_AT91
2608 return at91_suspend_entering_slow_clock();
2609 #else
2610 return false;
2611 #endif
2612 }
2613
atmel_serial_suspend(struct platform_device * pdev,pm_message_t state)2614 static int atmel_serial_suspend(struct platform_device *pdev,
2615 pm_message_t state)
2616 {
2617 struct uart_port *port = platform_get_drvdata(pdev);
2618 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2619
2620 if (atmel_is_console_port(port) && console_suspend_enabled) {
2621 /* Drain the TX shifter */
2622 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2623 ATMEL_US_TXEMPTY))
2624 cpu_relax();
2625 }
2626
2627 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2628 /* Cache register values as we won't get a full shutdown/startup
2629 * cycle
2630 */
2631 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2632 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2633 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2634 atmel_port->cache.rtor = atmel_uart_readl(port,
2635 atmel_port->rtor);
2636 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2637 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2638 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2639 }
2640
2641 /* we can not wake up if we're running on slow clock */
2642 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2643 if (atmel_serial_clk_will_stop()) {
2644 unsigned long flags;
2645
2646 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2647 atmel_port->suspended = true;
2648 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2649 device_set_wakeup_enable(&pdev->dev, 0);
2650 }
2651
2652 uart_suspend_port(&atmel_uart, port);
2653
2654 return 0;
2655 }
2656
atmel_serial_resume(struct platform_device * pdev)2657 static int atmel_serial_resume(struct platform_device *pdev)
2658 {
2659 struct uart_port *port = platform_get_drvdata(pdev);
2660 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2661 unsigned long flags;
2662
2663 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2664 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2665 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2666 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2667 atmel_uart_writel(port, atmel_port->rtor,
2668 atmel_port->cache.rtor);
2669 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2670
2671 if (atmel_port->fifo_size) {
2672 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2673 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2674 atmel_uart_writel(port, ATMEL_US_FMR,
2675 atmel_port->cache.fmr);
2676 atmel_uart_writel(port, ATMEL_US_FIER,
2677 atmel_port->cache.fimr);
2678 }
2679 atmel_start_rx(port);
2680 }
2681
2682 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2683 if (atmel_port->pending) {
2684 atmel_handle_receive(port, atmel_port->pending);
2685 atmel_handle_status(port, atmel_port->pending,
2686 atmel_port->pending_status);
2687 atmel_handle_transmit(port, atmel_port->pending);
2688 atmel_port->pending = 0;
2689 }
2690 atmel_port->suspended = false;
2691 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2692
2693 uart_resume_port(&atmel_uart, port);
2694 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2695
2696 return 0;
2697 }
2698 #else
2699 #define atmel_serial_suspend NULL
2700 #define atmel_serial_resume NULL
2701 #endif
2702
atmel_serial_probe_fifos(struct atmel_uart_port * atmel_port,struct platform_device * pdev)2703 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2704 struct platform_device *pdev)
2705 {
2706 atmel_port->fifo_size = 0;
2707 atmel_port->rts_low = 0;
2708 atmel_port->rts_high = 0;
2709
2710 if (of_property_read_u32(pdev->dev.of_node,
2711 "atmel,fifo-size",
2712 &atmel_port->fifo_size))
2713 return;
2714
2715 if (!atmel_port->fifo_size)
2716 return;
2717
2718 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2719 atmel_port->fifo_size = 0;
2720 dev_err(&pdev->dev, "Invalid FIFO size\n");
2721 return;
2722 }
2723
2724 /*
2725 * 0 <= rts_low <= rts_high <= fifo_size
2726 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2727 * to flush their internal TX FIFO, commonly up to 16 data, before
2728 * actually stopping to send new data. So we try to set the RTS High
2729 * Threshold to a reasonably high value respecting this 16 data
2730 * empirical rule when possible.
2731 */
2732 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2733 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2734 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2735 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2736
2737 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2738 atmel_port->fifo_size);
2739 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2740 atmel_port->rts_high);
2741 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2742 atmel_port->rts_low);
2743 }
2744
atmel_serial_probe(struct platform_device * pdev)2745 static int atmel_serial_probe(struct platform_device *pdev)
2746 {
2747 struct atmel_uart_port *atmel_port;
2748 struct device_node *np = pdev->dev.of_node;
2749 void *data;
2750 int ret = -ENODEV;
2751 bool rs485_enabled;
2752
2753 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2754
2755 ret = of_alias_get_id(np, "serial");
2756 if (ret < 0)
2757 /* port id not found in platform data nor device-tree aliases:
2758 * auto-enumerate it */
2759 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2760
2761 if (ret >= ATMEL_MAX_UART) {
2762 ret = -ENODEV;
2763 goto err;
2764 }
2765
2766 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2767 /* port already in use */
2768 ret = -EBUSY;
2769 goto err;
2770 }
2771
2772 atmel_port = &atmel_ports[ret];
2773 atmel_port->backup_imr = 0;
2774 atmel_port->uart.line = ret;
2775 atmel_serial_probe_fifos(atmel_port, pdev);
2776
2777 atomic_set(&atmel_port->tasklet_shutdown, 0);
2778 spin_lock_init(&atmel_port->lock_suspended);
2779
2780 ret = atmel_init_port(atmel_port, pdev);
2781 if (ret)
2782 goto err_clear_bit;
2783
2784 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2785 if (IS_ERR(atmel_port->gpios)) {
2786 ret = PTR_ERR(atmel_port->gpios);
2787 goto err_clear_bit;
2788 }
2789
2790 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2791 ret = -ENOMEM;
2792 data = kmalloc(sizeof(struct atmel_uart_char)
2793 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2794 if (!data)
2795 goto err_alloc_ring;
2796 atmel_port->rx_ring.buf = data;
2797 }
2798
2799 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2800
2801 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2802 if (ret)
2803 goto err_add_port;
2804
2805 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2806 if (atmel_is_console_port(&atmel_port->uart)
2807 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2808 /*
2809 * The serial core enabled the clock for us, so undo
2810 * the clk_prepare_enable() in atmel_console_setup()
2811 */
2812 clk_disable_unprepare(atmel_port->clk);
2813 }
2814 #endif
2815
2816 device_init_wakeup(&pdev->dev, 1);
2817 platform_set_drvdata(pdev, atmel_port);
2818
2819 /*
2820 * The peripheral clock has been disabled by atmel_init_port():
2821 * enable it before accessing I/O registers
2822 */
2823 clk_prepare_enable(atmel_port->clk);
2824
2825 if (rs485_enabled) {
2826 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2827 ATMEL_US_USMODE_NORMAL);
2828 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2829 ATMEL_US_RTSEN);
2830 }
2831
2832 /*
2833 * Get port name of usart or uart
2834 */
2835 atmel_get_ip_name(&atmel_port->uart);
2836
2837 /*
2838 * The peripheral clock can now safely be disabled till the port
2839 * is used
2840 */
2841 clk_disable_unprepare(atmel_port->clk);
2842
2843 return 0;
2844
2845 err_add_port:
2846 kfree(atmel_port->rx_ring.buf);
2847 atmel_port->rx_ring.buf = NULL;
2848 err_alloc_ring:
2849 if (!atmel_is_console_port(&atmel_port->uart)) {
2850 clk_put(atmel_port->clk);
2851 atmel_port->clk = NULL;
2852 }
2853 err_clear_bit:
2854 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2855 err:
2856 return ret;
2857 }
2858
2859 /*
2860 * Even if the driver is not modular, it makes sense to be able to
2861 * unbind a device: there can be many bound devices, and there are
2862 * situations where dynamic binding and unbinding can be useful.
2863 *
2864 * For example, a connected device can require a specific firmware update
2865 * protocol that needs bitbanging on IO lines, but use the regular serial
2866 * port in the normal case.
2867 */
atmel_serial_remove(struct platform_device * pdev)2868 static int atmel_serial_remove(struct platform_device *pdev)
2869 {
2870 struct uart_port *port = platform_get_drvdata(pdev);
2871 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2872 int ret = 0;
2873
2874 tasklet_kill(&atmel_port->tasklet_rx);
2875 tasklet_kill(&atmel_port->tasklet_tx);
2876
2877 device_init_wakeup(&pdev->dev, 0);
2878
2879 ret = uart_remove_one_port(&atmel_uart, port);
2880
2881 kfree(atmel_port->rx_ring.buf);
2882
2883 /* "port" is allocated statically, so we shouldn't free it */
2884
2885 clear_bit(port->line, atmel_ports_in_use);
2886
2887 clk_put(atmel_port->clk);
2888 atmel_port->clk = NULL;
2889
2890 return ret;
2891 }
2892
2893 static struct platform_driver atmel_serial_driver = {
2894 .probe = atmel_serial_probe,
2895 .remove = atmel_serial_remove,
2896 .suspend = atmel_serial_suspend,
2897 .resume = atmel_serial_resume,
2898 .driver = {
2899 .name = "atmel_usart",
2900 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2901 },
2902 };
2903
atmel_serial_init(void)2904 static int __init atmel_serial_init(void)
2905 {
2906 int ret;
2907
2908 ret = uart_register_driver(&atmel_uart);
2909 if (ret)
2910 return ret;
2911
2912 ret = platform_driver_register(&atmel_serial_driver);
2913 if (ret)
2914 uart_unregister_driver(&atmel_uart);
2915
2916 return ret;
2917 }
2918 device_initcall(atmel_serial_init);
2919