1 /*
2 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
3 * Author: Jon Ringle <jringle@gridpoint.com>
4 *
5 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13
14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16 #include <linux/bitops.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/gpio/driver.h>
21 #include <linux/i2c.h>
22 #include <linux/module.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/regmap.h>
26 #include <linux/serial_core.h>
27 #include <linux/serial.h>
28 #include <linux/tty.h>
29 #include <linux/tty_flip.h>
30 #include <linux/spi/spi.h>
31 #include <linux/uaccess.h>
32 #include <uapi/linux/sched/types.h>
33
34 #define SC16IS7XX_NAME "sc16is7xx"
35 #define SC16IS7XX_MAX_DEVS 8
36
37 /* SC16IS7XX register definitions */
38 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
39 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
40 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
41 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
42 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
43 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */
44 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
45 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */
46 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
47 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
48 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
49 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
50 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
51 * - only on 75x/76x
52 */
53 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
54 * - only on 75x/76x
55 */
56 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
57 * - only on 75x/76x
58 */
59 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
60 * - only on 75x/76x
61 */
62 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
63
64 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
65 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
66 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
67
68 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
69 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
70 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
71
72 /* Enhanced Register set: Only if (LCR == 0xBF) */
73 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
74 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
75 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
76 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
77 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
78
79 /* IER register bits */
80 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
81 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
82 * interrupt */
83 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
84 * interrupt */
85 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
86 * interrupt */
87
88 /* IER register bits - write only if (EFR[4] == 1) */
89 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
90 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
91 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
92 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
93
94 /* FCR register bits */
95 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
96 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
97 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
98 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
99 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
100
101 /* FCR register bits - write only if (EFR[4] == 1) */
102 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
103 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
104
105 /* IIR register bits */
106 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
107 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
108 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
109 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
110 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
111 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
112 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
113 * - only on 75x/76x
114 */
115 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
116 * - only on 75x/76x
117 */
118 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
119 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
120 * from active (LOW)
121 * to inactive (HIGH)
122 */
123 /* LCR register bits */
124 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
125 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
126 *
127 * Word length bits table:
128 * 00 -> 5 bit words
129 * 01 -> 6 bit words
130 * 10 -> 7 bit words
131 * 11 -> 8 bit words
132 */
133 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
134 *
135 * STOP length bit table:
136 * 0 -> 1 stop bit
137 * 1 -> 1-1.5 stop bits if
138 * word length is 5,
139 * 2 stop bits otherwise
140 */
141 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
142 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
143 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
144 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
145 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
146 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
147 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
148 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
149 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
150 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
151 * reg set */
152 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
153 * reg set */
154
155 /* MCR register bits */
156 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
157 * - only on 75x/76x
158 */
159 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
160 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
161 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
162 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
163 * - write enabled
164 * if (EFR[4] == 1)
165 */
166 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
167 * - write enabled
168 * if (EFR[4] == 1)
169 */
170 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
171 * - write enabled
172 * if (EFR[4] == 1)
173 */
174
175 /* LSR register bits */
176 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
177 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
178 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
179 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
180 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
181 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
182 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
183 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
184 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
185
186 /* MSR register bits */
187 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
188 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
189 * or (IO4)
190 * - only on 75x/76x
191 */
192 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
193 * or (IO7)
194 * - only on 75x/76x
195 */
196 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
197 * or (IO6)
198 * - only on 75x/76x
199 */
200 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */
201 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4)
202 * - only on 75x/76x
203 */
204 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7)
205 * - only on 75x/76x
206 */
207 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6)
208 * - only on 75x/76x
209 */
210 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
211
212 /*
213 * TCR register bits
214 * TCR trigger levels are available from 0 to 60 characters with a granularity
215 * of four.
216 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
217 * no built-in hardware check to make sure this condition is met. Also, the TCR
218 * must be programmed with this condition before auto RTS or software flow
219 * control is enabled to avoid spurious operation of the device.
220 */
221 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
222 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
223
224 /*
225 * TLR register bits
226 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
227 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
228 * trigger levels. Trigger levels from 4 characters to 60 characters are
229 * available with a granularity of four.
230 *
231 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
232 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
233 * the trigger level defined in FCR is discarded. This applies to both transmit
234 * FIFO and receive FIFO trigger level setting.
235 *
236 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
237 * default state, that is, '00'.
238 */
239 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
240 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
241
242 /* IOControl register bits (Only 750/760) */
243 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
244 #define SC16IS7XX_IOCONTROL_MODEM_BIT (1 << 1) /* Enable GPIO[7:4] as modem pins */
245 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
246
247 /* EFCR register bits */
248 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
249 * mode (RS485) */
250 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
251 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
252 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
253 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
254 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
255 * 0 = rate upto 115.2 kbit/s
256 * - Only 750/760
257 * 1 = rate upto 1.152 Mbit/s
258 * - Only 760
259 */
260
261 /* EFR register bits */
262 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
263 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
264 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
265 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
266 * and writing to IER[7:4],
267 * FCR[5:4], MCR[7:5]
268 */
269 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
270 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
271 *
272 * SWFLOW bits 3 & 2 table:
273 * 00 -> no transmitter flow
274 * control
275 * 01 -> transmitter generates
276 * XON2 and XOFF2
277 * 10 -> transmitter generates
278 * XON1 and XOFF1
279 * 11 -> transmitter generates
280 * XON1, XON2, XOFF1 and
281 * XOFF2
282 */
283 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
284 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
285 *
286 * SWFLOW bits 3 & 2 table:
287 * 00 -> no received flow
288 * control
289 * 01 -> receiver compares
290 * XON2 and XOFF2
291 * 10 -> receiver compares
292 * XON1 and XOFF1
293 * 11 -> receiver compares
294 * XON1, XON2, XOFF1 and
295 * XOFF2
296 */
297
298 /* Misc definitions */
299 #define SC16IS7XX_FIFO_SIZE (64)
300 #define SC16IS7XX_REG_SHIFT 2
301
302 struct sc16is7xx_devtype {
303 char name[10];
304 int nr_gpio;
305 int nr_uart;
306 };
307
308 #define SC16IS7XX_RECONF_MD (1 << 0)
309 #define SC16IS7XX_RECONF_IER (1 << 1)
310 #define SC16IS7XX_RECONF_RS485 (1 << 2)
311
312 struct sc16is7xx_one_config {
313 unsigned int flags;
314 u8 ier_clear;
315 };
316
317 struct sc16is7xx_one {
318 struct uart_port port;
319 u8 line;
320 struct kthread_work tx_work;
321 struct kthread_work reg_work;
322 struct sc16is7xx_one_config config;
323 };
324
325 struct sc16is7xx_port {
326 const struct sc16is7xx_devtype *devtype;
327 struct regmap *regmap;
328 struct clk *clk;
329 #ifdef CONFIG_GPIOLIB
330 struct gpio_chip gpio;
331 #endif
332 unsigned char buf[SC16IS7XX_FIFO_SIZE];
333 struct kthread_worker kworker;
334 struct task_struct *kworker_task;
335 struct kthread_work irq_work;
336 struct mutex efr_lock;
337 struct sc16is7xx_one p[0];
338 };
339
340 static unsigned long sc16is7xx_lines;
341
342 static struct uart_driver sc16is7xx_uart = {
343 .owner = THIS_MODULE,
344 .dev_name = "ttySC",
345 .nr = SC16IS7XX_MAX_DEVS,
346 };
347
348 #define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e)))
349 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
350
sc16is7xx_line(struct uart_port * port)351 static int sc16is7xx_line(struct uart_port *port)
352 {
353 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
354
355 return one->line;
356 }
357
sc16is7xx_port_read(struct uart_port * port,u8 reg)358 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
359 {
360 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
361 unsigned int val = 0;
362 const u8 line = sc16is7xx_line(port);
363
364 regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val);
365
366 return val;
367 }
368
sc16is7xx_port_write(struct uart_port * port,u8 reg,u8 val)369 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
370 {
371 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
372 const u8 line = sc16is7xx_line(port);
373
374 regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val);
375 }
376
sc16is7xx_fifo_read(struct uart_port * port,unsigned int rxlen)377 static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen)
378 {
379 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
380 const u8 line = sc16is7xx_line(port);
381 u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | line;
382
383 regcache_cache_bypass(s->regmap, true);
384 regmap_raw_read(s->regmap, addr, s->buf, rxlen);
385 regcache_cache_bypass(s->regmap, false);
386 }
387
sc16is7xx_fifo_write(struct uart_port * port,u8 to_send)388 static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send)
389 {
390 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
391 const u8 line = sc16is7xx_line(port);
392 u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | line;
393
394 /*
395 * Don't send zero-length data, at least on SPI it confuses the chip
396 * delivering wrong TXLVL data.
397 */
398 if (unlikely(!to_send))
399 return;
400
401 regcache_cache_bypass(s->regmap, true);
402 regmap_raw_write(s->regmap, addr, s->buf, to_send);
403 regcache_cache_bypass(s->regmap, false);
404 }
405
sc16is7xx_port_update(struct uart_port * port,u8 reg,u8 mask,u8 val)406 static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
407 u8 mask, u8 val)
408 {
409 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
410 const u8 line = sc16is7xx_line(port);
411
412 regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line,
413 mask, val);
414 }
415
sc16is7xx_alloc_line(void)416 static int sc16is7xx_alloc_line(void)
417 {
418 int i;
419
420 BUILD_BUG_ON(SC16IS7XX_MAX_DEVS > BITS_PER_LONG);
421
422 for (i = 0; i < SC16IS7XX_MAX_DEVS; i++)
423 if (!test_and_set_bit(i, &sc16is7xx_lines))
424 break;
425
426 return i;
427 }
428
sc16is7xx_power(struct uart_port * port,int on)429 static void sc16is7xx_power(struct uart_port *port, int on)
430 {
431 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
432 SC16IS7XX_IER_SLEEP_BIT,
433 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
434 }
435
436 static const struct sc16is7xx_devtype sc16is74x_devtype = {
437 .name = "SC16IS74X",
438 .nr_gpio = 0,
439 .nr_uart = 1,
440 };
441
442 static const struct sc16is7xx_devtype sc16is750_devtype = {
443 .name = "SC16IS750",
444 .nr_gpio = 8,
445 .nr_uart = 1,
446 };
447
448 static const struct sc16is7xx_devtype sc16is752_devtype = {
449 .name = "SC16IS752",
450 .nr_gpio = 8,
451 .nr_uart = 2,
452 };
453
454 static const struct sc16is7xx_devtype sc16is760_devtype = {
455 .name = "SC16IS760",
456 .nr_gpio = 8,
457 .nr_uart = 1,
458 };
459
460 static const struct sc16is7xx_devtype sc16is762_devtype = {
461 .name = "SC16IS762",
462 .nr_gpio = 8,
463 .nr_uart = 2,
464 };
465
sc16is7xx_regmap_volatile(struct device * dev,unsigned int reg)466 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
467 {
468 switch (reg >> SC16IS7XX_REG_SHIFT) {
469 case SC16IS7XX_RHR_REG:
470 case SC16IS7XX_IIR_REG:
471 case SC16IS7XX_LSR_REG:
472 case SC16IS7XX_MSR_REG:
473 case SC16IS7XX_TXLVL_REG:
474 case SC16IS7XX_RXLVL_REG:
475 case SC16IS7XX_IOSTATE_REG:
476 return true;
477 default:
478 break;
479 }
480
481 return false;
482 }
483
sc16is7xx_regmap_precious(struct device * dev,unsigned int reg)484 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
485 {
486 switch (reg >> SC16IS7XX_REG_SHIFT) {
487 case SC16IS7XX_RHR_REG:
488 return true;
489 default:
490 break;
491 }
492
493 return false;
494 }
495
sc16is7xx_set_baud(struct uart_port * port,int baud)496 static int sc16is7xx_set_baud(struct uart_port *port, int baud)
497 {
498 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
499 u8 lcr;
500 u8 prescaler = 0;
501 unsigned long clk = port->uartclk, div = clk / 16 / baud;
502
503 if (div > 0xffff) {
504 prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
505 div /= 4;
506 }
507
508 /* In an amazing feat of design, the Enhanced Features Register shares
509 * the address of the Interrupt Identification Register, and is
510 * switched in by writing a magic value (0xbf) to the Line Control
511 * Register. Any interrupt firing during this time will see the EFR
512 * where it expects the IIR to be, leading to "Unexpected interrupt"
513 * messages.
514 *
515 * Prevent this possibility by claiming a mutex while accessing the
516 * EFR, and claiming the same mutex from within the interrupt handler.
517 * This is similar to disabling the interrupt, but that doesn't work
518 * because the bulk of the interrupt processing is run as a workqueue
519 * job in thread context.
520 */
521 mutex_lock(&s->efr_lock);
522
523 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
524
525 /* Open the LCR divisors for configuration */
526 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
527 SC16IS7XX_LCR_CONF_MODE_B);
528
529 /* Enable enhanced features */
530 regcache_cache_bypass(s->regmap, true);
531 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
532 SC16IS7XX_EFR_ENABLE_BIT);
533 regcache_cache_bypass(s->regmap, false);
534
535 /* Put LCR back to the normal mode */
536 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
537
538 mutex_unlock(&s->efr_lock);
539
540 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
541 SC16IS7XX_MCR_CLKSEL_BIT,
542 prescaler);
543
544 /* Open the LCR divisors for configuration */
545 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
546 SC16IS7XX_LCR_CONF_MODE_A);
547
548 /* Write the new divisor */
549 regcache_cache_bypass(s->regmap, true);
550 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
551 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
552 regcache_cache_bypass(s->regmap, false);
553
554 /* Put LCR back to the normal mode */
555 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
556
557 return DIV_ROUND_CLOSEST(clk / 16, div);
558 }
559
sc16is7xx_handle_rx(struct uart_port * port,unsigned int rxlen,unsigned int iir)560 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
561 unsigned int iir)
562 {
563 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
564 unsigned int lsr = 0, ch, flag, bytes_read, i;
565 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
566
567 if (unlikely(rxlen >= sizeof(s->buf))) {
568 dev_warn_ratelimited(port->dev,
569 "ttySC%i: Possible RX FIFO overrun: %d\n",
570 port->line, rxlen);
571 port->icount.buf_overrun++;
572 /* Ensure sanity of RX level */
573 rxlen = sizeof(s->buf);
574 }
575
576 while (rxlen) {
577 /* Only read lsr if there are possible errors in FIFO */
578 if (read_lsr) {
579 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
580 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
581 read_lsr = false; /* No errors left in FIFO */
582 } else
583 lsr = 0;
584
585 if (read_lsr) {
586 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
587 bytes_read = 1;
588 } else {
589 sc16is7xx_fifo_read(port, rxlen);
590 bytes_read = rxlen;
591 }
592
593 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
594
595 port->icount.rx++;
596 flag = TTY_NORMAL;
597
598 if (unlikely(lsr)) {
599 if (lsr & SC16IS7XX_LSR_BI_BIT) {
600 port->icount.brk++;
601 if (uart_handle_break(port))
602 continue;
603 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
604 port->icount.parity++;
605 else if (lsr & SC16IS7XX_LSR_FE_BIT)
606 port->icount.frame++;
607 else if (lsr & SC16IS7XX_LSR_OE_BIT)
608 port->icount.overrun++;
609
610 lsr &= port->read_status_mask;
611 if (lsr & SC16IS7XX_LSR_BI_BIT)
612 flag = TTY_BREAK;
613 else if (lsr & SC16IS7XX_LSR_PE_BIT)
614 flag = TTY_PARITY;
615 else if (lsr & SC16IS7XX_LSR_FE_BIT)
616 flag = TTY_FRAME;
617 else if (lsr & SC16IS7XX_LSR_OE_BIT)
618 flag = TTY_OVERRUN;
619 }
620
621 for (i = 0; i < bytes_read; ++i) {
622 ch = s->buf[i];
623 if (uart_handle_sysrq_char(port, ch))
624 continue;
625
626 if (lsr & port->ignore_status_mask)
627 continue;
628
629 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
630 flag);
631 }
632 rxlen -= bytes_read;
633 }
634
635 tty_flip_buffer_push(&port->state->port);
636 }
637
sc16is7xx_handle_tx(struct uart_port * port)638 static void sc16is7xx_handle_tx(struct uart_port *port)
639 {
640 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
641 struct circ_buf *xmit = &port->state->xmit;
642 unsigned int txlen, to_send, i;
643
644 if (unlikely(port->x_char)) {
645 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
646 port->icount.tx++;
647 port->x_char = 0;
648 return;
649 }
650
651 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
652 return;
653
654 /* Get length of data pending in circular buffer */
655 to_send = uart_circ_chars_pending(xmit);
656 if (likely(to_send)) {
657 /* Limit to size of TX FIFO */
658 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
659 if (txlen > SC16IS7XX_FIFO_SIZE) {
660 dev_err_ratelimited(port->dev,
661 "chip reports %d free bytes in TX fifo, but it only has %d",
662 txlen, SC16IS7XX_FIFO_SIZE);
663 txlen = 0;
664 }
665 to_send = (to_send > txlen) ? txlen : to_send;
666
667 /* Add data to send */
668 port->icount.tx += to_send;
669
670 /* Convert to linear buffer */
671 for (i = 0; i < to_send; ++i) {
672 s->buf[i] = xmit->buf[xmit->tail];
673 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
674 }
675
676 sc16is7xx_fifo_write(port, to_send);
677 }
678
679 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
680 uart_write_wakeup(port);
681 }
682
sc16is7xx_port_irq(struct sc16is7xx_port * s,int portno)683 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
684 {
685 struct uart_port *port = &s->p[portno].port;
686
687 do {
688 unsigned int iir, rxlen;
689
690 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
691 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
692 return false;
693
694 iir &= SC16IS7XX_IIR_ID_MASK;
695
696 switch (iir) {
697 case SC16IS7XX_IIR_RDI_SRC:
698 case SC16IS7XX_IIR_RLSE_SRC:
699 case SC16IS7XX_IIR_RTOI_SRC:
700 case SC16IS7XX_IIR_XOFFI_SRC:
701 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
702 if (rxlen)
703 sc16is7xx_handle_rx(port, rxlen, iir);
704 break;
705 case SC16IS7XX_IIR_THRI_SRC:
706 sc16is7xx_handle_tx(port);
707 break;
708 default:
709 dev_err_ratelimited(port->dev,
710 "ttySC%i: Unexpected interrupt: %x",
711 port->line, iir);
712 break;
713 }
714 } while (0);
715 return true;
716 }
717
sc16is7xx_ist(struct kthread_work * ws)718 static void sc16is7xx_ist(struct kthread_work *ws)
719 {
720 struct sc16is7xx_port *s = to_sc16is7xx_port(ws, irq_work);
721
722 mutex_lock(&s->efr_lock);
723
724 while (1) {
725 bool keep_polling = false;
726 int i;
727
728 for (i = 0; i < s->devtype->nr_uart; ++i)
729 keep_polling |= sc16is7xx_port_irq(s, i);
730 if (!keep_polling)
731 break;
732 }
733
734 mutex_unlock(&s->efr_lock);
735 }
736
sc16is7xx_irq(int irq,void * dev_id)737 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
738 {
739 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
740
741 kthread_queue_work(&s->kworker, &s->irq_work);
742
743 return IRQ_HANDLED;
744 }
745
sc16is7xx_tx_proc(struct kthread_work * ws)746 static void sc16is7xx_tx_proc(struct kthread_work *ws)
747 {
748 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
749
750 if ((port->rs485.flags & SER_RS485_ENABLED) &&
751 (port->rs485.delay_rts_before_send > 0))
752 msleep(port->rs485.delay_rts_before_send);
753
754 sc16is7xx_handle_tx(port);
755 }
756
sc16is7xx_reconf_rs485(struct uart_port * port)757 static void sc16is7xx_reconf_rs485(struct uart_port *port)
758 {
759 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
760 SC16IS7XX_EFCR_RTS_INVERT_BIT;
761 u32 efcr = 0;
762 struct serial_rs485 *rs485 = &port->rs485;
763 unsigned long irqflags;
764
765 spin_lock_irqsave(&port->lock, irqflags);
766 if (rs485->flags & SER_RS485_ENABLED) {
767 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
768
769 if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
770 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
771 }
772 spin_unlock_irqrestore(&port->lock, irqflags);
773
774 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
775 }
776
sc16is7xx_reg_proc(struct kthread_work * ws)777 static void sc16is7xx_reg_proc(struct kthread_work *ws)
778 {
779 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
780 struct sc16is7xx_one_config config;
781 unsigned long irqflags;
782
783 spin_lock_irqsave(&one->port.lock, irqflags);
784 config = one->config;
785 memset(&one->config, 0, sizeof(one->config));
786 spin_unlock_irqrestore(&one->port.lock, irqflags);
787
788 if (config.flags & SC16IS7XX_RECONF_MD) {
789 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
790 SC16IS7XX_MCR_LOOP_BIT,
791 (one->port.mctrl & TIOCM_LOOP) ?
792 SC16IS7XX_MCR_LOOP_BIT : 0);
793 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
794 SC16IS7XX_MCR_RTS_BIT,
795 (one->port.mctrl & TIOCM_RTS) ?
796 SC16IS7XX_MCR_RTS_BIT : 0);
797 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
798 SC16IS7XX_MCR_DTR_BIT,
799 (one->port.mctrl & TIOCM_DTR) ?
800 SC16IS7XX_MCR_DTR_BIT : 0);
801 }
802 if (config.flags & SC16IS7XX_RECONF_IER)
803 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
804 config.ier_clear, 0);
805
806 if (config.flags & SC16IS7XX_RECONF_RS485)
807 sc16is7xx_reconf_rs485(&one->port);
808 }
809
sc16is7xx_ier_clear(struct uart_port * port,u8 bit)810 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
811 {
812 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
813 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
814
815 one->config.flags |= SC16IS7XX_RECONF_IER;
816 one->config.ier_clear |= bit;
817 kthread_queue_work(&s->kworker, &one->reg_work);
818 }
819
sc16is7xx_stop_tx(struct uart_port * port)820 static void sc16is7xx_stop_tx(struct uart_port *port)
821 {
822 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
823 }
824
sc16is7xx_stop_rx(struct uart_port * port)825 static void sc16is7xx_stop_rx(struct uart_port *port)
826 {
827 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
828 }
829
sc16is7xx_start_tx(struct uart_port * port)830 static void sc16is7xx_start_tx(struct uart_port *port)
831 {
832 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
833 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
834
835 kthread_queue_work(&s->kworker, &one->tx_work);
836 }
837
sc16is7xx_tx_empty(struct uart_port * port)838 static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
839 {
840 unsigned int lsr;
841
842 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
843
844 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
845 }
846
sc16is7xx_get_mctrl(struct uart_port * port)847 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
848 {
849 /* DCD and DSR are not wired and CTS/RTS is handled automatically
850 * so just indicate DSR and CAR asserted
851 */
852 return TIOCM_DSR | TIOCM_CAR;
853 }
854
sc16is7xx_set_mctrl(struct uart_port * port,unsigned int mctrl)855 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
856 {
857 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
858 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
859
860 one->config.flags |= SC16IS7XX_RECONF_MD;
861 kthread_queue_work(&s->kworker, &one->reg_work);
862 }
863
sc16is7xx_break_ctl(struct uart_port * port,int break_state)864 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
865 {
866 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
867 SC16IS7XX_LCR_TXBREAK_BIT,
868 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
869 }
870
sc16is7xx_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)871 static void sc16is7xx_set_termios(struct uart_port *port,
872 struct ktermios *termios,
873 struct ktermios *old)
874 {
875 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
876 unsigned int lcr, flow = 0;
877 int baud;
878
879 /* Mask termios capabilities we don't support */
880 termios->c_cflag &= ~CMSPAR;
881
882 /* Word size */
883 switch (termios->c_cflag & CSIZE) {
884 case CS5:
885 lcr = SC16IS7XX_LCR_WORD_LEN_5;
886 break;
887 case CS6:
888 lcr = SC16IS7XX_LCR_WORD_LEN_6;
889 break;
890 case CS7:
891 lcr = SC16IS7XX_LCR_WORD_LEN_7;
892 break;
893 case CS8:
894 lcr = SC16IS7XX_LCR_WORD_LEN_8;
895 break;
896 default:
897 lcr = SC16IS7XX_LCR_WORD_LEN_8;
898 termios->c_cflag &= ~CSIZE;
899 termios->c_cflag |= CS8;
900 break;
901 }
902
903 /* Parity */
904 if (termios->c_cflag & PARENB) {
905 lcr |= SC16IS7XX_LCR_PARITY_BIT;
906 if (!(termios->c_cflag & PARODD))
907 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
908 }
909
910 /* Stop bits */
911 if (termios->c_cflag & CSTOPB)
912 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
913
914 /* Set read status mask */
915 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
916 if (termios->c_iflag & INPCK)
917 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
918 SC16IS7XX_LSR_FE_BIT;
919 if (termios->c_iflag & (BRKINT | PARMRK))
920 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
921
922 /* Set status ignore mask */
923 port->ignore_status_mask = 0;
924 if (termios->c_iflag & IGNBRK)
925 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
926 if (!(termios->c_cflag & CREAD))
927 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
928
929 /* As above, claim the mutex while accessing the EFR. */
930 mutex_lock(&s->efr_lock);
931
932 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
933 SC16IS7XX_LCR_CONF_MODE_B);
934
935 /* Configure flow control */
936 regcache_cache_bypass(s->regmap, true);
937 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
938 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
939 if (termios->c_cflag & CRTSCTS)
940 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
941 SC16IS7XX_EFR_AUTORTS_BIT;
942 if (termios->c_iflag & IXON)
943 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
944 if (termios->c_iflag & IXOFF)
945 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
946
947 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);
948 regcache_cache_bypass(s->regmap, false);
949
950 /* Update LCR register */
951 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
952
953 mutex_unlock(&s->efr_lock);
954
955 /* Get baud rate generator configuration */
956 baud = uart_get_baud_rate(port, termios, old,
957 port->uartclk / 16 / 4 / 0xffff,
958 port->uartclk / 16);
959
960 /* Setup baudrate generator */
961 baud = sc16is7xx_set_baud(port, baud);
962
963 /* Update timeout according to new baud rate */
964 uart_update_timeout(port, termios->c_cflag, baud);
965 }
966
sc16is7xx_config_rs485(struct uart_port * port,struct serial_rs485 * rs485)967 static int sc16is7xx_config_rs485(struct uart_port *port,
968 struct serial_rs485 *rs485)
969 {
970 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
971 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
972
973 if (rs485->flags & SER_RS485_ENABLED) {
974 bool rts_during_rx, rts_during_tx;
975
976 rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND;
977 rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND;
978
979 if (rts_during_rx == rts_during_tx)
980 dev_err(port->dev,
981 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
982 rts_during_tx, rts_during_rx);
983
984 /*
985 * RTS signal is handled by HW, it's timing can't be influenced.
986 * However, it's sometimes useful to delay TX even without RTS
987 * control therefore we try to handle .delay_rts_before_send.
988 */
989 if (rs485->delay_rts_after_send)
990 return -EINVAL;
991 }
992
993 port->rs485 = *rs485;
994 one->config.flags |= SC16IS7XX_RECONF_RS485;
995 kthread_queue_work(&s->kworker, &one->reg_work);
996
997 return 0;
998 }
999
sc16is7xx_startup(struct uart_port * port)1000 static int sc16is7xx_startup(struct uart_port *port)
1001 {
1002 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1003 unsigned int val;
1004
1005 sc16is7xx_power(port, 1);
1006
1007 /* Reset FIFOs*/
1008 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
1009 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
1010 udelay(5);
1011 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
1012 SC16IS7XX_FCR_FIFO_BIT);
1013
1014 /* Enable EFR */
1015 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
1016 SC16IS7XX_LCR_CONF_MODE_B);
1017
1018 regcache_cache_bypass(s->regmap, true);
1019
1020 /* Enable write access to enhanced features and internal clock div */
1021 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
1022 SC16IS7XX_EFR_ENABLE_BIT);
1023
1024 /* Enable TCR/TLR */
1025 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1026 SC16IS7XX_MCR_TCRTLR_BIT,
1027 SC16IS7XX_MCR_TCRTLR_BIT);
1028
1029 /* Configure flow control levels */
1030 /* Flow control halt level 48, resume level 24 */
1031 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
1032 SC16IS7XX_TCR_RX_RESUME(24) |
1033 SC16IS7XX_TCR_RX_HALT(48));
1034
1035 regcache_cache_bypass(s->regmap, false);
1036
1037 /* Now, initialize the UART */
1038 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
1039
1040 /* Enable the Rx and Tx FIFO */
1041 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1042 SC16IS7XX_EFCR_RXDISABLE_BIT |
1043 SC16IS7XX_EFCR_TXDISABLE_BIT,
1044 0);
1045
1046 /* Enable RX, TX interrupts */
1047 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT;
1048 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
1049
1050 return 0;
1051 }
1052
sc16is7xx_shutdown(struct uart_port * port)1053 static void sc16is7xx_shutdown(struct uart_port *port)
1054 {
1055 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1056
1057 /* Disable all interrupts */
1058 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1059 /* Disable TX/RX */
1060 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1061 SC16IS7XX_EFCR_RXDISABLE_BIT |
1062 SC16IS7XX_EFCR_TXDISABLE_BIT,
1063 SC16IS7XX_EFCR_RXDISABLE_BIT |
1064 SC16IS7XX_EFCR_TXDISABLE_BIT);
1065
1066 sc16is7xx_power(port, 0);
1067
1068 kthread_flush_worker(&s->kworker);
1069 }
1070
sc16is7xx_type(struct uart_port * port)1071 static const char *sc16is7xx_type(struct uart_port *port)
1072 {
1073 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1074
1075 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
1076 }
1077
sc16is7xx_request_port(struct uart_port * port)1078 static int sc16is7xx_request_port(struct uart_port *port)
1079 {
1080 /* Do nothing */
1081 return 0;
1082 }
1083
sc16is7xx_config_port(struct uart_port * port,int flags)1084 static void sc16is7xx_config_port(struct uart_port *port, int flags)
1085 {
1086 if (flags & UART_CONFIG_TYPE)
1087 port->type = PORT_SC16IS7XX;
1088 }
1089
sc16is7xx_verify_port(struct uart_port * port,struct serial_struct * s)1090 static int sc16is7xx_verify_port(struct uart_port *port,
1091 struct serial_struct *s)
1092 {
1093 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1094 return -EINVAL;
1095 if (s->irq != port->irq)
1096 return -EINVAL;
1097
1098 return 0;
1099 }
1100
sc16is7xx_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)1101 static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1102 unsigned int oldstate)
1103 {
1104 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1105 }
1106
sc16is7xx_null_void(struct uart_port * port)1107 static void sc16is7xx_null_void(struct uart_port *port)
1108 {
1109 /* Do nothing */
1110 }
1111
1112 static const struct uart_ops sc16is7xx_ops = {
1113 .tx_empty = sc16is7xx_tx_empty,
1114 .set_mctrl = sc16is7xx_set_mctrl,
1115 .get_mctrl = sc16is7xx_get_mctrl,
1116 .stop_tx = sc16is7xx_stop_tx,
1117 .start_tx = sc16is7xx_start_tx,
1118 .stop_rx = sc16is7xx_stop_rx,
1119 .break_ctl = sc16is7xx_break_ctl,
1120 .startup = sc16is7xx_startup,
1121 .shutdown = sc16is7xx_shutdown,
1122 .set_termios = sc16is7xx_set_termios,
1123 .type = sc16is7xx_type,
1124 .request_port = sc16is7xx_request_port,
1125 .release_port = sc16is7xx_null_void,
1126 .config_port = sc16is7xx_config_port,
1127 .verify_port = sc16is7xx_verify_port,
1128 .pm = sc16is7xx_pm,
1129 };
1130
1131 #ifdef CONFIG_GPIOLIB
sc16is7xx_gpio_get(struct gpio_chip * chip,unsigned offset)1132 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1133 {
1134 unsigned int val;
1135 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1136 struct uart_port *port = &s->p[0].port;
1137
1138 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1139
1140 return !!(val & BIT(offset));
1141 }
1142
sc16is7xx_gpio_set(struct gpio_chip * chip,unsigned offset,int val)1143 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1144 {
1145 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1146 struct uart_port *port = &s->p[0].port;
1147
1148 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1149 val ? BIT(offset) : 0);
1150 }
1151
sc16is7xx_gpio_direction_input(struct gpio_chip * chip,unsigned offset)1152 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1153 unsigned offset)
1154 {
1155 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1156 struct uart_port *port = &s->p[0].port;
1157
1158 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1159
1160 return 0;
1161 }
1162
sc16is7xx_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int val)1163 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1164 unsigned offset, int val)
1165 {
1166 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1167 struct uart_port *port = &s->p[0].port;
1168 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1169
1170 if (val)
1171 state |= BIT(offset);
1172 else
1173 state &= ~BIT(offset);
1174 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);
1175 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1176 BIT(offset));
1177
1178 return 0;
1179 }
1180 #endif
1181
sc16is7xx_probe(struct device * dev,const struct sc16is7xx_devtype * devtype,struct regmap * regmap,int irq,unsigned long flags)1182 static int sc16is7xx_probe(struct device *dev,
1183 const struct sc16is7xx_devtype *devtype,
1184 struct regmap *regmap, int irq, unsigned long flags)
1185 {
1186 struct sched_param sched_param = { .sched_priority = MAX_RT_PRIO / 2 };
1187 unsigned long freq, *pfreq = dev_get_platdata(dev);
1188 int i, ret;
1189 struct sc16is7xx_port *s;
1190
1191 if (IS_ERR(regmap))
1192 return PTR_ERR(regmap);
1193
1194 /* Alloc port structure */
1195 s = devm_kzalloc(dev, sizeof(*s) +
1196 sizeof(struct sc16is7xx_one) * devtype->nr_uart,
1197 GFP_KERNEL);
1198 if (!s) {
1199 dev_err(dev, "Error allocating port structure\n");
1200 return -ENOMEM;
1201 }
1202
1203 s->clk = devm_clk_get(dev, NULL);
1204 if (IS_ERR(s->clk)) {
1205 if (pfreq)
1206 freq = *pfreq;
1207 else
1208 return PTR_ERR(s->clk);
1209 } else {
1210 clk_prepare_enable(s->clk);
1211 freq = clk_get_rate(s->clk);
1212 }
1213
1214 s->regmap = regmap;
1215 s->devtype = devtype;
1216 dev_set_drvdata(dev, s);
1217 mutex_init(&s->efr_lock);
1218
1219 kthread_init_worker(&s->kworker);
1220 kthread_init_work(&s->irq_work, sc16is7xx_ist);
1221 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1222 "sc16is7xx");
1223 if (IS_ERR(s->kworker_task)) {
1224 ret = PTR_ERR(s->kworker_task);
1225 goto out_clk;
1226 }
1227 sched_setscheduler(s->kworker_task, SCHED_FIFO, &sched_param);
1228
1229 #ifdef CONFIG_GPIOLIB
1230 if (devtype->nr_gpio) {
1231 /* Setup GPIO cotroller */
1232 s->gpio.owner = THIS_MODULE;
1233 s->gpio.parent = dev;
1234 s->gpio.label = dev_name(dev);
1235 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1236 s->gpio.get = sc16is7xx_gpio_get;
1237 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1238 s->gpio.set = sc16is7xx_gpio_set;
1239 s->gpio.base = -1;
1240 s->gpio.ngpio = devtype->nr_gpio;
1241 s->gpio.can_sleep = 1;
1242 ret = gpiochip_add_data(&s->gpio, s);
1243 if (ret)
1244 goto out_thread;
1245 }
1246 #endif
1247
1248 /* reset device, purging any pending irq / data */
1249 regmap_write(s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT,
1250 SC16IS7XX_IOCONTROL_SRESET_BIT);
1251
1252 for (i = 0; i < devtype->nr_uart; ++i) {
1253 s->p[i].line = i;
1254 /* Initialize port data */
1255 s->p[i].port.dev = dev;
1256 s->p[i].port.irq = irq;
1257 s->p[i].port.type = PORT_SC16IS7XX;
1258 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1259 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1260 s->p[i].port.iotype = UPIO_PORT;
1261 s->p[i].port.uartclk = freq;
1262 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
1263 s->p[i].port.ops = &sc16is7xx_ops;
1264 s->p[i].port.line = sc16is7xx_alloc_line();
1265 if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) {
1266 ret = -ENOMEM;
1267 goto out_ports;
1268 }
1269
1270 /* Disable all interrupts */
1271 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1272 /* Disable TX/RX */
1273 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1274 SC16IS7XX_EFCR_RXDISABLE_BIT |
1275 SC16IS7XX_EFCR_TXDISABLE_BIT);
1276 /* Initialize kthread work structs */
1277 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
1278 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
1279 /* Register port */
1280 uart_add_one_port(&sc16is7xx_uart, &s->p[i].port);
1281
1282 /* Enable EFR */
1283 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG,
1284 SC16IS7XX_LCR_CONF_MODE_B);
1285
1286 regcache_cache_bypass(s->regmap, true);
1287
1288 /* Enable write access to enhanced features */
1289 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG,
1290 SC16IS7XX_EFR_ENABLE_BIT);
1291
1292 regcache_cache_bypass(s->regmap, false);
1293
1294 /* Restore access to general registers */
1295 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00);
1296
1297 /* Go to suspend mode */
1298 sc16is7xx_power(&s->p[i].port, 0);
1299 }
1300
1301 /* Setup interrupt */
1302 ret = devm_request_irq(dev, irq, sc16is7xx_irq,
1303 flags, dev_name(dev), s);
1304 if (!ret)
1305 return 0;
1306
1307 out_ports:
1308 for (i--; i >= 0; i--) {
1309 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1310 clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1311 }
1312
1313 #ifdef CONFIG_GPIOLIB
1314 if (devtype->nr_gpio)
1315 gpiochip_remove(&s->gpio);
1316
1317 out_thread:
1318 #endif
1319 kthread_stop(s->kworker_task);
1320
1321 out_clk:
1322 if (!IS_ERR(s->clk))
1323 clk_disable_unprepare(s->clk);
1324
1325 return ret;
1326 }
1327
sc16is7xx_remove(struct device * dev)1328 static int sc16is7xx_remove(struct device *dev)
1329 {
1330 struct sc16is7xx_port *s = dev_get_drvdata(dev);
1331 int i;
1332
1333 #ifdef CONFIG_GPIOLIB
1334 if (s->devtype->nr_gpio)
1335 gpiochip_remove(&s->gpio);
1336 #endif
1337
1338 for (i = 0; i < s->devtype->nr_uart; i++) {
1339 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1340 clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1341 sc16is7xx_power(&s->p[i].port, 0);
1342 }
1343
1344 kthread_flush_worker(&s->kworker);
1345 kthread_stop(s->kworker_task);
1346
1347 if (!IS_ERR(s->clk))
1348 clk_disable_unprepare(s->clk);
1349
1350 return 0;
1351 }
1352
1353 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1354 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1355 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1356 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1357 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1358 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1359 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1360 { }
1361 };
1362 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1363
1364 static struct regmap_config regcfg = {
1365 .reg_bits = 7,
1366 .pad_bits = 1,
1367 .val_bits = 8,
1368 .cache_type = REGCACHE_RBTREE,
1369 .volatile_reg = sc16is7xx_regmap_volatile,
1370 .precious_reg = sc16is7xx_regmap_precious,
1371 };
1372
1373 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
sc16is7xx_spi_probe(struct spi_device * spi)1374 static int sc16is7xx_spi_probe(struct spi_device *spi)
1375 {
1376 const struct sc16is7xx_devtype *devtype;
1377 unsigned long flags = 0;
1378 struct regmap *regmap;
1379 int ret;
1380
1381 /* Setup SPI bus */
1382 spi->bits_per_word = 8;
1383 /* only supports mode 0 on SC16IS762 */
1384 spi->mode = spi->mode ? : SPI_MODE_0;
1385 spi->max_speed_hz = spi->max_speed_hz ? : 15000000;
1386 ret = spi_setup(spi);
1387 if (ret)
1388 return ret;
1389
1390 if (spi->dev.of_node) {
1391 const struct of_device_id *of_id =
1392 of_match_device(sc16is7xx_dt_ids, &spi->dev);
1393
1394 if (!of_id)
1395 return -ENODEV;
1396
1397 devtype = (struct sc16is7xx_devtype *)of_id->data;
1398 } else {
1399 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1400
1401 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
1402 flags = IRQF_TRIGGER_FALLING;
1403 }
1404
1405 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1406 (devtype->nr_uart - 1);
1407 regmap = devm_regmap_init_spi(spi, ®cfg);
1408
1409 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq, flags);
1410 }
1411
sc16is7xx_spi_remove(struct spi_device * spi)1412 static int sc16is7xx_spi_remove(struct spi_device *spi)
1413 {
1414 return sc16is7xx_remove(&spi->dev);
1415 }
1416
1417 static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1418 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1419 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1420 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1421 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1422 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1423 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1424 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1425 { }
1426 };
1427
1428 MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1429
1430 static struct spi_driver sc16is7xx_spi_uart_driver = {
1431 .driver = {
1432 .name = SC16IS7XX_NAME,
1433 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1434 },
1435 .probe = sc16is7xx_spi_probe,
1436 .remove = sc16is7xx_spi_remove,
1437 .id_table = sc16is7xx_spi_id_table,
1438 };
1439
1440 MODULE_ALIAS("spi:sc16is7xx");
1441 #endif
1442
1443 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
sc16is7xx_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)1444 static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1445 const struct i2c_device_id *id)
1446 {
1447 const struct sc16is7xx_devtype *devtype;
1448 unsigned long flags = 0;
1449 struct regmap *regmap;
1450
1451 if (i2c->dev.of_node) {
1452 const struct of_device_id *of_id =
1453 of_match_device(sc16is7xx_dt_ids, &i2c->dev);
1454
1455 if (!of_id)
1456 return -ENODEV;
1457
1458 devtype = (struct sc16is7xx_devtype *)of_id->data;
1459 } else {
1460 devtype = (struct sc16is7xx_devtype *)id->driver_data;
1461 flags = IRQF_TRIGGER_FALLING;
1462 }
1463
1464 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1465 (devtype->nr_uart - 1);
1466 regmap = devm_regmap_init_i2c(i2c, ®cfg);
1467
1468 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq, flags);
1469 }
1470
sc16is7xx_i2c_remove(struct i2c_client * client)1471 static int sc16is7xx_i2c_remove(struct i2c_client *client)
1472 {
1473 return sc16is7xx_remove(&client->dev);
1474 }
1475
1476 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1477 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1478 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1479 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1480 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1481 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1482 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1483 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1484 { }
1485 };
1486 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1487
1488 static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1489 .driver = {
1490 .name = SC16IS7XX_NAME,
1491 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1492 },
1493 .probe = sc16is7xx_i2c_probe,
1494 .remove = sc16is7xx_i2c_remove,
1495 .id_table = sc16is7xx_i2c_id_table,
1496 };
1497
1498 #endif
1499
sc16is7xx_init(void)1500 static int __init sc16is7xx_init(void)
1501 {
1502 int ret;
1503
1504 ret = uart_register_driver(&sc16is7xx_uart);
1505 if (ret) {
1506 pr_err("Registering UART driver failed\n");
1507 return ret;
1508 }
1509
1510 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1511 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1512 if (ret < 0) {
1513 pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1514 goto err_i2c;
1515 }
1516 #endif
1517
1518 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1519 ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1520 if (ret < 0) {
1521 pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1522 goto err_spi;
1523 }
1524 #endif
1525 return ret;
1526
1527 err_spi:
1528 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1529 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1530 #endif
1531 err_i2c:
1532 uart_unregister_driver(&sc16is7xx_uart);
1533 return ret;
1534 }
1535 module_init(sc16is7xx_init);
1536
sc16is7xx_exit(void)1537 static void __exit sc16is7xx_exit(void)
1538 {
1539 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1540 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1541 #endif
1542
1543 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1544 spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1545 #endif
1546 uart_unregister_driver(&sc16is7xx_uart);
1547 }
1548 module_exit(sc16is7xx_exit);
1549
1550 MODULE_LICENSE("GPL");
1551 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1552 MODULE_DESCRIPTION("SC16IS7XX serial driver");
1553