1 /*
2 * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37 /*
38 * This file contains the interrupt handlers for Host mode
39 */
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/spinlock.h>
43 #include <linux/interrupt.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/io.h>
46 #include <linux/slab.h>
47 #include <linux/usb.h>
48
49 #include <linux/usb/hcd.h>
50 #include <linux/usb/ch11.h>
51
52 #include "core.h"
53 #include "hcd.h"
54
55 /* This function is for debug only */
dwc2_track_missed_sofs(struct dwc2_hsotg * hsotg)56 static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
57 {
58 u16 curr_frame_number = hsotg->frame_number;
59 u16 expected = dwc2_frame_num_inc(hsotg->last_frame_num, 1);
60
61 if (expected != curr_frame_number)
62 dwc2_sch_vdbg(hsotg, "MISSED SOF %04x != %04x\n",
63 expected, curr_frame_number);
64
65 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
66 if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
67 if (expected != curr_frame_number) {
68 hsotg->frame_num_array[hsotg->frame_num_idx] =
69 curr_frame_number;
70 hsotg->last_frame_num_array[hsotg->frame_num_idx] =
71 hsotg->last_frame_num;
72 hsotg->frame_num_idx++;
73 }
74 } else if (!hsotg->dumped_frame_num_array) {
75 int i;
76
77 dev_info(hsotg->dev, "Frame Last Frame\n");
78 dev_info(hsotg->dev, "----- ----------\n");
79 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
80 dev_info(hsotg->dev, "0x%04x 0x%04x\n",
81 hsotg->frame_num_array[i],
82 hsotg->last_frame_num_array[i]);
83 }
84 hsotg->dumped_frame_num_array = 1;
85 }
86 #endif
87 hsotg->last_frame_num = curr_frame_number;
88 }
89
dwc2_hc_handle_tt_clear(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,struct dwc2_qtd * qtd)90 static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg,
91 struct dwc2_host_chan *chan,
92 struct dwc2_qtd *qtd)
93 {
94 struct usb_device *root_hub = dwc2_hsotg_to_hcd(hsotg)->self.root_hub;
95 struct urb *usb_urb;
96
97 if (!chan->qh)
98 return;
99
100 if (chan->qh->dev_speed == USB_SPEED_HIGH)
101 return;
102
103 if (!qtd->urb)
104 return;
105
106 usb_urb = qtd->urb->priv;
107 if (!usb_urb || !usb_urb->dev || !usb_urb->dev->tt)
108 return;
109
110 /*
111 * The root hub doesn't really have a TT, but Linux thinks it
112 * does because how could you have a "high speed hub" that
113 * directly talks directly to low speed devices without a TT?
114 * It's all lies. Lies, I tell you.
115 */
116 if (usb_urb->dev->tt->hub == root_hub)
117 return;
118
119 if (qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) {
120 chan->qh->tt_buffer_dirty = 1;
121 if (usb_hub_clear_tt_buffer(usb_urb))
122 /* Clear failed; let's hope things work anyway */
123 chan->qh->tt_buffer_dirty = 0;
124 }
125 }
126
127 /*
128 * Handles the start-of-frame interrupt in host mode. Non-periodic
129 * transactions may be queued to the DWC_otg controller for the current
130 * (micro)frame. Periodic transactions may be queued to the controller
131 * for the next (micro)frame.
132 */
dwc2_sof_intr(struct dwc2_hsotg * hsotg)133 static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
134 {
135 struct list_head *qh_entry;
136 struct dwc2_qh *qh;
137 enum dwc2_transaction_type tr_type;
138
139 /* Clear interrupt */
140 dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS);
141
142 #ifdef DEBUG_SOF
143 dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
144 #endif
145
146 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
147
148 dwc2_track_missed_sofs(hsotg);
149
150 /* Determine whether any periodic QHs should be executed */
151 qh_entry = hsotg->periodic_sched_inactive.next;
152 while (qh_entry != &hsotg->periodic_sched_inactive) {
153 qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry);
154 qh_entry = qh_entry->next;
155 if (dwc2_frame_num_le(qh->next_active_frame,
156 hsotg->frame_number)) {
157 dwc2_sch_vdbg(hsotg, "QH=%p ready fn=%04x, nxt=%04x\n",
158 qh, hsotg->frame_number,
159 qh->next_active_frame);
160
161 /*
162 * Move QH to the ready list to be executed next
163 * (micro)frame
164 */
165 list_move_tail(&qh->qh_list_entry,
166 &hsotg->periodic_sched_ready);
167 }
168 }
169 tr_type = dwc2_hcd_select_transactions(hsotg);
170 if (tr_type != DWC2_TRANSACTION_NONE)
171 dwc2_hcd_queue_transactions(hsotg, tr_type);
172 }
173
174 /*
175 * Handles the Rx FIFO Level Interrupt, which indicates that there is
176 * at least one packet in the Rx FIFO. The packets are moved from the FIFO to
177 * memory if the DWC_otg controller is operating in Slave mode.
178 */
dwc2_rx_fifo_level_intr(struct dwc2_hsotg * hsotg)179 static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
180 {
181 u32 grxsts, chnum, bcnt, dpid, pktsts;
182 struct dwc2_host_chan *chan;
183
184 if (dbg_perio())
185 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
186
187 grxsts = dwc2_readl(hsotg->regs + GRXSTSP);
188 chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT;
189 chan = hsotg->hc_ptr_array[chnum];
190 if (!chan) {
191 dev_err(hsotg->dev, "Unable to get corresponding channel\n");
192 return;
193 }
194
195 bcnt = (grxsts & GRXSTS_BYTECNT_MASK) >> GRXSTS_BYTECNT_SHIFT;
196 dpid = (grxsts & GRXSTS_DPID_MASK) >> GRXSTS_DPID_SHIFT;
197 pktsts = (grxsts & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT;
198
199 /* Packet Status */
200 if (dbg_perio()) {
201 dev_vdbg(hsotg->dev, " Ch num = %d\n", chnum);
202 dev_vdbg(hsotg->dev, " Count = %d\n", bcnt);
203 dev_vdbg(hsotg->dev, " DPID = %d, chan.dpid = %d\n", dpid,
204 chan->data_pid_start);
205 dev_vdbg(hsotg->dev, " PStatus = %d\n", pktsts);
206 }
207
208 switch (pktsts) {
209 case GRXSTS_PKTSTS_HCHIN:
210 /* Read the data into the host buffer */
211 if (bcnt > 0) {
212 dwc2_read_packet(hsotg, chan->xfer_buf, bcnt);
213
214 /* Update the HC fields for the next packet received */
215 chan->xfer_count += bcnt;
216 chan->xfer_buf += bcnt;
217 }
218 break;
219 case GRXSTS_PKTSTS_HCHIN_XFER_COMP:
220 case GRXSTS_PKTSTS_DATATOGGLEERR:
221 case GRXSTS_PKTSTS_HCHHALTED:
222 /* Handled in interrupt, just ignore data */
223 break;
224 default:
225 dev_err(hsotg->dev,
226 "RxFIFO Level Interrupt: Unknown status %d\n", pktsts);
227 break;
228 }
229 }
230
231 /*
232 * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
233 * data packets may be written to the FIFO for OUT transfers. More requests
234 * may be written to the non-periodic request queue for IN transfers. This
235 * interrupt is enabled only in Slave mode.
236 */
dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg * hsotg)237 static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
238 {
239 dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n");
240 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC);
241 }
242
243 /*
244 * This interrupt occurs when the periodic Tx FIFO is half-empty. More data
245 * packets may be written to the FIFO for OUT transfers. More requests may be
246 * written to the periodic request queue for IN transfers. This interrupt is
247 * enabled only in Slave mode.
248 */
dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg * hsotg)249 static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
250 {
251 if (dbg_perio())
252 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");
253 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);
254 }
255
dwc2_hprt0_enable(struct dwc2_hsotg * hsotg,u32 hprt0,u32 * hprt0_modify)256 static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
257 u32 *hprt0_modify)
258 {
259 struct dwc2_core_params *params = &hsotg->params;
260 int do_reset = 0;
261 u32 usbcfg;
262 u32 prtspd;
263 u32 hcfg;
264 u32 fslspclksel;
265 u32 hfir;
266
267 dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
268
269 /* Every time when port enables calculate HFIR.FrInterval */
270 hfir = dwc2_readl(hsotg->regs + HFIR);
271 hfir &= ~HFIR_FRINT_MASK;
272 hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
273 HFIR_FRINT_MASK;
274 dwc2_writel(hfir, hsotg->regs + HFIR);
275
276 /* Check if we need to adjust the PHY clock speed for low power */
277 if (!params->host_support_fs_ls_low_power) {
278 /* Port has been enabled, set the reset change flag */
279 hsotg->flags.b.port_reset_change = 1;
280 return;
281 }
282
283 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
284 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
285
286 if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
287 /* Low power */
288 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
289 /* Set PHY low power clock select for FS/LS devices */
290 usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
291 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
292 do_reset = 1;
293 }
294
295 hcfg = dwc2_readl(hsotg->regs + HCFG);
296 fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
297 HCFG_FSLSPCLKSEL_SHIFT;
298
299 if (prtspd == HPRT0_SPD_LOW_SPEED &&
300 params->host_ls_low_power_phy_clk) {
301 /* 6 MHZ */
302 dev_vdbg(hsotg->dev,
303 "FS_PHY programming HCFG to 6 MHz\n");
304 if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) {
305 fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
306 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
307 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
308 dwc2_writel(hcfg, hsotg->regs + HCFG);
309 do_reset = 1;
310 }
311 } else {
312 /* 48 MHZ */
313 dev_vdbg(hsotg->dev,
314 "FS_PHY programming HCFG to 48 MHz\n");
315 if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) {
316 fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
317 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
318 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
319 dwc2_writel(hcfg, hsotg->regs + HCFG);
320 do_reset = 1;
321 }
322 }
323 } else {
324 /* Not low power */
325 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
326 usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
327 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
328 do_reset = 1;
329 }
330 }
331
332 if (do_reset) {
333 *hprt0_modify |= HPRT0_RST;
334 dwc2_writel(*hprt0_modify, hsotg->regs + HPRT0);
335 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
336 msecs_to_jiffies(60));
337 } else {
338 /* Port has been enabled, set the reset change flag */
339 hsotg->flags.b.port_reset_change = 1;
340 }
341 }
342
343 /*
344 * There are multiple conditions that can cause a port interrupt. This function
345 * determines which interrupt conditions have occurred and handles them
346 * appropriately.
347 */
dwc2_port_intr(struct dwc2_hsotg * hsotg)348 static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
349 {
350 u32 hprt0;
351 u32 hprt0_modify;
352
353 dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
354
355 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
356 hprt0_modify = hprt0;
357
358 /*
359 * Clear appropriate bits in HPRT0 to clear the interrupt bit in
360 * GINTSTS
361 */
362 hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG |
363 HPRT0_OVRCURRCHG);
364
365 /*
366 * Port Connect Detected
367 * Set flag and clear if detected
368 */
369 if (hprt0 & HPRT0_CONNDET) {
370 dwc2_writel(hprt0_modify | HPRT0_CONNDET, hsotg->regs + HPRT0);
371
372 dev_vdbg(hsotg->dev,
373 "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n",
374 hprt0);
375 dwc2_hcd_connect(hsotg);
376
377 /*
378 * The Hub driver asserts a reset when it sees port connect
379 * status change flag
380 */
381 }
382
383 /*
384 * Port Enable Changed
385 * Clear if detected - Set internal flag if disabled
386 */
387 if (hprt0 & HPRT0_ENACHG) {
388 dwc2_writel(hprt0_modify | HPRT0_ENACHG, hsotg->regs + HPRT0);
389 dev_vdbg(hsotg->dev,
390 " --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n",
391 hprt0, !!(hprt0 & HPRT0_ENA));
392 if (hprt0 & HPRT0_ENA) {
393 hsotg->new_connection = true;
394 dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
395 } else {
396 hsotg->flags.b.port_enable_change = 1;
397 if (hsotg->params.dma_desc_fs_enable) {
398 u32 hcfg;
399
400 hsotg->params.dma_desc_enable = false;
401 hsotg->new_connection = false;
402 hcfg = dwc2_readl(hsotg->regs + HCFG);
403 hcfg &= ~HCFG_DESCDMA;
404 dwc2_writel(hcfg, hsotg->regs + HCFG);
405 }
406 }
407 }
408
409 /* Overcurrent Change Interrupt */
410 if (hprt0 & HPRT0_OVRCURRCHG) {
411 dwc2_writel(hprt0_modify | HPRT0_OVRCURRCHG,
412 hsotg->regs + HPRT0);
413 dev_vdbg(hsotg->dev,
414 " --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n",
415 hprt0);
416 hsotg->flags.b.port_over_current_change = 1;
417 }
418 }
419
420 /*
421 * Gets the actual length of a transfer after the transfer halts. halt_status
422 * holds the reason for the halt.
423 *
424 * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read
425 * is set to 1 upon return if less than the requested number of bytes were
426 * transferred. short_read may also be NULL on entry, in which case it remains
427 * unchanged.
428 */
dwc2_get_actual_xfer_length(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd,enum dwc2_halt_status halt_status,int * short_read)429 static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
430 struct dwc2_host_chan *chan, int chnum,
431 struct dwc2_qtd *qtd,
432 enum dwc2_halt_status halt_status,
433 int *short_read)
434 {
435 u32 hctsiz, count, length;
436
437 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
438
439 if (halt_status == DWC2_HC_XFER_COMPLETE) {
440 if (chan->ep_is_in) {
441 count = (hctsiz & TSIZ_XFERSIZE_MASK) >>
442 TSIZ_XFERSIZE_SHIFT;
443 length = chan->xfer_len - count;
444 if (short_read)
445 *short_read = (count != 0);
446 } else if (chan->qh->do_split) {
447 length = qtd->ssplit_out_xfer_count;
448 } else {
449 length = chan->xfer_len;
450 }
451 } else {
452 /*
453 * Must use the hctsiz.pktcnt field to determine how much data
454 * has been transferred. This field reflects the number of
455 * packets that have been transferred via the USB. This is
456 * always an integral number of packets if the transfer was
457 * halted before its normal completion. (Can't use the
458 * hctsiz.xfersize field because that reflects the number of
459 * bytes transferred via the AHB, not the USB).
460 */
461 count = (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT;
462 length = (chan->start_pkt_count - count) * chan->max_packet;
463 }
464
465 return length;
466 }
467
468 /**
469 * dwc2_update_urb_state() - Updates the state of the URB after a Transfer
470 * Complete interrupt on the host channel. Updates the actual_length field
471 * of the URB based on the number of bytes transferred via the host channel.
472 * Sets the URB status if the data transfer is finished.
473 *
474 * Return: 1 if the data transfer specified by the URB is completely finished,
475 * 0 otherwise
476 */
dwc2_update_urb_state(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_hcd_urb * urb,struct dwc2_qtd * qtd)477 static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
478 struct dwc2_host_chan *chan, int chnum,
479 struct dwc2_hcd_urb *urb,
480 struct dwc2_qtd *qtd)
481 {
482 u32 hctsiz;
483 int xfer_done = 0;
484 int short_read = 0;
485 int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
486 DWC2_HC_XFER_COMPLETE,
487 &short_read);
488
489 if (urb->actual_length + xfer_length > urb->length) {
490 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
491 xfer_length = urb->length - urb->actual_length;
492 }
493
494 dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n",
495 urb->actual_length, xfer_length);
496 urb->actual_length += xfer_length;
497
498 if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK &&
499 (urb->flags & URB_SEND_ZERO_PACKET) &&
500 urb->actual_length >= urb->length &&
501 !(urb->length % chan->max_packet)) {
502 xfer_done = 0;
503 } else if (short_read || urb->actual_length >= urb->length) {
504 xfer_done = 1;
505 urb->status = 0;
506 }
507
508 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
509 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
510 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
511 dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len);
512 dev_vdbg(hsotg->dev, " hctsiz.xfersize %d\n",
513 (hctsiz & TSIZ_XFERSIZE_MASK) >> TSIZ_XFERSIZE_SHIFT);
514 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", urb->length);
515 dev_vdbg(hsotg->dev, " urb->actual_length %d\n", urb->actual_length);
516 dev_vdbg(hsotg->dev, " short_read %d, xfer_done %d\n", short_read,
517 xfer_done);
518
519 return xfer_done;
520 }
521
522 /*
523 * Save the starting data toggle for the next transfer. The data toggle is
524 * saved in the QH for non-control transfers and it's saved in the QTD for
525 * control transfers.
526 */
dwc2_hcd_save_data_toggle(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)527 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
528 struct dwc2_host_chan *chan, int chnum,
529 struct dwc2_qtd *qtd)
530 {
531 u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
532 u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
533
534 if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
535 if (WARN(!chan || !chan->qh,
536 "chan->qh must be specified for non-control eps\n"))
537 return;
538
539 if (pid == TSIZ_SC_MC_PID_DATA0)
540 chan->qh->data_toggle = DWC2_HC_PID_DATA0;
541 else
542 chan->qh->data_toggle = DWC2_HC_PID_DATA1;
543 } else {
544 if (WARN(!qtd,
545 "qtd must be specified for control eps\n"))
546 return;
547
548 if (pid == TSIZ_SC_MC_PID_DATA0)
549 qtd->data_toggle = DWC2_HC_PID_DATA0;
550 else
551 qtd->data_toggle = DWC2_HC_PID_DATA1;
552 }
553 }
554
555 /**
556 * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when
557 * the transfer is stopped for any reason. The fields of the current entry in
558 * the frame descriptor array are set based on the transfer state and the input
559 * halt_status. Completes the Isochronous URB if all the URB frames have been
560 * completed.
561 *
562 * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be
563 * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE.
564 */
dwc2_update_isoc_urb_state(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd,enum dwc2_halt_status halt_status)565 static enum dwc2_halt_status dwc2_update_isoc_urb_state(
566 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
567 int chnum, struct dwc2_qtd *qtd,
568 enum dwc2_halt_status halt_status)
569 {
570 struct dwc2_hcd_iso_packet_desc *frame_desc;
571 struct dwc2_hcd_urb *urb = qtd->urb;
572
573 if (!urb)
574 return DWC2_HC_XFER_NO_HALT_STATUS;
575
576 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
577
578 switch (halt_status) {
579 case DWC2_HC_XFER_COMPLETE:
580 frame_desc->status = 0;
581 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
582 chan, chnum, qtd, halt_status, NULL);
583 break;
584 case DWC2_HC_XFER_FRAME_OVERRUN:
585 urb->error_count++;
586 if (chan->ep_is_in)
587 frame_desc->status = -ENOSR;
588 else
589 frame_desc->status = -ECOMM;
590 frame_desc->actual_length = 0;
591 break;
592 case DWC2_HC_XFER_BABBLE_ERR:
593 urb->error_count++;
594 frame_desc->status = -EOVERFLOW;
595 /* Don't need to update actual_length in this case */
596 break;
597 case DWC2_HC_XFER_XACT_ERR:
598 urb->error_count++;
599 frame_desc->status = -EPROTO;
600 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
601 chan, chnum, qtd, halt_status, NULL);
602
603 /* Skip whole frame */
604 if (chan->qh->do_split &&
605 chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
606 hsotg->params.host_dma) {
607 qtd->complete_split = 0;
608 qtd->isoc_split_offset = 0;
609 }
610
611 break;
612 default:
613 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n",
614 halt_status);
615 break;
616 }
617
618 if (++qtd->isoc_frame_index == urb->packet_count) {
619 /*
620 * urb->status is not used for isoc transfers. The individual
621 * frame_desc statuses are used instead.
622 */
623 dwc2_host_complete(hsotg, qtd, 0);
624 halt_status = DWC2_HC_XFER_URB_COMPLETE;
625 } else {
626 halt_status = DWC2_HC_XFER_COMPLETE;
627 }
628
629 return halt_status;
630 }
631
632 /*
633 * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
634 * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
635 * still linked to the QH, the QH is added to the end of the inactive
636 * non-periodic schedule. For periodic QHs, removes the QH from the periodic
637 * schedule if no more QTDs are linked to the QH.
638 */
dwc2_deactivate_qh(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh,int free_qtd)639 static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
640 int free_qtd)
641 {
642 int continue_split = 0;
643 struct dwc2_qtd *qtd;
644
645 if (dbg_qh(qh))
646 dev_vdbg(hsotg->dev, " %s(%p,%p,%d)\n", __func__,
647 hsotg, qh, free_qtd);
648
649 if (list_empty(&qh->qtd_list)) {
650 dev_dbg(hsotg->dev, "## QTD list empty ##\n");
651 goto no_qtd;
652 }
653
654 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
655
656 if (qtd->complete_split)
657 continue_split = 1;
658 else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID ||
659 qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END)
660 continue_split = 1;
661
662 if (free_qtd) {
663 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
664 continue_split = 0;
665 }
666
667 no_qtd:
668 qh->channel = NULL;
669 dwc2_hcd_qh_deactivate(hsotg, qh, continue_split);
670 }
671
672 /**
673 * dwc2_release_channel() - Releases a host channel for use by other transfers
674 *
675 * @hsotg: The HCD state structure
676 * @chan: The host channel to release
677 * @qtd: The QTD associated with the host channel. This QTD may be
678 * freed if the transfer is complete or an error has occurred.
679 * @halt_status: Reason the channel is being released. This status
680 * determines the actions taken by this function.
681 *
682 * Also attempts to select and queue more transactions since at least one host
683 * channel is available.
684 */
dwc2_release_channel(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,struct dwc2_qtd * qtd,enum dwc2_halt_status halt_status)685 static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
686 struct dwc2_host_chan *chan,
687 struct dwc2_qtd *qtd,
688 enum dwc2_halt_status halt_status)
689 {
690 enum dwc2_transaction_type tr_type;
691 u32 haintmsk;
692 int free_qtd = 0;
693
694 if (dbg_hc(chan))
695 dev_vdbg(hsotg->dev, " %s: channel %d, halt_status %d\n",
696 __func__, chan->hc_num, halt_status);
697
698 switch (halt_status) {
699 case DWC2_HC_XFER_URB_COMPLETE:
700 free_qtd = 1;
701 break;
702 case DWC2_HC_XFER_AHB_ERR:
703 case DWC2_HC_XFER_STALL:
704 case DWC2_HC_XFER_BABBLE_ERR:
705 free_qtd = 1;
706 break;
707 case DWC2_HC_XFER_XACT_ERR:
708 if (qtd && qtd->error_count >= 3) {
709 dev_vdbg(hsotg->dev,
710 " Complete URB with transaction error\n");
711 free_qtd = 1;
712 dwc2_host_complete(hsotg, qtd, -EPROTO);
713 }
714 break;
715 case DWC2_HC_XFER_URB_DEQUEUE:
716 /*
717 * The QTD has already been removed and the QH has been
718 * deactivated. Don't want to do anything except release the
719 * host channel and try to queue more transfers.
720 */
721 goto cleanup;
722 case DWC2_HC_XFER_PERIODIC_INCOMPLETE:
723 dev_vdbg(hsotg->dev, " Complete URB with I/O error\n");
724 free_qtd = 1;
725 dwc2_host_complete(hsotg, qtd, -EIO);
726 break;
727 case DWC2_HC_XFER_NO_HALT_STATUS:
728 default:
729 break;
730 }
731
732 dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
733
734 cleanup:
735 /*
736 * Release the host channel for use by other transfers. The cleanup
737 * function clears the channel interrupt enables and conditions, so
738 * there's no need to clear the Channel Halted interrupt separately.
739 */
740 if (!list_empty(&chan->hc_list_entry))
741 list_del(&chan->hc_list_entry);
742 dwc2_hc_cleanup(hsotg, chan);
743 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
744
745 if (hsotg->params.uframe_sched) {
746 hsotg->available_host_channels++;
747 } else {
748 switch (chan->ep_type) {
749 case USB_ENDPOINT_XFER_CONTROL:
750 case USB_ENDPOINT_XFER_BULK:
751 hsotg->non_periodic_channels--;
752 break;
753 default:
754 /*
755 * Don't release reservations for periodic channels
756 * here. That's done when a periodic transfer is
757 * descheduled (i.e. when the QH is removed from the
758 * periodic schedule).
759 */
760 break;
761 }
762 }
763
764 haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
765 haintmsk &= ~(1 << chan->hc_num);
766 dwc2_writel(haintmsk, hsotg->regs + HAINTMSK);
767
768 /* Try to queue more transfers now that there's a free channel */
769 tr_type = dwc2_hcd_select_transactions(hsotg);
770 if (tr_type != DWC2_TRANSACTION_NONE)
771 dwc2_hcd_queue_transactions(hsotg, tr_type);
772 }
773
774 /*
775 * Halts a host channel. If the channel cannot be halted immediately because
776 * the request queue is full, this function ensures that the FIFO empty
777 * interrupt for the appropriate queue is enabled so that the halt request can
778 * be queued when there is space in the request queue.
779 *
780 * This function may also be called in DMA mode. In that case, the channel is
781 * simply released since the core always halts the channel automatically in
782 * DMA mode.
783 */
dwc2_halt_channel(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,struct dwc2_qtd * qtd,enum dwc2_halt_status halt_status)784 static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
785 struct dwc2_host_chan *chan, struct dwc2_qtd *qtd,
786 enum dwc2_halt_status halt_status)
787 {
788 if (dbg_hc(chan))
789 dev_vdbg(hsotg->dev, "%s()\n", __func__);
790
791 if (hsotg->params.host_dma) {
792 if (dbg_hc(chan))
793 dev_vdbg(hsotg->dev, "DMA enabled\n");
794 dwc2_release_channel(hsotg, chan, qtd, halt_status);
795 return;
796 }
797
798 /* Slave mode processing */
799 dwc2_hc_halt(hsotg, chan, halt_status);
800
801 if (chan->halt_on_queue) {
802 u32 gintmsk;
803
804 dev_vdbg(hsotg->dev, "Halt on queue\n");
805 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
806 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
807 dev_vdbg(hsotg->dev, "control/bulk\n");
808 /*
809 * Make sure the Non-periodic Tx FIFO empty interrupt
810 * is enabled so that the non-periodic schedule will
811 * be processed
812 */
813 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
814 gintmsk |= GINTSTS_NPTXFEMP;
815 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
816 } else {
817 dev_vdbg(hsotg->dev, "isoc/intr\n");
818 /*
819 * Move the QH from the periodic queued schedule to
820 * the periodic assigned schedule. This allows the
821 * halt to be queued when the periodic schedule is
822 * processed.
823 */
824 list_move_tail(&chan->qh->qh_list_entry,
825 &hsotg->periodic_sched_assigned);
826
827 /*
828 * Make sure the Periodic Tx FIFO Empty interrupt is
829 * enabled so that the periodic schedule will be
830 * processed
831 */
832 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
833 gintmsk |= GINTSTS_PTXFEMP;
834 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
835 }
836 }
837 }
838
839 /*
840 * Performs common cleanup for non-periodic transfers after a Transfer
841 * Complete interrupt. This function should be called after any endpoint type
842 * specific handling is finished to release the host channel.
843 */
dwc2_complete_non_periodic_xfer(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd,enum dwc2_halt_status halt_status)844 static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg,
845 struct dwc2_host_chan *chan,
846 int chnum, struct dwc2_qtd *qtd,
847 enum dwc2_halt_status halt_status)
848 {
849 dev_vdbg(hsotg->dev, "%s()\n", __func__);
850
851 qtd->error_count = 0;
852
853 if (chan->hcint & HCINTMSK_NYET) {
854 /*
855 * Got a NYET on the last transaction of the transfer. This
856 * means that the endpoint should be in the PING state at the
857 * beginning of the next transfer.
858 */
859 dev_vdbg(hsotg->dev, "got NYET\n");
860 chan->qh->ping_state = 1;
861 }
862
863 /*
864 * Always halt and release the host channel to make it available for
865 * more transfers. There may still be more phases for a control
866 * transfer or more data packets for a bulk transfer at this point,
867 * but the host channel is still halted. A channel will be reassigned
868 * to the transfer when the non-periodic schedule is processed after
869 * the channel is released. This allows transactions to be queued
870 * properly via dwc2_hcd_queue_transactions, which also enables the
871 * Tx FIFO Empty interrupt if necessary.
872 */
873 if (chan->ep_is_in) {
874 /*
875 * IN transfers in Slave mode require an explicit disable to
876 * halt the channel. (In DMA mode, this call simply releases
877 * the channel.)
878 */
879 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
880 } else {
881 /*
882 * The channel is automatically disabled by the core for OUT
883 * transfers in Slave mode
884 */
885 dwc2_release_channel(hsotg, chan, qtd, halt_status);
886 }
887 }
888
889 /*
890 * Performs common cleanup for periodic transfers after a Transfer Complete
891 * interrupt. This function should be called after any endpoint type specific
892 * handling is finished to release the host channel.
893 */
dwc2_complete_periodic_xfer(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd,enum dwc2_halt_status halt_status)894 static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
895 struct dwc2_host_chan *chan, int chnum,
896 struct dwc2_qtd *qtd,
897 enum dwc2_halt_status halt_status)
898 {
899 u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
900
901 qtd->error_count = 0;
902
903 if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0)
904 /* Core halts channel in these cases */
905 dwc2_release_channel(hsotg, chan, qtd, halt_status);
906 else
907 /* Flush any outstanding requests from the Tx queue */
908 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
909 }
910
dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)911 static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
912 struct dwc2_host_chan *chan, int chnum,
913 struct dwc2_qtd *qtd)
914 {
915 struct dwc2_hcd_iso_packet_desc *frame_desc;
916 u32 len;
917 u32 hctsiz;
918 u32 pid;
919
920 if (!qtd->urb)
921 return 0;
922
923 frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
924 len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
925 DWC2_HC_XFER_COMPLETE, NULL);
926 if (!len && !qtd->isoc_split_offset) {
927 qtd->complete_split = 0;
928 return 0;
929 }
930
931 frame_desc->actual_length += len;
932
933 if (chan->align_buf) {
934 dev_vdbg(hsotg->dev, "non-aligned buffer\n");
935 dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
936 DWC2_KMEM_UNALIGNED_BUF_SIZE, DMA_FROM_DEVICE);
937 memcpy(qtd->urb->buf + (chan->xfer_dma - qtd->urb->dma),
938 chan->qh->dw_align_buf, len);
939 }
940
941 qtd->isoc_split_offset += len;
942
943 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
944 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
945
946 if (frame_desc->actual_length >= frame_desc->length || pid == 0) {
947 frame_desc->status = 0;
948 qtd->isoc_frame_index++;
949 qtd->complete_split = 0;
950 qtd->isoc_split_offset = 0;
951 }
952
953 if (qtd->isoc_frame_index == qtd->urb->packet_count) {
954 dwc2_host_complete(hsotg, qtd, 0);
955 dwc2_release_channel(hsotg, chan, qtd,
956 DWC2_HC_XFER_URB_COMPLETE);
957 } else {
958 dwc2_release_channel(hsotg, chan, qtd,
959 DWC2_HC_XFER_NO_HALT_STATUS);
960 }
961
962 return 1; /* Indicates that channel released */
963 }
964
965 /*
966 * Handles a host channel Transfer Complete interrupt. This handler may be
967 * called in either DMA mode or Slave mode.
968 */
dwc2_hc_xfercomp_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)969 static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
970 struct dwc2_host_chan *chan, int chnum,
971 struct dwc2_qtd *qtd)
972 {
973 struct dwc2_hcd_urb *urb = qtd->urb;
974 enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE;
975 int pipe_type;
976 int urb_xfer_done;
977
978 if (dbg_hc(chan))
979 dev_vdbg(hsotg->dev,
980 "--Host Channel %d Interrupt: Transfer Complete--\n",
981 chnum);
982
983 if (!urb)
984 goto handle_xfercomp_done;
985
986 pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
987
988 if (hsotg->params.dma_desc_enable) {
989 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
990 if (pipe_type == USB_ENDPOINT_XFER_ISOC)
991 /* Do not disable the interrupt, just clear it */
992 return;
993 goto handle_xfercomp_done;
994 }
995
996 /* Handle xfer complete on CSPLIT */
997 if (chan->qh->do_split) {
998 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
999 hsotg->params.host_dma) {
1000 if (qtd->complete_split &&
1001 dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
1002 qtd))
1003 goto handle_xfercomp_done;
1004 } else {
1005 qtd->complete_split = 0;
1006 }
1007 }
1008
1009 /* Update the QTD and URB states */
1010 switch (pipe_type) {
1011 case USB_ENDPOINT_XFER_CONTROL:
1012 switch (qtd->control_phase) {
1013 case DWC2_CONTROL_SETUP:
1014 if (urb->length > 0)
1015 qtd->control_phase = DWC2_CONTROL_DATA;
1016 else
1017 qtd->control_phase = DWC2_CONTROL_STATUS;
1018 dev_vdbg(hsotg->dev,
1019 " Control setup transaction done\n");
1020 halt_status = DWC2_HC_XFER_COMPLETE;
1021 break;
1022 case DWC2_CONTROL_DATA:
1023 urb_xfer_done = dwc2_update_urb_state(hsotg, chan,
1024 chnum, urb, qtd);
1025 if (urb_xfer_done) {
1026 qtd->control_phase = DWC2_CONTROL_STATUS;
1027 dev_vdbg(hsotg->dev,
1028 " Control data transfer done\n");
1029 } else {
1030 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1031 qtd);
1032 }
1033 halt_status = DWC2_HC_XFER_COMPLETE;
1034 break;
1035 case DWC2_CONTROL_STATUS:
1036 dev_vdbg(hsotg->dev, " Control transfer complete\n");
1037 if (urb->status == -EINPROGRESS)
1038 urb->status = 0;
1039 dwc2_host_complete(hsotg, qtd, urb->status);
1040 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1041 break;
1042 }
1043
1044 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1045 halt_status);
1046 break;
1047 case USB_ENDPOINT_XFER_BULK:
1048 dev_vdbg(hsotg->dev, " Bulk transfer complete\n");
1049 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1050 qtd);
1051 if (urb_xfer_done) {
1052 dwc2_host_complete(hsotg, qtd, urb->status);
1053 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1054 } else {
1055 halt_status = DWC2_HC_XFER_COMPLETE;
1056 }
1057
1058 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1059 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1060 halt_status);
1061 break;
1062 case USB_ENDPOINT_XFER_INT:
1063 dev_vdbg(hsotg->dev, " Interrupt transfer complete\n");
1064 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1065 qtd);
1066
1067 /*
1068 * Interrupt URB is done on the first transfer complete
1069 * interrupt
1070 */
1071 if (urb_xfer_done) {
1072 dwc2_host_complete(hsotg, qtd, urb->status);
1073 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1074 } else {
1075 halt_status = DWC2_HC_XFER_COMPLETE;
1076 }
1077
1078 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1079 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1080 halt_status);
1081 break;
1082 case USB_ENDPOINT_XFER_ISOC:
1083 if (dbg_perio())
1084 dev_vdbg(hsotg->dev, " Isochronous transfer complete\n");
1085 if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL)
1086 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1087 chnum, qtd,
1088 DWC2_HC_XFER_COMPLETE);
1089 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1090 halt_status);
1091 break;
1092 }
1093
1094 handle_xfercomp_done:
1095 disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL);
1096 }
1097
1098 /*
1099 * Handles a host channel STALL interrupt. This handler may be called in
1100 * either DMA mode or Slave mode.
1101 */
dwc2_hc_stall_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1102 static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
1103 struct dwc2_host_chan *chan, int chnum,
1104 struct dwc2_qtd *qtd)
1105 {
1106 struct dwc2_hcd_urb *urb = qtd->urb;
1107 int pipe_type;
1108
1109 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
1110 chnum);
1111
1112 if (hsotg->params.dma_desc_enable) {
1113 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1114 DWC2_HC_XFER_STALL);
1115 goto handle_stall_done;
1116 }
1117
1118 if (!urb)
1119 goto handle_stall_halt;
1120
1121 pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1122
1123 if (pipe_type == USB_ENDPOINT_XFER_CONTROL)
1124 dwc2_host_complete(hsotg, qtd, -EPIPE);
1125
1126 if (pipe_type == USB_ENDPOINT_XFER_BULK ||
1127 pipe_type == USB_ENDPOINT_XFER_INT) {
1128 dwc2_host_complete(hsotg, qtd, -EPIPE);
1129 /*
1130 * USB protocol requires resetting the data toggle for bulk
1131 * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1132 * setup command is issued to the endpoint. Anticipate the
1133 * CLEAR_FEATURE command since a STALL has occurred and reset
1134 * the data toggle now.
1135 */
1136 chan->qh->data_toggle = 0;
1137 }
1138
1139 handle_stall_halt:
1140 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL);
1141
1142 handle_stall_done:
1143 disable_hc_int(hsotg, chnum, HCINTMSK_STALL);
1144 }
1145
1146 /*
1147 * Updates the state of the URB when a transfer has been stopped due to an
1148 * abnormal condition before the transfer completes. Modifies the
1149 * actual_length field of the URB to reflect the number of bytes that have
1150 * actually been transferred via the host channel.
1151 */
dwc2_update_urb_state_abn(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_hcd_urb * urb,struct dwc2_qtd * qtd,enum dwc2_halt_status halt_status)1152 static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1153 struct dwc2_host_chan *chan, int chnum,
1154 struct dwc2_hcd_urb *urb,
1155 struct dwc2_qtd *qtd,
1156 enum dwc2_halt_status halt_status)
1157 {
1158 u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,
1159 qtd, halt_status, NULL);
1160 u32 hctsiz;
1161
1162 if (urb->actual_length + xfer_length > urb->length) {
1163 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
1164 xfer_length = urb->length - urb->actual_length;
1165 }
1166
1167 urb->actual_length += xfer_length;
1168
1169 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1170 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1171 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
1172 dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n",
1173 chan->start_pkt_count);
1174 dev_vdbg(hsotg->dev, " hctsiz.pktcnt %d\n",
1175 (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT);
1176 dev_vdbg(hsotg->dev, " chan->max_packet %d\n", chan->max_packet);
1177 dev_vdbg(hsotg->dev, " bytes_transferred %d\n",
1178 xfer_length);
1179 dev_vdbg(hsotg->dev, " urb->actual_length %d\n",
1180 urb->actual_length);
1181 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n",
1182 urb->length);
1183 }
1184
1185 /*
1186 * Handles a host channel NAK interrupt. This handler may be called in either
1187 * DMA mode or Slave mode.
1188 */
dwc2_hc_nak_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1189 static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
1190 struct dwc2_host_chan *chan, int chnum,
1191 struct dwc2_qtd *qtd)
1192 {
1193 if (!qtd) {
1194 dev_dbg(hsotg->dev, "%s: qtd is NULL\n", __func__);
1195 return;
1196 }
1197
1198 if (!qtd->urb) {
1199 dev_dbg(hsotg->dev, "%s: qtd->urb is NULL\n", __func__);
1200 return;
1201 }
1202
1203 if (dbg_hc(chan))
1204 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",
1205 chnum);
1206
1207 /*
1208 * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1209 * interrupt. Re-start the SSPLIT transfer.
1210 */
1211 if (chan->do_split) {
1212 if (chan->complete_split)
1213 qtd->error_count = 0;
1214 qtd->complete_split = 0;
1215 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1216 goto handle_nak_done;
1217 }
1218
1219 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1220 case USB_ENDPOINT_XFER_CONTROL:
1221 case USB_ENDPOINT_XFER_BULK:
1222 if (hsotg->params.host_dma && chan->ep_is_in) {
1223 /*
1224 * NAK interrupts are enabled on bulk/control IN
1225 * transfers in DMA mode for the sole purpose of
1226 * resetting the error count after a transaction error
1227 * occurs. The core will continue transferring data.
1228 */
1229 qtd->error_count = 0;
1230 break;
1231 }
1232
1233 /*
1234 * NAK interrupts normally occur during OUT transfers in DMA
1235 * or Slave mode. For IN transfers, more requests will be
1236 * queued as request queue space is available.
1237 */
1238 qtd->error_count = 0;
1239
1240 if (!chan->qh->ping_state) {
1241 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1242 qtd, DWC2_HC_XFER_NAK);
1243 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1244
1245 if (chan->speed == USB_SPEED_HIGH)
1246 chan->qh->ping_state = 1;
1247 }
1248
1249 /*
1250 * Halt the channel so the transfer can be re-started from
1251 * the appropriate point or the PING protocol will
1252 * start/continue
1253 */
1254 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1255 break;
1256 case USB_ENDPOINT_XFER_INT:
1257 qtd->error_count = 0;
1258 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1259 break;
1260 case USB_ENDPOINT_XFER_ISOC:
1261 /* Should never get called for isochronous transfers */
1262 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n");
1263 break;
1264 }
1265
1266 handle_nak_done:
1267 disable_hc_int(hsotg, chnum, HCINTMSK_NAK);
1268 }
1269
1270 /*
1271 * Handles a host channel ACK interrupt. This interrupt is enabled when
1272 * performing the PING protocol in Slave mode, when errors occur during
1273 * either Slave mode or DMA mode, and during Start Split transactions.
1274 */
dwc2_hc_ack_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1275 static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg,
1276 struct dwc2_host_chan *chan, int chnum,
1277 struct dwc2_qtd *qtd)
1278 {
1279 struct dwc2_hcd_iso_packet_desc *frame_desc;
1280
1281 if (dbg_hc(chan))
1282 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",
1283 chnum);
1284
1285 if (chan->do_split) {
1286 /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */
1287 if (!chan->ep_is_in &&
1288 chan->data_pid_start != DWC2_HC_PID_SETUP)
1289 qtd->ssplit_out_xfer_count = chan->xfer_len;
1290
1291 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) {
1292 qtd->complete_split = 1;
1293 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1294 } else {
1295 /* ISOC OUT */
1296 switch (chan->xact_pos) {
1297 case DWC2_HCSPLT_XACTPOS_ALL:
1298 break;
1299 case DWC2_HCSPLT_XACTPOS_END:
1300 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
1301 qtd->isoc_split_offset = 0;
1302 break;
1303 case DWC2_HCSPLT_XACTPOS_BEGIN:
1304 case DWC2_HCSPLT_XACTPOS_MID:
1305 /*
1306 * For BEGIN or MID, calculate the length for
1307 * the next microframe to determine the correct
1308 * SSPLIT token, either MID or END
1309 */
1310 frame_desc = &qtd->urb->iso_descs[
1311 qtd->isoc_frame_index];
1312 qtd->isoc_split_offset += 188;
1313
1314 if (frame_desc->length - qtd->isoc_split_offset
1315 <= 188)
1316 qtd->isoc_split_pos =
1317 DWC2_HCSPLT_XACTPOS_END;
1318 else
1319 qtd->isoc_split_pos =
1320 DWC2_HCSPLT_XACTPOS_MID;
1321 break;
1322 }
1323 }
1324 } else {
1325 qtd->error_count = 0;
1326
1327 if (chan->qh->ping_state) {
1328 chan->qh->ping_state = 0;
1329 /*
1330 * Halt the channel so the transfer can be re-started
1331 * from the appropriate point. This only happens in
1332 * Slave mode. In DMA mode, the ping_state is cleared
1333 * when the transfer is started because the core
1334 * automatically executes the PING, then the transfer.
1335 */
1336 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1337 }
1338 }
1339
1340 /*
1341 * If the ACK occurred when _not_ in the PING state, let the channel
1342 * continue transferring data after clearing the error count
1343 */
1344 disable_hc_int(hsotg, chnum, HCINTMSK_ACK);
1345 }
1346
1347 /*
1348 * Handles a host channel NYET interrupt. This interrupt should only occur on
1349 * Bulk and Control OUT endpoints and for complete split transactions. If a
1350 * NYET occurs at the same time as a Transfer Complete interrupt, it is
1351 * handled in the xfercomp interrupt handler, not here. This handler may be
1352 * called in either DMA mode or Slave mode.
1353 */
dwc2_hc_nyet_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1354 static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
1355 struct dwc2_host_chan *chan, int chnum,
1356 struct dwc2_qtd *qtd)
1357 {
1358 if (dbg_hc(chan))
1359 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",
1360 chnum);
1361
1362 /*
1363 * NYET on CSPLIT
1364 * re-do the CSPLIT immediately on non-periodic
1365 */
1366 if (chan->do_split && chan->complete_split) {
1367 if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC &&
1368 hsotg->params.host_dma) {
1369 qtd->complete_split = 0;
1370 qtd->isoc_split_offset = 0;
1371 qtd->isoc_frame_index++;
1372 if (qtd->urb &&
1373 qtd->isoc_frame_index == qtd->urb->packet_count) {
1374 dwc2_host_complete(hsotg, qtd, 0);
1375 dwc2_release_channel(hsotg, chan, qtd,
1376 DWC2_HC_XFER_URB_COMPLETE);
1377 } else {
1378 dwc2_release_channel(hsotg, chan, qtd,
1379 DWC2_HC_XFER_NO_HALT_STATUS);
1380 }
1381 goto handle_nyet_done;
1382 }
1383
1384 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1385 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1386 struct dwc2_qh *qh = chan->qh;
1387 bool past_end;
1388
1389 if (!hsotg->params.uframe_sched) {
1390 int frnum = dwc2_hcd_get_frame_number(hsotg);
1391
1392 /* Don't have num_hs_transfers; simple logic */
1393 past_end = dwc2_full_frame_num(frnum) !=
1394 dwc2_full_frame_num(qh->next_active_frame);
1395 } else {
1396 int end_frnum;
1397
1398 /*
1399 * Figure out the end frame based on
1400 * schedule.
1401 *
1402 * We don't want to go on trying again
1403 * and again forever. Let's stop when
1404 * we've done all the transfers that
1405 * were scheduled.
1406 *
1407 * We're going to be comparing
1408 * start_active_frame and
1409 * next_active_frame, both of which
1410 * are 1 before the time the packet
1411 * goes on the wire, so that cancels
1412 * out. Basically if had 1 transfer
1413 * and we saw 1 NYET then we're done.
1414 * We're getting a NYET here so if
1415 * next >= (start + num_transfers)
1416 * we're done. The complexity is that
1417 * for all but ISOC_OUT we skip one
1418 * slot.
1419 */
1420 end_frnum = dwc2_frame_num_inc(
1421 qh->start_active_frame,
1422 qh->num_hs_transfers);
1423
1424 if (qh->ep_type != USB_ENDPOINT_XFER_ISOC ||
1425 qh->ep_is_in)
1426 end_frnum =
1427 dwc2_frame_num_inc(end_frnum, 1);
1428
1429 past_end = dwc2_frame_num_le(
1430 end_frnum, qh->next_active_frame);
1431 }
1432
1433 if (past_end) {
1434 /* Treat this as a transaction error. */
1435 #if 0
1436 /*
1437 * Todo: Fix system performance so this can
1438 * be treated as an error. Right now complete
1439 * splits cannot be scheduled precisely enough
1440 * due to other system activity, so this error
1441 * occurs regularly in Slave mode.
1442 */
1443 qtd->error_count++;
1444 #endif
1445 qtd->complete_split = 0;
1446 dwc2_halt_channel(hsotg, chan, qtd,
1447 DWC2_HC_XFER_XACT_ERR);
1448 /* Todo: add support for isoc release */
1449 goto handle_nyet_done;
1450 }
1451 }
1452
1453 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1454 goto handle_nyet_done;
1455 }
1456
1457 chan->qh->ping_state = 1;
1458 qtd->error_count = 0;
1459
1460 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd,
1461 DWC2_HC_XFER_NYET);
1462 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1463
1464 /*
1465 * Halt the channel and re-start the transfer so the PING protocol
1466 * will start
1467 */
1468 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1469
1470 handle_nyet_done:
1471 disable_hc_int(hsotg, chnum, HCINTMSK_NYET);
1472 }
1473
1474 /*
1475 * Handles a host channel babble interrupt. This handler may be called in
1476 * either DMA mode or Slave mode.
1477 */
dwc2_hc_babble_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1478 static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
1479 struct dwc2_host_chan *chan, int chnum,
1480 struct dwc2_qtd *qtd)
1481 {
1482 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n",
1483 chnum);
1484
1485 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1486
1487 if (hsotg->params.dma_desc_enable) {
1488 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1489 DWC2_HC_XFER_BABBLE_ERR);
1490 goto disable_int;
1491 }
1492
1493 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
1494 dwc2_host_complete(hsotg, qtd, -EOVERFLOW);
1495 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR);
1496 } else {
1497 enum dwc2_halt_status halt_status;
1498
1499 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1500 qtd, DWC2_HC_XFER_BABBLE_ERR);
1501 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1502 }
1503
1504 disable_int:
1505 disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR);
1506 }
1507
1508 /*
1509 * Handles a host channel AHB error interrupt. This handler is only called in
1510 * DMA mode.
1511 */
dwc2_hc_ahberr_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1512 static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1513 struct dwc2_host_chan *chan, int chnum,
1514 struct dwc2_qtd *qtd)
1515 {
1516 struct dwc2_hcd_urb *urb = qtd->urb;
1517 char *pipetype, *speed;
1518 u32 hcchar;
1519 u32 hcsplt;
1520 u32 hctsiz;
1521 u32 hc_dma;
1522
1523 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n",
1524 chnum);
1525
1526 if (!urb)
1527 goto handle_ahberr_halt;
1528
1529 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1530
1531 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1532 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
1533 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1534 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum));
1535
1536 dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1537 dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
1538 dev_err(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma);
1539 dev_err(hsotg->dev, " Device address: %d\n",
1540 dwc2_hcd_get_dev_addr(&urb->pipe_info));
1541 dev_err(hsotg->dev, " Endpoint: %d, %s\n",
1542 dwc2_hcd_get_ep_num(&urb->pipe_info),
1543 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
1544
1545 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
1546 case USB_ENDPOINT_XFER_CONTROL:
1547 pipetype = "CONTROL";
1548 break;
1549 case USB_ENDPOINT_XFER_BULK:
1550 pipetype = "BULK";
1551 break;
1552 case USB_ENDPOINT_XFER_INT:
1553 pipetype = "INTERRUPT";
1554 break;
1555 case USB_ENDPOINT_XFER_ISOC:
1556 pipetype = "ISOCHRONOUS";
1557 break;
1558 default:
1559 pipetype = "UNKNOWN";
1560 break;
1561 }
1562
1563 dev_err(hsotg->dev, " Endpoint type: %s\n", pipetype);
1564
1565 switch (chan->speed) {
1566 case USB_SPEED_HIGH:
1567 speed = "HIGH";
1568 break;
1569 case USB_SPEED_FULL:
1570 speed = "FULL";
1571 break;
1572 case USB_SPEED_LOW:
1573 speed = "LOW";
1574 break;
1575 default:
1576 speed = "UNKNOWN";
1577 break;
1578 }
1579
1580 dev_err(hsotg->dev, " Speed: %s\n", speed);
1581
1582 dev_err(hsotg->dev, " Max packet size: %d (mult %d)\n",
1583 dwc2_hcd_get_maxp(&urb->pipe_info),
1584 dwc2_hcd_get_maxp_mult(&urb->pipe_info));
1585 dev_err(hsotg->dev, " Data buffer length: %d\n", urb->length);
1586 dev_err(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
1587 urb->buf, (unsigned long)urb->dma);
1588 dev_err(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
1589 urb->setup_packet, (unsigned long)urb->setup_dma);
1590 dev_err(hsotg->dev, " Interval: %d\n", urb->interval);
1591
1592 /* Core halts the channel for Descriptor DMA mode */
1593 if (hsotg->params.dma_desc_enable) {
1594 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1595 DWC2_HC_XFER_AHB_ERR);
1596 goto handle_ahberr_done;
1597 }
1598
1599 dwc2_host_complete(hsotg, qtd, -EIO);
1600
1601 handle_ahberr_halt:
1602 /*
1603 * Force a channel halt. Don't call dwc2_halt_channel because that won't
1604 * write to the HCCHARn register in DMA mode to force the halt.
1605 */
1606 dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR);
1607
1608 handle_ahberr_done:
1609 disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR);
1610 }
1611
1612 /*
1613 * Handles a host channel transaction error interrupt. This handler may be
1614 * called in either DMA mode or Slave mode.
1615 */
dwc2_hc_xacterr_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1616 static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1617 struct dwc2_host_chan *chan, int chnum,
1618 struct dwc2_qtd *qtd)
1619 {
1620 dev_dbg(hsotg->dev,
1621 "--Host Channel %d Interrupt: Transaction Error--\n", chnum);
1622
1623 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1624
1625 if (hsotg->params.dma_desc_enable) {
1626 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1627 DWC2_HC_XFER_XACT_ERR);
1628 goto handle_xacterr_done;
1629 }
1630
1631 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1632 case USB_ENDPOINT_XFER_CONTROL:
1633 case USB_ENDPOINT_XFER_BULK:
1634 qtd->error_count++;
1635 if (!chan->qh->ping_state) {
1636 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1637 qtd, DWC2_HC_XFER_XACT_ERR);
1638 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1639 if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH)
1640 chan->qh->ping_state = 1;
1641 }
1642
1643 /*
1644 * Halt the channel so the transfer can be re-started from
1645 * the appropriate point or the PING protocol will start
1646 */
1647 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1648 break;
1649 case USB_ENDPOINT_XFER_INT:
1650 qtd->error_count++;
1651 if (chan->do_split && chan->complete_split)
1652 qtd->complete_split = 0;
1653 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1654 break;
1655 case USB_ENDPOINT_XFER_ISOC:
1656 {
1657 enum dwc2_halt_status halt_status;
1658
1659 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1660 chnum, qtd, DWC2_HC_XFER_XACT_ERR);
1661 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1662 }
1663 break;
1664 }
1665
1666 handle_xacterr_done:
1667 disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR);
1668 }
1669
1670 /*
1671 * Handles a host channel frame overrun interrupt. This handler may be called
1672 * in either DMA mode or Slave mode.
1673 */
dwc2_hc_frmovrun_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1674 static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
1675 struct dwc2_host_chan *chan, int chnum,
1676 struct dwc2_qtd *qtd)
1677 {
1678 enum dwc2_halt_status halt_status;
1679
1680 if (dbg_hc(chan))
1681 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",
1682 chnum);
1683
1684 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1685
1686 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1687 case USB_ENDPOINT_XFER_CONTROL:
1688 case USB_ENDPOINT_XFER_BULK:
1689 break;
1690 case USB_ENDPOINT_XFER_INT:
1691 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1692 break;
1693 case USB_ENDPOINT_XFER_ISOC:
1694 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1695 qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1696 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1697 break;
1698 }
1699
1700 disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN);
1701 }
1702
1703 /*
1704 * Handles a host channel data toggle error interrupt. This handler may be
1705 * called in either DMA mode or Slave mode.
1706 */
dwc2_hc_datatglerr_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1707 static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg,
1708 struct dwc2_host_chan *chan, int chnum,
1709 struct dwc2_qtd *qtd)
1710 {
1711 dev_dbg(hsotg->dev,
1712 "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum);
1713
1714 if (chan->ep_is_in)
1715 qtd->error_count = 0;
1716 else
1717 dev_err(hsotg->dev,
1718 "Data Toggle Error on OUT transfer, channel %d\n",
1719 chnum);
1720
1721 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1722 disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR);
1723 }
1724
1725 /*
1726 * For debug only. It checks that a valid halt status is set and that
1727 * HCCHARn.chdis is clear. If there's a problem, corrective action is
1728 * taken and a warning is issued.
1729 *
1730 * Return: true if halt status is ok, false otherwise
1731 */
dwc2_halt_status_ok(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1732 static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1733 struct dwc2_host_chan *chan, int chnum,
1734 struct dwc2_qtd *qtd)
1735 {
1736 #ifdef DEBUG
1737 u32 hcchar;
1738 u32 hctsiz;
1739 u32 hcintmsk;
1740 u32 hcsplt;
1741
1742 if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) {
1743 /*
1744 * This code is here only as a check. This condition should
1745 * never happen. Ignore the halt if it does occur.
1746 */
1747 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1748 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1749 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1750 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
1751 dev_dbg(hsotg->dev,
1752 "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
1753 __func__);
1754 dev_dbg(hsotg->dev,
1755 "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n",
1756 chnum, hcchar, hctsiz);
1757 dev_dbg(hsotg->dev,
1758 "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n",
1759 chan->hcint, hcintmsk, hcsplt);
1760 if (qtd)
1761 dev_dbg(hsotg->dev, "qtd->complete_split %d\n",
1762 qtd->complete_split);
1763 dev_warn(hsotg->dev,
1764 "%s: no halt status, channel %d, ignoring interrupt\n",
1765 __func__, chnum);
1766 return false;
1767 }
1768
1769 /*
1770 * This code is here only as a check. hcchar.chdis should never be set
1771 * when the halt interrupt occurs. Halt the channel again if it does
1772 * occur.
1773 */
1774 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1775 if (hcchar & HCCHAR_CHDIS) {
1776 dev_warn(hsotg->dev,
1777 "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
1778 __func__, hcchar);
1779 chan->halt_pending = 0;
1780 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status);
1781 return false;
1782 }
1783 #endif
1784
1785 return true;
1786 }
1787
1788 /*
1789 * Handles a host Channel Halted interrupt in DMA mode. This handler
1790 * determines the reason the channel halted and proceeds accordingly.
1791 */
dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1792 static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1793 struct dwc2_host_chan *chan, int chnum,
1794 struct dwc2_qtd *qtd)
1795 {
1796 u32 hcintmsk;
1797 int out_nak_enh = 0;
1798
1799 if (dbg_hc(chan))
1800 dev_vdbg(hsotg->dev,
1801 "--Host Channel %d Interrupt: DMA Channel Halted--\n",
1802 chnum);
1803
1804 /*
1805 * For core with OUT NAK enhancement, the flow for high-speed
1806 * CONTROL/BULK OUT is handled a little differently
1807 */
1808 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) {
1809 if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in &&
1810 (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1811 chan->ep_type == USB_ENDPOINT_XFER_BULK)) {
1812 out_nak_enh = 1;
1813 }
1814 }
1815
1816 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1817 (chan->halt_status == DWC2_HC_XFER_AHB_ERR &&
1818 !hsotg->params.dma_desc_enable)) {
1819 if (hsotg->params.dma_desc_enable)
1820 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1821 chan->halt_status);
1822 else
1823 /*
1824 * Just release the channel. A dequeue can happen on a
1825 * transfer timeout. In the case of an AHB Error, the
1826 * channel was forced to halt because there's no way to
1827 * gracefully recover.
1828 */
1829 dwc2_release_channel(hsotg, chan, qtd,
1830 chan->halt_status);
1831 return;
1832 }
1833
1834 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1835
1836 if (chan->hcint & HCINTMSK_XFERCOMPL) {
1837 /*
1838 * Todo: This is here because of a possible hardware bug. Spec
1839 * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1840 * interrupt w/ACK bit set should occur, but I only see the
1841 * XFERCOMP bit, even with it masked out. This is a workaround
1842 * for that behavior. Should fix this when hardware is fixed.
1843 */
1844 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in)
1845 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1846 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1847 } else if (chan->hcint & HCINTMSK_STALL) {
1848 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
1849 } else if ((chan->hcint & HCINTMSK_XACTERR) &&
1850 !hsotg->params.dma_desc_enable) {
1851 if (out_nak_enh) {
1852 if (chan->hcint &
1853 (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) {
1854 dev_vdbg(hsotg->dev,
1855 "XactErr with NYET/NAK/ACK\n");
1856 qtd->error_count = 0;
1857 } else {
1858 dev_vdbg(hsotg->dev,
1859 "XactErr without NYET/NAK/ACK\n");
1860 }
1861 }
1862
1863 /*
1864 * Must handle xacterr before nak or ack. Could get a xacterr
1865 * at the same time as either of these on a BULK/CONTROL OUT
1866 * that started with a PING. The xacterr takes precedence.
1867 */
1868 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1869 } else if ((chan->hcint & HCINTMSK_XCS_XACT) &&
1870 hsotg->params.dma_desc_enable) {
1871 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1872 } else if ((chan->hcint & HCINTMSK_AHBERR) &&
1873 hsotg->params.dma_desc_enable) {
1874 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
1875 } else if (chan->hcint & HCINTMSK_BBLERR) {
1876 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
1877 } else if (chan->hcint & HCINTMSK_FRMOVRUN) {
1878 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
1879 } else if (!out_nak_enh) {
1880 if (chan->hcint & HCINTMSK_NYET) {
1881 /*
1882 * Must handle nyet before nak or ack. Could get a nyet
1883 * at the same time as either of those on a BULK/CONTROL
1884 * OUT that started with a PING. The nyet takes
1885 * precedence.
1886 */
1887 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
1888 } else if ((chan->hcint & HCINTMSK_NAK) &&
1889 !(hcintmsk & HCINTMSK_NAK)) {
1890 /*
1891 * If nak is not masked, it's because a non-split IN
1892 * transfer is in an error state. In that case, the nak
1893 * is handled by the nak interrupt handler, not here.
1894 * Handle nak here for BULK/CONTROL OUT transfers, which
1895 * halt on a NAK to allow rewinding the buffer pointer.
1896 */
1897 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
1898 } else if ((chan->hcint & HCINTMSK_ACK) &&
1899 !(hcintmsk & HCINTMSK_ACK)) {
1900 /*
1901 * If ack is not masked, it's because a non-split IN
1902 * transfer is in an error state. In that case, the ack
1903 * is handled by the ack interrupt handler, not here.
1904 * Handle ack here for split transfers. Start splits
1905 * halt on ACK.
1906 */
1907 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1908 } else {
1909 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1910 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1911 /*
1912 * A periodic transfer halted with no other
1913 * channel interrupts set. Assume it was halted
1914 * by the core because it could not be completed
1915 * in its scheduled (micro)frame.
1916 */
1917 dev_dbg(hsotg->dev,
1918 "%s: Halt channel %d (assume incomplete periodic transfer)\n",
1919 __func__, chnum);
1920 dwc2_halt_channel(hsotg, chan, qtd,
1921 DWC2_HC_XFER_PERIODIC_INCOMPLETE);
1922 } else {
1923 dev_err(hsotg->dev,
1924 "%s: Channel %d - ChHltd set, but reason is unknown\n",
1925 __func__, chnum);
1926 dev_err(hsotg->dev,
1927 "hcint 0x%08x, intsts 0x%08x\n",
1928 chan->hcint,
1929 dwc2_readl(hsotg->regs + GINTSTS));
1930 goto error;
1931 }
1932 }
1933 } else {
1934 dev_info(hsotg->dev,
1935 "NYET/NAK/ACK/other in non-error case, 0x%08x\n",
1936 chan->hcint);
1937 error:
1938 /* Failthrough: use 3-strikes rule */
1939 qtd->error_count++;
1940 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1941 qtd, DWC2_HC_XFER_XACT_ERR);
1942 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1943 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1944 }
1945 }
1946
1947 /*
1948 * Handles a host channel Channel Halted interrupt
1949 *
1950 * In slave mode, this handler is called only when the driver specifically
1951 * requests a halt. This occurs during handling other host channel interrupts
1952 * (e.g. nak, xacterr, stall, nyet, etc.).
1953 *
1954 * In DMA mode, this is the interrupt that occurs when the core has finished
1955 * processing a transfer on a channel. Other host channel interrupts (except
1956 * ahberr) are disabled in DMA mode.
1957 */
dwc2_hc_chhltd_intr(struct dwc2_hsotg * hsotg,struct dwc2_host_chan * chan,int chnum,struct dwc2_qtd * qtd)1958 static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
1959 struct dwc2_host_chan *chan, int chnum,
1960 struct dwc2_qtd *qtd)
1961 {
1962 if (dbg_hc(chan))
1963 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
1964 chnum);
1965
1966 if (hsotg->params.host_dma) {
1967 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
1968 } else {
1969 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
1970 return;
1971 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
1972 }
1973 }
1974
1975 /*
1976 * Check if the given qtd is still the top of the list (and thus valid).
1977 *
1978 * If dwc2_hcd_qtd_unlink_and_free() has been called since we grabbed
1979 * the qtd from the top of the list, this will return false (otherwise true).
1980 */
dwc2_check_qtd_still_ok(struct dwc2_qtd * qtd,struct dwc2_qh * qh)1981 static bool dwc2_check_qtd_still_ok(struct dwc2_qtd *qtd, struct dwc2_qh *qh)
1982 {
1983 struct dwc2_qtd *cur_head;
1984
1985 if (!qh)
1986 return false;
1987
1988 cur_head = list_first_entry(&qh->qtd_list, struct dwc2_qtd,
1989 qtd_list_entry);
1990 return (cur_head == qtd);
1991 }
1992
1993 /* Handles interrupt for a specific Host Channel */
dwc2_hc_n_intr(struct dwc2_hsotg * hsotg,int chnum)1994 static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
1995 {
1996 struct dwc2_qtd *qtd;
1997 struct dwc2_host_chan *chan;
1998 u32 hcint, hcintmsk;
1999
2000 chan = hsotg->hc_ptr_array[chnum];
2001
2002 hcint = dwc2_readl(hsotg->regs + HCINT(chnum));
2003 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
2004 if (!chan) {
2005 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
2006 dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
2007 return;
2008 }
2009
2010 if (dbg_hc(chan)) {
2011 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",
2012 chnum);
2013 dev_vdbg(hsotg->dev,
2014 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2015 hcint, hcintmsk, hcint & hcintmsk);
2016 }
2017
2018 dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
2019
2020 /*
2021 * If we got an interrupt after someone called
2022 * dwc2_hcd_endpoint_disable() we don't want to crash below
2023 */
2024 if (!chan->qh) {
2025 dev_warn(hsotg->dev, "Interrupt on disabled channel\n");
2026 return;
2027 }
2028
2029 chan->hcint = hcint;
2030 hcint &= hcintmsk;
2031
2032 /*
2033 * If the channel was halted due to a dequeue, the qtd list might
2034 * be empty or at least the first entry will not be the active qtd.
2035 * In this case, take a shortcut and just release the channel.
2036 */
2037 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) {
2038 /*
2039 * If the channel was halted, this should be the only
2040 * interrupt unmasked
2041 */
2042 WARN_ON(hcint != HCINTMSK_CHHLTD);
2043 if (hsotg->params.dma_desc_enable)
2044 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
2045 chan->halt_status);
2046 else
2047 dwc2_release_channel(hsotg, chan, NULL,
2048 chan->halt_status);
2049 return;
2050 }
2051
2052 if (list_empty(&chan->qh->qtd_list)) {
2053 /*
2054 * TODO: Will this ever happen with the
2055 * DWC2_HC_XFER_URB_DEQUEUE handling above?
2056 */
2057 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n",
2058 chnum);
2059 dev_dbg(hsotg->dev,
2060 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2061 chan->hcint, hcintmsk, hcint);
2062 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2063 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD);
2064 chan->hcint = 0;
2065 return;
2066 }
2067
2068 qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd,
2069 qtd_list_entry);
2070
2071 if (!hsotg->params.host_dma) {
2072 if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD)
2073 hcint &= ~HCINTMSK_CHHLTD;
2074 }
2075
2076 if (hcint & HCINTMSK_XFERCOMPL) {
2077 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
2078 /*
2079 * If NYET occurred at same time as Xfer Complete, the NYET is
2080 * handled by the Xfer Complete interrupt handler. Don't want
2081 * to call the NYET interrupt handler in this case.
2082 */
2083 hcint &= ~HCINTMSK_NYET;
2084 }
2085
2086 if (hcint & HCINTMSK_CHHLTD) {
2087 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd);
2088 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2089 goto exit;
2090 }
2091 if (hcint & HCINTMSK_AHBERR) {
2092 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
2093 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2094 goto exit;
2095 }
2096 if (hcint & HCINTMSK_STALL) {
2097 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
2098 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2099 goto exit;
2100 }
2101 if (hcint & HCINTMSK_NAK) {
2102 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
2103 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2104 goto exit;
2105 }
2106 if (hcint & HCINTMSK_ACK) {
2107 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
2108 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2109 goto exit;
2110 }
2111 if (hcint & HCINTMSK_NYET) {
2112 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
2113 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2114 goto exit;
2115 }
2116 if (hcint & HCINTMSK_XACTERR) {
2117 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
2118 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2119 goto exit;
2120 }
2121 if (hcint & HCINTMSK_BBLERR) {
2122 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
2123 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2124 goto exit;
2125 }
2126 if (hcint & HCINTMSK_FRMOVRUN) {
2127 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
2128 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2129 goto exit;
2130 }
2131 if (hcint & HCINTMSK_DATATGLERR) {
2132 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd);
2133 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2134 goto exit;
2135 }
2136
2137 exit:
2138 chan->hcint = 0;
2139 }
2140
2141 /*
2142 * This interrupt indicates that one or more host channels has a pending
2143 * interrupt. There are multiple conditions that can cause each host channel
2144 * interrupt. This function determines which conditions have occurred for each
2145 * host channel interrupt and handles them appropriately.
2146 */
dwc2_hc_intr(struct dwc2_hsotg * hsotg)2147 static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2148 {
2149 u32 haint;
2150 int i;
2151 struct dwc2_host_chan *chan, *chan_tmp;
2152
2153 haint = dwc2_readl(hsotg->regs + HAINT);
2154 if (dbg_perio()) {
2155 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2156
2157 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
2158 }
2159
2160 /*
2161 * According to USB 2.0 spec section 11.18.8, a host must
2162 * issue complete-split transactions in a microframe for a
2163 * set of full-/low-speed endpoints in the same relative
2164 * order as the start-splits were issued in a microframe for.
2165 */
2166 list_for_each_entry_safe(chan, chan_tmp, &hsotg->split_order,
2167 split_order_list_entry) {
2168 int hc_num = chan->hc_num;
2169
2170 if (haint & (1 << hc_num)) {
2171 dwc2_hc_n_intr(hsotg, hc_num);
2172 haint &= ~(1 << hc_num);
2173 }
2174 }
2175
2176 for (i = 0; i < hsotg->params.host_channels; i++) {
2177 if (haint & (1 << i))
2178 dwc2_hc_n_intr(hsotg, i);
2179 }
2180 }
2181
2182 /* This function handles interrupts for the HCD */
dwc2_handle_hcd_intr(struct dwc2_hsotg * hsotg)2183 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
2184 {
2185 u32 gintsts, dbg_gintsts;
2186 irqreturn_t retval = IRQ_NONE;
2187
2188 if (!dwc2_is_controller_alive(hsotg)) {
2189 dev_warn(hsotg->dev, "Controller is dead\n");
2190 return retval;
2191 }
2192
2193 spin_lock(&hsotg->lock);
2194
2195 /* Check if HOST Mode */
2196 if (dwc2_is_host_mode(hsotg)) {
2197 gintsts = dwc2_read_core_intr(hsotg);
2198 if (!gintsts) {
2199 spin_unlock(&hsotg->lock);
2200 return retval;
2201 }
2202
2203 retval = IRQ_HANDLED;
2204
2205 dbg_gintsts = gintsts;
2206 #ifndef DEBUG_SOF
2207 dbg_gintsts &= ~GINTSTS_SOF;
2208 #endif
2209 if (!dbg_perio())
2210 dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL |
2211 GINTSTS_PTXFEMP);
2212
2213 /* Only print if there are any non-suppressed interrupts left */
2214 if (dbg_gintsts)
2215 dev_vdbg(hsotg->dev,
2216 "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
2217 gintsts);
2218
2219 if (gintsts & GINTSTS_SOF)
2220 dwc2_sof_intr(hsotg);
2221 if (gintsts & GINTSTS_RXFLVL)
2222 dwc2_rx_fifo_level_intr(hsotg);
2223 if (gintsts & GINTSTS_NPTXFEMP)
2224 dwc2_np_tx_fifo_empty_intr(hsotg);
2225 if (gintsts & GINTSTS_PRTINT)
2226 dwc2_port_intr(hsotg);
2227 if (gintsts & GINTSTS_HCHINT)
2228 dwc2_hc_intr(hsotg);
2229 if (gintsts & GINTSTS_PTXFEMP)
2230 dwc2_perio_tx_fifo_empty_intr(hsotg);
2231
2232 if (dbg_gintsts) {
2233 dev_vdbg(hsotg->dev,
2234 "DWC OTG HCD Finished Servicing Interrupts\n");
2235 dev_vdbg(hsotg->dev,
2236 "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
2237 dwc2_readl(hsotg->regs + GINTSTS),
2238 dwc2_readl(hsotg->regs + GINTMSK));
2239 }
2240 }
2241
2242 spin_unlock(&hsotg->lock);
2243
2244 return retval;
2245 }
2246