1 /**
2 * core.c - DesignWare USB3 DRD Controller Core file
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include <linux/version.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/io.h>
32 #include <linux/list.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/of.h>
36 #include <linux/acpi.h>
37 #include <linux/pinctrl/consumer.h>
38
39 #include <linux/usb/ch9.h>
40 #include <linux/usb/gadget.h>
41 #include <linux/usb/of.h>
42 #include <linux/usb/otg.h>
43
44 #include "core.h"
45 #include "gadget.h"
46 #include "io.h"
47
48 #include "debug.h"
49
50 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
51
52 /**
53 * dwc3_get_dr_mode - Validates and sets dr_mode
54 * @dwc: pointer to our context structure
55 */
dwc3_get_dr_mode(struct dwc3 * dwc)56 static int dwc3_get_dr_mode(struct dwc3 *dwc)
57 {
58 enum usb_dr_mode mode;
59 struct device *dev = dwc->dev;
60 unsigned int hw_mode;
61
62 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
63 dwc->dr_mode = USB_DR_MODE_OTG;
64
65 mode = dwc->dr_mode;
66 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
67
68 switch (hw_mode) {
69 case DWC3_GHWPARAMS0_MODE_GADGET:
70 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
71 dev_err(dev,
72 "Controller does not support host mode.\n");
73 return -EINVAL;
74 }
75 mode = USB_DR_MODE_PERIPHERAL;
76 break;
77 case DWC3_GHWPARAMS0_MODE_HOST:
78 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
79 dev_err(dev,
80 "Controller does not support device mode.\n");
81 return -EINVAL;
82 }
83 mode = USB_DR_MODE_HOST;
84 break;
85 default:
86 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
87 mode = USB_DR_MODE_HOST;
88 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
89 mode = USB_DR_MODE_PERIPHERAL;
90 }
91
92 if (mode != dwc->dr_mode) {
93 dev_warn(dev,
94 "Configuration mismatch. dr_mode forced to %s\n",
95 mode == USB_DR_MODE_HOST ? "host" : "gadget");
96
97 dwc->dr_mode = mode;
98 }
99
100 return 0;
101 }
102
103 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
104 static int dwc3_event_buffers_setup(struct dwc3 *dwc);
105
dwc3_set_prtcap(struct dwc3 * dwc,u32 mode)106 static void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
107 {
108 u32 reg;
109
110 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
111 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
112 reg |= DWC3_GCTL_PRTCAPDIR(mode);
113 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
114 }
115
__dwc3_set_mode(struct work_struct * work)116 static void __dwc3_set_mode(struct work_struct *work)
117 {
118 struct dwc3 *dwc = work_to_dwc(work);
119 unsigned long flags;
120 int ret;
121
122 if (!dwc->desired_dr_role)
123 return;
124
125 if (dwc->desired_dr_role == dwc->current_dr_role)
126 return;
127
128 if (dwc->dr_mode != USB_DR_MODE_OTG)
129 return;
130
131 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG)
132 return;
133
134 switch (dwc->current_dr_role) {
135 case DWC3_GCTL_PRTCAP_HOST:
136 dwc3_host_exit(dwc);
137 break;
138 case DWC3_GCTL_PRTCAP_DEVICE:
139 dwc3_gadget_exit(dwc);
140 dwc3_event_buffers_cleanup(dwc);
141 break;
142 default:
143 break;
144 }
145
146 spin_lock_irqsave(&dwc->lock, flags);
147
148 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
149
150 dwc->current_dr_role = dwc->desired_dr_role;
151
152 spin_unlock_irqrestore(&dwc->lock, flags);
153
154 switch (dwc->desired_dr_role) {
155 case DWC3_GCTL_PRTCAP_HOST:
156 ret = dwc3_host_init(dwc);
157 if (ret) {
158 dev_err(dwc->dev, "failed to initialize host\n");
159 } else {
160 if (dwc->usb2_phy)
161 otg_set_vbus(dwc->usb2_phy->otg, true);
162 if (dwc->usb2_generic_phy)
163 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
164
165 }
166 break;
167 case DWC3_GCTL_PRTCAP_DEVICE:
168 dwc3_event_buffers_setup(dwc);
169
170 if (dwc->usb2_phy)
171 otg_set_vbus(dwc->usb2_phy->otg, false);
172 if (dwc->usb2_generic_phy)
173 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
174
175 ret = dwc3_gadget_init(dwc);
176 if (ret)
177 dev_err(dwc->dev, "failed to initialize peripheral\n");
178 break;
179 default:
180 break;
181 }
182 }
183
dwc3_set_mode(struct dwc3 * dwc,u32 mode)184 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
185 {
186 unsigned long flags;
187
188 spin_lock_irqsave(&dwc->lock, flags);
189 dwc->desired_dr_role = mode;
190 spin_unlock_irqrestore(&dwc->lock, flags);
191
192 queue_work(system_freezable_wq, &dwc->drd_work);
193 }
194
dwc3_core_fifo_space(struct dwc3_ep * dep,u8 type)195 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
196 {
197 struct dwc3 *dwc = dep->dwc;
198 u32 reg;
199
200 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
201 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
202 DWC3_GDBGFIFOSPACE_TYPE(type));
203
204 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
205
206 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
207 }
208
209 /**
210 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
211 * @dwc: pointer to our context structure
212 */
dwc3_core_soft_reset(struct dwc3 * dwc)213 static int dwc3_core_soft_reset(struct dwc3 *dwc)
214 {
215 u32 reg;
216 int retries = 1000;
217 int ret;
218
219 usb_phy_init(dwc->usb2_phy);
220 usb_phy_init(dwc->usb3_phy);
221 ret = phy_init(dwc->usb2_generic_phy);
222 if (ret < 0)
223 return ret;
224
225 ret = phy_init(dwc->usb3_generic_phy);
226 if (ret < 0) {
227 phy_exit(dwc->usb2_generic_phy);
228 return ret;
229 }
230
231 /*
232 * We're resetting only the device side because, if we're in host mode,
233 * XHCI driver will reset the host block. If dwc3 was configured for
234 * host-only mode, then we can return early.
235 */
236 if (dwc->dr_mode == USB_DR_MODE_HOST)
237 return 0;
238
239 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
240 reg |= DWC3_DCTL_CSFTRST;
241 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
242
243 do {
244 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
245 if (!(reg & DWC3_DCTL_CSFTRST))
246 goto done;
247
248 udelay(1);
249 } while (--retries);
250
251 phy_exit(dwc->usb3_generic_phy);
252 phy_exit(dwc->usb2_generic_phy);
253
254 return -ETIMEDOUT;
255
256 done:
257 /*
258 * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
259 * we must wait at least 50ms before accessing the PHY domain
260 * (synchronization delay). DWC_usb31 programming guide section 1.3.2.
261 */
262 if (dwc3_is_usb31(dwc))
263 msleep(50);
264
265 return 0;
266 }
267
268 /*
269 * dwc3_frame_length_adjustment - Adjusts frame length if required
270 * @dwc3: Pointer to our controller context structure
271 */
dwc3_frame_length_adjustment(struct dwc3 * dwc)272 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
273 {
274 u32 reg;
275 u32 dft;
276
277 if (dwc->revision < DWC3_REVISION_250A)
278 return;
279
280 if (dwc->fladj == 0)
281 return;
282
283 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
284 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
285 if (dft != dwc->fladj) {
286 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
287 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
288 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
289 }
290 }
291
292 /**
293 * dwc3_free_one_event_buffer - Frees one event buffer
294 * @dwc: Pointer to our controller context structure
295 * @evt: Pointer to event buffer to be freed
296 */
dwc3_free_one_event_buffer(struct dwc3 * dwc,struct dwc3_event_buffer * evt)297 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
298 struct dwc3_event_buffer *evt)
299 {
300 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
301 }
302
303 /**
304 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
305 * @dwc: Pointer to our controller context structure
306 * @length: size of the event buffer
307 *
308 * Returns a pointer to the allocated event buffer structure on success
309 * otherwise ERR_PTR(errno).
310 */
dwc3_alloc_one_event_buffer(struct dwc3 * dwc,unsigned length)311 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
312 unsigned length)
313 {
314 struct dwc3_event_buffer *evt;
315
316 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
317 if (!evt)
318 return ERR_PTR(-ENOMEM);
319
320 evt->dwc = dwc;
321 evt->length = length;
322 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
323 if (!evt->cache)
324 return ERR_PTR(-ENOMEM);
325
326 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
327 &evt->dma, GFP_KERNEL);
328 if (!evt->buf)
329 return ERR_PTR(-ENOMEM);
330
331 return evt;
332 }
333
334 /**
335 * dwc3_free_event_buffers - frees all allocated event buffers
336 * @dwc: Pointer to our controller context structure
337 */
dwc3_free_event_buffers(struct dwc3 * dwc)338 static void dwc3_free_event_buffers(struct dwc3 *dwc)
339 {
340 struct dwc3_event_buffer *evt;
341
342 evt = dwc->ev_buf;
343 if (evt)
344 dwc3_free_one_event_buffer(dwc, evt);
345 }
346
347 /**
348 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
349 * @dwc: pointer to our controller context structure
350 * @length: size of event buffer
351 *
352 * Returns 0 on success otherwise negative errno. In the error case, dwc
353 * may contain some buffers allocated but not all which were requested.
354 */
dwc3_alloc_event_buffers(struct dwc3 * dwc,unsigned length)355 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
356 {
357 struct dwc3_event_buffer *evt;
358
359 evt = dwc3_alloc_one_event_buffer(dwc, length);
360 if (IS_ERR(evt)) {
361 dev_err(dwc->dev, "can't allocate event buffer\n");
362 return PTR_ERR(evt);
363 }
364 dwc->ev_buf = evt;
365
366 return 0;
367 }
368
369 /**
370 * dwc3_event_buffers_setup - setup our allocated event buffers
371 * @dwc: pointer to our controller context structure
372 *
373 * Returns 0 on success otherwise negative errno.
374 */
dwc3_event_buffers_setup(struct dwc3 * dwc)375 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
376 {
377 struct dwc3_event_buffer *evt;
378
379 evt = dwc->ev_buf;
380 evt->lpos = 0;
381 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
382 lower_32_bits(evt->dma));
383 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
384 upper_32_bits(evt->dma));
385 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
386 DWC3_GEVNTSIZ_SIZE(evt->length));
387 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
388
389 return 0;
390 }
391
dwc3_event_buffers_cleanup(struct dwc3 * dwc)392 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
393 {
394 struct dwc3_event_buffer *evt;
395
396 evt = dwc->ev_buf;
397
398 evt->lpos = 0;
399
400 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
401 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
402 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
403 | DWC3_GEVNTSIZ_SIZE(0));
404 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
405 }
406
dwc3_alloc_scratch_buffers(struct dwc3 * dwc)407 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
408 {
409 if (!dwc->has_hibernation)
410 return 0;
411
412 if (!dwc->nr_scratch)
413 return 0;
414
415 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
416 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
417 if (!dwc->scratchbuf)
418 return -ENOMEM;
419
420 return 0;
421 }
422
dwc3_setup_scratch_buffers(struct dwc3 * dwc)423 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
424 {
425 dma_addr_t scratch_addr;
426 u32 param;
427 int ret;
428
429 if (!dwc->has_hibernation)
430 return 0;
431
432 if (!dwc->nr_scratch)
433 return 0;
434
435 /* should never fall here */
436 if (!WARN_ON(dwc->scratchbuf))
437 return 0;
438
439 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
440 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
441 DMA_BIDIRECTIONAL);
442 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
443 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
444 ret = -EFAULT;
445 goto err0;
446 }
447
448 dwc->scratch_addr = scratch_addr;
449
450 param = lower_32_bits(scratch_addr);
451
452 ret = dwc3_send_gadget_generic_command(dwc,
453 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
454 if (ret < 0)
455 goto err1;
456
457 param = upper_32_bits(scratch_addr);
458
459 ret = dwc3_send_gadget_generic_command(dwc,
460 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
461 if (ret < 0)
462 goto err1;
463
464 return 0;
465
466 err1:
467 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
468 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
469
470 err0:
471 return ret;
472 }
473
dwc3_free_scratch_buffers(struct dwc3 * dwc)474 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
475 {
476 if (!dwc->has_hibernation)
477 return;
478
479 if (!dwc->nr_scratch)
480 return;
481
482 /* should never fall here */
483 if (!WARN_ON(dwc->scratchbuf))
484 return;
485
486 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
487 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
488 kfree(dwc->scratchbuf);
489 }
490
dwc3_core_num_eps(struct dwc3 * dwc)491 static void dwc3_core_num_eps(struct dwc3 *dwc)
492 {
493 struct dwc3_hwparams *parms = &dwc->hwparams;
494
495 dwc->num_eps = DWC3_NUM_EPS(parms);
496 }
497
dwc3_cache_hwparams(struct dwc3 * dwc)498 static void dwc3_cache_hwparams(struct dwc3 *dwc)
499 {
500 struct dwc3_hwparams *parms = &dwc->hwparams;
501
502 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
503 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
504 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
505 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
506 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
507 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
508 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
509 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
510 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
511 }
512
dwc3_core_ulpi_init(struct dwc3 * dwc)513 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
514 {
515 int intf;
516 int ret = 0;
517
518 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
519
520 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
521 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
522 dwc->hsphy_interface &&
523 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
524 ret = dwc3_ulpi_init(dwc);
525
526 return ret;
527 }
528
529 /**
530 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
531 * @dwc: Pointer to our controller context structure
532 *
533 * Returns 0 on success. The USB PHY interfaces are configured but not
534 * initialized. The PHY interfaces and the PHYs get initialized together with
535 * the core in dwc3_core_init.
536 */
dwc3_phy_setup(struct dwc3 * dwc)537 static int dwc3_phy_setup(struct dwc3 *dwc)
538 {
539 u32 reg;
540
541 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
542
543 /*
544 * Make sure UX_EXIT_PX is cleared as that causes issues with some
545 * PHYs. Also, this bit is not supposed to be used in normal operation.
546 */
547 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
548
549 /*
550 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
551 * to '0' during coreConsultant configuration. So default value
552 * will be '0' when the core is reset. Application needs to set it
553 * to '1' after the core initialization is completed.
554 */
555 if (dwc->revision > DWC3_REVISION_194A)
556 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
557
558 if (dwc->u2ss_inp3_quirk)
559 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
560
561 if (dwc->dis_rxdet_inp3_quirk)
562 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
563
564 if (dwc->req_p1p2p3_quirk)
565 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
566
567 if (dwc->del_p1p2p3_quirk)
568 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
569
570 if (dwc->del_phy_power_chg_quirk)
571 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
572
573 if (dwc->lfps_filter_quirk)
574 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
575
576 if (dwc->rx_detect_poll_quirk)
577 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
578
579 if (dwc->tx_de_emphasis_quirk)
580 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
581
582 if (dwc->dis_u3_susphy_quirk)
583 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
584
585 if (dwc->dis_del_phy_power_chg_quirk)
586 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
587
588 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
589
590 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
591
592 /* Select the HS PHY interface */
593 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
594 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
595 if (dwc->hsphy_interface &&
596 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
597 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
598 break;
599 } else if (dwc->hsphy_interface &&
600 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
601 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
602 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
603 } else {
604 /* Relying on default value. */
605 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
606 break;
607 }
608 /* FALLTHROUGH */
609 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
610 /* FALLTHROUGH */
611 default:
612 break;
613 }
614
615 switch (dwc->hsphy_mode) {
616 case USBPHY_INTERFACE_MODE_UTMI:
617 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
618 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
619 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
620 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
621 break;
622 case USBPHY_INTERFACE_MODE_UTMIW:
623 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
624 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
625 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
626 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
627 break;
628 default:
629 break;
630 }
631
632 /*
633 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
634 * '0' during coreConsultant configuration. So default value will
635 * be '0' when the core is reset. Application needs to set it to
636 * '1' after the core initialization is completed.
637 */
638 if (dwc->revision > DWC3_REVISION_194A)
639 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
640
641 if (dwc->dis_u2_susphy_quirk)
642 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
643
644 if (dwc->dis_enblslpm_quirk)
645 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
646
647 if (dwc->dis_u2_freeclk_exists_quirk)
648 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
649
650 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
651
652 return 0;
653 }
654
dwc3_core_exit(struct dwc3 * dwc)655 static void dwc3_core_exit(struct dwc3 *dwc)
656 {
657 dwc3_event_buffers_cleanup(dwc);
658
659 usb_phy_shutdown(dwc->usb2_phy);
660 usb_phy_shutdown(dwc->usb3_phy);
661 phy_exit(dwc->usb2_generic_phy);
662 phy_exit(dwc->usb3_generic_phy);
663
664 usb_phy_set_suspend(dwc->usb2_phy, 1);
665 usb_phy_set_suspend(dwc->usb3_phy, 1);
666 phy_power_off(dwc->usb2_generic_phy);
667 phy_power_off(dwc->usb3_generic_phy);
668 }
669
dwc3_core_is_valid(struct dwc3 * dwc)670 static bool dwc3_core_is_valid(struct dwc3 *dwc)
671 {
672 u32 reg;
673
674 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
675
676 /* This should read as U3 followed by revision number */
677 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
678 /* Detected DWC_usb3 IP */
679 dwc->revision = reg;
680 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
681 /* Detected DWC_usb31 IP */
682 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
683 dwc->revision |= DWC3_REVISION_IS_DWC31;
684 } else {
685 return false;
686 }
687
688 return true;
689 }
690
dwc3_core_setup_global_control(struct dwc3 * dwc)691 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
692 {
693 u32 hwparams4 = dwc->hwparams.hwparams4;
694 u32 reg;
695
696 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
697 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
698
699 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
700 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
701 /**
702 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
703 * issue which would cause xHCI compliance tests to fail.
704 *
705 * Because of that we cannot enable clock gating on such
706 * configurations.
707 *
708 * Refers to:
709 *
710 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
711 * SOF/ITP Mode Used
712 */
713 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
714 dwc->dr_mode == USB_DR_MODE_OTG) &&
715 (dwc->revision >= DWC3_REVISION_210A &&
716 dwc->revision <= DWC3_REVISION_250A))
717 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
718 else
719 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
720 break;
721 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
722 /* enable hibernation here */
723 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
724
725 /*
726 * REVISIT Enabling this bit so that host-mode hibernation
727 * will work. Device-mode hibernation is not yet implemented.
728 */
729 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
730 break;
731 default:
732 /* nothing */
733 break;
734 }
735
736 /* check if current dwc3 is on simulation board */
737 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
738 dev_info(dwc->dev, "Running with FPGA optmizations\n");
739 dwc->is_fpga = true;
740 }
741
742 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
743 "disable_scramble cannot be used on non-FPGA builds\n");
744
745 if (dwc->disable_scramble_quirk && dwc->is_fpga)
746 reg |= DWC3_GCTL_DISSCRAMBLE;
747 else
748 reg &= ~DWC3_GCTL_DISSCRAMBLE;
749
750 if (dwc->u2exit_lfps_quirk)
751 reg |= DWC3_GCTL_U2EXIT_LFPS;
752
753 /*
754 * WORKAROUND: DWC3 revisions <1.90a have a bug
755 * where the device can fail to connect at SuperSpeed
756 * and falls back to high-speed mode which causes
757 * the device to enter a Connect/Disconnect loop
758 */
759 if (dwc->revision < DWC3_REVISION_190A)
760 reg |= DWC3_GCTL_U2RSTECN;
761
762 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
763 }
764
765 static int dwc3_core_get_phy(struct dwc3 *dwc);
766 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
767
768 /**
769 * dwc3_core_init - Low-level initialization of DWC3 Core
770 * @dwc: Pointer to our controller context structure
771 *
772 * Returns 0 on success otherwise negative errno.
773 */
dwc3_core_init(struct dwc3 * dwc)774 static int dwc3_core_init(struct dwc3 *dwc)
775 {
776 u32 reg;
777 int ret;
778
779 if (!dwc3_core_is_valid(dwc)) {
780 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
781 ret = -ENODEV;
782 goto err0;
783 }
784
785 /*
786 * Write Linux Version Code to our GUID register so it's easy to figure
787 * out which kernel version a bug was found.
788 */
789 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
790
791 /* Handle USB2.0-only core configuration */
792 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
793 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
794 if (dwc->maximum_speed == USB_SPEED_SUPER)
795 dwc->maximum_speed = USB_SPEED_HIGH;
796 }
797
798 ret = dwc3_phy_setup(dwc);
799 if (ret)
800 goto err0;
801
802 if (!dwc->ulpi_ready) {
803 ret = dwc3_core_ulpi_init(dwc);
804 if (ret)
805 goto err0;
806 dwc->ulpi_ready = true;
807 }
808
809 if (!dwc->phys_ready) {
810 ret = dwc3_core_get_phy(dwc);
811 if (ret)
812 goto err0a;
813 dwc->phys_ready = true;
814 }
815
816 ret = dwc3_core_soft_reset(dwc);
817 if (ret)
818 goto err0a;
819
820 dwc3_core_setup_global_control(dwc);
821 dwc3_core_num_eps(dwc);
822
823 ret = dwc3_setup_scratch_buffers(dwc);
824 if (ret)
825 goto err1;
826
827 /* Adjust Frame Length */
828 dwc3_frame_length_adjustment(dwc);
829
830 usb_phy_set_suspend(dwc->usb2_phy, 0);
831 usb_phy_set_suspend(dwc->usb3_phy, 0);
832 ret = phy_power_on(dwc->usb2_generic_phy);
833 if (ret < 0)
834 goto err2;
835
836 ret = phy_power_on(dwc->usb3_generic_phy);
837 if (ret < 0)
838 goto err3;
839
840 ret = dwc3_event_buffers_setup(dwc);
841 if (ret) {
842 dev_err(dwc->dev, "failed to setup event buffers\n");
843 goto err4;
844 }
845
846 /*
847 * ENDXFER polling is available on version 3.10a and later of
848 * the DWC_usb3 controller. It is NOT available in the
849 * DWC_usb31 controller.
850 */
851 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
852 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
853 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
854 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
855 }
856
857 if (dwc->revision >= DWC3_REVISION_250A) {
858 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
859
860 /*
861 * Enable hardware control of sending remote wakeup
862 * in HS when the device is in the L1 state.
863 */
864 if (dwc->revision >= DWC3_REVISION_290A)
865 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
866
867 if (dwc->dis_tx_ipgap_linecheck_quirk)
868 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
869
870 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
871 }
872
873 return 0;
874
875 err4:
876 phy_power_off(dwc->usb3_generic_phy);
877
878 err3:
879 phy_power_off(dwc->usb2_generic_phy);
880
881 err2:
882 usb_phy_set_suspend(dwc->usb2_phy, 1);
883 usb_phy_set_suspend(dwc->usb3_phy, 1);
884
885 err1:
886 usb_phy_shutdown(dwc->usb2_phy);
887 usb_phy_shutdown(dwc->usb3_phy);
888 phy_exit(dwc->usb2_generic_phy);
889 phy_exit(dwc->usb3_generic_phy);
890
891 err0a:
892 dwc3_ulpi_exit(dwc);
893
894 err0:
895 return ret;
896 }
897
dwc3_core_get_phy(struct dwc3 * dwc)898 static int dwc3_core_get_phy(struct dwc3 *dwc)
899 {
900 struct device *dev = dwc->dev;
901 struct device_node *node = dev->of_node;
902 int ret;
903
904 if (node) {
905 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
906 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
907 } else {
908 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
909 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
910 }
911
912 if (IS_ERR(dwc->usb2_phy)) {
913 ret = PTR_ERR(dwc->usb2_phy);
914 if (ret == -ENXIO || ret == -ENODEV) {
915 dwc->usb2_phy = NULL;
916 } else if (ret == -EPROBE_DEFER) {
917 return ret;
918 } else {
919 dev_err(dev, "no usb2 phy configured\n");
920 return ret;
921 }
922 }
923
924 if (IS_ERR(dwc->usb3_phy)) {
925 ret = PTR_ERR(dwc->usb3_phy);
926 if (ret == -ENXIO || ret == -ENODEV) {
927 dwc->usb3_phy = NULL;
928 } else if (ret == -EPROBE_DEFER) {
929 return ret;
930 } else {
931 dev_err(dev, "no usb3 phy configured\n");
932 return ret;
933 }
934 }
935
936 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
937 if (IS_ERR(dwc->usb2_generic_phy)) {
938 ret = PTR_ERR(dwc->usb2_generic_phy);
939 if (ret == -ENOSYS || ret == -ENODEV) {
940 dwc->usb2_generic_phy = NULL;
941 } else if (ret == -EPROBE_DEFER) {
942 return ret;
943 } else {
944 dev_err(dev, "no usb2 phy configured\n");
945 return ret;
946 }
947 }
948
949 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
950 if (IS_ERR(dwc->usb3_generic_phy)) {
951 ret = PTR_ERR(dwc->usb3_generic_phy);
952 if (ret == -ENOSYS || ret == -ENODEV) {
953 dwc->usb3_generic_phy = NULL;
954 } else if (ret == -EPROBE_DEFER) {
955 return ret;
956 } else {
957 dev_err(dev, "no usb3 phy configured\n");
958 return ret;
959 }
960 }
961
962 return 0;
963 }
964
dwc3_core_init_mode(struct dwc3 * dwc)965 static int dwc3_core_init_mode(struct dwc3 *dwc)
966 {
967 struct device *dev = dwc->dev;
968 int ret;
969
970 switch (dwc->dr_mode) {
971 case USB_DR_MODE_PERIPHERAL:
972 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
973
974 if (dwc->usb2_phy)
975 otg_set_vbus(dwc->usb2_phy->otg, false);
976 if (dwc->usb2_generic_phy)
977 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
978
979 ret = dwc3_gadget_init(dwc);
980 if (ret) {
981 if (ret != -EPROBE_DEFER)
982 dev_err(dev, "failed to initialize gadget\n");
983 return ret;
984 }
985 break;
986 case USB_DR_MODE_HOST:
987 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
988
989 if (dwc->usb2_phy)
990 otg_set_vbus(dwc->usb2_phy->otg, true);
991 if (dwc->usb2_generic_phy)
992 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
993
994 ret = dwc3_host_init(dwc);
995 if (ret) {
996 if (ret != -EPROBE_DEFER)
997 dev_err(dev, "failed to initialize host\n");
998 return ret;
999 }
1000 break;
1001 case USB_DR_MODE_OTG:
1002 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1003 ret = dwc3_drd_init(dwc);
1004 if (ret) {
1005 if (ret != -EPROBE_DEFER)
1006 dev_err(dev, "failed to initialize dual-role\n");
1007 return ret;
1008 }
1009 break;
1010 default:
1011 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1012 return -EINVAL;
1013 }
1014
1015 return 0;
1016 }
1017
dwc3_core_exit_mode(struct dwc3 * dwc)1018 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1019 {
1020 switch (dwc->dr_mode) {
1021 case USB_DR_MODE_PERIPHERAL:
1022 dwc3_gadget_exit(dwc);
1023 break;
1024 case USB_DR_MODE_HOST:
1025 dwc3_host_exit(dwc);
1026 break;
1027 case USB_DR_MODE_OTG:
1028 dwc3_drd_exit(dwc);
1029 break;
1030 default:
1031 /* do nothing */
1032 break;
1033 }
1034
1035 /* de-assert DRVVBUS for HOST and OTG mode */
1036 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1037 }
1038
dwc3_get_properties(struct dwc3 * dwc)1039 static void dwc3_get_properties(struct dwc3 *dwc)
1040 {
1041 struct device *dev = dwc->dev;
1042 u8 lpm_nyet_threshold;
1043 u8 tx_de_emphasis;
1044 u8 hird_threshold;
1045
1046 /* default to highest possible threshold */
1047 lpm_nyet_threshold = 0xf;
1048
1049 /* default to -3.5dB de-emphasis */
1050 tx_de_emphasis = 1;
1051
1052 /*
1053 * default to assert utmi_sleep_n and use maximum allowed HIRD
1054 * threshold value of 0b1100
1055 */
1056 hird_threshold = 12;
1057
1058 dwc->maximum_speed = usb_get_maximum_speed(dev);
1059 dwc->dr_mode = usb_get_dr_mode(dev);
1060 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1061
1062 dwc->sysdev_is_parent = device_property_read_bool(dev,
1063 "linux,sysdev_is_parent");
1064 if (dwc->sysdev_is_parent)
1065 dwc->sysdev = dwc->dev->parent;
1066 else
1067 dwc->sysdev = dwc->dev;
1068
1069 dwc->has_lpm_erratum = device_property_read_bool(dev,
1070 "snps,has-lpm-erratum");
1071 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1072 &lpm_nyet_threshold);
1073 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1074 "snps,is-utmi-l1-suspend");
1075 device_property_read_u8(dev, "snps,hird-threshold",
1076 &hird_threshold);
1077 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1078 "snps,usb3_lpm_capable");
1079
1080 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1081 "snps,disable_scramble_quirk");
1082 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1083 "snps,u2exit_lfps_quirk");
1084 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1085 "snps,u2ss_inp3_quirk");
1086 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1087 "snps,req_p1p2p3_quirk");
1088 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1089 "snps,del_p1p2p3_quirk");
1090 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1091 "snps,del_phy_power_chg_quirk");
1092 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1093 "snps,lfps_filter_quirk");
1094 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1095 "snps,rx_detect_poll_quirk");
1096 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1097 "snps,dis_u3_susphy_quirk");
1098 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1099 "snps,dis_u2_susphy_quirk");
1100 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1101 "snps,dis_enblslpm_quirk");
1102 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1103 "snps,dis_rxdet_inp3_quirk");
1104 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1105 "snps,dis-u2-freeclk-exists-quirk");
1106 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1107 "snps,dis-del-phy-power-chg-quirk");
1108 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1109 "snps,dis-tx-ipgap-linecheck-quirk");
1110
1111 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1112 "snps,tx_de_emphasis_quirk");
1113 device_property_read_u8(dev, "snps,tx_de_emphasis",
1114 &tx_de_emphasis);
1115 device_property_read_string(dev, "snps,hsphy_interface",
1116 &dwc->hsphy_interface);
1117 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1118 &dwc->fladj);
1119
1120 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1121 "snps,dis_metastability_quirk");
1122
1123 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1124 dwc->tx_de_emphasis = tx_de_emphasis;
1125
1126 dwc->hird_threshold = hird_threshold
1127 | (dwc->is_utmi_l1_suspend << 4);
1128
1129 dwc->imod_interval = 0;
1130 }
1131
1132 /* check whether the core supports IMOD */
dwc3_has_imod(struct dwc3 * dwc)1133 bool dwc3_has_imod(struct dwc3 *dwc)
1134 {
1135 return ((dwc3_is_usb3(dwc) &&
1136 dwc->revision >= DWC3_REVISION_300A) ||
1137 (dwc3_is_usb31(dwc) &&
1138 dwc->revision >= DWC3_USB31_REVISION_120A));
1139 }
1140
dwc3_check_params(struct dwc3 * dwc)1141 static void dwc3_check_params(struct dwc3 *dwc)
1142 {
1143 struct device *dev = dwc->dev;
1144
1145 /* Check for proper value of imod_interval */
1146 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1147 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1148 dwc->imod_interval = 0;
1149 }
1150
1151 /*
1152 * Workaround for STAR 9000961433 which affects only version
1153 * 3.00a of the DWC_usb3 core. This prevents the controller
1154 * interrupt from being masked while handling events. IMOD
1155 * allows us to work around this issue. Enable it for the
1156 * affected version.
1157 */
1158 if (!dwc->imod_interval &&
1159 (dwc->revision == DWC3_REVISION_300A))
1160 dwc->imod_interval = 1;
1161
1162 /* Check the maximum_speed parameter */
1163 switch (dwc->maximum_speed) {
1164 case USB_SPEED_LOW:
1165 case USB_SPEED_FULL:
1166 case USB_SPEED_HIGH:
1167 case USB_SPEED_SUPER:
1168 case USB_SPEED_SUPER_PLUS:
1169 break;
1170 default:
1171 dev_err(dev, "invalid maximum_speed parameter %d\n",
1172 dwc->maximum_speed);
1173 /* fall through */
1174 case USB_SPEED_UNKNOWN:
1175 /* default to superspeed */
1176 dwc->maximum_speed = USB_SPEED_SUPER;
1177
1178 /*
1179 * default to superspeed plus if we are capable.
1180 */
1181 if (dwc3_is_usb31(dwc) &&
1182 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1183 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1184 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1185
1186 break;
1187 }
1188 }
1189
dwc3_probe(struct platform_device * pdev)1190 static int dwc3_probe(struct platform_device *pdev)
1191 {
1192 struct device *dev = &pdev->dev;
1193 struct resource *res;
1194 struct dwc3 *dwc;
1195
1196 int ret;
1197
1198 void __iomem *regs;
1199
1200 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1201 if (!dwc)
1202 return -ENOMEM;
1203
1204 dwc->dev = dev;
1205
1206 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1207 if (!res) {
1208 dev_err(dev, "missing memory resource\n");
1209 return -ENODEV;
1210 }
1211
1212 dwc->xhci_resources[0].start = res->start;
1213 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1214 DWC3_XHCI_REGS_END;
1215 dwc->xhci_resources[0].flags = res->flags;
1216 dwc->xhci_resources[0].name = res->name;
1217
1218 res->start += DWC3_GLOBALS_REGS_START;
1219
1220 /*
1221 * Request memory region but exclude xHCI regs,
1222 * since it will be requested by the xhci-plat driver.
1223 */
1224 regs = devm_ioremap_resource(dev, res);
1225 if (IS_ERR(regs)) {
1226 ret = PTR_ERR(regs);
1227 goto err0;
1228 }
1229
1230 dwc->regs = regs;
1231 dwc->regs_size = resource_size(res);
1232
1233 dwc3_get_properties(dwc);
1234
1235 platform_set_drvdata(pdev, dwc);
1236 dwc3_cache_hwparams(dwc);
1237
1238 spin_lock_init(&dwc->lock);
1239
1240 pm_runtime_set_active(dev);
1241 pm_runtime_use_autosuspend(dev);
1242 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1243 pm_runtime_enable(dev);
1244 ret = pm_runtime_get_sync(dev);
1245 if (ret < 0)
1246 goto err1;
1247
1248 pm_runtime_forbid(dev);
1249
1250 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1251 if (ret) {
1252 dev_err(dwc->dev, "failed to allocate event buffers\n");
1253 ret = -ENOMEM;
1254 goto err2;
1255 }
1256
1257 ret = dwc3_get_dr_mode(dwc);
1258 if (ret)
1259 goto err3;
1260
1261 ret = dwc3_alloc_scratch_buffers(dwc);
1262 if (ret)
1263 goto err3;
1264
1265 ret = dwc3_core_init(dwc);
1266 if (ret) {
1267 if (ret != -EPROBE_DEFER)
1268 dev_err(dev, "failed to initialize core: %d\n", ret);
1269 goto err4;
1270 }
1271
1272 dwc3_check_params(dwc);
1273
1274 ret = dwc3_core_init_mode(dwc);
1275 if (ret)
1276 goto err5;
1277
1278 dwc3_debugfs_init(dwc);
1279 pm_runtime_put(dev);
1280
1281 return 0;
1282
1283 err5:
1284 dwc3_event_buffers_cleanup(dwc);
1285 dwc3_ulpi_exit(dwc);
1286
1287 err4:
1288 dwc3_free_scratch_buffers(dwc);
1289
1290 err3:
1291 dwc3_free_event_buffers(dwc);
1292
1293 err2:
1294 pm_runtime_allow(&pdev->dev);
1295
1296 err1:
1297 pm_runtime_put_sync(&pdev->dev);
1298 pm_runtime_disable(&pdev->dev);
1299
1300 err0:
1301 /*
1302 * restore res->start back to its original value so that, in case the
1303 * probe is deferred, we don't end up getting error in request the
1304 * memory region the next time probe is called.
1305 */
1306 res->start -= DWC3_GLOBALS_REGS_START;
1307
1308 return ret;
1309 }
1310
dwc3_remove(struct platform_device * pdev)1311 static int dwc3_remove(struct platform_device *pdev)
1312 {
1313 struct dwc3 *dwc = platform_get_drvdata(pdev);
1314 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1315
1316 pm_runtime_get_sync(&pdev->dev);
1317 /*
1318 * restore res->start back to its original value so that, in case the
1319 * probe is deferred, we don't end up getting error in request the
1320 * memory region the next time probe is called.
1321 */
1322 res->start -= DWC3_GLOBALS_REGS_START;
1323
1324 dwc3_debugfs_exit(dwc);
1325 dwc3_core_exit_mode(dwc);
1326
1327 dwc3_core_exit(dwc);
1328 dwc3_ulpi_exit(dwc);
1329
1330 pm_runtime_put_sync(&pdev->dev);
1331 pm_runtime_allow(&pdev->dev);
1332 pm_runtime_disable(&pdev->dev);
1333
1334 dwc3_free_event_buffers(dwc);
1335 dwc3_free_scratch_buffers(dwc);
1336
1337 return 0;
1338 }
1339
1340 #ifdef CONFIG_PM
dwc3_suspend_common(struct dwc3 * dwc)1341 static int dwc3_suspend_common(struct dwc3 *dwc)
1342 {
1343 unsigned long flags;
1344
1345 switch (dwc->dr_mode) {
1346 case USB_DR_MODE_PERIPHERAL:
1347 case USB_DR_MODE_OTG:
1348 spin_lock_irqsave(&dwc->lock, flags);
1349 dwc3_gadget_suspend(dwc);
1350 spin_unlock_irqrestore(&dwc->lock, flags);
1351 break;
1352 case USB_DR_MODE_HOST:
1353 default:
1354 /* do nothing */
1355 break;
1356 }
1357
1358 dwc3_core_exit(dwc);
1359
1360 return 0;
1361 }
1362
dwc3_resume_common(struct dwc3 * dwc)1363 static int dwc3_resume_common(struct dwc3 *dwc)
1364 {
1365 unsigned long flags;
1366 int ret;
1367
1368 ret = dwc3_core_init(dwc);
1369 if (ret)
1370 return ret;
1371
1372 switch (dwc->dr_mode) {
1373 case USB_DR_MODE_PERIPHERAL:
1374 case USB_DR_MODE_OTG:
1375 spin_lock_irqsave(&dwc->lock, flags);
1376 dwc3_gadget_resume(dwc);
1377 spin_unlock_irqrestore(&dwc->lock, flags);
1378 /* FALLTHROUGH */
1379 case USB_DR_MODE_HOST:
1380 default:
1381 /* do nothing */
1382 break;
1383 }
1384
1385 return 0;
1386 }
1387
dwc3_runtime_checks(struct dwc3 * dwc)1388 static int dwc3_runtime_checks(struct dwc3 *dwc)
1389 {
1390 switch (dwc->dr_mode) {
1391 case USB_DR_MODE_PERIPHERAL:
1392 case USB_DR_MODE_OTG:
1393 if (dwc->connected)
1394 return -EBUSY;
1395 break;
1396 case USB_DR_MODE_HOST:
1397 default:
1398 /* do nothing */
1399 break;
1400 }
1401
1402 return 0;
1403 }
1404
dwc3_runtime_suspend(struct device * dev)1405 static int dwc3_runtime_suspend(struct device *dev)
1406 {
1407 struct dwc3 *dwc = dev_get_drvdata(dev);
1408 int ret;
1409
1410 if (dwc3_runtime_checks(dwc))
1411 return -EBUSY;
1412
1413 ret = dwc3_suspend_common(dwc);
1414 if (ret)
1415 return ret;
1416
1417 device_init_wakeup(dev, true);
1418
1419 return 0;
1420 }
1421
dwc3_runtime_resume(struct device * dev)1422 static int dwc3_runtime_resume(struct device *dev)
1423 {
1424 struct dwc3 *dwc = dev_get_drvdata(dev);
1425 int ret;
1426
1427 device_init_wakeup(dev, false);
1428
1429 ret = dwc3_resume_common(dwc);
1430 if (ret)
1431 return ret;
1432
1433 switch (dwc->dr_mode) {
1434 case USB_DR_MODE_PERIPHERAL:
1435 case USB_DR_MODE_OTG:
1436 dwc3_gadget_process_pending_events(dwc);
1437 break;
1438 case USB_DR_MODE_HOST:
1439 default:
1440 /* do nothing */
1441 break;
1442 }
1443
1444 pm_runtime_mark_last_busy(dev);
1445 pm_runtime_put(dev);
1446
1447 return 0;
1448 }
1449
dwc3_runtime_idle(struct device * dev)1450 static int dwc3_runtime_idle(struct device *dev)
1451 {
1452 struct dwc3 *dwc = dev_get_drvdata(dev);
1453
1454 switch (dwc->dr_mode) {
1455 case USB_DR_MODE_PERIPHERAL:
1456 case USB_DR_MODE_OTG:
1457 if (dwc3_runtime_checks(dwc))
1458 return -EBUSY;
1459 break;
1460 case USB_DR_MODE_HOST:
1461 default:
1462 /* do nothing */
1463 break;
1464 }
1465
1466 pm_runtime_mark_last_busy(dev);
1467 pm_runtime_autosuspend(dev);
1468
1469 return 0;
1470 }
1471 #endif /* CONFIG_PM */
1472
1473 #ifdef CONFIG_PM_SLEEP
dwc3_suspend(struct device * dev)1474 static int dwc3_suspend(struct device *dev)
1475 {
1476 struct dwc3 *dwc = dev_get_drvdata(dev);
1477 int ret;
1478
1479 ret = dwc3_suspend_common(dwc);
1480 if (ret)
1481 return ret;
1482
1483 pinctrl_pm_select_sleep_state(dev);
1484
1485 return 0;
1486 }
1487
dwc3_resume(struct device * dev)1488 static int dwc3_resume(struct device *dev)
1489 {
1490 struct dwc3 *dwc = dev_get_drvdata(dev);
1491 int ret;
1492
1493 pinctrl_pm_select_default_state(dev);
1494
1495 ret = dwc3_resume_common(dwc);
1496 if (ret)
1497 return ret;
1498
1499 pm_runtime_disable(dev);
1500 pm_runtime_set_active(dev);
1501 pm_runtime_enable(dev);
1502
1503 return 0;
1504 }
1505 #endif /* CONFIG_PM_SLEEP */
1506
1507 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1508 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1509 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1510 dwc3_runtime_idle)
1511 };
1512
1513 #ifdef CONFIG_OF
1514 static const struct of_device_id of_dwc3_match[] = {
1515 {
1516 .compatible = "snps,dwc3"
1517 },
1518 {
1519 .compatible = "synopsys,dwc3"
1520 },
1521 { },
1522 };
1523 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1524 #endif
1525
1526 #ifdef CONFIG_ACPI
1527
1528 #define ACPI_ID_INTEL_BSW "808622B7"
1529
1530 static const struct acpi_device_id dwc3_acpi_match[] = {
1531 { ACPI_ID_INTEL_BSW, 0 },
1532 { },
1533 };
1534 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1535 #endif
1536
1537 static struct platform_driver dwc3_driver = {
1538 .probe = dwc3_probe,
1539 .remove = dwc3_remove,
1540 .driver = {
1541 .name = "dwc3",
1542 .of_match_table = of_match_ptr(of_dwc3_match),
1543 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1544 .pm = &dwc3_dev_pm_ops,
1545 },
1546 };
1547
1548 module_platform_driver(dwc3_driver);
1549
1550 MODULE_ALIAS("platform:dwc3");
1551 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1552 MODULE_LICENSE("GPL v2");
1553 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
1554